if_mvxpe.c revision 1.2.2.4
1 1.2.2.4 skrll /* $NetBSD: if_mvxpe.c,v 1.2.2.4 2016/07/09 20:25:03 skrll Exp $ */ 2 1.2.2.2 skrll /* 3 1.2.2.2 skrll * Copyright (c) 2015 Internet Initiative Japan Inc. 4 1.2.2.2 skrll * All rights reserved. 5 1.2.2.2 skrll * 6 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll * modification, are permitted provided that the following conditions 8 1.2.2.2 skrll * are met: 9 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.2.2.2 skrll * 15 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.2.2.2 skrll * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.2.2.2 skrll * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.2.2.2 skrll * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.2.2.2 skrll * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.2.2.2 skrll * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.2.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.2.2.2 skrll * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.2.2.2 skrll * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.2.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 26 1.2.2.2 skrll */ 27 1.2.2.2 skrll #include <sys/cdefs.h> 28 1.2.2.4 skrll __KERNEL_RCSID(0, "$NetBSD: if_mvxpe.c,v 1.2.2.4 2016/07/09 20:25:03 skrll Exp $"); 29 1.2.2.2 skrll 30 1.2.2.2 skrll #include "opt_multiprocessor.h" 31 1.2.2.2 skrll 32 1.2.2.2 skrll #include <sys/param.h> 33 1.2.2.2 skrll #include <sys/bus.h> 34 1.2.2.2 skrll #include <sys/callout.h> 35 1.2.2.2 skrll #include <sys/device.h> 36 1.2.2.2 skrll #include <sys/endian.h> 37 1.2.2.2 skrll #include <sys/errno.h> 38 1.2.2.2 skrll #include <sys/evcnt.h> 39 1.2.2.2 skrll #include <sys/kernel.h> 40 1.2.2.2 skrll #include <sys/kmem.h> 41 1.2.2.2 skrll #include <sys/mutex.h> 42 1.2.2.2 skrll #include <sys/sockio.h> 43 1.2.2.2 skrll #include <sys/sysctl.h> 44 1.2.2.2 skrll #include <sys/syslog.h> 45 1.2.2.2 skrll #include <sys/rndsource.h> 46 1.2.2.2 skrll 47 1.2.2.2 skrll #include <net/if.h> 48 1.2.2.2 skrll #include <net/if_ether.h> 49 1.2.2.2 skrll #include <net/if_media.h> 50 1.2.2.2 skrll #include <net/bpf.h> 51 1.2.2.2 skrll 52 1.2.2.2 skrll #include <netinet/in.h> 53 1.2.2.2 skrll #include <netinet/in_systm.h> 54 1.2.2.2 skrll #include <netinet/ip.h> 55 1.2.2.2 skrll 56 1.2.2.2 skrll #include <dev/mii/mii.h> 57 1.2.2.2 skrll #include <dev/mii/miivar.h> 58 1.2.2.2 skrll 59 1.2.2.2 skrll #include <dev/marvell/marvellreg.h> 60 1.2.2.2 skrll #include <dev/marvell/marvellvar.h> 61 1.2.2.2 skrll #include <dev/marvell/mvxpbmvar.h> 62 1.2.2.2 skrll #include <dev/marvell/if_mvxpereg.h> 63 1.2.2.2 skrll #include <dev/marvell/if_mvxpevar.h> 64 1.2.2.2 skrll 65 1.2.2.2 skrll #include "locators.h" 66 1.2.2.2 skrll 67 1.2.2.2 skrll #if BYTE_ORDER == BIG_ENDIAN 68 1.2.2.2 skrll #error "BIG ENDIAN not supported" 69 1.2.2.2 skrll #endif 70 1.2.2.2 skrll 71 1.2.2.2 skrll #ifdef MVXPE_DEBUG 72 1.2.2.2 skrll #define STATIC /* nothing */ 73 1.2.2.2 skrll #else 74 1.2.2.2 skrll #define STATIC static 75 1.2.2.2 skrll #endif 76 1.2.2.2 skrll 77 1.2.2.2 skrll /* autoconf(9) */ 78 1.2.2.2 skrll STATIC int mvxpe_match(device_t, struct cfdata *, void *); 79 1.2.2.2 skrll STATIC void mvxpe_attach(device_t, device_t, void *); 80 1.2.2.2 skrll STATIC int mvxpe_evcnt_attach(struct mvxpe_softc *); 81 1.2.2.2 skrll CFATTACH_DECL_NEW(mvxpe_mbus, sizeof(struct mvxpe_softc), 82 1.2.2.2 skrll mvxpe_match, mvxpe_attach, NULL, NULL); 83 1.2.2.2 skrll STATIC void mvxpe_sc_lock(struct mvxpe_softc *); 84 1.2.2.2 skrll STATIC void mvxpe_sc_unlock(struct mvxpe_softc *); 85 1.2.2.2 skrll 86 1.2.2.2 skrll /* MII */ 87 1.2.2.2 skrll STATIC int mvxpe_miibus_readreg(device_t, int, int); 88 1.2.2.2 skrll STATIC void mvxpe_miibus_writereg(device_t, int, int, int); 89 1.2.2.2 skrll STATIC void mvxpe_miibus_statchg(struct ifnet *); 90 1.2.2.2 skrll 91 1.2.2.2 skrll /* Addres Decoding Window */ 92 1.2.2.2 skrll STATIC void mvxpe_wininit(struct mvxpe_softc *, enum marvell_tags *); 93 1.2.2.2 skrll 94 1.2.2.2 skrll /* Device Register Initialization */ 95 1.2.2.2 skrll STATIC int mvxpe_initreg(struct ifnet *); 96 1.2.2.2 skrll 97 1.2.2.2 skrll /* Descriptor Ring Control for each of queues */ 98 1.2.2.2 skrll STATIC void *mvxpe_dma_memalloc(struct mvxpe_softc *, bus_dmamap_t *, size_t); 99 1.2.2.2 skrll STATIC int mvxpe_ring_alloc_queue(struct mvxpe_softc *, int); 100 1.2.2.2 skrll STATIC void mvxpe_ring_dealloc_queue(struct mvxpe_softc *, int); 101 1.2.2.2 skrll STATIC void mvxpe_ring_init_queue(struct mvxpe_softc *, int); 102 1.2.2.2 skrll STATIC void mvxpe_ring_flush_queue(struct mvxpe_softc *, int); 103 1.2.2.2 skrll STATIC void mvxpe_ring_sync_rx(struct mvxpe_softc *, int, int, int, int); 104 1.2.2.2 skrll STATIC void mvxpe_ring_sync_tx(struct mvxpe_softc *, int, int, int, int); 105 1.2.2.2 skrll 106 1.2.2.2 skrll /* Rx/Tx Queue Control */ 107 1.2.2.2 skrll STATIC int mvxpe_rx_queue_init(struct ifnet *, int); 108 1.2.2.2 skrll STATIC int mvxpe_tx_queue_init(struct ifnet *, int); 109 1.2.2.2 skrll STATIC int mvxpe_rx_queue_enable(struct ifnet *, int); 110 1.2.2.2 skrll STATIC int mvxpe_tx_queue_enable(struct ifnet *, int); 111 1.2.2.2 skrll STATIC void mvxpe_rx_lockq(struct mvxpe_softc *, int); 112 1.2.2.2 skrll STATIC void mvxpe_rx_unlockq(struct mvxpe_softc *, int); 113 1.2.2.2 skrll STATIC void mvxpe_tx_lockq(struct mvxpe_softc *, int); 114 1.2.2.2 skrll STATIC void mvxpe_tx_unlockq(struct mvxpe_softc *, int); 115 1.2.2.2 skrll 116 1.2.2.2 skrll /* Interrupt Handlers */ 117 1.2.2.2 skrll STATIC void mvxpe_disable_intr(struct mvxpe_softc *); 118 1.2.2.2 skrll STATIC void mvxpe_enable_intr(struct mvxpe_softc *); 119 1.2.2.2 skrll STATIC int mvxpe_rxtxth_intr(void *); 120 1.2.2.2 skrll STATIC int mvxpe_misc_intr(void *); 121 1.2.2.2 skrll STATIC int mvxpe_rxtx_intr(void *); 122 1.2.2.2 skrll STATIC void mvxpe_tick(void *); 123 1.2.2.2 skrll 124 1.2.2.2 skrll /* struct ifnet and mii callbacks*/ 125 1.2.2.2 skrll STATIC void mvxpe_start(struct ifnet *); 126 1.2.2.2 skrll STATIC int mvxpe_ioctl(struct ifnet *, u_long, void *); 127 1.2.2.2 skrll STATIC int mvxpe_init(struct ifnet *); 128 1.2.2.2 skrll STATIC void mvxpe_stop(struct ifnet *, int); 129 1.2.2.2 skrll STATIC void mvxpe_watchdog(struct ifnet *); 130 1.2.2.2 skrll STATIC int mvxpe_ifflags_cb(struct ethercom *); 131 1.2.2.2 skrll STATIC int mvxpe_mediachange(struct ifnet *); 132 1.2.2.2 skrll STATIC void mvxpe_mediastatus(struct ifnet *, struct ifmediareq *); 133 1.2.2.2 skrll 134 1.2.2.2 skrll /* Link State Notify */ 135 1.2.2.2 skrll STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc); 136 1.2.2.2 skrll STATIC void mvxpe_linkup(struct mvxpe_softc *); 137 1.2.2.2 skrll STATIC void mvxpe_linkdown(struct mvxpe_softc *); 138 1.2.2.2 skrll STATIC void mvxpe_linkreset(struct mvxpe_softc *); 139 1.2.2.2 skrll 140 1.2.2.2 skrll /* Tx Subroutines */ 141 1.2.2.2 skrll STATIC int mvxpe_tx_queue_select(struct mvxpe_softc *, struct mbuf *); 142 1.2.2.2 skrll STATIC int mvxpe_tx_queue(struct mvxpe_softc *, struct mbuf *, int); 143 1.2.2.2 skrll STATIC void mvxpe_tx_set_csumflag(struct ifnet *, 144 1.2.2.2 skrll struct mvxpe_tx_desc *, struct mbuf *); 145 1.2.2.2 skrll STATIC void mvxpe_tx_complete(struct mvxpe_softc *, uint32_t); 146 1.2.2.2 skrll STATIC void mvxpe_tx_queue_complete(struct mvxpe_softc *, int); 147 1.2.2.2 skrll 148 1.2.2.2 skrll /* Rx Subroutines */ 149 1.2.2.2 skrll STATIC void mvxpe_rx(struct mvxpe_softc *, uint32_t); 150 1.2.2.2 skrll STATIC void mvxpe_rx_queue(struct mvxpe_softc *, int, int); 151 1.2.2.2 skrll STATIC int mvxpe_rx_queue_select(struct mvxpe_softc *, uint32_t, int *); 152 1.2.2.2 skrll STATIC void mvxpe_rx_refill(struct mvxpe_softc *, uint32_t); 153 1.2.2.2 skrll STATIC void mvxpe_rx_queue_refill(struct mvxpe_softc *, int); 154 1.2.2.2 skrll STATIC int mvxpe_rx_queue_add(struct mvxpe_softc *, int); 155 1.2.2.2 skrll STATIC void mvxpe_rx_set_csumflag(struct ifnet *, 156 1.2.2.2 skrll struct mvxpe_rx_desc *, struct mbuf *); 157 1.2.2.2 skrll 158 1.2.2.2 skrll /* MAC address filter */ 159 1.2.2.2 skrll STATIC uint8_t mvxpe_crc8(const uint8_t *, size_t); 160 1.2.2.2 skrll STATIC void mvxpe_filter_setup(struct mvxpe_softc *); 161 1.2.2.2 skrll 162 1.2.2.2 skrll /* sysctl(9) */ 163 1.2.2.2 skrll STATIC int sysctl_read_mib(SYSCTLFN_PROTO); 164 1.2.2.2 skrll STATIC int sysctl_clear_mib(SYSCTLFN_PROTO); 165 1.2.2.2 skrll STATIC int sysctl_set_queue_length(SYSCTLFN_PROTO); 166 1.2.2.2 skrll STATIC int sysctl_set_queue_rxthtime(SYSCTLFN_PROTO); 167 1.2.2.2 skrll STATIC void sysctl_mvxpe_init(struct mvxpe_softc *); 168 1.2.2.2 skrll 169 1.2.2.2 skrll /* MIB */ 170 1.2.2.2 skrll STATIC void mvxpe_clear_mib(struct mvxpe_softc *); 171 1.2.2.2 skrll STATIC void mvxpe_update_mib(struct mvxpe_softc *); 172 1.2.2.2 skrll 173 1.2.2.2 skrll /* for Debug */ 174 1.2.2.2 skrll STATIC void mvxpe_dump_txdesc(struct mvxpe_tx_desc *, int) __attribute__((__unused__)); 175 1.2.2.2 skrll STATIC void mvxpe_dump_rxdesc(struct mvxpe_rx_desc *, int) __attribute__((__unused__)); 176 1.2.2.2 skrll 177 1.2.2.2 skrll STATIC int mvxpe_root_num; 178 1.2.2.2 skrll STATIC kmutex_t mii_mutex; 179 1.2.2.2 skrll STATIC int mii_init = 0; 180 1.2.2.2 skrll #ifdef MVXPE_DEBUG 181 1.2.2.2 skrll STATIC int mvxpe_debug = MVXPE_DEBUG; 182 1.2.2.2 skrll #endif 183 1.2.2.2 skrll 184 1.2.2.2 skrll /* 185 1.2.2.2 skrll * List of MIB register and names 186 1.2.2.2 skrll */ 187 1.2.2.2 skrll STATIC struct mvxpe_mib_def { 188 1.2.2.2 skrll uint32_t regnum; 189 1.2.2.2 skrll int reg64; 190 1.2.2.2 skrll const char *sysctl_name; 191 1.2.2.2 skrll const char *desc; 192 1.2.2.3 skrll int ext; 193 1.2.2.3 skrll #define MVXPE_MIBEXT_IF_OERRORS 1 194 1.2.2.3 skrll #define MVXPE_MIBEXT_IF_IERRORS 2 195 1.2.2.3 skrll #define MVXPE_MIBEXT_IF_COLLISIONS 3 196 1.2.2.2 skrll } mvxpe_mib_list[] = { 197 1.2.2.2 skrll {MVXPE_MIB_RX_GOOD_OCT, 1, "rx_good_oct", 198 1.2.2.3 skrll "Good Octets Rx", 0}, 199 1.2.2.2 skrll {MVXPE_MIB_RX_BAD_OCT, 0, "rx_bad_oct", 200 1.2.2.3 skrll "Bad Octets Rx", 0}, 201 1.2.2.3 skrll {MVXPE_MIB_TX_MAC_TRNS_ERR, 0, "tx_mac_err", 202 1.2.2.3 skrll "MAC Transmit Error", MVXPE_MIBEXT_IF_OERRORS}, 203 1.2.2.2 skrll {MVXPE_MIB_RX_GOOD_FRAME, 0, "rx_good_frame", 204 1.2.2.3 skrll "Good Frames Rx", 0}, 205 1.2.2.2 skrll {MVXPE_MIB_RX_BAD_FRAME, 0, "rx_bad_frame", 206 1.2.2.3 skrll "Bad Frames Rx", 0}, 207 1.2.2.2 skrll {MVXPE_MIB_RX_BCAST_FRAME, 0, "rx_bcast_frame", 208 1.2.2.3 skrll "Broadcast Frames Rx", 0}, 209 1.2.2.2 skrll {MVXPE_MIB_RX_MCAST_FRAME, 0, "rx_mcast_frame", 210 1.2.2.3 skrll "Multicast Frames Rx", 0}, 211 1.2.2.2 skrll {MVXPE_MIB_RX_FRAME64_OCT, 0, "rx_frame_1_64", 212 1.2.2.3 skrll "Frame Size 1 - 64", 0}, 213 1.2.2.2 skrll {MVXPE_MIB_RX_FRAME127_OCT, 0, "rx_frame_65_127", 214 1.2.2.3 skrll "Frame Size 65 - 127", 0}, 215 1.2.2.2 skrll {MVXPE_MIB_RX_FRAME255_OCT, 0, "rx_frame_128_255", 216 1.2.2.3 skrll "Frame Size 128 - 255", 0}, 217 1.2.2.2 skrll {MVXPE_MIB_RX_FRAME511_OCT, 0, "rx_frame_256_511", 218 1.2.2.2 skrll "Frame Size 256 - 511"}, 219 1.2.2.2 skrll {MVXPE_MIB_RX_FRAME1023_OCT, 0, "rx_frame_512_1023", 220 1.2.2.3 skrll "Frame Size 512 - 1023", 0}, 221 1.2.2.2 skrll {MVXPE_MIB_RX_FRAMEMAX_OCT, 0, "rx_fame_1024_max", 222 1.2.2.3 skrll "Frame Size 1024 - Max", 0}, 223 1.2.2.2 skrll {MVXPE_MIB_TX_GOOD_OCT, 1, "tx_good_oct", 224 1.2.2.3 skrll "Good Octets Tx", 0}, 225 1.2.2.2 skrll {MVXPE_MIB_TX_GOOD_FRAME, 0, "tx_good_frame", 226 1.2.2.3 skrll "Good Frames Tx", 0}, 227 1.2.2.2 skrll {MVXPE_MIB_TX_EXCES_COL, 0, "tx_exces_collision", 228 1.2.2.3 skrll "Excessive Collision", MVXPE_MIBEXT_IF_OERRORS}, 229 1.2.2.2 skrll {MVXPE_MIB_TX_MCAST_FRAME, 0, "tx_mcast_frame", 230 1.2.2.2 skrll "Multicast Frames Tx"}, 231 1.2.2.2 skrll {MVXPE_MIB_TX_BCAST_FRAME, 0, "tx_bcast_frame", 232 1.2.2.2 skrll "Broadcast Frames Tx"}, 233 1.2.2.2 skrll {MVXPE_MIB_TX_MAC_CTL_ERR, 0, "tx_mac_err", 234 1.2.2.3 skrll "Unknown MAC Control", 0}, 235 1.2.2.2 skrll {MVXPE_MIB_FC_SENT, 0, "fc_tx", 236 1.2.2.3 skrll "Flow Control Tx", 0}, 237 1.2.2.2 skrll {MVXPE_MIB_FC_GOOD, 0, "fc_rx_good", 238 1.2.2.3 skrll "Good Flow Control Rx", 0}, 239 1.2.2.2 skrll {MVXPE_MIB_FC_BAD, 0, "fc_rx_bad", 240 1.2.2.3 skrll "Bad Flow Control Rx", 0}, 241 1.2.2.2 skrll {MVXPE_MIB_PKT_UNDERSIZE, 0, "pkt_undersize", 242 1.2.2.3 skrll "Undersized Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 243 1.2.2.2 skrll {MVXPE_MIB_PKT_FRAGMENT, 0, "pkt_fragment", 244 1.2.2.3 skrll "Fragmented Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 245 1.2.2.2 skrll {MVXPE_MIB_PKT_OVERSIZE, 0, "pkt_oversize", 246 1.2.2.3 skrll "Oversized Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 247 1.2.2.2 skrll {MVXPE_MIB_PKT_JABBER, 0, "pkt_jabber", 248 1.2.2.3 skrll "Jabber Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 249 1.2.2.2 skrll {MVXPE_MIB_MAC_RX_ERR, 0, "mac_rx_err", 250 1.2.2.3 skrll "MAC Rx Errors", MVXPE_MIBEXT_IF_IERRORS}, 251 1.2.2.2 skrll {MVXPE_MIB_MAC_CRC_ERR, 0, "mac_crc_err", 252 1.2.2.3 skrll "MAC CRC Errors", MVXPE_MIBEXT_IF_IERRORS}, 253 1.2.2.2 skrll {MVXPE_MIB_MAC_COL, 0, "mac_collision", 254 1.2.2.3 skrll "MAC Collision", MVXPE_MIBEXT_IF_COLLISIONS}, 255 1.2.2.2 skrll {MVXPE_MIB_MAC_LATE_COL, 0, "mac_late_collision", 256 1.2.2.3 skrll "MAC Late Collision", MVXPE_MIBEXT_IF_OERRORS}, 257 1.2.2.2 skrll }; 258 1.2.2.2 skrll 259 1.2.2.2 skrll /* 260 1.2.2.2 skrll * autoconf(9) 261 1.2.2.2 skrll */ 262 1.2.2.2 skrll /* ARGSUSED */ 263 1.2.2.2 skrll STATIC int 264 1.2.2.2 skrll mvxpe_match(device_t parent, cfdata_t match, void *aux) 265 1.2.2.2 skrll { 266 1.2.2.2 skrll struct marvell_attach_args *mva = aux; 267 1.2.2.2 skrll bus_size_t pv_off; 268 1.2.2.2 skrll uint32_t pv; 269 1.2.2.2 skrll 270 1.2.2.2 skrll if (strcmp(mva->mva_name, match->cf_name) != 0) 271 1.2.2.2 skrll return 0; 272 1.2.2.2 skrll if (mva->mva_offset == MVA_OFFSET_DEFAULT) 273 1.2.2.2 skrll return 0; 274 1.2.2.2 skrll 275 1.2.2.2 skrll /* check port version */ 276 1.2.2.2 skrll pv_off = mva->mva_offset + MVXPE_PV; 277 1.2.2.2 skrll pv = bus_space_read_4(mva->mva_iot, mva->mva_ioh, pv_off); 278 1.2.2.2 skrll if (MVXPE_PV_GET_VERSION(pv) < 0x10) 279 1.2.2.2 skrll return 0; /* old version is not supported */ 280 1.2.2.2 skrll 281 1.2.2.2 skrll return 1; 282 1.2.2.2 skrll } 283 1.2.2.2 skrll 284 1.2.2.2 skrll /* ARGSUSED */ 285 1.2.2.2 skrll STATIC void 286 1.2.2.2 skrll mvxpe_attach(device_t parent, device_t self, void *aux) 287 1.2.2.2 skrll { 288 1.2.2.2 skrll struct mvxpe_softc *sc = device_private(self); 289 1.2.2.2 skrll struct mii_softc *mii; 290 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 291 1.2.2.2 skrll struct marvell_attach_args *mva = aux; 292 1.2.2.2 skrll prop_dictionary_t dict; 293 1.2.2.2 skrll prop_data_t enaddrp = NULL; 294 1.2.2.2 skrll uint32_t phyaddr, maddrh, maddrl; 295 1.2.2.2 skrll uint8_t enaddr[ETHER_ADDR_LEN]; 296 1.2.2.2 skrll int q; 297 1.2.2.2 skrll 298 1.2.2.2 skrll aprint_naive("\n"); 299 1.2.2.2 skrll aprint_normal(": Marvell ARMADA GbE Controller\n"); 300 1.2.2.2 skrll memset(sc, 0, sizeof(*sc)); 301 1.2.2.2 skrll sc->sc_dev = self; 302 1.2.2.2 skrll sc->sc_port = mva->mva_unit; 303 1.2.2.2 skrll sc->sc_iot = mva->mva_iot; 304 1.2.2.2 skrll sc->sc_dmat = mva->mva_dmat; 305 1.2.2.2 skrll mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 306 1.2.2.2 skrll callout_init(&sc->sc_tick_ch, 0); 307 1.2.2.2 skrll callout_setfunc(&sc->sc_tick_ch, mvxpe_tick, sc); 308 1.2.2.2 skrll 309 1.2.2.2 skrll /* 310 1.2.2.2 skrll * BUS space 311 1.2.2.2 skrll */ 312 1.2.2.2 skrll if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 313 1.2.2.2 skrll mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 314 1.2.2.2 skrll aprint_error_dev(self, "Cannot map registers\n"); 315 1.2.2.2 skrll goto fail; 316 1.2.2.2 skrll } 317 1.2.2.2 skrll if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 318 1.2.2.2 skrll mva->mva_offset + MVXPE_PORTMIB_BASE, MVXPE_PORTMIB_SIZE, 319 1.2.2.2 skrll &sc->sc_mibh)) { 320 1.2.2.2 skrll aprint_error_dev(self, 321 1.2.2.2 skrll "Cannot map destination address filter registers\n"); 322 1.2.2.2 skrll goto fail; 323 1.2.2.2 skrll } 324 1.2.2.2 skrll sc->sc_version = MVXPE_READ(sc, MVXPE_PV); 325 1.2.2.2 skrll aprint_normal_dev(self, "Port Version %#x\n", sc->sc_version); 326 1.2.2.2 skrll 327 1.2.2.2 skrll /* 328 1.2.2.2 skrll * Buffer Manager(BM) subsystem. 329 1.2.2.2 skrll */ 330 1.2.2.2 skrll sc->sc_bm = mvxpbm_device(mva); 331 1.2.2.2 skrll if (sc->sc_bm == NULL) { 332 1.2.2.2 skrll aprint_error_dev(self, "no Buffer Manager.\n"); 333 1.2.2.2 skrll goto fail; 334 1.2.2.2 skrll } 335 1.2.2.2 skrll aprint_normal_dev(self, 336 1.2.2.2 skrll "Using Buffer Manager: %s\n", mvxpbm_xname(sc->sc_bm)); 337 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 338 1.2.2.2 skrll "%zu kbytes managed buffer, %zu bytes * %u entries allocated.\n", 339 1.2.2.2 skrll mvxpbm_buf_size(sc->sc_bm) / 1024, 340 1.2.2.2 skrll mvxpbm_chunk_size(sc->sc_bm), mvxpbm_chunk_count(sc->sc_bm)); 341 1.2.2.2 skrll 342 1.2.2.2 skrll /* 343 1.2.2.2 skrll * make sure DMA engines are in reset state 344 1.2.2.2 skrll */ 345 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 346 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 347 1.2.2.2 skrll 348 1.2.2.2 skrll /* 349 1.2.2.2 skrll * Address decoding window 350 1.2.2.2 skrll */ 351 1.2.2.2 skrll mvxpe_wininit(sc, mva->mva_tags); 352 1.2.2.2 skrll 353 1.2.2.2 skrll /* 354 1.2.2.2 skrll * MAC address 355 1.2.2.2 skrll */ 356 1.2.2.2 skrll dict = device_properties(self); 357 1.2.2.2 skrll if (dict) 358 1.2.2.2 skrll enaddrp = prop_dictionary_get(dict, "mac-address"); 359 1.2.2.2 skrll if (enaddrp) { 360 1.2.2.2 skrll memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN); 361 1.2.2.2 skrll maddrh = enaddr[0] << 24; 362 1.2.2.2 skrll maddrh |= enaddr[1] << 16; 363 1.2.2.2 skrll maddrh |= enaddr[2] << 8; 364 1.2.2.2 skrll maddrh |= enaddr[3]; 365 1.2.2.2 skrll maddrl = enaddr[4] << 8; 366 1.2.2.2 skrll maddrl |= enaddr[5]; 367 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_MACAH, maddrh); 368 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_MACAL, maddrl); 369 1.2.2.2 skrll } 370 1.2.2.2 skrll else { 371 1.2.2.2 skrll /* 372 1.2.2.2 skrll * even if enaddr is not found in dictionary, 373 1.2.2.2 skrll * the port may be initialized by IPL program such as U-BOOT. 374 1.2.2.2 skrll */ 375 1.2.2.2 skrll maddrh = MVXPE_READ(sc, MVXPE_MACAH); 376 1.2.2.2 skrll maddrl = MVXPE_READ(sc, MVXPE_MACAL); 377 1.2.2.2 skrll if ((maddrh | maddrl) == 0) { 378 1.2.2.2 skrll aprint_error_dev(self, "No Ethernet address\n"); 379 1.2.2.2 skrll return; 380 1.2.2.2 skrll } 381 1.2.2.2 skrll } 382 1.2.2.2 skrll sc->sc_enaddr[0] = maddrh >> 24; 383 1.2.2.2 skrll sc->sc_enaddr[1] = maddrh >> 16; 384 1.2.2.2 skrll sc->sc_enaddr[2] = maddrh >> 8; 385 1.2.2.2 skrll sc->sc_enaddr[3] = maddrh >> 0; 386 1.2.2.2 skrll sc->sc_enaddr[4] = maddrl >> 8; 387 1.2.2.2 skrll sc->sc_enaddr[5] = maddrl >> 0; 388 1.2.2.2 skrll aprint_normal_dev(self, "Ethernet address %s\n", 389 1.2.2.2 skrll ether_sprintf(sc->sc_enaddr)); 390 1.2.2.2 skrll 391 1.2.2.2 skrll /* 392 1.2.2.2 skrll * Register interrupt handlers 393 1.2.2.2 skrll * XXX: handle Ethernet unit intr. and Error intr. 394 1.2.2.2 skrll */ 395 1.2.2.2 skrll mvxpe_disable_intr(sc); 396 1.2.2.2 skrll marvell_intr_establish(mva->mva_irq, IPL_NET, mvxpe_rxtxth_intr, sc); 397 1.2.2.2 skrll 398 1.2.2.2 skrll /* 399 1.2.2.2 skrll * MIB buffer allocation 400 1.2.2.2 skrll */ 401 1.2.2.2 skrll sc->sc_sysctl_mib_size = 402 1.2.2.2 skrll __arraycount(mvxpe_mib_list) * sizeof(struct mvxpe_sysctl_mib); 403 1.2.2.2 skrll sc->sc_sysctl_mib = kmem_alloc(sc->sc_sysctl_mib_size, KM_NOSLEEP); 404 1.2.2.2 skrll if (sc->sc_sysctl_mib == NULL) 405 1.2.2.2 skrll goto fail; 406 1.2.2.2 skrll memset(sc->sc_sysctl_mib, 0, sc->sc_sysctl_mib_size); 407 1.2.2.2 skrll 408 1.2.2.2 skrll /* 409 1.2.2.2 skrll * Device DMA Buffer allocation 410 1.2.2.2 skrll */ 411 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 412 1.2.2.2 skrll if (mvxpe_ring_alloc_queue(sc, q) != 0) 413 1.2.2.2 skrll goto fail; 414 1.2.2.2 skrll mvxpe_ring_init_queue(sc, q); 415 1.2.2.2 skrll } 416 1.2.2.2 skrll 417 1.2.2.2 skrll /* 418 1.2.2.2 skrll * We can support 802.1Q VLAN-sized frames and jumbo 419 1.2.2.2 skrll * Ethernet frames. 420 1.2.2.2 skrll */ 421 1.2.2.2 skrll sc->sc_ethercom.ec_capabilities |= 422 1.2.2.2 skrll ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 423 1.2.2.2 skrll ifp->if_softc = sc; 424 1.2.2.2 skrll ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 425 1.2.2.2 skrll ifp->if_start = mvxpe_start; 426 1.2.2.2 skrll ifp->if_ioctl = mvxpe_ioctl; 427 1.2.2.2 skrll ifp->if_init = mvxpe_init; 428 1.2.2.2 skrll ifp->if_stop = mvxpe_stop; 429 1.2.2.2 skrll ifp->if_watchdog = mvxpe_watchdog; 430 1.2.2.2 skrll 431 1.2.2.2 skrll /* 432 1.2.2.2 skrll * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 433 1.2.2.2 skrll */ 434 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx; 435 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx; 436 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 437 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 438 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx; 439 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx; 440 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx; 441 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Rx; 442 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Tx; 443 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Rx; 444 1.2.2.2 skrll 445 1.2.2.2 skrll /* 446 1.2.2.2 skrll * Initialize struct ifnet 447 1.2.2.2 skrll */ 448 1.2.2.2 skrll IFQ_SET_MAXLEN(&ifp->if_snd, max(MVXPE_TX_RING_CNT - 1, IFQ_MAXLEN)); 449 1.2.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 450 1.2.2.2 skrll strlcpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname)); 451 1.2.2.2 skrll 452 1.2.2.2 skrll /* 453 1.2.2.2 skrll * Enable DMA engines and Initiazlie Device Regisers. 454 1.2.2.2 skrll */ 455 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 456 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 457 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 458 1.2.2.2 skrll mvxpe_sc_lock(sc); /* XXX */ 459 1.2.2.2 skrll mvxpe_filter_setup(sc); 460 1.2.2.2 skrll mvxpe_sc_unlock(sc); 461 1.2.2.2 skrll mvxpe_initreg(ifp); 462 1.2.2.2 skrll 463 1.2.2.2 skrll /* 464 1.2.2.2 skrll * Now MAC is working, setup MII. 465 1.2.2.2 skrll */ 466 1.2.2.2 skrll if (mii_init == 0) { 467 1.2.2.2 skrll /* 468 1.2.2.2 skrll * MII bus is shared by all MACs and all PHYs in SoC. 469 1.2.2.2 skrll * serializing the bus access should be safe. 470 1.2.2.2 skrll */ 471 1.2.2.2 skrll mutex_init(&mii_mutex, MUTEX_DEFAULT, IPL_NET); 472 1.2.2.2 skrll mii_init = 1; 473 1.2.2.2 skrll } 474 1.2.2.2 skrll sc->sc_mii.mii_ifp = ifp; 475 1.2.2.2 skrll sc->sc_mii.mii_readreg = mvxpe_miibus_readreg; 476 1.2.2.2 skrll sc->sc_mii.mii_writereg = mvxpe_miibus_writereg; 477 1.2.2.2 skrll sc->sc_mii.mii_statchg = mvxpe_miibus_statchg; 478 1.2.2.2 skrll 479 1.2.2.2 skrll sc->sc_ethercom.ec_mii = &sc->sc_mii; 480 1.2.2.2 skrll ifmedia_init(&sc->sc_mii.mii_media, 0, 481 1.2.2.2 skrll mvxpe_mediachange, mvxpe_mediastatus); 482 1.2.2.2 skrll /* 483 1.2.2.2 skrll * XXX: phy addressing highly depends on Board Design. 484 1.2.2.2 skrll * we assume phyaddress == MAC unit number here, 485 1.2.2.2 skrll * but some boards may not. 486 1.2.2.2 skrll */ 487 1.2.2.2 skrll mii_attach(self, &sc->sc_mii, 0xffffffff, 488 1.2.2.2 skrll MII_PHY_ANY, sc->sc_dev->dv_unit, 0); 489 1.2.2.2 skrll mii = LIST_FIRST(&sc->sc_mii.mii_phys); 490 1.2.2.2 skrll if (mii == NULL) { 491 1.2.2.2 skrll aprint_error_dev(self, "no PHY found!\n"); 492 1.2.2.2 skrll ifmedia_add(&sc->sc_mii.mii_media, 493 1.2.2.2 skrll IFM_ETHER|IFM_MANUAL, 0, NULL); 494 1.2.2.2 skrll ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 495 1.2.2.2 skrll } else { 496 1.2.2.2 skrll ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 497 1.2.2.2 skrll phyaddr = MVXPE_PHYADDR_PHYAD(mii->mii_phy); 498 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PHYADDR, phyaddr); 499 1.2.2.2 skrll DPRINTSC(sc, 1, "PHYADDR: %#x\n", MVXPE_READ(sc, MVXPE_PHYADDR)); 500 1.2.2.2 skrll } 501 1.2.2.2 skrll 502 1.2.2.2 skrll /* 503 1.2.2.2 skrll * Call MI attach routines. 504 1.2.2.2 skrll */ 505 1.2.2.2 skrll if_attach(ifp); 506 1.2.2.2 skrll 507 1.2.2.2 skrll ether_ifattach(ifp, sc->sc_enaddr); 508 1.2.2.2 skrll ether_set_ifflags_cb(&sc->sc_ethercom, mvxpe_ifflags_cb); 509 1.2.2.2 skrll 510 1.2.2.2 skrll sysctl_mvxpe_init(sc); 511 1.2.2.2 skrll mvxpe_evcnt_attach(sc); 512 1.2.2.2 skrll rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 513 1.2.2.2 skrll RND_TYPE_NET, RND_FLAG_DEFAULT); 514 1.2.2.2 skrll 515 1.2.2.2 skrll return; 516 1.2.2.2 skrll 517 1.2.2.2 skrll fail: 518 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) 519 1.2.2.2 skrll mvxpe_ring_dealloc_queue(sc, q); 520 1.2.2.2 skrll if (sc->sc_sysctl_mib) 521 1.2.2.2 skrll kmem_free(sc->sc_sysctl_mib, sc->sc_sysctl_mib_size); 522 1.2.2.2 skrll 523 1.2.2.2 skrll return; 524 1.2.2.2 skrll } 525 1.2.2.2 skrll 526 1.2.2.2 skrll STATIC int 527 1.2.2.2 skrll mvxpe_evcnt_attach(struct mvxpe_softc *sc) 528 1.2.2.2 skrll { 529 1.2.2.2 skrll #ifdef MVXPE_EVENT_COUNTERS 530 1.2.2.2 skrll int q; 531 1.2.2.2 skrll 532 1.2.2.2 skrll /* Master Interrupt Handler */ 533 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtxth, EVCNT_TYPE_INTR, 534 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTxTH Intr."); 535 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtx, EVCNT_TYPE_INTR, 536 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx Intr."); 537 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_i_misc, EVCNT_TYPE_INTR, 538 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC Intr."); 539 1.2.2.2 skrll 540 1.2.2.2 skrll /* RXTXTH Interrupt */ 541 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtxth_txerr, EVCNT_TYPE_INTR, 542 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTxTH Tx error summary"); 543 1.2.2.2 skrll 544 1.2.2.2 skrll /* MISC Interrupt */ 545 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_phystatuschng, EVCNT_TYPE_INTR, 546 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC phy status changed"); 547 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_linkchange, EVCNT_TYPE_INTR, 548 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC link status changed"); 549 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_iae, EVCNT_TYPE_INTR, 550 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC internal address error"); 551 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxoverrun, EVCNT_TYPE_INTR, 552 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC Rx FIFO overrun"); 553 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxcrc, EVCNT_TYPE_INTR, 554 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC Rx CRC error"); 555 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxlargepacket, EVCNT_TYPE_INTR, 556 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC Rx too large frame"); 557 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txunderrun, EVCNT_TYPE_INTR, 558 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC Tx FIFO underrun"); 559 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_prbserr, EVCNT_TYPE_INTR, 560 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC SERDES loopback test err"); 561 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_srse, EVCNT_TYPE_INTR, 562 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC SERDES sync error"); 563 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txreq, EVCNT_TYPE_INTR, 564 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "MISC Tx resource erorr"); 565 1.2.2.2 skrll 566 1.2.2.2 skrll /* RxTx Interrupt */ 567 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rreq, EVCNT_TYPE_INTR, 568 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx Rx resource erorr"); 569 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rpq, EVCNT_TYPE_INTR, 570 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx Rx pakcet"); 571 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_tbrq, EVCNT_TYPE_INTR, 572 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx Tx complete"); 573 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rxtxth, EVCNT_TYPE_INTR, 574 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx RxTxTH summary"); 575 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_txerr, EVCNT_TYPE_INTR, 576 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx Tx error summary"); 577 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_misc, EVCNT_TYPE_INTR, 578 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "RxTx MISC summary"); 579 1.2.2.2 skrll 580 1.2.2.2 skrll /* Link */ 581 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_link_up, EVCNT_TYPE_MISC, 582 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "link up"); 583 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_link_down, EVCNT_TYPE_MISC, 584 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "link down"); 585 1.2.2.2 skrll 586 1.2.2.2 skrll /* Rx Descriptor */ 587 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_ce, EVCNT_TYPE_MISC, 588 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx CRC error counter"); 589 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_or, EVCNT_TYPE_MISC, 590 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx FIFO overrun counter"); 591 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_mf, EVCNT_TYPE_MISC, 592 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx too large frame counter"); 593 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_re, EVCNT_TYPE_MISC, 594 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx resource error counter"); 595 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_scat, EVCNT_TYPE_MISC, 596 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx unexpected scatter bufs"); 597 1.2.2.2 skrll 598 1.2.2.2 skrll /* Tx Descriptor */ 599 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_txd_lc, EVCNT_TYPE_MISC, 600 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx late collision counter"); 601 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_txd_rl, EVCNT_TYPE_MISC, 602 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx excess. collision counter"); 603 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_txd_ur, EVCNT_TYPE_MISC, 604 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx FIFO underrun counter"); 605 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_txd_oth, EVCNT_TYPE_MISC, 606 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx unkonwn erorr counter"); 607 1.2.2.2 skrll 608 1.2.2.2 skrll /* Status Registers */ 609 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pdfc, EVCNT_TYPE_MISC, 610 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx discard counter"); 611 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pofc, EVCNT_TYPE_MISC, 612 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Rx overrun counter"); 613 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txbadfcs, EVCNT_TYPE_MISC, 614 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx bad FCS counter"); 615 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txdropped, EVCNT_TYPE_MISC, 616 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx dorpped counter"); 617 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_reg_lpic, EVCNT_TYPE_MISC, 618 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "LP_IDLE counter"); 619 1.2.2.2 skrll 620 1.2.2.2 skrll /* Device Driver Errors */ 621 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_drv_wdogsoft, EVCNT_TYPE_MISC, 622 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "watchdog timer expired"); 623 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txerr, EVCNT_TYPE_MISC, 624 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), "Tx descriptor alloc failed"); 625 1.2.2.2 skrll #define MVXPE_QUEUE_DESC(q) "Rx success in queue " # q 626 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 627 1.2.2.2 skrll static const char *rxq_desc[] = { 628 1.2.2.2 skrll MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 629 1.2.2.2 skrll MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 630 1.2.2.2 skrll MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 631 1.2.2.2 skrll MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 632 1.2.2.2 skrll }; 633 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxq[q], EVCNT_TYPE_MISC, 634 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), rxq_desc[q]); 635 1.2.2.2 skrll } 636 1.2.2.2 skrll #undef MVXPE_QUEUE_DESC 637 1.2.2.2 skrll #define MVXPE_QUEUE_DESC(q) "Tx success in queue " # q 638 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 639 1.2.2.2 skrll static const char *txq_desc[] = { 640 1.2.2.2 skrll MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 641 1.2.2.2 skrll MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 642 1.2.2.2 skrll MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 643 1.2.2.2 skrll MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 644 1.2.2.2 skrll }; 645 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txq[q], EVCNT_TYPE_MISC, 646 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), txq_desc[q]); 647 1.2.2.2 skrll } 648 1.2.2.2 skrll #undef MVXPE_QUEUE_DESC 649 1.2.2.2 skrll #define MVXPE_QUEUE_DESC(q) "Rx error in queue " # q 650 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 651 1.2.2.2 skrll static const char *rxqe_desc[] = { 652 1.2.2.2 skrll MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 653 1.2.2.2 skrll MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 654 1.2.2.2 skrll MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 655 1.2.2.2 skrll MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 656 1.2.2.2 skrll }; 657 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxqe[q], EVCNT_TYPE_MISC, 658 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), rxqe_desc[q]); 659 1.2.2.2 skrll } 660 1.2.2.2 skrll #undef MVXPE_QUEUE_DESC 661 1.2.2.2 skrll #define MVXPE_QUEUE_DESC(q) "Tx error in queue " # q 662 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 663 1.2.2.2 skrll static const char *txqe_desc[] = { 664 1.2.2.2 skrll MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 665 1.2.2.2 skrll MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 666 1.2.2.2 skrll MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 667 1.2.2.2 skrll MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 668 1.2.2.2 skrll }; 669 1.2.2.2 skrll evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txqe[q], EVCNT_TYPE_MISC, 670 1.2.2.2 skrll NULL, device_xname(sc->sc_dev), txqe_desc[q]); 671 1.2.2.2 skrll } 672 1.2.2.2 skrll #undef MVXPE_QUEUE_DESC 673 1.2.2.2 skrll 674 1.2.2.2 skrll #endif /* MVXPE_EVENT_COUNTERS */ 675 1.2.2.2 skrll return 0; 676 1.2.2.2 skrll } 677 1.2.2.2 skrll 678 1.2.2.2 skrll STATIC void 679 1.2.2.2 skrll mvxpe_sc_lock(struct mvxpe_softc *sc) 680 1.2.2.2 skrll { 681 1.2.2.2 skrll mutex_enter(&sc->sc_mtx); 682 1.2.2.2 skrll } 683 1.2.2.2 skrll 684 1.2.2.2 skrll STATIC void 685 1.2.2.2 skrll mvxpe_sc_unlock(struct mvxpe_softc *sc) 686 1.2.2.2 skrll { 687 1.2.2.2 skrll mutex_exit(&sc->sc_mtx); 688 1.2.2.2 skrll } 689 1.2.2.2 skrll 690 1.2.2.2 skrll /* 691 1.2.2.2 skrll * MII 692 1.2.2.2 skrll */ 693 1.2.2.2 skrll STATIC int 694 1.2.2.2 skrll mvxpe_miibus_readreg(device_t dev, int phy, int reg) 695 1.2.2.2 skrll { 696 1.2.2.2 skrll struct mvxpe_softc *sc = device_private(dev); 697 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 698 1.2.2.2 skrll uint32_t smi, val; 699 1.2.2.2 skrll int i; 700 1.2.2.2 skrll 701 1.2.2.2 skrll mutex_enter(&mii_mutex); 702 1.2.2.2 skrll 703 1.2.2.2 skrll for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 704 1.2.2.2 skrll DELAY(1); 705 1.2.2.2 skrll if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 706 1.2.2.2 skrll break; 707 1.2.2.2 skrll } 708 1.2.2.2 skrll if (i == MVXPE_PHY_TIMEOUT) { 709 1.2.2.2 skrll aprint_error_ifnet(ifp, "SMI busy timeout\n"); 710 1.2.2.2 skrll mutex_exit(&mii_mutex); 711 1.2.2.2 skrll return -1; 712 1.2.2.2 skrll } 713 1.2.2.2 skrll 714 1.2.2.2 skrll smi = 715 1.2.2.2 skrll MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | MVXPE_SMI_OPCODE_READ; 716 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_SMI, smi); 717 1.2.2.2 skrll 718 1.2.2.2 skrll for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 719 1.2.2.2 skrll DELAY(1); 720 1.2.2.2 skrll smi = MVXPE_READ(sc, MVXPE_SMI); 721 1.2.2.2 skrll if (smi & MVXPE_SMI_READVALID) 722 1.2.2.2 skrll break; 723 1.2.2.2 skrll } 724 1.2.2.2 skrll 725 1.2.2.2 skrll mutex_exit(&mii_mutex); 726 1.2.2.2 skrll 727 1.2.2.2 skrll DPRINTDEV(dev, 9, "i=%d, timeout=%d\n", i, MVXPE_PHY_TIMEOUT); 728 1.2.2.2 skrll 729 1.2.2.2 skrll val = smi & MVXPE_SMI_DATA_MASK; 730 1.2.2.2 skrll 731 1.2.2.2 skrll DPRINTDEV(dev, 9, "phy=%d, reg=%#x, val=%#x\n", phy, reg, val); 732 1.2.2.2 skrll 733 1.2.2.2 skrll return val; 734 1.2.2.2 skrll } 735 1.2.2.2 skrll 736 1.2.2.2 skrll STATIC void 737 1.2.2.2 skrll mvxpe_miibus_writereg(device_t dev, int phy, int reg, int val) 738 1.2.2.2 skrll { 739 1.2.2.2 skrll struct mvxpe_softc *sc = device_private(dev); 740 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 741 1.2.2.2 skrll uint32_t smi; 742 1.2.2.2 skrll int i; 743 1.2.2.2 skrll 744 1.2.2.2 skrll DPRINTDEV(dev, 9, "phy=%d reg=%#x val=%#x\n", phy, reg, val); 745 1.2.2.2 skrll 746 1.2.2.2 skrll mutex_enter(&mii_mutex); 747 1.2.2.2 skrll 748 1.2.2.2 skrll for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 749 1.2.2.2 skrll DELAY(1); 750 1.2.2.2 skrll if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 751 1.2.2.2 skrll break; 752 1.2.2.2 skrll } 753 1.2.2.2 skrll if (i == MVXPE_PHY_TIMEOUT) { 754 1.2.2.2 skrll aprint_error_ifnet(ifp, "SMI busy timeout\n"); 755 1.2.2.2 skrll mutex_exit(&mii_mutex); 756 1.2.2.2 skrll return; 757 1.2.2.2 skrll } 758 1.2.2.2 skrll 759 1.2.2.2 skrll smi = MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | 760 1.2.2.2 skrll MVXPE_SMI_OPCODE_WRITE | (val & MVXPE_SMI_DATA_MASK); 761 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_SMI, smi); 762 1.2.2.2 skrll 763 1.2.2.2 skrll for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 764 1.2.2.2 skrll DELAY(1); 765 1.2.2.2 skrll if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 766 1.2.2.2 skrll break; 767 1.2.2.2 skrll } 768 1.2.2.2 skrll 769 1.2.2.2 skrll mutex_exit(&mii_mutex); 770 1.2.2.2 skrll 771 1.2.2.2 skrll if (i == MVXPE_PHY_TIMEOUT) 772 1.2.2.2 skrll aprint_error_ifnet(ifp, "phy write timed out\n"); 773 1.2.2.2 skrll } 774 1.2.2.2 skrll 775 1.2.2.2 skrll STATIC void 776 1.2.2.2 skrll mvxpe_miibus_statchg(struct ifnet *ifp) 777 1.2.2.2 skrll { 778 1.2.2.2 skrll 779 1.2.2.2 skrll /* nothing to do */ 780 1.2.2.2 skrll } 781 1.2.2.2 skrll 782 1.2.2.2 skrll /* 783 1.2.2.2 skrll * Address Decoding Window 784 1.2.2.2 skrll */ 785 1.2.2.2 skrll STATIC void 786 1.2.2.2 skrll mvxpe_wininit(struct mvxpe_softc *sc, enum marvell_tags *tags) 787 1.2.2.2 skrll { 788 1.2.2.2 skrll device_t pdev = device_parent(sc->sc_dev); 789 1.2.2.2 skrll uint64_t base; 790 1.2.2.2 skrll uint32_t en, ac, size; 791 1.2.2.2 skrll int window, target, attr, rv, i; 792 1.2.2.2 skrll 793 1.2.2.2 skrll /* First disable all address decode windows */ 794 1.2.2.2 skrll en = MVXPE_BARE_EN_MASK; 795 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_BARE, en); 796 1.2.2.2 skrll 797 1.2.2.2 skrll ac = 0; 798 1.2.2.2 skrll for (window = 0, i = 0; 799 1.2.2.2 skrll tags[i] != MARVELL_TAG_UNDEFINED && window < MVXPE_NWINDOW; i++) { 800 1.2.2.2 skrll rv = marvell_winparams_by_tag(pdev, tags[i], 801 1.2.2.2 skrll &target, &attr, &base, &size); 802 1.2.2.2 skrll if (rv != 0 || size == 0) 803 1.2.2.2 skrll continue; 804 1.2.2.2 skrll 805 1.2.2.2 skrll if (base > 0xffffffffULL) { 806 1.2.2.2 skrll if (window >= MVXPE_NREMAP) { 807 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 808 1.2.2.2 skrll "can't remap window %d\n", window); 809 1.2.2.2 skrll continue; 810 1.2.2.2 skrll } 811 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_HA(window), 812 1.2.2.2 skrll (base >> 32) & 0xffffffff); 813 1.2.2.2 skrll } 814 1.2.2.2 skrll 815 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_BASEADDR(window), 816 1.2.2.2 skrll MVXPE_BASEADDR_TARGET(target) | 817 1.2.2.2 skrll MVXPE_BASEADDR_ATTR(attr) | 818 1.2.2.2 skrll MVXPE_BASEADDR_BASE(base)); 819 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_S(window), MVXPE_S_SIZE(size)); 820 1.2.2.2 skrll 821 1.2.2.2 skrll DPRINTSC(sc, 1, "Window %d Base 0x%016llx: Size 0x%08x\n", 822 1.2.2.2 skrll window, base, size); 823 1.2.2.2 skrll 824 1.2.2.2 skrll en &= ~(1 << window); 825 1.2.2.2 skrll /* set full access (r/w) */ 826 1.2.2.2 skrll ac |= MVXPE_EPAP_EPAR(window, MVXPE_EPAP_AC_FA); 827 1.2.2.2 skrll window++; 828 1.2.2.2 skrll } 829 1.2.2.2 skrll /* allow to access decode window */ 830 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_EPAP, ac); 831 1.2.2.2 skrll 832 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_BARE, en); 833 1.2.2.2 skrll } 834 1.2.2.2 skrll 835 1.2.2.2 skrll /* 836 1.2.2.2 skrll * Device Register Initialization 837 1.2.2.2 skrll * reset device registers to device driver default value. 838 1.2.2.2 skrll * the device is not enabled here. 839 1.2.2.2 skrll */ 840 1.2.2.2 skrll STATIC int 841 1.2.2.2 skrll mvxpe_initreg(struct ifnet *ifp) 842 1.2.2.2 skrll { 843 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 844 1.2.2.2 skrll int serdes = 0; 845 1.2.2.2 skrll uint32_t reg; 846 1.2.2.2 skrll int q, i; 847 1.2.2.2 skrll 848 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "initializing device register\n"); 849 1.2.2.2 skrll 850 1.2.2.2 skrll /* Init TX/RX Queue Registers */ 851 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 852 1.2.2.2 skrll mvxpe_rx_lockq(sc, q); 853 1.2.2.2 skrll if (mvxpe_rx_queue_init(ifp, q) != 0) { 854 1.2.2.2 skrll aprint_error_ifnet(ifp, 855 1.2.2.2 skrll "initialization failed: cannot initialize queue\n"); 856 1.2.2.2 skrll mvxpe_rx_unlockq(sc, q); 857 1.2.2.2 skrll return ENOBUFS; 858 1.2.2.2 skrll } 859 1.2.2.2 skrll mvxpe_rx_unlockq(sc, q); 860 1.2.2.2 skrll 861 1.2.2.2 skrll mvxpe_tx_lockq(sc, q); 862 1.2.2.2 skrll if (mvxpe_tx_queue_init(ifp, q) != 0) { 863 1.2.2.2 skrll aprint_error_ifnet(ifp, 864 1.2.2.2 skrll "initialization failed: cannot initialize queue\n"); 865 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 866 1.2.2.2 skrll return ENOBUFS; 867 1.2.2.2 skrll } 868 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 869 1.2.2.2 skrll } 870 1.2.2.2 skrll 871 1.2.2.2 skrll /* Tx MTU Limit */ 872 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_TXMTU, MVXPE_MTU); 873 1.2.2.2 skrll 874 1.2.2.2 skrll /* Check SGMII or SERDES(asume IPL/U-BOOT initialize this) */ 875 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PMACC0); 876 1.2.2.2 skrll if ((reg & MVXPE_PMACC0_PORTTYPE) != 0) 877 1.2.2.2 skrll serdes = 1; 878 1.2.2.2 skrll 879 1.2.2.2 skrll /* Ethernet Unit Control */ 880 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_EUC); 881 1.2.2.2 skrll reg |= MVXPE_EUC_POLLING; 882 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_EUC, reg); 883 1.2.2.2 skrll 884 1.2.2.2 skrll /* Auto Negotiation */ 885 1.2.2.2 skrll reg = MVXPE_PANC_MUSTSET; /* must write 0x1 */ 886 1.2.2.2 skrll reg |= MVXPE_PANC_FORCELINKFAIL;/* force link state down */ 887 1.2.2.2 skrll reg |= MVXPE_PANC_ANSPEEDEN; /* interface speed negotiation */ 888 1.2.2.2 skrll reg |= MVXPE_PANC_ANDUPLEXEN; /* negotiate duplex mode */ 889 1.2.2.2 skrll if (serdes) { 890 1.2.2.2 skrll reg |= MVXPE_PANC_INBANDANEN; /* In Band negotiation */ 891 1.2.2.2 skrll reg |= MVXPE_PANC_INBANDANBYPASSEN; /* bypass negotiation */ 892 1.2.2.2 skrll reg |= MVXPE_PANC_SETFULLDX; /* set full-duplex on failure */ 893 1.2.2.2 skrll } 894 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PANC, reg); 895 1.2.2.2 skrll 896 1.2.2.2 skrll /* EEE: Low Power Idle */ 897 1.2.2.2 skrll reg = MVXPE_LPIC0_LILIMIT(MVXPE_LPI_LI); 898 1.2.2.2 skrll reg |= MVXPE_LPIC0_TSLIMIT(MVXPE_LPI_TS); 899 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_LPIC0, reg); 900 1.2.2.2 skrll 901 1.2.2.2 skrll reg = MVXPE_LPIC1_TWLIMIT(MVXPE_LPI_TS); 902 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 903 1.2.2.2 skrll 904 1.2.2.2 skrll reg = MVXPE_LPIC2_MUSTSET; 905 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_LPIC2, reg); 906 1.2.2.2 skrll 907 1.2.2.2 skrll /* Port MAC Control set 0 */ 908 1.2.2.2 skrll reg = MVXPE_PMACC0_MUSTSET; /* must write 0x1 */ 909 1.2.2.2 skrll reg &= ~MVXPE_PMACC0_PORTEN; /* port is still disabled */ 910 1.2.2.2 skrll reg |= MVXPE_PMACC0_FRAMESIZELIMIT(MVXPE_MRU); 911 1.2.2.2 skrll if (serdes) 912 1.2.2.2 skrll reg |= MVXPE_PMACC0_PORTTYPE; 913 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 914 1.2.2.2 skrll 915 1.2.2.2 skrll /* Port MAC Control set 1 is only used for loop-back test */ 916 1.2.2.2 skrll 917 1.2.2.2 skrll /* Port MAC Control set 2 */ 918 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PMACC2); 919 1.2.2.2 skrll reg &= (MVXPE_PMACC2_PCSEN | MVXPE_PMACC2_RGMIIEN); 920 1.2.2.2 skrll reg |= MVXPE_PMACC2_MUSTSET; 921 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMACC2, reg); 922 1.2.2.2 skrll 923 1.2.2.2 skrll /* Port MAC Control set 3 is used for IPG tune */ 924 1.2.2.2 skrll 925 1.2.2.2 skrll /* Port MAC Control set 4 is not used */ 926 1.2.2.2 skrll 927 1.2.2.3 skrll /* Port Configuration */ 928 1.2.2.3 skrll /* Use queue 0 only */ 929 1.2.2.3 skrll reg = MVXPE_READ(sc, MVXPE_PXC); 930 1.2.2.3 skrll reg &= ~(MVXPE_PXC_RXQ_MASK | MVXPE_PXC_RXQARP_MASK | 931 1.2.2.3 skrll MVXPE_PXC_TCPQ_MASK | MVXPE_PXC_UDPQ_MASK | MVXPE_PXC_BPDUQ_MASK); 932 1.2.2.3 skrll MVXPE_WRITE(sc, MVXPE_PXC, reg); 933 1.2.2.3 skrll 934 1.2.2.2 skrll /* Port Configuration Extended: enable Tx CRC generation */ 935 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PXCX); 936 1.2.2.2 skrll reg &= ~MVXPE_PXCX_TXCRCDIS; 937 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PXCX, reg); 938 1.2.2.2 skrll 939 1.2.2.2 skrll /* clear MIB counter registers(clear by read) */ 940 1.2.2.2 skrll for (i = 0; i < __arraycount(mvxpe_mib_list); i++) 941 1.2.2.2 skrll MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum)); 942 1.2.2.2 skrll 943 1.2.2.2 skrll /* Set SDC register except IPGINT bits */ 944 1.2.2.2 skrll reg = MVXPE_SDC_RXBSZ_16_64BITWORDS; 945 1.2.2.2 skrll reg |= MVXPE_SDC_TXBSZ_16_64BITWORDS; 946 1.2.2.2 skrll reg |= MVXPE_SDC_BLMR; 947 1.2.2.2 skrll reg |= MVXPE_SDC_BLMT; 948 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_SDC, reg); 949 1.2.2.2 skrll 950 1.2.2.2 skrll return 0; 951 1.2.2.2 skrll } 952 1.2.2.2 skrll 953 1.2.2.2 skrll /* 954 1.2.2.2 skrll * Descriptor Ring Controls for each of queues 955 1.2.2.2 skrll */ 956 1.2.2.2 skrll STATIC void * 957 1.2.2.2 skrll mvxpe_dma_memalloc(struct mvxpe_softc *sc, bus_dmamap_t *map, size_t size) 958 1.2.2.2 skrll { 959 1.2.2.2 skrll bus_dma_segment_t segs; 960 1.2.2.2 skrll void *kva = NULL; 961 1.2.2.2 skrll int nsegs; 962 1.2.2.2 skrll 963 1.2.2.2 skrll /* 964 1.2.2.2 skrll * Allocate the descriptor queues. 965 1.2.2.2 skrll * struct mvxpe_ring_data contians array of descriptor per queue. 966 1.2.2.2 skrll */ 967 1.2.2.2 skrll if (bus_dmamem_alloc(sc->sc_dmat, 968 1.2.2.2 skrll size, PAGE_SIZE, 0, &segs, 1, &nsegs, BUS_DMA_NOWAIT)) { 969 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 970 1.2.2.2 skrll "can't alloc device memory (%zu bytes)\n", size); 971 1.2.2.2 skrll return NULL; 972 1.2.2.2 skrll } 973 1.2.2.2 skrll if (bus_dmamem_map(sc->sc_dmat, 974 1.2.2.2 skrll &segs, nsegs, size, &kva, BUS_DMA_NOWAIT)) { 975 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 976 1.2.2.2 skrll "can't map dma buffers (%zu bytes)\n", size); 977 1.2.2.2 skrll goto fail1; 978 1.2.2.2 skrll } 979 1.2.2.2 skrll 980 1.2.2.2 skrll if (bus_dmamap_create(sc->sc_dmat, 981 1.2.2.2 skrll size, 1, size, 0, BUS_DMA_NOWAIT, map)) { 982 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 983 1.2.2.2 skrll goto fail2; 984 1.2.2.2 skrll } 985 1.2.2.2 skrll if (bus_dmamap_load(sc->sc_dmat, 986 1.2.2.2 skrll *map, kva, size, NULL, BUS_DMA_NOWAIT)) { 987 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 988 1.2.2.2 skrll goto fail3; 989 1.2.2.2 skrll } 990 1.2.2.2 skrll memset(kva, 0, size); 991 1.2.2.2 skrll return kva; 992 1.2.2.2 skrll 993 1.2.2.2 skrll fail3: 994 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, *map); 995 1.2.2.2 skrll memset(map, 0, sizeof(*map)); 996 1.2.2.2 skrll fail2: 997 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, kva, size); 998 1.2.2.2 skrll fail1: 999 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, &segs, nsegs); 1000 1.2.2.2 skrll return NULL; 1001 1.2.2.2 skrll } 1002 1.2.2.2 skrll 1003 1.2.2.2 skrll STATIC int 1004 1.2.2.2 skrll mvxpe_ring_alloc_queue(struct mvxpe_softc *sc, int q) 1005 1.2.2.2 skrll { 1006 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1007 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1008 1.2.2.2 skrll 1009 1.2.2.2 skrll /* 1010 1.2.2.2 skrll * MVXPE_RX_RING_CNT and MVXPE_TX_RING_CNT is a hard limit of 1011 1.2.2.2 skrll * queue length. real queue length is limited by 1012 1.2.2.2 skrll * sc->sc_rx_ring[q].rx_queue_len and sc->sc_tx_ring[q].tx_queue_len. 1013 1.2.2.2 skrll * 1014 1.2.2.2 skrll * because descriptor ring reallocation needs reprogramming of 1015 1.2.2.2 skrll * DMA registers, we allocate enough descriptor for hard limit 1016 1.2.2.2 skrll * of queue length. 1017 1.2.2.2 skrll */ 1018 1.2.2.2 skrll rx->rx_descriptors = 1019 1.2.2.2 skrll mvxpe_dma_memalloc(sc, &rx->rx_descriptors_map, 1020 1.2.2.2 skrll (sizeof(struct mvxpe_rx_desc) * MVXPE_RX_RING_CNT)); 1021 1.2.2.2 skrll if (rx->rx_descriptors == NULL) 1022 1.2.2.2 skrll goto fail; 1023 1.2.2.2 skrll 1024 1.2.2.2 skrll tx->tx_descriptors = 1025 1.2.2.2 skrll mvxpe_dma_memalloc(sc, &tx->tx_descriptors_map, 1026 1.2.2.2 skrll (sizeof(struct mvxpe_tx_desc) * MVXPE_TX_RING_CNT)); 1027 1.2.2.2 skrll if (tx->tx_descriptors == NULL) 1028 1.2.2.2 skrll goto fail; 1029 1.2.2.2 skrll 1030 1.2.2.2 skrll return 0; 1031 1.2.2.2 skrll fail: 1032 1.2.2.2 skrll mvxpe_ring_dealloc_queue(sc, q); 1033 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, "DMA Ring buffer allocation failure.\n"); 1034 1.2.2.2 skrll return ENOMEM; 1035 1.2.2.2 skrll } 1036 1.2.2.2 skrll 1037 1.2.2.2 skrll STATIC void 1038 1.2.2.2 skrll mvxpe_ring_dealloc_queue(struct mvxpe_softc *sc, int q) 1039 1.2.2.2 skrll { 1040 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1041 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1042 1.2.2.2 skrll bus_dma_segment_t *segs; 1043 1.2.2.2 skrll bus_size_t size; 1044 1.2.2.2 skrll void *kva; 1045 1.2.2.2 skrll int nsegs; 1046 1.2.2.2 skrll 1047 1.2.2.2 skrll /* Rx */ 1048 1.2.2.2 skrll kva = (void *)MVXPE_RX_RING_MEM_VA(sc, q); 1049 1.2.2.2 skrll if (kva) { 1050 1.2.2.2 skrll segs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_segs; 1051 1.2.2.2 skrll nsegs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_nsegs; 1052 1.2.2.2 skrll size = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_mapsize; 1053 1.2.2.2 skrll 1054 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1055 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1056 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, kva, size); 1057 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1058 1.2.2.2 skrll } 1059 1.2.2.2 skrll 1060 1.2.2.2 skrll /* Tx */ 1061 1.2.2.2 skrll kva = (void *)MVXPE_TX_RING_MEM_VA(sc, q); 1062 1.2.2.2 skrll if (kva) { 1063 1.2.2.2 skrll segs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_segs; 1064 1.2.2.2 skrll nsegs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_nsegs; 1065 1.2.2.2 skrll size = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_mapsize; 1066 1.2.2.2 skrll 1067 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1068 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1069 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, kva, size); 1070 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1071 1.2.2.2 skrll } 1072 1.2.2.2 skrll 1073 1.2.2.2 skrll /* Clear doungling pointers all */ 1074 1.2.2.2 skrll memset(rx, 0, sizeof(*rx)); 1075 1.2.2.2 skrll memset(tx, 0, sizeof(*tx)); 1076 1.2.2.2 skrll } 1077 1.2.2.2 skrll 1078 1.2.2.2 skrll STATIC void 1079 1.2.2.2 skrll mvxpe_ring_init_queue(struct mvxpe_softc *sc, int q) 1080 1.2.2.2 skrll { 1081 1.2.2.2 skrll struct mvxpe_rx_desc *rxd = MVXPE_RX_RING_MEM_VA(sc, q); 1082 1.2.2.2 skrll struct mvxpe_tx_desc *txd = MVXPE_TX_RING_MEM_VA(sc, q); 1083 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1084 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1085 1.2.2.2 skrll static const int rx_default_queue_len[] = { 1086 1.2.2.2 skrll MVXPE_RX_QUEUE_LIMIT_0, MVXPE_RX_QUEUE_LIMIT_1, 1087 1.2.2.2 skrll MVXPE_RX_QUEUE_LIMIT_2, MVXPE_RX_QUEUE_LIMIT_3, 1088 1.2.2.2 skrll MVXPE_RX_QUEUE_LIMIT_4, MVXPE_RX_QUEUE_LIMIT_5, 1089 1.2.2.2 skrll MVXPE_RX_QUEUE_LIMIT_6, MVXPE_RX_QUEUE_LIMIT_7, 1090 1.2.2.2 skrll }; 1091 1.2.2.2 skrll static const int tx_default_queue_len[] = { 1092 1.2.2.2 skrll MVXPE_TX_QUEUE_LIMIT_0, MVXPE_TX_QUEUE_LIMIT_1, 1093 1.2.2.2 skrll MVXPE_TX_QUEUE_LIMIT_2, MVXPE_TX_QUEUE_LIMIT_3, 1094 1.2.2.2 skrll MVXPE_TX_QUEUE_LIMIT_4, MVXPE_TX_QUEUE_LIMIT_5, 1095 1.2.2.2 skrll MVXPE_TX_QUEUE_LIMIT_6, MVXPE_TX_QUEUE_LIMIT_7, 1096 1.2.2.2 skrll }; 1097 1.2.2.2 skrll extern uint32_t mvTclk; 1098 1.2.2.2 skrll int i; 1099 1.2.2.2 skrll 1100 1.2.2.2 skrll /* Rx handle */ 1101 1.2.2.2 skrll for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1102 1.2.2.2 skrll MVXPE_RX_DESC(sc, q, i) = &rxd[i]; 1103 1.2.2.2 skrll MVXPE_RX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_rx_desc) * i; 1104 1.2.2.2 skrll MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1105 1.2.2.2 skrll } 1106 1.2.2.2 skrll mutex_init(&rx->rx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1107 1.2.2.2 skrll rx->rx_dma = rx->rx_cpu = 0; 1108 1.2.2.2 skrll rx->rx_queue_len = rx_default_queue_len[q]; 1109 1.2.2.2 skrll if (rx->rx_queue_len > MVXPE_RX_RING_CNT) 1110 1.2.2.2 skrll rx->rx_queue_len = MVXPE_RX_RING_CNT; 1111 1.2.2.2 skrll rx->rx_queue_th_received = rx->rx_queue_len / MVXPE_RXTH_RATIO; 1112 1.2.2.2 skrll rx->rx_queue_th_free = rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 1113 1.2.2.2 skrll rx->rx_queue_th_time = (mvTclk / 1000) / 2; /* 0.5 [ms] */ 1114 1.2.2.2 skrll 1115 1.2.2.2 skrll /* Tx handle */ 1116 1.2.2.2 skrll for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1117 1.2.2.2 skrll MVXPE_TX_DESC(sc, q, i) = &txd[i]; 1118 1.2.2.2 skrll MVXPE_TX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_tx_desc) * i; 1119 1.2.2.2 skrll MVXPE_TX_MBUF(sc, q, i) = NULL; 1120 1.2.2.2 skrll /* Tx handle needs DMA map for busdma_load_mbuf() */ 1121 1.2.2.2 skrll if (bus_dmamap_create(sc->sc_dmat, 1122 1.2.2.2 skrll mvxpbm_chunk_size(sc->sc_bm), 1123 1.2.2.2 skrll MVXPE_TX_SEGLIMIT, mvxpbm_chunk_size(sc->sc_bm), 0, 1124 1.2.2.2 skrll BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 1125 1.2.2.2 skrll &MVXPE_TX_MAP(sc, q, i))) { 1126 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 1127 1.2.2.2 skrll "can't create dma map (tx ring %d)\n", i); 1128 1.2.2.2 skrll } 1129 1.2.2.2 skrll } 1130 1.2.2.2 skrll mutex_init(&tx->tx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1131 1.2.2.2 skrll tx->tx_dma = tx->tx_cpu = 0; 1132 1.2.2.2 skrll tx->tx_queue_len = tx_default_queue_len[q]; 1133 1.2.2.2 skrll if (tx->tx_queue_len > MVXPE_TX_RING_CNT) 1134 1.2.2.2 skrll tx->tx_queue_len = MVXPE_TX_RING_CNT; 1135 1.2.2.2 skrll tx->tx_used = 0; 1136 1.2.2.2 skrll tx->tx_queue_th_free = tx->tx_queue_len / MVXPE_TXTH_RATIO; 1137 1.2.2.2 skrll } 1138 1.2.2.2 skrll 1139 1.2.2.2 skrll STATIC void 1140 1.2.2.2 skrll mvxpe_ring_flush_queue(struct mvxpe_softc *sc, int q) 1141 1.2.2.2 skrll { 1142 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1143 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1144 1.2.2.2 skrll int i; 1145 1.2.2.2 skrll 1146 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 1147 1.2.2.2 skrll KASSERT_TX_MTX(sc, q); 1148 1.2.2.2 skrll 1149 1.2.2.2 skrll /* Rx handle */ 1150 1.2.2.2 skrll for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1151 1.2.2.2 skrll if (MVXPE_RX_PKTBUF(sc, q, i) == NULL) 1152 1.2.2.2 skrll continue; 1153 1.2.2.2 skrll mvxpbm_free_chunk(MVXPE_RX_PKTBUF(sc, q, i)); 1154 1.2.2.2 skrll MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1155 1.2.2.2 skrll } 1156 1.2.2.2 skrll rx->rx_dma = rx->rx_cpu = 0; 1157 1.2.2.2 skrll 1158 1.2.2.2 skrll /* Tx handle */ 1159 1.2.2.2 skrll for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1160 1.2.2.2 skrll if (MVXPE_TX_MBUF(sc, q, i) == NULL) 1161 1.2.2.2 skrll continue; 1162 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, i)); 1163 1.2.2.2 skrll m_freem(MVXPE_TX_MBUF(sc, q, i)); 1164 1.2.2.2 skrll MVXPE_TX_MBUF(sc, q, i) = NULL; 1165 1.2.2.2 skrll } 1166 1.2.2.2 skrll tx->tx_dma = tx->tx_cpu = 0; 1167 1.2.2.2 skrll tx->tx_used = 0; 1168 1.2.2.2 skrll } 1169 1.2.2.2 skrll 1170 1.2.2.2 skrll STATIC void 1171 1.2.2.2 skrll mvxpe_ring_sync_rx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1172 1.2.2.2 skrll { 1173 1.2.2.2 skrll int wrap; 1174 1.2.2.2 skrll 1175 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 1176 1.2.2.2 skrll KASSERT(count > 0 && count <= MVXPE_RX_RING_CNT); 1177 1.2.2.2 skrll KASSERT(idx >= 0 && idx < MVXPE_RX_RING_CNT); 1178 1.2.2.2 skrll 1179 1.2.2.2 skrll wrap = (idx + count) - MVXPE_RX_RING_CNT; 1180 1.2.2.2 skrll if (wrap > 0) { 1181 1.2.2.2 skrll count -= wrap; 1182 1.2.2.2 skrll KASSERT(count > 0); 1183 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1184 1.2.2.2 skrll 0, sizeof(struct mvxpe_rx_desc) * wrap, ops); 1185 1.2.2.2 skrll } 1186 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1187 1.2.2.2 skrll MVXPE_RX_DESC_OFF(sc, q, idx), 1188 1.2.2.2 skrll sizeof(struct mvxpe_rx_desc) * count, ops); 1189 1.2.2.2 skrll } 1190 1.2.2.2 skrll 1191 1.2.2.2 skrll STATIC void 1192 1.2.2.2 skrll mvxpe_ring_sync_tx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1193 1.2.2.2 skrll { 1194 1.2.2.2 skrll int wrap = 0; 1195 1.2.2.2 skrll 1196 1.2.2.2 skrll KASSERT_TX_MTX(sc, q); 1197 1.2.2.2 skrll KASSERT(count > 0 && count <= MVXPE_TX_RING_CNT); 1198 1.2.2.2 skrll KASSERT(idx >= 0 && idx < MVXPE_TX_RING_CNT); 1199 1.2.2.2 skrll 1200 1.2.2.2 skrll wrap = (idx + count) - MVXPE_TX_RING_CNT; 1201 1.2.2.2 skrll if (wrap > 0) { 1202 1.2.2.2 skrll count -= wrap; 1203 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1204 1.2.2.2 skrll 0, sizeof(struct mvxpe_tx_desc) * wrap, ops); 1205 1.2.2.2 skrll } 1206 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1207 1.2.2.2 skrll MVXPE_TX_DESC_OFF(sc, q, idx), 1208 1.2.2.2 skrll sizeof(struct mvxpe_tx_desc) * count, ops); 1209 1.2.2.2 skrll } 1210 1.2.2.2 skrll 1211 1.2.2.2 skrll /* 1212 1.2.2.2 skrll * Rx/Tx Queue Control 1213 1.2.2.2 skrll */ 1214 1.2.2.2 skrll STATIC int 1215 1.2.2.2 skrll mvxpe_rx_queue_init(struct ifnet *ifp, int q) 1216 1.2.2.2 skrll { 1217 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1218 1.2.2.2 skrll uint32_t reg; 1219 1.2.2.2 skrll 1220 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 1221 1.2.2.2 skrll KASSERT(MVXPE_RX_RING_MEM_PA(sc, q) != 0); 1222 1.2.2.2 skrll 1223 1.2.2.2 skrll /* descriptor address */ 1224 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXDQA(q), MVXPE_RX_RING_MEM_PA(sc, q)); 1225 1.2.2.2 skrll 1226 1.2.2.2 skrll /* Rx buffer size and descriptor ring size */ 1227 1.2.2.2 skrll reg = MVXPE_PRXDQS_BUFFERSIZE(mvxpbm_chunk_size(sc->sc_bm) >> 3); 1228 1.2.2.2 skrll reg |= MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(MVXPE_RX_RING_CNT); 1229 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXDQS(q), reg); 1230 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PRXDQS(%d): %#x\n", 1231 1.2.2.2 skrll q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 1232 1.2.2.2 skrll 1233 1.2.2.2 skrll /* Rx packet offset address */ 1234 1.2.2.2 skrll reg = MVXPE_PRXC_PACKETOFFSET(mvxpbm_packet_offset(sc->sc_bm) >> 3); 1235 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXC(q), reg); 1236 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PRXC(%d): %#x\n", 1237 1.2.2.2 skrll q, MVXPE_READ(sc, MVXPE_PRXC(q))); 1238 1.2.2.2 skrll 1239 1.2.2.2 skrll /* Rx DMA SNOOP */ 1240 1.2.2.2 skrll reg = MVXPE_PRXSNP_SNOOPNOOFBYTES(MVXPE_MRU); 1241 1.2.2.2 skrll reg |= MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(MVXPE_MRU); 1242 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXSNP(q), reg); 1243 1.2.2.2 skrll 1244 1.2.2.2 skrll /* if DMA is not working, register is not updated */ 1245 1.2.2.2 skrll KASSERT(MVXPE_READ(sc, MVXPE_PRXDQA(q)) == MVXPE_RX_RING_MEM_PA(sc, q)); 1246 1.2.2.2 skrll return 0; 1247 1.2.2.2 skrll } 1248 1.2.2.2 skrll 1249 1.2.2.2 skrll STATIC int 1250 1.2.2.2 skrll mvxpe_tx_queue_init(struct ifnet *ifp, int q) 1251 1.2.2.2 skrll { 1252 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1253 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1254 1.2.2.2 skrll uint32_t reg; 1255 1.2.2.2 skrll 1256 1.2.2.2 skrll KASSERT_TX_MTX(sc, q); 1257 1.2.2.2 skrll KASSERT(MVXPE_TX_RING_MEM_PA(sc, q) != 0); 1258 1.2.2.2 skrll 1259 1.2.2.2 skrll /* descriptor address */ 1260 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXDQA(q), MVXPE_TX_RING_MEM_PA(sc, q)); 1261 1.2.2.2 skrll 1262 1.2.2.2 skrll /* Tx threshold, and descriptor ring size */ 1263 1.2.2.2 skrll reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1264 1.2.2.2 skrll reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 1265 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1266 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PTXDQS(%d): %#x\n", 1267 1.2.2.2 skrll q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 1268 1.2.2.2 skrll 1269 1.2.2.2 skrll /* if DMA is not working, register is not updated */ 1270 1.2.2.2 skrll KASSERT(MVXPE_READ(sc, MVXPE_PTXDQA(q)) == MVXPE_TX_RING_MEM_PA(sc, q)); 1271 1.2.2.2 skrll return 0; 1272 1.2.2.2 skrll } 1273 1.2.2.2 skrll 1274 1.2.2.2 skrll STATIC int 1275 1.2.2.2 skrll mvxpe_rx_queue_enable(struct ifnet *ifp, int q) 1276 1.2.2.2 skrll { 1277 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1278 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1279 1.2.2.2 skrll uint32_t reg; 1280 1.2.2.2 skrll 1281 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 1282 1.2.2.2 skrll 1283 1.2.2.2 skrll /* Set Rx interrupt threshold */ 1284 1.2.2.2 skrll reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1285 1.2.2.2 skrll reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 1286 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXDQTH(q), reg); 1287 1.2.2.2 skrll 1288 1.2.2.2 skrll reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 1289 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1290 1.2.2.2 skrll 1291 1.2.2.2 skrll /* Unmask RXTX_TH Intr. */ 1292 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1293 1.2.2.2 skrll reg |= MVXPE_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1294 1.2.2.2 skrll reg |= MVXPE_PRXTXTI_RDTAQ(q); /* Rx Descriptor Alart */ 1295 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1296 1.2.2.2 skrll 1297 1.2.2.2 skrll /* Enable Rx queue */ 1298 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1299 1.2.2.2 skrll reg |= MVXPE_RQC_ENQ(q); 1300 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_RQC, reg); 1301 1.2.2.2 skrll 1302 1.2.2.2 skrll return 0; 1303 1.2.2.2 skrll } 1304 1.2.2.2 skrll 1305 1.2.2.2 skrll STATIC int 1306 1.2.2.2 skrll mvxpe_tx_queue_enable(struct ifnet *ifp, int q) 1307 1.2.2.2 skrll { 1308 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1309 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1310 1.2.2.2 skrll uint32_t reg; 1311 1.2.2.2 skrll 1312 1.2.2.2 skrll KASSERT_TX_MTX(sc, q); 1313 1.2.2.2 skrll 1314 1.2.2.2 skrll /* Set Tx interrupt threshold */ 1315 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PTXDQS(q)); 1316 1.2.2.2 skrll reg &= ~MVXPE_PTXDQS_TBT_MASK; /* keep queue size */ 1317 1.2.2.2 skrll reg |= MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1318 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1319 1.2.2.2 skrll 1320 1.2.2.2 skrll /* Unmask RXTX_TH Intr. */ 1321 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1322 1.2.2.2 skrll reg |= MVXPE_PRXTXTI_TBTCQ(q); /* Tx Threshold cross */ 1323 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1324 1.2.2.2 skrll 1325 1.2.2.2 skrll /* Don't update MVXPE_TQC here, there is no packet yet. */ 1326 1.2.2.2 skrll return 0; 1327 1.2.2.2 skrll } 1328 1.2.2.2 skrll 1329 1.2.2.2 skrll STATIC void 1330 1.2.2.2 skrll mvxpe_rx_lockq(struct mvxpe_softc *sc, int q) 1331 1.2.2.2 skrll { 1332 1.2.2.2 skrll KASSERT(q >= 0); 1333 1.2.2.2 skrll KASSERT(q < MVXPE_QUEUE_SIZE); 1334 1.2.2.2 skrll mutex_enter(&sc->sc_rx_ring[q].rx_ring_mtx); 1335 1.2.2.2 skrll } 1336 1.2.2.2 skrll 1337 1.2.2.2 skrll STATIC void 1338 1.2.2.2 skrll mvxpe_rx_unlockq(struct mvxpe_softc *sc, int q) 1339 1.2.2.2 skrll { 1340 1.2.2.2 skrll KASSERT(q >= 0); 1341 1.2.2.2 skrll KASSERT(q < MVXPE_QUEUE_SIZE); 1342 1.2.2.2 skrll mutex_exit(&sc->sc_rx_ring[q].rx_ring_mtx); 1343 1.2.2.2 skrll } 1344 1.2.2.2 skrll 1345 1.2.2.2 skrll STATIC void 1346 1.2.2.2 skrll mvxpe_tx_lockq(struct mvxpe_softc *sc, int q) 1347 1.2.2.2 skrll { 1348 1.2.2.2 skrll KASSERT(q >= 0); 1349 1.2.2.2 skrll KASSERT(q < MVXPE_QUEUE_SIZE); 1350 1.2.2.2 skrll mutex_enter(&sc->sc_tx_ring[q].tx_ring_mtx); 1351 1.2.2.2 skrll } 1352 1.2.2.2 skrll 1353 1.2.2.2 skrll STATIC void 1354 1.2.2.2 skrll mvxpe_tx_unlockq(struct mvxpe_softc *sc, int q) 1355 1.2.2.2 skrll { 1356 1.2.2.2 skrll KASSERT(q >= 0); 1357 1.2.2.2 skrll KASSERT(q < MVXPE_QUEUE_SIZE); 1358 1.2.2.2 skrll mutex_exit(&sc->sc_tx_ring[q].tx_ring_mtx); 1359 1.2.2.2 skrll } 1360 1.2.2.2 skrll 1361 1.2.2.2 skrll /* 1362 1.2.2.2 skrll * Interrupt Handlers 1363 1.2.2.2 skrll */ 1364 1.2.2.2 skrll STATIC void 1365 1.2.2.2 skrll mvxpe_disable_intr(struct mvxpe_softc *sc) 1366 1.2.2.2 skrll { 1367 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_EUIM, 0); 1368 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_EUIC, 0); 1369 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIM, 0); 1370 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIC, 0); 1371 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXIM, 0); 1372 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXIC, 0); 1373 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMIM, 0); 1374 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMIC, 0); 1375 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PIE, 0); 1376 1.2.2.2 skrll } 1377 1.2.2.2 skrll 1378 1.2.2.2 skrll STATIC void 1379 1.2.2.2 skrll mvxpe_enable_intr(struct mvxpe_softc *sc) 1380 1.2.2.2 skrll { 1381 1.2.2.2 skrll uint32_t reg; 1382 1.2.2.2 skrll 1383 1.2.2.2 skrll /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1384 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PMIM); 1385 1.2.2.2 skrll reg |= MVXPE_PMI_PHYSTATUSCHNG; 1386 1.2.2.2 skrll reg |= MVXPE_PMI_LINKCHANGE; 1387 1.2.2.2 skrll reg |= MVXPE_PMI_IAE; 1388 1.2.2.2 skrll reg |= MVXPE_PMI_RXOVERRUN; 1389 1.2.2.2 skrll reg |= MVXPE_PMI_RXCRCERROR; 1390 1.2.2.2 skrll reg |= MVXPE_PMI_RXLARGEPACKET; 1391 1.2.2.2 skrll reg |= MVXPE_PMI_TXUNDRN; 1392 1.2.2.3 skrll #if 0 1393 1.2.2.3 skrll /* 1394 1.2.2.3 skrll * The device may raise false interrupts for SERDES even if the device 1395 1.2.2.3 skrll * is not configured to use SERDES connection. 1396 1.2.2.3 skrll */ 1397 1.2.2.2 skrll reg |= MVXPE_PMI_PRBSERROR; 1398 1.2.2.2 skrll reg |= MVXPE_PMI_SRSE; 1399 1.2.2.3 skrll #else 1400 1.2.2.3 skrll reg &= ~MVXPE_PMI_PRBSERROR; 1401 1.2.2.3 skrll reg &= ~MVXPE_PMI_SRSE; 1402 1.2.2.3 skrll #endif 1403 1.2.2.2 skrll reg |= MVXPE_PMI_TREQ_MASK; 1404 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMIM, reg); 1405 1.2.2.2 skrll 1406 1.2.2.2 skrll /* Enable Summary Bit to check all interrupt cause. */ 1407 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1408 1.2.2.2 skrll reg |= MVXPE_PRXTXTI_PMISCICSUMMARY; 1409 1.2.2.2 skrll reg |= MVXPE_PRXTXTI_PTXERRORSUMMARY; 1410 1.2.2.2 skrll reg |= MVXPE_PRXTXTI_PRXTXICSUMMARY; 1411 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1412 1.2.2.2 skrll 1413 1.2.2.2 skrll /* Enable All Queue Interrupt */ 1414 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PIE); 1415 1.2.2.2 skrll reg |= MVXPE_PIE_RXPKTINTRPTENB_MASK; 1416 1.2.2.2 skrll reg |= MVXPE_PIE_TXPKTINTRPTENB_MASK; 1417 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PIE, reg); 1418 1.2.2.2 skrll } 1419 1.2.2.2 skrll 1420 1.2.2.2 skrll STATIC int 1421 1.2.2.2 skrll mvxpe_rxtxth_intr(void *arg) 1422 1.2.2.2 skrll { 1423 1.2.2.2 skrll struct mvxpe_softc *sc = arg; 1424 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1425 1.2.2.2 skrll uint32_t ic, queues, datum = 0; 1426 1.2.2.2 skrll 1427 1.2.2.2 skrll DPRINTSC(sc, 2, "got RXTX_TH_Intr\n"); 1428 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtxth); 1429 1.2.2.2 skrll 1430 1.2.2.2 skrll mvxpe_sc_lock(sc); 1431 1.2.2.2 skrll ic = MVXPE_READ(sc, MVXPE_PRXTXTIC); 1432 1.2.2.3 skrll if (ic == 0) { 1433 1.2.2.3 skrll mvxpe_sc_unlock(sc); 1434 1.2.2.2 skrll return 0; 1435 1.2.2.3 skrll } 1436 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIC, ~ic); 1437 1.2.2.2 skrll datum = datum ^ ic; 1438 1.2.2.2 skrll 1439 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PRXTXTIC: %#x\n", ic); 1440 1.2.2.2 skrll 1441 1.2.2.2 skrll /* ack maintance interrupt first */ 1442 1.2.2.2 skrll if (ic & MVXPE_PRXTXTI_PTXERRORSUMMARY) { 1443 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PRXTXTIC: +PTXERRORSUMMARY\n"); 1444 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtxth_txerr); 1445 1.2.2.2 skrll } 1446 1.2.2.2 skrll if ((ic & MVXPE_PRXTXTI_PMISCICSUMMARY)) { 1447 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PTXTXTIC: +PMISCICSUMMARY\n"); 1448 1.2.2.2 skrll mvxpe_misc_intr(sc); 1449 1.2.2.2 skrll } 1450 1.2.2.2 skrll if (ic & MVXPE_PRXTXTI_PRXTXICSUMMARY) { 1451 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PTXTXTIC: +PRXTXICSUMMARY\n"); 1452 1.2.2.2 skrll mvxpe_rxtx_intr(sc); 1453 1.2.2.2 skrll } 1454 1.2.2.3 skrll if (!(ifp->if_flags & IFF_RUNNING)) { 1455 1.2.2.3 skrll mvxpe_sc_unlock(sc); 1456 1.2.2.2 skrll return 1; 1457 1.2.2.3 skrll } 1458 1.2.2.2 skrll 1459 1.2.2.2 skrll /* RxTxTH interrupt */ 1460 1.2.2.2 skrll queues = MVXPE_PRXTXTI_GET_RBICTAPQ(ic); 1461 1.2.2.2 skrll if (queues) { 1462 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PRXTXTIC: +RXEOF\n"); 1463 1.2.2.2 skrll mvxpe_rx(sc, queues); 1464 1.2.2.2 skrll } 1465 1.2.2.2 skrll queues = MVXPE_PRXTXTI_GET_TBTCQ(ic); 1466 1.2.2.2 skrll if (queues) { 1467 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PRXTXTIC: +TBTCQ\n"); 1468 1.2.2.2 skrll mvxpe_tx_complete(sc, queues); 1469 1.2.2.2 skrll } 1470 1.2.2.2 skrll queues = MVXPE_PRXTXTI_GET_RDTAQ(ic); 1471 1.2.2.2 skrll if (queues) { 1472 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PRXTXTIC: +RDTAQ\n"); 1473 1.2.2.2 skrll mvxpe_rx_refill(sc, queues); 1474 1.2.2.2 skrll } 1475 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1476 1.2.2.2 skrll 1477 1.2.2.2 skrll if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1478 1.2.2.2 skrll mvxpe_start(ifp); 1479 1.2.2.2 skrll 1480 1.2.2.2 skrll rnd_add_uint32(&sc->sc_rnd_source, datum); 1481 1.2.2.2 skrll 1482 1.2.2.2 skrll return 1; 1483 1.2.2.2 skrll } 1484 1.2.2.2 skrll 1485 1.2.2.2 skrll STATIC int 1486 1.2.2.2 skrll mvxpe_misc_intr(void *arg) 1487 1.2.2.2 skrll { 1488 1.2.2.2 skrll struct mvxpe_softc *sc = arg; 1489 1.2.2.2 skrll #ifdef MVXPE_DEBUG 1490 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1491 1.2.2.2 skrll #endif 1492 1.2.2.2 skrll uint32_t ic; 1493 1.2.2.2 skrll uint32_t datum = 0; 1494 1.2.2.2 skrll int claimed = 0; 1495 1.2.2.2 skrll 1496 1.2.2.2 skrll DPRINTSC(sc, 2, "got MISC_INTR\n"); 1497 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_misc); 1498 1.2.2.2 skrll 1499 1.2.2.2 skrll KASSERT_SC_MTX(sc); 1500 1.2.2.2 skrll 1501 1.2.2.2 skrll for (;;) { 1502 1.2.2.2 skrll ic = MVXPE_READ(sc, MVXPE_PMIC); 1503 1.2.2.2 skrll ic &= MVXPE_READ(sc, MVXPE_PMIM); 1504 1.2.2.2 skrll if (ic == 0) 1505 1.2.2.2 skrll break; 1506 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMIC, ~ic); 1507 1.2.2.2 skrll datum = datum ^ ic; 1508 1.2.2.2 skrll claimed = 1; 1509 1.2.2.2 skrll 1510 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "PMIC=%#x\n", ic); 1511 1.2.2.2 skrll if (ic & MVXPE_PMI_PHYSTATUSCHNG) { 1512 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+PHYSTATUSCHNG\n"); 1513 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_phystatuschng); 1514 1.2.2.2 skrll } 1515 1.2.2.2 skrll if (ic & MVXPE_PMI_LINKCHANGE) { 1516 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+LINKCHANGE\n"); 1517 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_linkchange); 1518 1.2.2.2 skrll mvxpe_linkupdate(sc); 1519 1.2.2.2 skrll } 1520 1.2.2.2 skrll if (ic & MVXPE_PMI_IAE) { 1521 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+IAE\n"); 1522 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_iae); 1523 1.2.2.2 skrll } 1524 1.2.2.2 skrll if (ic & MVXPE_PMI_RXOVERRUN) { 1525 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+RXOVERRUN\n"); 1526 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxoverrun); 1527 1.2.2.2 skrll } 1528 1.2.2.2 skrll if (ic & MVXPE_PMI_RXCRCERROR) { 1529 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+RXCRCERROR\n"); 1530 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxcrc); 1531 1.2.2.2 skrll } 1532 1.2.2.2 skrll if (ic & MVXPE_PMI_RXLARGEPACKET) { 1533 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+RXLARGEPACKET\n"); 1534 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxlargepacket); 1535 1.2.2.2 skrll } 1536 1.2.2.2 skrll if (ic & MVXPE_PMI_TXUNDRN) { 1537 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+TXUNDRN\n"); 1538 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txunderrun); 1539 1.2.2.2 skrll } 1540 1.2.2.2 skrll if (ic & MVXPE_PMI_PRBSERROR) { 1541 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+PRBSERROR\n"); 1542 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_prbserr); 1543 1.2.2.2 skrll } 1544 1.2.2.2 skrll if (ic & MVXPE_PMI_TREQ_MASK) { 1545 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "+TREQ\n"); 1546 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txreq); 1547 1.2.2.2 skrll } 1548 1.2.2.2 skrll } 1549 1.2.2.2 skrll if (datum) 1550 1.2.2.2 skrll rnd_add_uint32(&sc->sc_rnd_source, datum); 1551 1.2.2.2 skrll 1552 1.2.2.2 skrll return claimed; 1553 1.2.2.2 skrll } 1554 1.2.2.2 skrll 1555 1.2.2.2 skrll STATIC int 1556 1.2.2.2 skrll mvxpe_rxtx_intr(void *arg) 1557 1.2.2.2 skrll { 1558 1.2.2.2 skrll struct mvxpe_softc *sc = arg; 1559 1.2.2.2 skrll #ifdef MVXPE_DEBUG 1560 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1561 1.2.2.2 skrll #endif 1562 1.2.2.2 skrll uint32_t datum = 0; 1563 1.2.2.2 skrll uint32_t prxtxic; 1564 1.2.2.2 skrll int claimed = 0; 1565 1.2.2.2 skrll 1566 1.2.2.2 skrll DPRINTSC(sc, 2, "got RXTX_Intr\n"); 1567 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtx); 1568 1.2.2.2 skrll 1569 1.2.2.2 skrll KASSERT_SC_MTX(sc); 1570 1.2.2.2 skrll 1571 1.2.2.2 skrll for (;;) { 1572 1.2.2.2 skrll prxtxic = MVXPE_READ(sc, MVXPE_PRXTXIC); 1573 1.2.2.2 skrll prxtxic &= MVXPE_READ(sc, MVXPE_PRXTXIM); 1574 1.2.2.2 skrll if (prxtxic == 0) 1575 1.2.2.2 skrll break; 1576 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXIC, ~prxtxic); 1577 1.2.2.2 skrll datum = datum ^ prxtxic; 1578 1.2.2.2 skrll claimed = 1; 1579 1.2.2.2 skrll 1580 1.2.2.2 skrll DPRINTSC(sc, 2, "PRXTXIC: %#x\n", prxtxic); 1581 1.2.2.2 skrll 1582 1.2.2.2 skrll if (prxtxic & MVXPE_PRXTXI_RREQ_MASK) { 1583 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "Rx Resource Error.\n"); 1584 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rreq); 1585 1.2.2.2 skrll } 1586 1.2.2.2 skrll if (prxtxic & MVXPE_PRXTXI_RPQ_MASK) { 1587 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "Rx Packet in Queue.\n"); 1588 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rpq); 1589 1.2.2.2 skrll } 1590 1.2.2.2 skrll if (prxtxic & MVXPE_PRXTXI_TBRQ_MASK) { 1591 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "Tx Buffer Return.\n"); 1592 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_tbrq); 1593 1.2.2.2 skrll } 1594 1.2.2.2 skrll if (prxtxic & MVXPE_PRXTXI_PRXTXTHICSUMMARY) { 1595 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PRXTXTHIC Sumary\n"); 1596 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rxtxth); 1597 1.2.2.2 skrll } 1598 1.2.2.2 skrll if (prxtxic & MVXPE_PRXTXI_PTXERRORSUMMARY) { 1599 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PTXERROR Sumary\n"); 1600 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_txerr); 1601 1.2.2.2 skrll } 1602 1.2.2.2 skrll if (prxtxic & MVXPE_PRXTXI_PMISCICSUMMARY) { 1603 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "PMISCIC Sumary\n"); 1604 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_misc); 1605 1.2.2.2 skrll } 1606 1.2.2.2 skrll } 1607 1.2.2.2 skrll if (datum) 1608 1.2.2.2 skrll rnd_add_uint32(&sc->sc_rnd_source, datum); 1609 1.2.2.2 skrll 1610 1.2.2.2 skrll return claimed; 1611 1.2.2.2 skrll } 1612 1.2.2.2 skrll 1613 1.2.2.2 skrll STATIC void 1614 1.2.2.2 skrll mvxpe_tick(void *arg) 1615 1.2.2.2 skrll { 1616 1.2.2.2 skrll struct mvxpe_softc *sc = arg; 1617 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 1618 1.2.2.2 skrll 1619 1.2.2.2 skrll mvxpe_sc_lock(sc); 1620 1.2.2.2 skrll 1621 1.2.2.2 skrll mii_tick(mii); 1622 1.2.2.2 skrll mii_pollstat(&sc->sc_mii); 1623 1.2.2.2 skrll 1624 1.2.2.2 skrll /* read mib regisers(clear by read) */ 1625 1.2.2.2 skrll mvxpe_update_mib(sc); 1626 1.2.2.2 skrll 1627 1.2.2.2 skrll /* read counter registers(clear by read) */ 1628 1.2.2.2 skrll MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pdfc, 1629 1.2.2.2 skrll MVXPE_READ(sc, MVXPE_PDFC)); 1630 1.2.2.2 skrll MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pofc, 1631 1.2.2.2 skrll MVXPE_READ(sc, MVXPE_POFC)); 1632 1.2.2.2 skrll MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txbadfcs, 1633 1.2.2.2 skrll MVXPE_READ(sc, MVXPE_TXBADFCS)); 1634 1.2.2.2 skrll MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txdropped, 1635 1.2.2.2 skrll MVXPE_READ(sc, MVXPE_TXDROPPED)); 1636 1.2.2.2 skrll MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_lpic, 1637 1.2.2.2 skrll MVXPE_READ(sc, MVXPE_LPIC)); 1638 1.2.2.2 skrll 1639 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1640 1.2.2.2 skrll 1641 1.2.2.2 skrll callout_schedule(&sc->sc_tick_ch, hz); 1642 1.2.2.2 skrll } 1643 1.2.2.2 skrll 1644 1.2.2.2 skrll 1645 1.2.2.2 skrll /* 1646 1.2.2.2 skrll * struct ifnet and mii callbacks 1647 1.2.2.2 skrll */ 1648 1.2.2.2 skrll STATIC void 1649 1.2.2.2 skrll mvxpe_start(struct ifnet *ifp) 1650 1.2.2.2 skrll { 1651 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1652 1.2.2.2 skrll struct mbuf *m; 1653 1.2.2.2 skrll int q; 1654 1.2.2.2 skrll 1655 1.2.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1656 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "not running\n"); 1657 1.2.2.2 skrll return; 1658 1.2.2.2 skrll } 1659 1.2.2.2 skrll 1660 1.2.2.2 skrll mvxpe_sc_lock(sc); 1661 1.2.2.2 skrll if (!MVXPE_IS_LINKUP(sc)) { 1662 1.2.2.2 skrll /* If Link is DOWN, can't start TX */ 1663 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "link fail\n"); 1664 1.2.2.2 skrll for (;;) { 1665 1.2.2.2 skrll /* 1666 1.2.2.2 skrll * discard stale packets all. 1667 1.2.2.2 skrll * these may confuse DAD, ARP or timer based protocols. 1668 1.2.2.2 skrll */ 1669 1.2.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 1670 1.2.2.2 skrll if (m == NULL) 1671 1.2.2.2 skrll break; 1672 1.2.2.2 skrll m_freem(m); 1673 1.2.2.2 skrll } 1674 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1675 1.2.2.2 skrll return; 1676 1.2.2.2 skrll } 1677 1.2.2.2 skrll for (;;) { 1678 1.2.2.2 skrll /* 1679 1.2.2.2 skrll * don't use IFQ_POLL(). 1680 1.2.2.2 skrll * there is lock problem between IFQ_POLL and IFQ_DEQUEUE 1681 1.2.2.2 skrll * on SMP enabled networking stack. 1682 1.2.2.2 skrll */ 1683 1.2.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 1684 1.2.2.2 skrll if (m == NULL) 1685 1.2.2.2 skrll break; 1686 1.2.2.2 skrll 1687 1.2.2.2 skrll q = mvxpe_tx_queue_select(sc, m); 1688 1.2.2.2 skrll if (q < 0) 1689 1.2.2.2 skrll break; 1690 1.2.2.2 skrll /* mutex is held in mvxpe_tx_queue_select() */ 1691 1.2.2.2 skrll 1692 1.2.2.2 skrll if (mvxpe_tx_queue(sc, m, q) != 0) { 1693 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "cannot add packet to tx ring\n"); 1694 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txerr); 1695 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 1696 1.2.2.2 skrll break; 1697 1.2.2.2 skrll } 1698 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 1699 1.2.2.2 skrll KASSERT(sc->sc_tx_ring[q].tx_used >= 0); 1700 1.2.2.2 skrll KASSERT(sc->sc_tx_ring[q].tx_used <= 1701 1.2.2.2 skrll sc->sc_tx_ring[q].tx_queue_len); 1702 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "a packet is added to tx ring\n"); 1703 1.2.2.2 skrll sc->sc_tx_pending++; 1704 1.2.2.3 skrll ifp->if_opackets++; 1705 1.2.2.2 skrll ifp->if_timer = 1; 1706 1.2.2.2 skrll sc->sc_wdogsoft = 1; 1707 1.2.2.2 skrll bpf_mtap(ifp, m); 1708 1.2.2.2 skrll } 1709 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1710 1.2.2.2 skrll 1711 1.2.2.2 skrll return; 1712 1.2.2.2 skrll } 1713 1.2.2.2 skrll 1714 1.2.2.2 skrll STATIC int 1715 1.2.2.2 skrll mvxpe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1716 1.2.2.2 skrll { 1717 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1718 1.2.2.2 skrll struct ifreq *ifr = data; 1719 1.2.2.2 skrll int error = 0; 1720 1.2.2.2 skrll int s; 1721 1.2.2.2 skrll 1722 1.2.2.2 skrll switch (cmd) { 1723 1.2.2.2 skrll case SIOCGIFMEDIA: 1724 1.2.2.2 skrll case SIOCSIFMEDIA: 1725 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "mvxpe_ioctl MEDIA\n"); 1726 1.2.2.2 skrll s = splnet(); /* XXX: is there suitable mutex? */ 1727 1.2.2.2 skrll error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1728 1.2.2.2 skrll splx(s); 1729 1.2.2.2 skrll break; 1730 1.2.2.2 skrll default: 1731 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "mvxpe_ioctl ETHER\n"); 1732 1.2.2.2 skrll error = ether_ioctl(ifp, cmd, data); 1733 1.2.2.2 skrll if (error == ENETRESET) { 1734 1.2.2.2 skrll if (ifp->if_flags & IFF_RUNNING) { 1735 1.2.2.2 skrll mvxpe_sc_lock(sc); 1736 1.2.2.2 skrll mvxpe_filter_setup(sc); 1737 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1738 1.2.2.2 skrll } 1739 1.2.2.2 skrll error = 0; 1740 1.2.2.2 skrll } 1741 1.2.2.2 skrll break; 1742 1.2.2.2 skrll } 1743 1.2.2.2 skrll 1744 1.2.2.2 skrll return error; 1745 1.2.2.2 skrll } 1746 1.2.2.2 skrll 1747 1.2.2.2 skrll STATIC int 1748 1.2.2.2 skrll mvxpe_init(struct ifnet *ifp) 1749 1.2.2.2 skrll { 1750 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1751 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 1752 1.2.2.2 skrll uint32_t reg; 1753 1.2.2.2 skrll int q; 1754 1.2.2.2 skrll 1755 1.2.2.2 skrll mvxpe_sc_lock(sc); 1756 1.2.2.2 skrll 1757 1.2.2.2 skrll /* Start DMA Engine */ 1758 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 1759 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 1760 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 1761 1.2.2.2 skrll 1762 1.2.2.2 skrll /* Enable port */ 1763 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PMACC0); 1764 1.2.2.2 skrll reg |= MVXPE_PMACC0_PORTEN; 1765 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1766 1.2.2.2 skrll 1767 1.2.2.2 skrll /* Link up */ 1768 1.2.2.2 skrll mvxpe_linkup(sc); 1769 1.2.2.2 skrll 1770 1.2.2.2 skrll /* Enable All Queue and interrupt of each Queue */ 1771 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1772 1.2.2.2 skrll mvxpe_rx_lockq(sc, q); 1773 1.2.2.2 skrll mvxpe_rx_queue_enable(ifp, q); 1774 1.2.2.2 skrll mvxpe_rx_queue_refill(sc, q); 1775 1.2.2.2 skrll mvxpe_rx_unlockq(sc, q); 1776 1.2.2.2 skrll 1777 1.2.2.2 skrll mvxpe_tx_lockq(sc, q); 1778 1.2.2.2 skrll mvxpe_tx_queue_enable(ifp, q); 1779 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 1780 1.2.2.2 skrll } 1781 1.2.2.2 skrll 1782 1.2.2.2 skrll /* Enable interrupt */ 1783 1.2.2.2 skrll mvxpe_enable_intr(sc); 1784 1.2.2.2 skrll 1785 1.2.2.2 skrll /* Set Counter */ 1786 1.2.2.2 skrll callout_schedule(&sc->sc_tick_ch, hz); 1787 1.2.2.2 skrll 1788 1.2.2.2 skrll /* Media check */ 1789 1.2.2.2 skrll mii_mediachg(mii); 1790 1.2.2.2 skrll 1791 1.2.2.2 skrll ifp->if_flags |= IFF_RUNNING; 1792 1.2.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1793 1.2.2.2 skrll 1794 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1795 1.2.2.2 skrll return 0; 1796 1.2.2.2 skrll } 1797 1.2.2.2 skrll 1798 1.2.2.2 skrll /* ARGSUSED */ 1799 1.2.2.2 skrll STATIC void 1800 1.2.2.2 skrll mvxpe_stop(struct ifnet *ifp, int disable) 1801 1.2.2.2 skrll { 1802 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1803 1.2.2.2 skrll uint32_t reg; 1804 1.2.2.2 skrll int q, cnt; 1805 1.2.2.2 skrll 1806 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "stop device dma and interrupts.\n"); 1807 1.2.2.2 skrll 1808 1.2.2.2 skrll mvxpe_sc_lock(sc); 1809 1.2.2.2 skrll 1810 1.2.2.2 skrll callout_stop(&sc->sc_tick_ch); 1811 1.2.2.2 skrll 1812 1.2.2.2 skrll /* Link down */ 1813 1.2.2.2 skrll mvxpe_linkdown(sc); 1814 1.2.2.2 skrll 1815 1.2.2.2 skrll /* Disable Rx interrupt */ 1816 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PIE); 1817 1.2.2.2 skrll reg &= ~MVXPE_PIE_RXPKTINTRPTENB_MASK; 1818 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PIE, reg); 1819 1.2.2.2 skrll 1820 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1821 1.2.2.2 skrll reg &= ~MVXPE_PRXTXTI_RBICTAPQ_MASK; 1822 1.2.2.2 skrll reg &= ~MVXPE_PRXTXTI_RDTAQ_MASK; 1823 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1824 1.2.2.2 skrll 1825 1.2.2.2 skrll /* Wait for all Rx activity to terminate. */ 1826 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1827 1.2.2.2 skrll reg = MVXPE_RQC_DIS(reg); 1828 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_RQC, reg); 1829 1.2.2.2 skrll cnt = 0; 1830 1.2.2.2 skrll do { 1831 1.2.2.2 skrll if (cnt >= RX_DISABLE_TIMEOUT) { 1832 1.2.2.2 skrll aprint_error_ifnet(ifp, 1833 1.2.2.2 skrll "timeout for RX stopped. rqc 0x%x\n", reg); 1834 1.2.2.2 skrll break; 1835 1.2.2.2 skrll } 1836 1.2.2.2 skrll cnt++; 1837 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_RQC); 1838 1.2.2.2 skrll } while (reg & MVXPE_RQC_EN_MASK); 1839 1.2.2.2 skrll 1840 1.2.2.2 skrll /* Wait for all Tx activety to terminate. */ 1841 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PIE); 1842 1.2.2.2 skrll reg &= ~MVXPE_PIE_TXPKTINTRPTENB_MASK; 1843 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PIE, reg); 1844 1.2.2.2 skrll 1845 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1846 1.2.2.2 skrll reg &= ~MVXPE_PRXTXTI_TBTCQ_MASK; 1847 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1848 1.2.2.2 skrll 1849 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_TQC) & MVXPE_TQC_EN_MASK; 1850 1.2.2.2 skrll reg = MVXPE_TQC_DIS(reg); 1851 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_TQC, reg); 1852 1.2.2.2 skrll cnt = 0; 1853 1.2.2.2 skrll do { 1854 1.2.2.2 skrll if (cnt >= TX_DISABLE_TIMEOUT) { 1855 1.2.2.2 skrll aprint_error_ifnet(ifp, 1856 1.2.2.2 skrll "timeout for TX stopped. tqc 0x%x\n", reg); 1857 1.2.2.2 skrll break; 1858 1.2.2.2 skrll } 1859 1.2.2.2 skrll cnt++; 1860 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_TQC); 1861 1.2.2.2 skrll } while (reg & MVXPE_TQC_EN_MASK); 1862 1.2.2.2 skrll 1863 1.2.2.2 skrll /* Wait for all Tx FIFO is empty */ 1864 1.2.2.2 skrll cnt = 0; 1865 1.2.2.2 skrll do { 1866 1.2.2.2 skrll if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1867 1.2.2.2 skrll aprint_error_ifnet(ifp, 1868 1.2.2.2 skrll "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1869 1.2.2.2 skrll break; 1870 1.2.2.2 skrll } 1871 1.2.2.2 skrll cnt++; 1872 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PS0); 1873 1.2.2.2 skrll } while (!(reg & MVXPE_PS0_TXFIFOEMP) && (reg & MVXPE_PS0_TXINPROG)); 1874 1.2.2.2 skrll 1875 1.2.2.2 skrll /* Reset the MAC Port Enable bit */ 1876 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PMACC0); 1877 1.2.2.2 skrll reg &= ~MVXPE_PMACC0_PORTEN; 1878 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1879 1.2.2.2 skrll 1880 1.2.2.2 skrll /* Disable each of queue */ 1881 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1882 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1883 1.2.2.2 skrll 1884 1.2.2.2 skrll mvxpe_rx_lockq(sc, q); 1885 1.2.2.2 skrll mvxpe_tx_lockq(sc, q); 1886 1.2.2.2 skrll 1887 1.2.2.2 skrll /* Disable Rx packet buffer refill request */ 1888 1.2.2.2 skrll reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1889 1.2.2.2 skrll reg |= MVXPE_PRXDQTH_NODT(0); 1890 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1891 1.2.2.2 skrll 1892 1.2.2.2 skrll if (disable) { 1893 1.2.2.2 skrll /* 1894 1.2.2.2 skrll * Hold Reset state of DMA Engine 1895 1.2.2.2 skrll * (must write 0x0 to restart it) 1896 1.2.2.2 skrll */ 1897 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 1898 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 1899 1.2.2.2 skrll mvxpe_ring_flush_queue(sc, q); 1900 1.2.2.2 skrll } 1901 1.2.2.2 skrll 1902 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 1903 1.2.2.2 skrll mvxpe_rx_unlockq(sc, q); 1904 1.2.2.2 skrll } 1905 1.2.2.2 skrll 1906 1.2.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1907 1.2.2.2 skrll 1908 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1909 1.2.2.2 skrll } 1910 1.2.2.2 skrll 1911 1.2.2.2 skrll STATIC void 1912 1.2.2.2 skrll mvxpe_watchdog(struct ifnet *ifp) 1913 1.2.2.2 skrll { 1914 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1915 1.2.2.2 skrll int q; 1916 1.2.2.2 skrll 1917 1.2.2.2 skrll mvxpe_sc_lock(sc); 1918 1.2.2.2 skrll 1919 1.2.2.2 skrll /* 1920 1.2.2.2 skrll * Reclaim first as there is a possibility of losing Tx completion 1921 1.2.2.2 skrll * interrupts. 1922 1.2.2.2 skrll */ 1923 1.2.2.2 skrll mvxpe_tx_complete(sc, 0xff); 1924 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1925 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1926 1.2.2.2 skrll 1927 1.2.2.2 skrll if (tx->tx_dma != tx->tx_cpu) { 1928 1.2.2.2 skrll if (sc->sc_wdogsoft) { 1929 1.2.2.2 skrll /* 1930 1.2.2.2 skrll * There is race condition between CPU and DMA 1931 1.2.2.2 skrll * engine. When DMA engine encounters queue end, 1932 1.2.2.2 skrll * it clears MVXPE_TQC_ENQ bit. 1933 1.2.2.2 skrll * XXX: how about enhanced mode? 1934 1.2.2.2 skrll */ 1935 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 1936 1.2.2.2 skrll ifp->if_timer = 5; 1937 1.2.2.2 skrll sc->sc_wdogsoft = 0; 1938 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_wdogsoft); 1939 1.2.2.2 skrll } else { 1940 1.2.2.2 skrll aprint_error_ifnet(ifp, "watchdog timeout\n"); 1941 1.2.2.2 skrll ifp->if_oerrors++; 1942 1.2.2.2 skrll mvxpe_linkreset(sc); 1943 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1944 1.2.2.2 skrll 1945 1.2.2.2 skrll /* trigger reinitialize sequence */ 1946 1.2.2.2 skrll mvxpe_stop(ifp, 1); 1947 1.2.2.2 skrll mvxpe_init(ifp); 1948 1.2.2.2 skrll 1949 1.2.2.2 skrll mvxpe_sc_lock(sc); 1950 1.2.2.2 skrll } 1951 1.2.2.2 skrll } 1952 1.2.2.2 skrll } 1953 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1954 1.2.2.2 skrll } 1955 1.2.2.2 skrll 1956 1.2.2.2 skrll STATIC int 1957 1.2.2.2 skrll mvxpe_ifflags_cb(struct ethercom *ec) 1958 1.2.2.2 skrll { 1959 1.2.2.2 skrll struct ifnet *ifp = &ec->ec_if; 1960 1.2.2.2 skrll struct mvxpe_softc *sc = ifp->if_softc; 1961 1.2.2.2 skrll int change = ifp->if_flags ^ sc->sc_if_flags; 1962 1.2.2.2 skrll 1963 1.2.2.2 skrll mvxpe_sc_lock(sc); 1964 1.2.2.2 skrll 1965 1.2.2.2 skrll if (change != 0) 1966 1.2.2.2 skrll sc->sc_if_flags = ifp->if_flags; 1967 1.2.2.2 skrll 1968 1.2.2.2 skrll if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) { 1969 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1970 1.2.2.2 skrll return ENETRESET; 1971 1.2.2.2 skrll } 1972 1.2.2.2 skrll 1973 1.2.2.2 skrll if ((change & IFF_PROMISC) != 0) 1974 1.2.2.2 skrll mvxpe_filter_setup(sc); 1975 1.2.2.2 skrll 1976 1.2.2.2 skrll if ((change & IFF_UP) != 0) 1977 1.2.2.2 skrll mvxpe_linkreset(sc); 1978 1.2.2.2 skrll 1979 1.2.2.2 skrll mvxpe_sc_unlock(sc); 1980 1.2.2.2 skrll return 0; 1981 1.2.2.2 skrll } 1982 1.2.2.2 skrll 1983 1.2.2.2 skrll STATIC int 1984 1.2.2.2 skrll mvxpe_mediachange(struct ifnet *ifp) 1985 1.2.2.2 skrll { 1986 1.2.2.2 skrll return ether_mediachange(ifp); 1987 1.2.2.2 skrll } 1988 1.2.2.2 skrll 1989 1.2.2.2 skrll STATIC void 1990 1.2.2.2 skrll mvxpe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1991 1.2.2.2 skrll { 1992 1.2.2.2 skrll ether_mediastatus(ifp, ifmr); 1993 1.2.2.2 skrll } 1994 1.2.2.2 skrll 1995 1.2.2.2 skrll /* 1996 1.2.2.2 skrll * Link State Notify 1997 1.2.2.2 skrll */ 1998 1.2.2.2 skrll STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc) 1999 1.2.2.2 skrll { 2000 1.2.2.2 skrll int linkup; /* bool */ 2001 1.2.2.2 skrll 2002 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2003 1.2.2.2 skrll 2004 1.2.2.2 skrll /* tell miibus */ 2005 1.2.2.2 skrll mii_pollstat(&sc->sc_mii); 2006 1.2.2.2 skrll 2007 1.2.2.2 skrll /* syslog */ 2008 1.2.2.2 skrll linkup = MVXPE_IS_LINKUP(sc); 2009 1.2.2.2 skrll if (sc->sc_linkstate == linkup) 2010 1.2.2.2 skrll return; 2011 1.2.2.2 skrll 2012 1.2.2.2 skrll #ifdef DEBUG 2013 1.2.2.2 skrll log(LOG_DEBUG, 2014 1.2.2.2 skrll "%s: link %s\n", device_xname(sc->sc_dev), linkup ? "up" : "down"); 2015 1.2.2.2 skrll #endif 2016 1.2.2.2 skrll if (linkup) 2017 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_up); 2018 1.2.2.2 skrll else 2019 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_down); 2020 1.2.2.2 skrll 2021 1.2.2.2 skrll sc->sc_linkstate = linkup; 2022 1.2.2.2 skrll } 2023 1.2.2.2 skrll 2024 1.2.2.2 skrll STATIC void 2025 1.2.2.2 skrll mvxpe_linkup(struct mvxpe_softc *sc) 2026 1.2.2.2 skrll { 2027 1.2.2.2 skrll uint32_t reg; 2028 1.2.2.2 skrll 2029 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2030 1.2.2.2 skrll 2031 1.2.2.2 skrll /* set EEE parameters */ 2032 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_LPIC1); 2033 1.2.2.2 skrll if (sc->sc_cf.cf_lpi) 2034 1.2.2.2 skrll reg |= MVXPE_LPIC1_LPIRE; 2035 1.2.2.2 skrll else 2036 1.2.2.2 skrll reg &= ~MVXPE_LPIC1_LPIRE; 2037 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 2038 1.2.2.2 skrll 2039 1.2.2.2 skrll /* set auto-negotiation parameters */ 2040 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PANC); 2041 1.2.2.2 skrll if (sc->sc_cf.cf_fc) { 2042 1.2.2.2 skrll /* flow control negotiation */ 2043 1.2.2.2 skrll reg |= MVXPE_PANC_PAUSEADV; 2044 1.2.2.2 skrll reg |= MVXPE_PANC_ANFCEN; 2045 1.2.2.2 skrll } 2046 1.2.2.2 skrll else { 2047 1.2.2.2 skrll reg &= ~MVXPE_PANC_PAUSEADV; 2048 1.2.2.2 skrll reg &= ~MVXPE_PANC_ANFCEN; 2049 1.2.2.2 skrll } 2050 1.2.2.2 skrll reg &= ~MVXPE_PANC_FORCELINKFAIL; 2051 1.2.2.2 skrll reg &= ~MVXPE_PANC_FORCELINKPASS; 2052 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PANC, reg); 2053 1.2.2.2 skrll 2054 1.2.2.2 skrll mii_mediachg(&sc->sc_mii); 2055 1.2.2.2 skrll } 2056 1.2.2.2 skrll 2057 1.2.2.2 skrll STATIC void 2058 1.2.2.2 skrll mvxpe_linkdown(struct mvxpe_softc *sc) 2059 1.2.2.2 skrll { 2060 1.2.2.2 skrll struct mii_softc *mii; 2061 1.2.2.2 skrll uint32_t reg; 2062 1.2.2.2 skrll 2063 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2064 1.2.2.2 skrll return; 2065 1.2.2.2 skrll 2066 1.2.2.2 skrll reg = MVXPE_READ(sc, MVXPE_PANC); 2067 1.2.2.2 skrll reg |= MVXPE_PANC_FORCELINKFAIL; 2068 1.2.2.2 skrll reg &= MVXPE_PANC_FORCELINKPASS; 2069 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PANC, reg); 2070 1.2.2.2 skrll 2071 1.2.2.2 skrll mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2072 1.2.2.2 skrll if (mii) 2073 1.2.2.2 skrll mii_phy_down(mii); 2074 1.2.2.2 skrll } 2075 1.2.2.2 skrll 2076 1.2.2.2 skrll STATIC void 2077 1.2.2.2 skrll mvxpe_linkreset(struct mvxpe_softc *sc) 2078 1.2.2.2 skrll { 2079 1.2.2.2 skrll struct mii_softc *mii; 2080 1.2.2.2 skrll 2081 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2082 1.2.2.2 skrll 2083 1.2.2.2 skrll /* force reset PHY first */ 2084 1.2.2.2 skrll mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2085 1.2.2.2 skrll if (mii) 2086 1.2.2.2 skrll mii_phy_reset(mii); 2087 1.2.2.2 skrll 2088 1.2.2.2 skrll /* reinit MAC and PHY */ 2089 1.2.2.2 skrll mvxpe_linkdown(sc); 2090 1.2.2.2 skrll if ((sc->sc_if_flags & IFF_UP) != 0) 2091 1.2.2.2 skrll mvxpe_linkup(sc); 2092 1.2.2.2 skrll } 2093 1.2.2.2 skrll 2094 1.2.2.2 skrll /* 2095 1.2.2.2 skrll * Tx Subroutines 2096 1.2.2.2 skrll */ 2097 1.2.2.2 skrll STATIC int 2098 1.2.2.2 skrll mvxpe_tx_queue_select(struct mvxpe_softc *sc, struct mbuf *m) 2099 1.2.2.2 skrll { 2100 1.2.2.2 skrll int q = 0; 2101 1.2.2.2 skrll 2102 1.2.2.2 skrll /* XXX: get attribute from ALTQ framework? */ 2103 1.2.2.2 skrll mvxpe_tx_lockq(sc, q); 2104 1.2.2.2 skrll return 0; 2105 1.2.2.2 skrll } 2106 1.2.2.2 skrll 2107 1.2.2.2 skrll STATIC int 2108 1.2.2.2 skrll mvxpe_tx_queue(struct mvxpe_softc *sc, struct mbuf *m, int q) 2109 1.2.2.2 skrll { 2110 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2111 1.2.2.2 skrll bus_dma_segment_t *txsegs; 2112 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2113 1.2.2.2 skrll struct mvxpe_tx_desc *t = NULL; 2114 1.2.2.2 skrll uint32_t ptxsu; 2115 1.2.2.2 skrll int txnsegs; 2116 1.2.2.2 skrll int start, used; 2117 1.2.2.2 skrll int i; 2118 1.2.2.2 skrll 2119 1.2.2.2 skrll KASSERT_TX_MTX(sc, q); 2120 1.2.2.2 skrll KASSERT(tx->tx_used >= 0); 2121 1.2.2.2 skrll KASSERT(tx->tx_used <= tx->tx_queue_len); 2122 1.2.2.2 skrll 2123 1.2.2.2 skrll /* load mbuf using dmamap of 1st descriptor */ 2124 1.2.2.2 skrll if (bus_dmamap_load_mbuf(sc->sc_dmat, 2125 1.2.2.2 skrll MVXPE_TX_MAP(sc, q, tx->tx_cpu), m, BUS_DMA_NOWAIT) != 0) { 2126 1.2.2.2 skrll m_freem(m); 2127 1.2.2.2 skrll return ENOBUFS; 2128 1.2.2.2 skrll } 2129 1.2.2.2 skrll txsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_segs; 2130 1.2.2.2 skrll txnsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_nsegs; 2131 1.2.2.2 skrll if (txnsegs <= 0 || (txnsegs + tx->tx_used) > tx->tx_queue_len) { 2132 1.2.2.2 skrll /* we have no enough descriptors or mbuf is broken */ 2133 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, tx->tx_cpu)); 2134 1.2.2.2 skrll m_freem(m); 2135 1.2.2.2 skrll return ENOBUFS; 2136 1.2.2.2 skrll } 2137 1.2.2.2 skrll DPRINTSC(sc, 2, "send packet %p descriptor %d\n", m, tx->tx_cpu); 2138 1.2.2.2 skrll KASSERT(MVXPE_TX_MBUF(sc, q, tx->tx_cpu) == NULL); 2139 1.2.2.2 skrll 2140 1.2.2.2 skrll /* remember mbuf using 1st descriptor */ 2141 1.2.2.2 skrll MVXPE_TX_MBUF(sc, q, tx->tx_cpu) = m; 2142 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, 2143 1.2.2.2 skrll MVXPE_TX_MAP(sc, q, tx->tx_cpu), 0, m->m_pkthdr.len, 2144 1.2.2.3 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2145 1.2.2.2 skrll 2146 1.2.2.2 skrll /* load to tx descriptors */ 2147 1.2.2.2 skrll start = tx->tx_cpu; 2148 1.2.2.2 skrll used = 0; 2149 1.2.2.2 skrll for (i = 0; i < txnsegs; i++) { 2150 1.2.2.2 skrll if (__predict_false(txsegs[i].ds_len == 0)) 2151 1.2.2.2 skrll continue; 2152 1.2.2.2 skrll t = MVXPE_TX_DESC(sc, q, tx->tx_cpu); 2153 1.2.2.2 skrll t->command = 0; 2154 1.2.2.2 skrll t->l4ichk = 0; 2155 1.2.2.2 skrll t->flags = 0; 2156 1.2.2.2 skrll if (i == 0) { 2157 1.2.2.2 skrll /* 1st descriptor */ 2158 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_W_PACKET_OFFSET(0); 2159 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_PADDING; 2160 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_F; 2161 1.2.2.2 skrll mvxpe_tx_set_csumflag(ifp, t, m); 2162 1.2.2.2 skrll } 2163 1.2.2.2 skrll t->bufptr = txsegs[i].ds_addr; 2164 1.2.2.2 skrll t->bytecnt = txsegs[i].ds_len; 2165 1.2.2.2 skrll tx->tx_cpu = tx_counter_adv(tx->tx_cpu, 1); 2166 1.2.2.2 skrll tx->tx_used++; 2167 1.2.2.2 skrll used++; 2168 1.2.2.2 skrll } 2169 1.2.2.2 skrll /* t is last descriptor here */ 2170 1.2.2.2 skrll KASSERT(t != NULL); 2171 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L; 2172 1.2.2.2 skrll 2173 1.2.2.2 skrll DPRINTSC(sc, 2, "queue %d, %d descriptors used\n", q, used); 2174 1.2.2.2 skrll #ifdef MVXPE_DEBUG 2175 1.2.2.2 skrll if (mvxpe_debug > 2) 2176 1.2.2.2 skrll for (i = start; i <= tx->tx_cpu; i++) { 2177 1.2.2.2 skrll t = MVXPE_TX_DESC(sc, q, i); 2178 1.2.2.2 skrll mvxpe_dump_txdesc(t, i); 2179 1.2.2.2 skrll } 2180 1.2.2.2 skrll #endif 2181 1.2.2.2 skrll mvxpe_ring_sync_tx(sc, q, start, used, 2182 1.2.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2183 1.2.2.2 skrll 2184 1.2.2.2 skrll while (used > 255) { 2185 1.2.2.2 skrll ptxsu = MVXPE_PTXSU_NOWD(255); 2186 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2187 1.2.2.2 skrll used -= 255; 2188 1.2.2.2 skrll } 2189 1.2.2.2 skrll if (used > 0) { 2190 1.2.2.2 skrll ptxsu = MVXPE_PTXSU_NOWD(used); 2191 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2192 1.2.2.2 skrll } 2193 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 2194 1.2.2.2 skrll 2195 1.2.2.2 skrll DPRINTSC(sc, 2, 2196 1.2.2.2 skrll "PTXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQA(q))); 2197 1.2.2.2 skrll DPRINTSC(sc, 2, 2198 1.2.2.2 skrll "PTXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 2199 1.2.2.2 skrll DPRINTSC(sc, 2, 2200 1.2.2.2 skrll "PTXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXS(q))); 2201 1.2.2.2 skrll DPRINTSC(sc, 2, 2202 1.2.2.2 skrll "PTXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PTXDI(q))); 2203 1.2.2.2 skrll DPRINTSC(sc, 2, "TQC: %#x\n", MVXPE_READ(sc, MVXPE_TQC)); 2204 1.2.2.2 skrll DPRINTIFNET(ifp, 2, 2205 1.2.2.2 skrll "Tx: tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2206 1.2.2.2 skrll tx->tx_cpu, tx->tx_dma, tx->tx_used); 2207 1.2.2.2 skrll return 0; 2208 1.2.2.2 skrll } 2209 1.2.2.2 skrll 2210 1.2.2.2 skrll STATIC void 2211 1.2.2.2 skrll mvxpe_tx_set_csumflag(struct ifnet *ifp, 2212 1.2.2.2 skrll struct mvxpe_tx_desc *t, struct mbuf *m) 2213 1.2.2.2 skrll { 2214 1.2.2.2 skrll struct ether_header *eh; 2215 1.2.2.2 skrll int csum_flags; 2216 1.2.2.2 skrll uint32_t iphl = 0, ipoff = 0; 2217 1.2.2.2 skrll 2218 1.2.2.2 skrll 2219 1.2.2.2 skrll csum_flags = ifp->if_csum_flags_tx & m->m_pkthdr.csum_flags; 2220 1.2.2.2 skrll 2221 1.2.2.2 skrll eh = mtod(m, struct ether_header *); 2222 1.2.2.2 skrll switch (htons(eh->ether_type)) { 2223 1.2.2.2 skrll case ETHERTYPE_IP: 2224 1.2.2.2 skrll case ETHERTYPE_IPV6: 2225 1.2.2.2 skrll ipoff = ETHER_HDR_LEN; 2226 1.2.2.2 skrll break; 2227 1.2.2.2 skrll case ETHERTYPE_VLAN: 2228 1.2.2.2 skrll ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2229 1.2.2.2 skrll break; 2230 1.2.2.2 skrll } 2231 1.2.2.2 skrll 2232 1.2.2.2 skrll if (csum_flags & (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 2233 1.2.2.2 skrll iphl = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2234 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L3_IP4; 2235 1.2.2.2 skrll } 2236 1.2.2.2 skrll else if (csum_flags & (M_CSUM_TCPv6|M_CSUM_UDPv6)) { 2237 1.2.2.2 skrll iphl = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 2238 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L3_IP6; 2239 1.2.2.2 skrll } 2240 1.2.2.2 skrll else { 2241 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2242 1.2.2.2 skrll return; 2243 1.2.2.2 skrll } 2244 1.2.2.2 skrll 2245 1.2.2.2 skrll 2246 1.2.2.2 skrll /* L3 */ 2247 1.2.2.2 skrll if (csum_flags & M_CSUM_IPv4) { 2248 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_IP4_CHECKSUM; 2249 1.2.2.2 skrll } 2250 1.2.2.2 skrll 2251 1.2.2.2 skrll /* L4 */ 2252 1.2.2.2 skrll if ((csum_flags & 2253 1.2.2.2 skrll (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6)) == 0) { 2254 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2255 1.2.2.2 skrll } 2256 1.2.2.2 skrll else if (csum_flags & M_CSUM_TCPv4) { 2257 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2258 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_TCP; 2259 1.2.2.2 skrll } 2260 1.2.2.2 skrll else if (csum_flags & M_CSUM_UDPv4) { 2261 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2262 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_UDP; 2263 1.2.2.2 skrll } 2264 1.2.2.2 skrll else if (csum_flags & M_CSUM_TCPv6) { 2265 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2266 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_TCP; 2267 1.2.2.2 skrll } 2268 1.2.2.2 skrll else if (csum_flags & M_CSUM_UDPv6) { 2269 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2270 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L4_UDP; 2271 1.2.2.2 skrll } 2272 1.2.2.2 skrll 2273 1.2.2.2 skrll t->l4ichk = 0; 2274 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2275 1.2.2.2 skrll t->command |= MVXPE_TX_CMD_L3_OFFSET(ipoff); 2276 1.2.2.2 skrll } 2277 1.2.2.2 skrll 2278 1.2.2.2 skrll STATIC void 2279 1.2.2.2 skrll mvxpe_tx_complete(struct mvxpe_softc *sc, uint32_t queues) 2280 1.2.2.2 skrll { 2281 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2282 1.2.2.2 skrll int q; 2283 1.2.2.2 skrll 2284 1.2.2.2 skrll DPRINTSC(sc, 2, "tx completed.\n"); 2285 1.2.2.2 skrll 2286 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2287 1.2.2.2 skrll 2288 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2289 1.2.2.2 skrll if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2290 1.2.2.2 skrll continue; 2291 1.2.2.2 skrll mvxpe_tx_lockq(sc, q); 2292 1.2.2.2 skrll mvxpe_tx_queue_complete(sc, q); 2293 1.2.2.2 skrll mvxpe_tx_unlockq(sc, q); 2294 1.2.2.2 skrll } 2295 1.2.2.2 skrll KASSERT(sc->sc_tx_pending >= 0); 2296 1.2.2.2 skrll if (sc->sc_tx_pending == 0) 2297 1.2.2.2 skrll ifp->if_timer = 0; 2298 1.2.2.2 skrll } 2299 1.2.2.2 skrll 2300 1.2.2.2 skrll STATIC void 2301 1.2.2.2 skrll mvxpe_tx_queue_complete(struct mvxpe_softc *sc, int q) 2302 1.2.2.2 skrll { 2303 1.2.2.2 skrll struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2304 1.2.2.2 skrll struct mvxpe_tx_desc *t; 2305 1.2.2.2 skrll uint32_t ptxs, ptxsu, ndesc; 2306 1.2.2.2 skrll int i; 2307 1.2.2.2 skrll 2308 1.2.2.2 skrll KASSERT_TX_MTX(sc, q); 2309 1.2.2.2 skrll 2310 1.2.2.2 skrll ptxs = MVXPE_READ(sc, MVXPE_PTXS(q)); 2311 1.2.2.2 skrll ndesc = MVXPE_PTXS_GET_TBC(ptxs); 2312 1.2.2.2 skrll if (ndesc == 0) 2313 1.2.2.2 skrll return; 2314 1.2.2.2 skrll 2315 1.2.2.2 skrll DPRINTSC(sc, 2, 2316 1.2.2.2 skrll "tx complete queue %d, %d descriptors.\n", q, ndesc); 2317 1.2.2.2 skrll 2318 1.2.2.2 skrll mvxpe_ring_sync_tx(sc, q, tx->tx_dma, ndesc, 2319 1.2.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2320 1.2.2.2 skrll 2321 1.2.2.2 skrll for (i = 0; i < ndesc; i++) { 2322 1.2.2.2 skrll int error = 0; 2323 1.2.2.2 skrll 2324 1.2.2.2 skrll t = MVXPE_TX_DESC(sc, q, tx->tx_dma); 2325 1.2.2.2 skrll if (t->flags & MVXPE_TX_F_ES) { 2326 1.2.2.2 skrll DPRINTSC(sc, 1, 2327 1.2.2.2 skrll "tx error queue %d desc %d\n", 2328 1.2.2.2 skrll q, tx->tx_dma); 2329 1.2.2.2 skrll switch (t->flags & MVXPE_TX_F_EC_MASK) { 2330 1.2.2.2 skrll case MVXPE_TX_F_EC_LC: 2331 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_lc); 2332 1.2.2.3 skrll break; 2333 1.2.2.2 skrll case MVXPE_TX_F_EC_UR: 2334 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_ur); 2335 1.2.2.3 skrll break; 2336 1.2.2.2 skrll case MVXPE_TX_F_EC_RL: 2337 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_rl); 2338 1.2.2.3 skrll break; 2339 1.2.2.2 skrll default: 2340 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_oth); 2341 1.2.2.3 skrll break; 2342 1.2.2.2 skrll } 2343 1.2.2.2 skrll error = 1; 2344 1.2.2.2 skrll } 2345 1.2.2.2 skrll if (MVXPE_TX_MBUF(sc, q, tx->tx_dma) != NULL) { 2346 1.2.2.2 skrll KASSERT((t->command & MVXPE_TX_CMD_F) != 0); 2347 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, 2348 1.2.2.2 skrll MVXPE_TX_MAP(sc, q, tx->tx_dma)); 2349 1.2.2.2 skrll m_freem(MVXPE_TX_MBUF(sc, q, tx->tx_dma)); 2350 1.2.2.2 skrll MVXPE_TX_MBUF(sc, q, tx->tx_dma) = NULL; 2351 1.2.2.2 skrll sc->sc_tx_pending--; 2352 1.2.2.2 skrll } 2353 1.2.2.2 skrll else 2354 1.2.2.2 skrll KASSERT((t->flags & MVXPE_TX_CMD_F) == 0); 2355 1.2.2.2 skrll tx->tx_dma = tx_counter_adv(tx->tx_dma, 1); 2356 1.2.2.2 skrll tx->tx_used--; 2357 1.2.2.2 skrll if (error) 2358 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txqe[q]); 2359 1.2.2.2 skrll else 2360 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txq[q]); 2361 1.2.2.2 skrll } 2362 1.2.2.2 skrll KASSERT(tx->tx_used >= 0); 2363 1.2.2.2 skrll KASSERT(tx->tx_used <= tx->tx_queue_len); 2364 1.2.2.2 skrll while (ndesc > 255) { 2365 1.2.2.2 skrll ptxsu = MVXPE_PTXSU_NORB(255); 2366 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2367 1.2.2.2 skrll ndesc -= 255; 2368 1.2.2.2 skrll } 2369 1.2.2.2 skrll if (ndesc > 0) { 2370 1.2.2.2 skrll ptxsu = MVXPE_PTXSU_NORB(ndesc); 2371 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2372 1.2.2.2 skrll } 2373 1.2.2.2 skrll DPRINTSC(sc, 2, 2374 1.2.2.2 skrll "Tx complete q %d, tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2375 1.2.2.2 skrll q, tx->tx_cpu, tx->tx_dma, tx->tx_used); 2376 1.2.2.2 skrll } 2377 1.2.2.2 skrll 2378 1.2.2.2 skrll /* 2379 1.2.2.2 skrll * Rx Subroutines 2380 1.2.2.2 skrll */ 2381 1.2.2.2 skrll STATIC void 2382 1.2.2.2 skrll mvxpe_rx(struct mvxpe_softc *sc, uint32_t queues) 2383 1.2.2.2 skrll { 2384 1.2.2.2 skrll int q, npkt; 2385 1.2.2.2 skrll 2386 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2387 1.2.2.2 skrll 2388 1.2.2.2 skrll while ( (npkt = mvxpe_rx_queue_select(sc, queues, &q))) { 2389 1.2.2.2 skrll /* mutex is held by rx_queue_select */ 2390 1.2.2.2 skrll mvxpe_rx_queue(sc, q, npkt); 2391 1.2.2.2 skrll mvxpe_rx_unlockq(sc, q); 2392 1.2.2.2 skrll } 2393 1.2.2.2 skrll } 2394 1.2.2.2 skrll 2395 1.2.2.2 skrll STATIC void 2396 1.2.2.2 skrll mvxpe_rx_queue(struct mvxpe_softc *sc, int q, int npkt) 2397 1.2.2.2 skrll { 2398 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2399 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2400 1.2.2.2 skrll struct mvxpe_rx_desc *r; 2401 1.2.2.2 skrll struct mvxpbm_chunk *chunk; 2402 1.2.2.2 skrll struct mbuf *m; 2403 1.2.2.2 skrll uint32_t prxsu; 2404 1.2.2.2 skrll int error = 0; 2405 1.2.2.2 skrll int i; 2406 1.2.2.2 skrll 2407 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 2408 1.2.2.2 skrll 2409 1.2.2.2 skrll mvxpe_ring_sync_rx(sc, q, rx->rx_dma, npkt, 2410 1.2.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2411 1.2.2.2 skrll 2412 1.2.2.2 skrll for (i = 0; i < npkt; i++) { 2413 1.2.2.2 skrll /* get descriptor and packet */ 2414 1.2.2.2 skrll chunk = MVXPE_RX_PKTBUF(sc, q, rx->rx_dma); 2415 1.2.2.2 skrll MVXPE_RX_PKTBUF(sc, q, rx->rx_dma) = NULL; 2416 1.2.2.2 skrll r = MVXPE_RX_DESC(sc, q, rx->rx_dma); 2417 1.2.2.2 skrll mvxpbm_dmamap_sync(chunk, r->bytecnt, BUS_DMASYNC_POSTREAD); 2418 1.2.2.2 skrll 2419 1.2.2.2 skrll /* check errors */ 2420 1.2.2.2 skrll if (r->status & MVXPE_RX_ES) { 2421 1.2.2.2 skrll switch (r->status & MVXPE_RX_EC_MASK) { 2422 1.2.2.2 skrll case MVXPE_RX_EC_CE: 2423 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "CRC error\n"); 2424 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_ce); 2425 1.2.2.2 skrll break; 2426 1.2.2.2 skrll case MVXPE_RX_EC_OR: 2427 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "Rx FIFO overrun\n"); 2428 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_or); 2429 1.2.2.2 skrll break; 2430 1.2.2.2 skrll case MVXPE_RX_EC_MF: 2431 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "Rx too large frame\n"); 2432 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_mf); 2433 1.2.2.2 skrll break; 2434 1.2.2.2 skrll case MVXPE_RX_EC_RE: 2435 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "Rx resource error\n"); 2436 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_re); 2437 1.2.2.2 skrll break; 2438 1.2.2.2 skrll } 2439 1.2.2.2 skrll error = 1; 2440 1.2.2.2 skrll goto rx_done; 2441 1.2.2.2 skrll } 2442 1.2.2.2 skrll if (!(r->status & MVXPE_RX_F) || !(r->status & MVXPE_RX_L)) { 2443 1.2.2.2 skrll DPRINTIFNET(ifp, 1, "not support scatter buf\n"); 2444 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_scat); 2445 1.2.2.2 skrll error = 1; 2446 1.2.2.2 skrll goto rx_done; 2447 1.2.2.2 skrll } 2448 1.2.2.2 skrll 2449 1.2.2.2 skrll if (chunk == NULL) { 2450 1.2.2.2 skrll device_printf(sc->sc_dev, 2451 1.2.2.2 skrll "got rx interrupt, but no chunk\n"); 2452 1.2.2.2 skrll error = 1; 2453 1.2.2.2 skrll goto rx_done; 2454 1.2.2.2 skrll } 2455 1.2.2.2 skrll 2456 1.2.2.2 skrll /* extract packet buffer */ 2457 1.2.2.2 skrll if (mvxpbm_init_mbuf_hdr(chunk) != 0) { 2458 1.2.2.2 skrll error = 1; 2459 1.2.2.2 skrll goto rx_done; 2460 1.2.2.2 skrll } 2461 1.2.2.2 skrll m = chunk->m; 2462 1.2.2.4 skrll m_set_rcvif(m, ifp); 2463 1.2.2.2 skrll m->m_pkthdr.len = m->m_len = r->bytecnt - ETHER_CRC_LEN; 2464 1.2.2.2 skrll m_adj(m, MVXPE_HWHEADER_SIZE); /* strip MH */ 2465 1.2.2.2 skrll mvxpe_rx_set_csumflag(ifp, r, m); 2466 1.2.2.2 skrll ifp->if_ipackets++; 2467 1.2.2.2 skrll bpf_mtap(ifp, m); 2468 1.2.2.3 skrll if_percpuq_enqueue(ifp->if_percpuq, m); 2469 1.2.2.2 skrll chunk = NULL; /* the BM chunk goes to networking stack now */ 2470 1.2.2.2 skrll rx_done: 2471 1.2.2.2 skrll if (chunk) { 2472 1.2.2.2 skrll /* rx error. just return the chunk to BM. */ 2473 1.2.2.2 skrll mvxpbm_free_chunk(chunk); 2474 1.2.2.2 skrll } 2475 1.2.2.2 skrll if (error) 2476 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxqe[q]); 2477 1.2.2.2 skrll else 2478 1.2.2.2 skrll MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxq[q]); 2479 1.2.2.2 skrll rx->rx_dma = rx_counter_adv(rx->rx_dma, 1); 2480 1.2.2.2 skrll } 2481 1.2.2.2 skrll /* DMA status update */ 2482 1.2.2.2 skrll DPRINTSC(sc, 2, "%d packets received from queue %d\n", npkt, q); 2483 1.2.2.2 skrll while (npkt > 255) { 2484 1.2.2.2 skrll prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2485 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2486 1.2.2.2 skrll npkt -= 255; 2487 1.2.2.2 skrll } 2488 1.2.2.2 skrll if (npkt > 0) { 2489 1.2.2.2 skrll prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(npkt); 2490 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2491 1.2.2.2 skrll } 2492 1.2.2.2 skrll 2493 1.2.2.2 skrll DPRINTSC(sc, 2, 2494 1.2.2.2 skrll "PRXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQA(q))); 2495 1.2.2.2 skrll DPRINTSC(sc, 2, 2496 1.2.2.2 skrll "PRXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 2497 1.2.2.2 skrll DPRINTSC(sc, 2, 2498 1.2.2.2 skrll "PRXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXS(q))); 2499 1.2.2.2 skrll DPRINTSC(sc, 2, 2500 1.2.2.2 skrll "PRXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PRXDI(q))); 2501 1.2.2.2 skrll DPRINTSC(sc, 2, "RQC: %#x\n", MVXPE_READ(sc, MVXPE_RQC)); 2502 1.2.2.2 skrll DPRINTIFNET(ifp, 2, "Rx: rx_cpu = %d, rx_dma = %d\n", 2503 1.2.2.2 skrll rx->rx_cpu, rx->rx_dma); 2504 1.2.2.2 skrll } 2505 1.2.2.2 skrll 2506 1.2.2.2 skrll STATIC int 2507 1.2.2.2 skrll mvxpe_rx_queue_select(struct mvxpe_softc *sc, uint32_t queues, int *queue) 2508 1.2.2.2 skrll { 2509 1.2.2.2 skrll uint32_t prxs, npkt; 2510 1.2.2.2 skrll int q; 2511 1.2.2.2 skrll 2512 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2513 1.2.2.2 skrll KASSERT(queue != NULL); 2514 1.2.2.2 skrll DPRINTSC(sc, 2, "selecting rx queue\n"); 2515 1.2.2.2 skrll 2516 1.2.2.2 skrll for (q = MVXPE_QUEUE_SIZE - 1; q >= 0; q--) { 2517 1.2.2.2 skrll if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2518 1.2.2.2 skrll continue; 2519 1.2.2.2 skrll 2520 1.2.2.2 skrll prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2521 1.2.2.2 skrll npkt = MVXPE_PRXS_GET_ODC(prxs); 2522 1.2.2.2 skrll if (npkt == 0) 2523 1.2.2.2 skrll continue; 2524 1.2.2.2 skrll 2525 1.2.2.2 skrll DPRINTSC(sc, 2, 2526 1.2.2.2 skrll "queue %d selected: prxs=%#x, %u pakcet received.\n", 2527 1.2.2.2 skrll q, prxs, npkt); 2528 1.2.2.2 skrll *queue = q; 2529 1.2.2.2 skrll mvxpe_rx_lockq(sc, q); 2530 1.2.2.2 skrll return npkt; 2531 1.2.2.2 skrll } 2532 1.2.2.2 skrll 2533 1.2.2.2 skrll return 0; 2534 1.2.2.2 skrll } 2535 1.2.2.2 skrll 2536 1.2.2.2 skrll STATIC void 2537 1.2.2.2 skrll mvxpe_rx_refill(struct mvxpe_softc *sc, uint32_t queues) 2538 1.2.2.2 skrll { 2539 1.2.2.2 skrll int q; 2540 1.2.2.2 skrll 2541 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2542 1.2.2.2 skrll 2543 1.2.2.2 skrll /* XXX: check rx bit array */ 2544 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2545 1.2.2.2 skrll if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2546 1.2.2.2 skrll continue; 2547 1.2.2.2 skrll 2548 1.2.2.2 skrll mvxpe_rx_lockq(sc, q); 2549 1.2.2.2 skrll mvxpe_rx_queue_refill(sc, q); 2550 1.2.2.2 skrll mvxpe_rx_unlockq(sc, q); 2551 1.2.2.2 skrll } 2552 1.2.2.2 skrll } 2553 1.2.2.2 skrll 2554 1.2.2.2 skrll STATIC void 2555 1.2.2.2 skrll mvxpe_rx_queue_refill(struct mvxpe_softc *sc, int q) 2556 1.2.2.2 skrll { 2557 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2558 1.2.2.2 skrll uint32_t prxs, prxsu, ndesc; 2559 1.2.2.2 skrll int idx, refill = 0; 2560 1.2.2.2 skrll int npkt; 2561 1.2.2.2 skrll 2562 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 2563 1.2.2.2 skrll 2564 1.2.2.2 skrll prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2565 1.2.2.2 skrll ndesc = MVXPE_PRXS_GET_NODC(prxs) + MVXPE_PRXS_GET_ODC(prxs); 2566 1.2.2.2 skrll refill = rx->rx_queue_len - ndesc; 2567 1.2.2.2 skrll if (refill <= 0) 2568 1.2.2.2 skrll return; 2569 1.2.2.2 skrll DPRINTPRXS(2, q); 2570 1.2.2.2 skrll DPRINTSC(sc, 2, "%d buffers to refill.\n", refill); 2571 1.2.2.2 skrll 2572 1.2.2.2 skrll idx = rx->rx_cpu; 2573 1.2.2.2 skrll for (npkt = 0; npkt < refill; npkt++) 2574 1.2.2.2 skrll if (mvxpe_rx_queue_add(sc, q) != 0) 2575 1.2.2.2 skrll break; 2576 1.2.2.2 skrll DPRINTSC(sc, 2, "queue %d, %d buffer refilled.\n", q, npkt); 2577 1.2.2.2 skrll if (npkt == 0) 2578 1.2.2.2 skrll return; 2579 1.2.2.2 skrll 2580 1.2.2.2 skrll mvxpe_ring_sync_rx(sc, q, idx, npkt, 2581 1.2.2.2 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2582 1.2.2.2 skrll 2583 1.2.2.2 skrll while (npkt > 255) { 2584 1.2.2.2 skrll prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(255); 2585 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2586 1.2.2.2 skrll npkt -= 255; 2587 1.2.2.2 skrll } 2588 1.2.2.2 skrll if (npkt > 0) { 2589 1.2.2.2 skrll prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(npkt); 2590 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2591 1.2.2.2 skrll } 2592 1.2.2.2 skrll DPRINTPRXS(2, q); 2593 1.2.2.2 skrll return; 2594 1.2.2.2 skrll } 2595 1.2.2.2 skrll 2596 1.2.2.2 skrll STATIC int 2597 1.2.2.2 skrll mvxpe_rx_queue_add(struct mvxpe_softc *sc, int q) 2598 1.2.2.2 skrll { 2599 1.2.2.2 skrll struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2600 1.2.2.2 skrll struct mvxpe_rx_desc *r; 2601 1.2.2.2 skrll struct mvxpbm_chunk *chunk = NULL; 2602 1.2.2.2 skrll 2603 1.2.2.2 skrll KASSERT_RX_MTX(sc, q); 2604 1.2.2.2 skrll 2605 1.2.2.2 skrll /* Allocate the packet buffer */ 2606 1.2.2.2 skrll chunk = mvxpbm_alloc(sc->sc_bm); 2607 1.2.2.2 skrll if (chunk == NULL) { 2608 1.2.2.2 skrll DPRINTSC(sc, 1, "BM chunk allocation failed.\n"); 2609 1.2.2.2 skrll return ENOBUFS; 2610 1.2.2.2 skrll } 2611 1.2.2.2 skrll 2612 1.2.2.2 skrll /* Add the packet to descritor */ 2613 1.2.2.2 skrll KASSERT(MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) == NULL); 2614 1.2.2.2 skrll MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) = chunk; 2615 1.2.2.2 skrll mvxpbm_dmamap_sync(chunk, BM_SYNC_ALL, BUS_DMASYNC_PREREAD); 2616 1.2.2.2 skrll 2617 1.2.2.2 skrll r = MVXPE_RX_DESC(sc, q, rx->rx_cpu); 2618 1.2.2.2 skrll r->bufptr = chunk->buf_pa; 2619 1.2.2.2 skrll DPRINTSC(sc, 9, "chunk added to index %d\n", rx->rx_cpu); 2620 1.2.2.2 skrll rx->rx_cpu = rx_counter_adv(rx->rx_cpu, 1); 2621 1.2.2.2 skrll return 0; 2622 1.2.2.2 skrll } 2623 1.2.2.2 skrll 2624 1.2.2.2 skrll STATIC void 2625 1.2.2.2 skrll mvxpe_rx_set_csumflag(struct ifnet *ifp, 2626 1.2.2.2 skrll struct mvxpe_rx_desc *r, struct mbuf *m0) 2627 1.2.2.2 skrll { 2628 1.2.2.2 skrll uint32_t csum_flags = 0; 2629 1.2.2.2 skrll 2630 1.2.2.2 skrll if ((r->status & (MVXPE_RX_IP_HEADER_OK|MVXPE_RX_L3_IP)) == 0) 2631 1.2.2.2 skrll return; /* not a IP packet */ 2632 1.2.2.2 skrll 2633 1.2.2.2 skrll /* L3 */ 2634 1.2.2.2 skrll if (r->status & MVXPE_RX_L3_IP) { 2635 1.2.2.3 skrll csum_flags |= M_CSUM_IPv4 & ifp->if_csum_flags_rx; 2636 1.2.2.3 skrll if ((r->status & MVXPE_RX_IP_HEADER_OK) == 0 && 2637 1.2.2.3 skrll (csum_flags & M_CSUM_IPv4) != 0) { 2638 1.2.2.2 skrll csum_flags |= M_CSUM_IPv4_BAD; 2639 1.2.2.2 skrll goto finish; 2640 1.2.2.2 skrll } 2641 1.2.2.2 skrll else if (r->status & MVXPE_RX_IPV4_FRAGMENT) { 2642 1.2.2.2 skrll /* 2643 1.2.2.2 skrll * r->l4chk has partial checksum of each framgment. 2644 1.2.2.2 skrll * but there is no way to use it in NetBSD. 2645 1.2.2.2 skrll */ 2646 1.2.2.2 skrll return; 2647 1.2.2.2 skrll } 2648 1.2.2.2 skrll } 2649 1.2.2.2 skrll 2650 1.2.2.2 skrll /* L4 */ 2651 1.2.2.2 skrll switch (r->status & MVXPE_RX_L4_MASK) { 2652 1.2.2.2 skrll case MVXPE_RX_L4_TCP: 2653 1.2.2.2 skrll if (r->status & MVXPE_RX_L3_IP) 2654 1.2.2.3 skrll csum_flags |= M_CSUM_TCPv4 & ifp->if_csum_flags_rx; 2655 1.2.2.2 skrll else 2656 1.2.2.3 skrll csum_flags |= M_CSUM_TCPv6 & ifp->if_csum_flags_rx; 2657 1.2.2.2 skrll break; 2658 1.2.2.2 skrll case MVXPE_RX_L4_UDP: 2659 1.2.2.2 skrll if (r->status & MVXPE_RX_L3_IP) 2660 1.2.2.3 skrll csum_flags |= M_CSUM_UDPv4 & ifp->if_csum_flags_rx; 2661 1.2.2.2 skrll else 2662 1.2.2.3 skrll csum_flags |= M_CSUM_UDPv6 & ifp->if_csum_flags_rx; 2663 1.2.2.2 skrll break; 2664 1.2.2.2 skrll case MVXPE_RX_L4_OTH: 2665 1.2.2.2 skrll default: 2666 1.2.2.2 skrll break; 2667 1.2.2.2 skrll } 2668 1.2.2.3 skrll if ((r->status & MVXPE_RX_L4_CHECKSUM_OK) == 0 && (csum_flags & 2669 1.2.2.3 skrll (M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2670 1.2.2.3 skrll csum_flags |= M_CSUM_TCP_UDP_BAD; 2671 1.2.2.2 skrll finish: 2672 1.2.2.3 skrll m0->m_pkthdr.csum_flags = csum_flags; 2673 1.2.2.2 skrll } 2674 1.2.2.2 skrll 2675 1.2.2.2 skrll /* 2676 1.2.2.2 skrll * MAC address filter 2677 1.2.2.2 skrll */ 2678 1.2.2.2 skrll STATIC uint8_t 2679 1.2.2.2 skrll mvxpe_crc8(const uint8_t *data, size_t size) 2680 1.2.2.2 skrll { 2681 1.2.2.2 skrll int bit; 2682 1.2.2.2 skrll uint8_t byte; 2683 1.2.2.2 skrll uint8_t crc = 0; 2684 1.2.2.2 skrll const uint8_t poly = 0x07; 2685 1.2.2.2 skrll 2686 1.2.2.2 skrll while(size--) 2687 1.2.2.2 skrll for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2688 1.2.2.2 skrll crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2689 1.2.2.2 skrll 2690 1.2.2.2 skrll return crc; 2691 1.2.2.2 skrll } 2692 1.2.2.2 skrll 2693 1.2.2.2 skrll CTASSERT(MVXPE_NDFSMT == MVXPE_NDFOMT); 2694 1.2.2.2 skrll 2695 1.2.2.2 skrll STATIC void 2696 1.2.2.2 skrll mvxpe_filter_setup(struct mvxpe_softc *sc) 2697 1.2.2.2 skrll { 2698 1.2.2.2 skrll struct ethercom *ec = &sc->sc_ethercom; 2699 1.2.2.2 skrll struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2700 1.2.2.2 skrll struct ether_multi *enm; 2701 1.2.2.2 skrll struct ether_multistep step; 2702 1.2.2.2 skrll uint32_t dfut[MVXPE_NDFUT], dfsmt[MVXPE_NDFSMT], dfomt[MVXPE_NDFOMT]; 2703 1.2.2.2 skrll uint32_t pxc; 2704 1.2.2.2 skrll int i; 2705 1.2.2.2 skrll const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2706 1.2.2.2 skrll 2707 1.2.2.2 skrll KASSERT_SC_MTX(sc); 2708 1.2.2.2 skrll 2709 1.2.2.2 skrll memset(dfut, 0, sizeof(dfut)); 2710 1.2.2.2 skrll memset(dfsmt, 0, sizeof(dfsmt)); 2711 1.2.2.2 skrll memset(dfomt, 0, sizeof(dfomt)); 2712 1.2.2.2 skrll 2713 1.2.2.2 skrll if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2714 1.2.2.2 skrll goto allmulti; 2715 1.2.2.2 skrll } 2716 1.2.2.2 skrll 2717 1.2.2.2 skrll ETHER_FIRST_MULTI(step, ec, enm); 2718 1.2.2.2 skrll while (enm != NULL) { 2719 1.2.2.2 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2720 1.2.2.2 skrll /* ranges are complex and somewhat rare */ 2721 1.2.2.2 skrll goto allmulti; 2722 1.2.2.2 skrll } 2723 1.2.2.2 skrll /* chip handles some IPv4 multicast specially */ 2724 1.2.2.2 skrll if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2725 1.2.2.2 skrll i = enm->enm_addrlo[5]; 2726 1.2.2.2 skrll dfsmt[i>>2] |= 2727 1.2.2.3 skrll MVXPE_DF(i&3, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS); 2728 1.2.2.2 skrll } else { 2729 1.2.2.2 skrll i = mvxpe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2730 1.2.2.2 skrll dfomt[i>>2] |= 2731 1.2.2.3 skrll MVXPE_DF(i&3, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS); 2732 1.2.2.2 skrll } 2733 1.2.2.2 skrll 2734 1.2.2.2 skrll ETHER_NEXT_MULTI(step, enm); 2735 1.2.2.2 skrll } 2736 1.2.2.2 skrll goto set; 2737 1.2.2.2 skrll 2738 1.2.2.2 skrll allmulti: 2739 1.2.2.2 skrll if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2740 1.2.2.2 skrll for (i = 0; i < MVXPE_NDFSMT; i++) { 2741 1.2.2.2 skrll dfsmt[i] = dfomt[i] = 2742 1.2.2.3 skrll MVXPE_DF(0, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS) | 2743 1.2.2.3 skrll MVXPE_DF(1, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS) | 2744 1.2.2.3 skrll MVXPE_DF(2, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS) | 2745 1.2.2.3 skrll MVXPE_DF(3, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS); 2746 1.2.2.2 skrll } 2747 1.2.2.2 skrll } 2748 1.2.2.2 skrll 2749 1.2.2.2 skrll set: 2750 1.2.2.2 skrll pxc = MVXPE_READ(sc, MVXPE_PXC); 2751 1.2.2.2 skrll pxc &= ~MVXPE_PXC_UPM; 2752 1.2.2.2 skrll pxc |= MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP; 2753 1.2.2.2 skrll if (ifp->if_flags & IFF_BROADCAST) { 2754 1.2.2.2 skrll pxc &= ~(MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP); 2755 1.2.2.2 skrll } 2756 1.2.2.2 skrll if (ifp->if_flags & IFF_PROMISC) { 2757 1.2.2.2 skrll pxc |= MVXPE_PXC_UPM; 2758 1.2.2.2 skrll } 2759 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PXC, pxc); 2760 1.2.2.2 skrll 2761 1.2.2.2 skrll /* Set Destination Address Filter Unicast Table */ 2762 1.2.2.3 skrll if (ifp->if_flags & IFF_PROMISC) { 2763 1.2.2.3 skrll /* pass all unicast addresses */ 2764 1.2.2.3 skrll for (i = 0; i < MVXPE_NDFUT; i++) { 2765 1.2.2.3 skrll dfut[i] = 2766 1.2.2.3 skrll MVXPE_DF(0, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS) | 2767 1.2.2.3 skrll MVXPE_DF(1, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS) | 2768 1.2.2.3 skrll MVXPE_DF(2, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS) | 2769 1.2.2.3 skrll MVXPE_DF(3, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS); 2770 1.2.2.3 skrll } 2771 1.2.2.3 skrll } 2772 1.2.2.3 skrll else { 2773 1.2.2.3 skrll i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2774 1.2.2.3 skrll dfut[i>>2] = MVXPE_DF(i&3, MVXPE_DF_QUEUE(0) | MVXPE_DF_PASS); 2775 1.2.2.3 skrll } 2776 1.2.2.2 skrll MVXPE_WRITE_REGION(sc, MVXPE_DFUT(0), dfut, MVXPE_NDFUT); 2777 1.2.2.2 skrll 2778 1.2.2.2 skrll /* Set Destination Address Filter Multicast Tables */ 2779 1.2.2.2 skrll MVXPE_WRITE_REGION(sc, MVXPE_DFSMT(0), dfsmt, MVXPE_NDFSMT); 2780 1.2.2.2 skrll MVXPE_WRITE_REGION(sc, MVXPE_DFOMT(0), dfomt, MVXPE_NDFOMT); 2781 1.2.2.2 skrll } 2782 1.2.2.2 skrll 2783 1.2.2.2 skrll /* 2784 1.2.2.2 skrll * sysctl(9) 2785 1.2.2.2 skrll */ 2786 1.2.2.2 skrll SYSCTL_SETUP(sysctl_mvxpe, "sysctl mvxpe subtree setup") 2787 1.2.2.2 skrll { 2788 1.2.2.2 skrll int rc; 2789 1.2.2.2 skrll const struct sysctlnode *node; 2790 1.2.2.2 skrll 2791 1.2.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 2792 1.2.2.2 skrll 0, CTLTYPE_NODE, "mvxpe", 2793 1.2.2.2 skrll SYSCTL_DESCR("mvxpe interface controls"), 2794 1.2.2.2 skrll NULL, 0, NULL, 0, 2795 1.2.2.2 skrll CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2796 1.2.2.2 skrll goto err; 2797 1.2.2.2 skrll } 2798 1.2.2.2 skrll 2799 1.2.2.2 skrll mvxpe_root_num = node->sysctl_num; 2800 1.2.2.2 skrll return; 2801 1.2.2.2 skrll 2802 1.2.2.2 skrll err: 2803 1.2.2.2 skrll aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2804 1.2.2.2 skrll } 2805 1.2.2.2 skrll 2806 1.2.2.2 skrll STATIC int 2807 1.2.2.2 skrll sysctl_read_mib(SYSCTLFN_ARGS) 2808 1.2.2.2 skrll { 2809 1.2.2.2 skrll struct mvxpe_sysctl_mib *arg; 2810 1.2.2.2 skrll struct mvxpe_softc *sc; 2811 1.2.2.2 skrll struct sysctlnode node; 2812 1.2.2.2 skrll uint64_t val; 2813 1.2.2.2 skrll int err; 2814 1.2.2.2 skrll 2815 1.2.2.2 skrll node = *rnode; 2816 1.2.2.2 skrll arg = (struct mvxpe_sysctl_mib *)rnode->sysctl_data; 2817 1.2.2.2 skrll if (arg == NULL) 2818 1.2.2.2 skrll return EINVAL; 2819 1.2.2.2 skrll 2820 1.2.2.2 skrll sc = arg->sc; 2821 1.2.2.2 skrll if (sc == NULL) 2822 1.2.2.2 skrll return EINVAL; 2823 1.2.2.2 skrll if (arg->index < 0 || arg->index > __arraycount(mvxpe_mib_list)) 2824 1.2.2.2 skrll return EINVAL; 2825 1.2.2.2 skrll 2826 1.2.2.2 skrll mvxpe_sc_lock(sc); 2827 1.2.2.2 skrll val = arg->counter; 2828 1.2.2.2 skrll mvxpe_sc_unlock(sc); 2829 1.2.2.2 skrll 2830 1.2.2.2 skrll node.sysctl_data = &val; 2831 1.2.2.2 skrll err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2832 1.2.2.2 skrll if (err) 2833 1.2.2.2 skrll return err; 2834 1.2.2.2 skrll if (newp) 2835 1.2.2.2 skrll return EINVAL; 2836 1.2.2.2 skrll 2837 1.2.2.2 skrll return 0; 2838 1.2.2.2 skrll } 2839 1.2.2.2 skrll 2840 1.2.2.2 skrll 2841 1.2.2.2 skrll STATIC int 2842 1.2.2.2 skrll sysctl_clear_mib(SYSCTLFN_ARGS) 2843 1.2.2.2 skrll { 2844 1.2.2.2 skrll struct mvxpe_softc *sc; 2845 1.2.2.2 skrll struct sysctlnode node; 2846 1.2.2.2 skrll int val; 2847 1.2.2.2 skrll int err; 2848 1.2.2.2 skrll 2849 1.2.2.2 skrll node = *rnode; 2850 1.2.2.2 skrll sc = (struct mvxpe_softc *)rnode->sysctl_data; 2851 1.2.2.2 skrll if (sc == NULL) 2852 1.2.2.2 skrll return EINVAL; 2853 1.2.2.2 skrll 2854 1.2.2.2 skrll val = 0; 2855 1.2.2.2 skrll node.sysctl_data = &val; 2856 1.2.2.2 skrll err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2857 1.2.2.2 skrll if (err || newp == NULL) 2858 1.2.2.2 skrll return err; 2859 1.2.2.2 skrll if (val < 0 || val > 1) 2860 1.2.2.2 skrll return EINVAL; 2861 1.2.2.2 skrll if (val == 1) { 2862 1.2.2.2 skrll mvxpe_sc_lock(sc); 2863 1.2.2.2 skrll mvxpe_clear_mib(sc); 2864 1.2.2.2 skrll mvxpe_sc_unlock(sc); 2865 1.2.2.2 skrll } 2866 1.2.2.2 skrll 2867 1.2.2.2 skrll return 0; 2868 1.2.2.2 skrll } 2869 1.2.2.2 skrll 2870 1.2.2.2 skrll STATIC int 2871 1.2.2.2 skrll sysctl_set_queue_length(SYSCTLFN_ARGS) 2872 1.2.2.2 skrll { 2873 1.2.2.2 skrll struct mvxpe_sysctl_queue *arg; 2874 1.2.2.2 skrll struct mvxpe_rx_ring *rx = NULL; 2875 1.2.2.2 skrll struct mvxpe_tx_ring *tx = NULL; 2876 1.2.2.2 skrll struct mvxpe_softc *sc; 2877 1.2.2.2 skrll struct sysctlnode node; 2878 1.2.2.2 skrll uint32_t reg; 2879 1.2.2.2 skrll int val; 2880 1.2.2.2 skrll int err; 2881 1.2.2.2 skrll 2882 1.2.2.2 skrll node = *rnode; 2883 1.2.2.2 skrll 2884 1.2.2.2 skrll arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2885 1.2.2.2 skrll if (arg == NULL) 2886 1.2.2.2 skrll return EINVAL; 2887 1.2.2.2 skrll if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2888 1.2.2.2 skrll return EINVAL; 2889 1.2.2.2 skrll if (arg->rxtx != MVXPE_SYSCTL_RX && arg->rxtx != MVXPE_SYSCTL_TX) 2890 1.2.2.2 skrll return EINVAL; 2891 1.2.2.2 skrll 2892 1.2.2.2 skrll sc = arg->sc; 2893 1.2.2.2 skrll if (sc == NULL) 2894 1.2.2.2 skrll return EINVAL; 2895 1.2.2.2 skrll 2896 1.2.2.2 skrll /* read queue length */ 2897 1.2.2.2 skrll mvxpe_sc_lock(sc); 2898 1.2.2.2 skrll switch (arg->rxtx) { 2899 1.2.2.2 skrll case MVXPE_SYSCTL_RX: 2900 1.2.2.2 skrll mvxpe_rx_lockq(sc, arg->queue); 2901 1.2.2.2 skrll rx = MVXPE_RX_RING(sc, arg->queue); 2902 1.2.2.2 skrll val = rx->rx_queue_len; 2903 1.2.2.2 skrll mvxpe_rx_unlockq(sc, arg->queue); 2904 1.2.2.2 skrll break; 2905 1.2.2.2 skrll case MVXPE_SYSCTL_TX: 2906 1.2.2.2 skrll mvxpe_tx_lockq(sc, arg->queue); 2907 1.2.2.2 skrll tx = MVXPE_TX_RING(sc, arg->queue); 2908 1.2.2.2 skrll val = tx->tx_queue_len; 2909 1.2.2.2 skrll mvxpe_tx_unlockq(sc, arg->queue); 2910 1.2.2.2 skrll break; 2911 1.2.2.2 skrll } 2912 1.2.2.2 skrll 2913 1.2.2.2 skrll node.sysctl_data = &val; 2914 1.2.2.2 skrll err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2915 1.2.2.2 skrll if (err || newp == NULL) { 2916 1.2.2.2 skrll mvxpe_sc_unlock(sc); 2917 1.2.2.2 skrll return err; 2918 1.2.2.2 skrll } 2919 1.2.2.2 skrll 2920 1.2.2.2 skrll /* update queue length */ 2921 1.2.2.2 skrll if (val < 8 || val > MVXPE_RX_RING_CNT) { 2922 1.2.2.2 skrll mvxpe_sc_unlock(sc); 2923 1.2.2.2 skrll return EINVAL; 2924 1.2.2.2 skrll } 2925 1.2.2.2 skrll switch (arg->rxtx) { 2926 1.2.2.2 skrll case MVXPE_SYSCTL_RX: 2927 1.2.2.2 skrll mvxpe_rx_lockq(sc, arg->queue); 2928 1.2.2.2 skrll rx->rx_queue_len = val; 2929 1.2.2.2 skrll rx->rx_queue_th_received = 2930 1.2.2.2 skrll rx->rx_queue_len / MVXPE_RXTH_RATIO; 2931 1.2.2.2 skrll rx->rx_queue_th_free = 2932 1.2.2.2 skrll rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 2933 1.2.2.2 skrll 2934 1.2.2.2 skrll reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 2935 1.2.2.2 skrll reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 2936 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXDQTH(arg->queue), reg); 2937 1.2.2.2 skrll 2938 1.2.2.2 skrll mvxpe_rx_unlockq(sc, arg->queue); 2939 1.2.2.2 skrll break; 2940 1.2.2.2 skrll case MVXPE_SYSCTL_TX: 2941 1.2.2.2 skrll mvxpe_tx_lockq(sc, arg->queue); 2942 1.2.2.2 skrll tx->tx_queue_len = val; 2943 1.2.2.2 skrll tx->tx_queue_th_free = 2944 1.2.2.2 skrll tx->tx_queue_len / MVXPE_TXTH_RATIO; 2945 1.2.2.2 skrll 2946 1.2.2.2 skrll reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 2947 1.2.2.2 skrll reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 2948 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PTXDQS(arg->queue), reg); 2949 1.2.2.2 skrll 2950 1.2.2.2 skrll mvxpe_tx_unlockq(sc, arg->queue); 2951 1.2.2.2 skrll break; 2952 1.2.2.2 skrll } 2953 1.2.2.2 skrll mvxpe_sc_unlock(sc); 2954 1.2.2.2 skrll 2955 1.2.2.2 skrll return 0; 2956 1.2.2.2 skrll } 2957 1.2.2.2 skrll 2958 1.2.2.2 skrll STATIC int 2959 1.2.2.2 skrll sysctl_set_queue_rxthtime(SYSCTLFN_ARGS) 2960 1.2.2.2 skrll { 2961 1.2.2.2 skrll struct mvxpe_sysctl_queue *arg; 2962 1.2.2.2 skrll struct mvxpe_rx_ring *rx = NULL; 2963 1.2.2.2 skrll struct mvxpe_softc *sc; 2964 1.2.2.2 skrll struct sysctlnode node; 2965 1.2.2.2 skrll extern uint32_t mvTclk; 2966 1.2.2.2 skrll uint32_t reg, time_mvtclk; 2967 1.2.2.2 skrll int time_us; 2968 1.2.2.2 skrll int err; 2969 1.2.2.2 skrll 2970 1.2.2.2 skrll node = *rnode; 2971 1.2.2.2 skrll 2972 1.2.2.2 skrll arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2973 1.2.2.2 skrll if (arg == NULL) 2974 1.2.2.2 skrll return EINVAL; 2975 1.2.2.2 skrll if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2976 1.2.2.2 skrll return EINVAL; 2977 1.2.2.2 skrll if (arg->rxtx != MVXPE_SYSCTL_RX) 2978 1.2.2.2 skrll return EINVAL; 2979 1.2.2.2 skrll 2980 1.2.2.2 skrll sc = arg->sc; 2981 1.2.2.2 skrll if (sc == NULL) 2982 1.2.2.2 skrll return EINVAL; 2983 1.2.2.2 skrll 2984 1.2.2.2 skrll /* read queue length */ 2985 1.2.2.2 skrll mvxpe_sc_lock(sc); 2986 1.2.2.2 skrll mvxpe_rx_lockq(sc, arg->queue); 2987 1.2.2.2 skrll rx = MVXPE_RX_RING(sc, arg->queue); 2988 1.2.2.2 skrll time_mvtclk = rx->rx_queue_th_time; 2989 1.2.2.2 skrll time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvTclk; 2990 1.2.2.2 skrll node.sysctl_data = &time_us; 2991 1.2.2.2 skrll DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", 2992 1.2.2.2 skrll arg->queue, MVXPE_READ(sc, MVXPE_PRXITTH(arg->queue))); 2993 1.2.2.2 skrll err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2994 1.2.2.2 skrll if (err || newp == NULL) { 2995 1.2.2.2 skrll mvxpe_rx_unlockq(sc, arg->queue); 2996 1.2.2.2 skrll mvxpe_sc_unlock(sc); 2997 1.2.2.2 skrll return err; 2998 1.2.2.2 skrll } 2999 1.2.2.2 skrll 3000 1.2.2.2 skrll /* update queue length (0[sec] - 1[sec]) */ 3001 1.2.2.2 skrll if (time_us < 0 || time_us > (1000 * 1000)) { 3002 1.2.2.2 skrll mvxpe_rx_unlockq(sc, arg->queue); 3003 1.2.2.2 skrll mvxpe_sc_unlock(sc); 3004 1.2.2.2 skrll return EINVAL; 3005 1.2.2.2 skrll } 3006 1.2.2.2 skrll time_mvtclk = 3007 1.2.2.2 skrll (uint64_t)mvTclk * (uint64_t)time_us / (1000ULL * 1000ULL); 3008 1.2.2.2 skrll rx->rx_queue_th_time = time_mvtclk; 3009 1.2.2.2 skrll reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 3010 1.2.2.2 skrll MVXPE_WRITE(sc, MVXPE_PRXITTH(arg->queue), reg); 3011 1.2.2.2 skrll DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", arg->queue, reg); 3012 1.2.2.2 skrll mvxpe_rx_unlockq(sc, arg->queue); 3013 1.2.2.2 skrll mvxpe_sc_unlock(sc); 3014 1.2.2.2 skrll 3015 1.2.2.2 skrll return 0; 3016 1.2.2.2 skrll } 3017 1.2.2.2 skrll 3018 1.2.2.2 skrll 3019 1.2.2.2 skrll STATIC void 3020 1.2.2.2 skrll sysctl_mvxpe_init(struct mvxpe_softc *sc) 3021 1.2.2.2 skrll { 3022 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3023 1.2.2.2 skrll const struct sysctlnode *node; 3024 1.2.2.2 skrll int mvxpe_nodenum; 3025 1.2.2.2 skrll int mvxpe_mibnum; 3026 1.2.2.2 skrll int mvxpe_rxqueuenum; 3027 1.2.2.2 skrll int mvxpe_txqueuenum; 3028 1.2.2.2 skrll int q, i; 3029 1.2.2.2 skrll 3030 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit] */ 3031 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3032 1.2.2.2 skrll 0, CTLTYPE_NODE, ifp->if_xname, 3033 1.2.2.2 skrll SYSCTL_DESCR("mvxpe per-controller controls"), 3034 1.2.2.2 skrll NULL, 0, NULL, 0, 3035 1.2.2.2 skrll CTL_HW, mvxpe_root_num, CTL_CREATE, 3036 1.2.2.2 skrll CTL_EOL) != 0) { 3037 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3038 1.2.2.2 skrll return; 3039 1.2.2.2 skrll } 3040 1.2.2.2 skrll mvxpe_nodenum = node->sysctl_num; 3041 1.2.2.2 skrll 3042 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].mib */ 3043 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3044 1.2.2.2 skrll 0, CTLTYPE_NODE, "mib", 3045 1.2.2.2 skrll SYSCTL_DESCR("mvxpe per-controller MIB counters"), 3046 1.2.2.2 skrll NULL, 0, NULL, 0, 3047 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3048 1.2.2.2 skrll CTL_EOL) != 0) { 3049 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3050 1.2.2.2 skrll return; 3051 1.2.2.2 skrll } 3052 1.2.2.2 skrll mvxpe_mibnum = node->sysctl_num; 3053 1.2.2.2 skrll 3054 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].rx */ 3055 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3056 1.2.2.2 skrll 0, CTLTYPE_NODE, "rx", 3057 1.2.2.2 skrll SYSCTL_DESCR("Rx Queues"), 3058 1.2.2.2 skrll NULL, 0, NULL, 0, 3059 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3060 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3061 1.2.2.2 skrll return; 3062 1.2.2.2 skrll } 3063 1.2.2.2 skrll mvxpe_rxqueuenum = node->sysctl_num; 3064 1.2.2.2 skrll 3065 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].tx */ 3066 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3067 1.2.2.2 skrll 0, CTLTYPE_NODE, "tx", 3068 1.2.2.2 skrll SYSCTL_DESCR("Tx Queues"), 3069 1.2.2.2 skrll NULL, 0, NULL, 0, 3070 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3071 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3072 1.2.2.2 skrll return; 3073 1.2.2.2 skrll } 3074 1.2.2.2 skrll mvxpe_txqueuenum = node->sysctl_num; 3075 1.2.2.2 skrll 3076 1.2.2.2 skrll #ifdef MVXPE_DEBUG 3077 1.2.2.2 skrll /* hw.mvxpe.debug */ 3078 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3079 1.2.2.2 skrll CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 3080 1.2.2.3 skrll SYSCTL_DESCR("mvxpe device driver debug control"), 3081 1.2.2.2 skrll NULL, 0, &mvxpe_debug, 0, 3082 1.2.2.2 skrll CTL_HW, mvxpe_root_num, CTL_CREATE, CTL_EOL) != 0) { 3083 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3084 1.2.2.2 skrll return; 3085 1.2.2.2 skrll } 3086 1.2.2.2 skrll #endif 3087 1.2.2.2 skrll /* 3088 1.2.2.2 skrll * MIB access 3089 1.2.2.2 skrll */ 3090 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].mib.<mibs> */ 3091 1.2.2.2 skrll for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3092 1.2.2.2 skrll const char *name = mvxpe_mib_list[i].sysctl_name; 3093 1.2.2.2 skrll const char *desc = mvxpe_mib_list[i].desc; 3094 1.2.2.2 skrll struct mvxpe_sysctl_mib *mib_arg = &sc->sc_sysctl_mib[i]; 3095 1.2.2.2 skrll 3096 1.2.2.2 skrll mib_arg->sc = sc; 3097 1.2.2.2 skrll mib_arg->index = i; 3098 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3099 1.2.2.2 skrll CTLFLAG_READONLY, CTLTYPE_QUAD, name, desc, 3100 1.2.2.2 skrll sysctl_read_mib, 0, (void *)mib_arg, 0, 3101 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_mibnum, 3102 1.2.2.2 skrll CTL_CREATE, CTL_EOL) != 0) { 3103 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 3104 1.2.2.2 skrll "couldn't create sysctl node\n"); 3105 1.2.2.2 skrll break; 3106 1.2.2.2 skrll } 3107 1.2.2.2 skrll } 3108 1.2.2.2 skrll 3109 1.2.2.2 skrll for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 3110 1.2.2.2 skrll struct mvxpe_sysctl_queue *rxarg = &sc->sc_sysctl_rx_queue[q]; 3111 1.2.2.2 skrll struct mvxpe_sysctl_queue *txarg = &sc->sc_sysctl_tx_queue[q]; 3112 1.2.2.2 skrll #define MVXPE_SYSCTL_NAME(num) "queue" # num 3113 1.2.2.2 skrll static const char *sysctl_queue_names[] = { 3114 1.2.2.2 skrll MVXPE_SYSCTL_NAME(0), MVXPE_SYSCTL_NAME(1), 3115 1.2.2.2 skrll MVXPE_SYSCTL_NAME(2), MVXPE_SYSCTL_NAME(3), 3116 1.2.2.2 skrll MVXPE_SYSCTL_NAME(4), MVXPE_SYSCTL_NAME(5), 3117 1.2.2.2 skrll MVXPE_SYSCTL_NAME(6), MVXPE_SYSCTL_NAME(7), 3118 1.2.2.2 skrll }; 3119 1.2.2.2 skrll #undef MVXPE_SYSCTL_NAME 3120 1.2.2.2 skrll #ifdef SYSCTL_INCLUDE_DESCR 3121 1.2.2.2 skrll #define MVXPE_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3122 1.2.2.2 skrll static const char *sysctl_queue_descrs[] = { 3123 1.2.2.3 skrll MVXPE_SYSCTL_DESCR(0), MVXPE_SYSCTL_DESCR(1), 3124 1.2.2.3 skrll MVXPE_SYSCTL_DESCR(2), MVXPE_SYSCTL_DESCR(3), 3125 1.2.2.3 skrll MVXPE_SYSCTL_DESCR(4), MVXPE_SYSCTL_DESCR(5), 3126 1.2.2.3 skrll MVXPE_SYSCTL_DESCR(6), MVXPE_SYSCTL_DESCR(7), 3127 1.2.2.2 skrll }; 3128 1.2.2.2 skrll #undef MVXPE_SYSCTL_DESCR 3129 1.2.2.2 skrll #endif /* SYSCTL_INCLUDE_DESCR */ 3130 1.2.2.2 skrll int mvxpe_curnum; 3131 1.2.2.2 skrll 3132 1.2.2.2 skrll rxarg->sc = txarg->sc = sc; 3133 1.2.2.2 skrll rxarg->queue = txarg->queue = q; 3134 1.2.2.2 skrll rxarg->rxtx = MVXPE_SYSCTL_RX; 3135 1.2.2.2 skrll txarg->rxtx = MVXPE_SYSCTL_TX; 3136 1.2.2.2 skrll 3137 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].rx.[queue] */ 3138 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3139 1.2.2.2 skrll 0, CTLTYPE_NODE, 3140 1.2.2.2 skrll sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descrs[q]), 3141 1.2.2.2 skrll NULL, 0, NULL, 0, 3142 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3143 1.2.2.2 skrll CTL_CREATE, CTL_EOL) != 0) { 3144 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 3145 1.2.2.2 skrll "couldn't create sysctl node\n"); 3146 1.2.2.2 skrll break; 3147 1.2.2.2 skrll } 3148 1.2.2.2 skrll mvxpe_curnum = node->sysctl_num; 3149 1.2.2.2 skrll 3150 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].rx.[queue].length */ 3151 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3152 1.2.2.2 skrll CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3153 1.2.2.2 skrll SYSCTL_DESCR("maximum length of the queue"), 3154 1.2.2.2 skrll sysctl_set_queue_length, 0, (void *)rxarg, 0, 3155 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3156 1.2.2.2 skrll mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3157 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 3158 1.2.2.2 skrll "couldn't create sysctl node\n"); 3159 1.2.2.2 skrll break; 3160 1.2.2.2 skrll } 3161 1.2.2.2 skrll 3162 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].rx.[queue].threshold_timer_us */ 3163 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3164 1.2.2.2 skrll CTLFLAG_READWRITE, CTLTYPE_INT, "threshold_timer_us", 3165 1.2.2.2 skrll SYSCTL_DESCR("interrupt coalescing threshold timer [us]"), 3166 1.2.2.2 skrll sysctl_set_queue_rxthtime, 0, (void *)rxarg, 0, 3167 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3168 1.2.2.2 skrll mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3169 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 3170 1.2.2.2 skrll "couldn't create sysctl node\n"); 3171 1.2.2.2 skrll break; 3172 1.2.2.2 skrll } 3173 1.2.2.2 skrll 3174 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].tx.[queue] */ 3175 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3176 1.2.2.2 skrll 0, CTLTYPE_NODE, 3177 1.2.2.2 skrll sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descs[q]), 3178 1.2.2.2 skrll NULL, 0, NULL, 0, 3179 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3180 1.2.2.2 skrll CTL_CREATE, CTL_EOL) != 0) { 3181 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 3182 1.2.2.2 skrll "couldn't create sysctl node\n"); 3183 1.2.2.2 skrll break; 3184 1.2.2.2 skrll } 3185 1.2.2.2 skrll mvxpe_curnum = node->sysctl_num; 3186 1.2.2.2 skrll 3187 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].tx.length[queue] */ 3188 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3189 1.2.2.2 skrll CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3190 1.2.2.2 skrll SYSCTL_DESCR("maximum length of the queue"), 3191 1.2.2.2 skrll sysctl_set_queue_length, 0, (void *)txarg, 0, 3192 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3193 1.2.2.2 skrll mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3194 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, 3195 1.2.2.2 skrll "couldn't create sysctl node\n"); 3196 1.2.2.2 skrll break; 3197 1.2.2.2 skrll } 3198 1.2.2.2 skrll } 3199 1.2.2.2 skrll 3200 1.2.2.2 skrll /* hw.mvxpe.mvxpe[unit].clear_mib */ 3201 1.2.2.2 skrll if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3202 1.2.2.2 skrll CTLFLAG_READWRITE, CTLTYPE_INT, "clear_mib", 3203 1.2.2.3 skrll SYSCTL_DESCR("mvxpe device driver debug control"), 3204 1.2.2.2 skrll sysctl_clear_mib, 0, (void *)sc, 0, 3205 1.2.2.2 skrll CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3206 1.2.2.2 skrll CTL_EOL) != 0) { 3207 1.2.2.2 skrll aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3208 1.2.2.2 skrll return; 3209 1.2.2.2 skrll } 3210 1.2.2.2 skrll 3211 1.2.2.2 skrll } 3212 1.2.2.2 skrll 3213 1.2.2.2 skrll /* 3214 1.2.2.2 skrll * MIB 3215 1.2.2.2 skrll */ 3216 1.2.2.2 skrll STATIC void 3217 1.2.2.2 skrll mvxpe_clear_mib(struct mvxpe_softc *sc) 3218 1.2.2.2 skrll { 3219 1.2.2.2 skrll int i; 3220 1.2.2.2 skrll 3221 1.2.2.2 skrll KASSERT_SC_MTX(sc); 3222 1.2.2.2 skrll 3223 1.2.2.2 skrll for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3224 1.2.2.2 skrll if (mvxpe_mib_list[i].reg64) 3225 1.2.2.2 skrll MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum + 4)); 3226 1.2.2.2 skrll MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3227 1.2.2.2 skrll sc->sc_sysctl_mib[i].counter = 0; 3228 1.2.2.2 skrll } 3229 1.2.2.2 skrll } 3230 1.2.2.2 skrll 3231 1.2.2.2 skrll STATIC void 3232 1.2.2.2 skrll mvxpe_update_mib(struct mvxpe_softc *sc) 3233 1.2.2.2 skrll { 3234 1.2.2.3 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3235 1.2.2.2 skrll int i; 3236 1.2.2.2 skrll 3237 1.2.2.2 skrll KASSERT_SC_MTX(sc); 3238 1.2.2.2 skrll 3239 1.2.2.2 skrll for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3240 1.2.2.2 skrll uint32_t val_hi; 3241 1.2.2.2 skrll uint32_t val_lo; 3242 1.2.2.3 skrll uint64_t val; 3243 1.2.2.2 skrll 3244 1.2.2.2 skrll if (mvxpe_mib_list[i].reg64) { 3245 1.2.2.2 skrll /* XXX: implement bus_space_read_8() */ 3246 1.2.2.2 skrll val_lo = MVXPE_READ_MIB(sc, 3247 1.2.2.2 skrll (mvxpe_mib_list[i].regnum + 4)); 3248 1.2.2.2 skrll val_hi = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3249 1.2.2.2 skrll } 3250 1.2.2.2 skrll else { 3251 1.2.2.2 skrll val_lo = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3252 1.2.2.2 skrll val_hi = 0; 3253 1.2.2.2 skrll } 3254 1.2.2.2 skrll 3255 1.2.2.2 skrll if ((val_lo | val_hi) == 0) 3256 1.2.2.2 skrll continue; 3257 1.2.2.2 skrll 3258 1.2.2.3 skrll val = ((uint64_t)val_hi << 32) | (uint64_t)val_lo; 3259 1.2.2.3 skrll sc->sc_sysctl_mib[i].counter += val; 3260 1.2.2.3 skrll 3261 1.2.2.3 skrll switch (mvxpe_mib_list[i].ext) { 3262 1.2.2.3 skrll case MVXPE_MIBEXT_IF_OERRORS: 3263 1.2.2.3 skrll ifp->if_oerrors += val; 3264 1.2.2.3 skrll break; 3265 1.2.2.3 skrll case MVXPE_MIBEXT_IF_IERRORS: 3266 1.2.2.3 skrll ifp->if_ierrors += val; 3267 1.2.2.3 skrll break; 3268 1.2.2.3 skrll case MVXPE_MIBEXT_IF_COLLISIONS: 3269 1.2.2.3 skrll ifp->if_collisions += val; 3270 1.2.2.3 skrll break; 3271 1.2.2.3 skrll default: 3272 1.2.2.3 skrll break; 3273 1.2.2.3 skrll } 3274 1.2.2.3 skrll 3275 1.2.2.2 skrll } 3276 1.2.2.2 skrll } 3277 1.2.2.2 skrll 3278 1.2.2.2 skrll /* 3279 1.2.2.2 skrll * for Debug 3280 1.2.2.2 skrll */ 3281 1.2.2.2 skrll STATIC void 3282 1.2.2.2 skrll mvxpe_dump_txdesc(struct mvxpe_tx_desc *desc, int idx) 3283 1.2.2.2 skrll { 3284 1.2.2.2 skrll #define DESC_PRINT(X) \ 3285 1.2.2.2 skrll if (X) \ 3286 1.2.2.2 skrll printf("txdesc[%d]." #X "=%#x\n", idx, X); 3287 1.2.2.2 skrll 3288 1.2.2.2 skrll DESC_PRINT(desc->command); 3289 1.2.2.2 skrll DESC_PRINT(desc->l4ichk); 3290 1.2.2.2 skrll DESC_PRINT(desc->bytecnt); 3291 1.2.2.2 skrll DESC_PRINT(desc->bufptr); 3292 1.2.2.2 skrll DESC_PRINT(desc->flags); 3293 1.2.2.2 skrll #undef DESC_PRINT 3294 1.2.2.2 skrll } 3295 1.2.2.2 skrll 3296 1.2.2.2 skrll STATIC void 3297 1.2.2.2 skrll mvxpe_dump_rxdesc(struct mvxpe_rx_desc *desc, int idx) 3298 1.2.2.2 skrll { 3299 1.2.2.2 skrll #define DESC_PRINT(X) \ 3300 1.2.2.2 skrll if (X) \ 3301 1.2.2.2 skrll printf("rxdesc[%d]." #X "=%#x\n", idx, X); 3302 1.2.2.2 skrll 3303 1.2.2.2 skrll DESC_PRINT(desc->status); 3304 1.2.2.2 skrll DESC_PRINT(desc->bytecnt); 3305 1.2.2.2 skrll DESC_PRINT(desc->bufptr); 3306 1.2.2.2 skrll DESC_PRINT(desc->l4chk); 3307 1.2.2.2 skrll #undef DESC_PRINT 3308 1.2.2.2 skrll } 3309
Indexes created Tue Oct 21 16:10:11 GMT 2025