if_mvxpe.c revision 1.11
1 /* $NetBSD: if_mvxpe.c,v 1.11 2016/02/13 06:44:22 hikaru Exp $ */ 2 /* 3 * Copyright (c) 2015 Internet Initiative Japan Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvxpe.c,v 1.11 2016/02/13 06:44:22 hikaru Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/callout.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 #include <sys/errno.h> 38 #include <sys/evcnt.h> 39 #include <sys/kernel.h> 40 #include <sys/kmem.h> 41 #include <sys/mutex.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/syslog.h> 45 #include <sys/rndsource.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 #include <net/bpf.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/ip.h> 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include <dev/marvell/marvellreg.h> 60 #include <dev/marvell/marvellvar.h> 61 #include <dev/marvell/mvxpbmvar.h> 62 #include <dev/marvell/if_mvxpereg.h> 63 #include <dev/marvell/if_mvxpevar.h> 64 65 #include "locators.h" 66 67 #if BYTE_ORDER == BIG_ENDIAN 68 #error "BIG ENDIAN not supported" 69 #endif 70 71 #ifdef MVXPE_DEBUG 72 #define STATIC /* nothing */ 73 #else 74 #define STATIC static 75 #endif 76 77 /* autoconf(9) */ 78 STATIC int mvxpe_match(device_t, struct cfdata *, void *); 79 STATIC void mvxpe_attach(device_t, device_t, void *); 80 STATIC int mvxpe_evcnt_attach(struct mvxpe_softc *); 81 CFATTACH_DECL_NEW(mvxpe_mbus, sizeof(struct mvxpe_softc), 82 mvxpe_match, mvxpe_attach, NULL, NULL); 83 STATIC void mvxpe_sc_lock(struct mvxpe_softc *); 84 STATIC void mvxpe_sc_unlock(struct mvxpe_softc *); 85 86 /* MII */ 87 STATIC int mvxpe_miibus_readreg(device_t, int, int); 88 STATIC void mvxpe_miibus_writereg(device_t, int, int, int); 89 STATIC void mvxpe_miibus_statchg(struct ifnet *); 90 91 /* Addres Decoding Window */ 92 STATIC void mvxpe_wininit(struct mvxpe_softc *, enum marvell_tags *); 93 94 /* Device Register Initialization */ 95 STATIC int mvxpe_initreg(struct ifnet *); 96 97 /* Descriptor Ring Control for each of queues */ 98 STATIC void *mvxpe_dma_memalloc(struct mvxpe_softc *, bus_dmamap_t *, size_t); 99 STATIC int mvxpe_ring_alloc_queue(struct mvxpe_softc *, int); 100 STATIC void mvxpe_ring_dealloc_queue(struct mvxpe_softc *, int); 101 STATIC void mvxpe_ring_init_queue(struct mvxpe_softc *, int); 102 STATIC void mvxpe_ring_flush_queue(struct mvxpe_softc *, int); 103 STATIC void mvxpe_ring_sync_rx(struct mvxpe_softc *, int, int, int, int); 104 STATIC void mvxpe_ring_sync_tx(struct mvxpe_softc *, int, int, int, int); 105 106 /* Rx/Tx Queue Control */ 107 STATIC int mvxpe_rx_queue_init(struct ifnet *, int); 108 STATIC int mvxpe_tx_queue_init(struct ifnet *, int); 109 STATIC int mvxpe_rx_queue_enable(struct ifnet *, int); 110 STATIC int mvxpe_tx_queue_enable(struct ifnet *, int); 111 STATIC void mvxpe_rx_lockq(struct mvxpe_softc *, int); 112 STATIC void mvxpe_rx_unlockq(struct mvxpe_softc *, int); 113 STATIC void mvxpe_tx_lockq(struct mvxpe_softc *, int); 114 STATIC void mvxpe_tx_unlockq(struct mvxpe_softc *, int); 115 116 /* Interrupt Handlers */ 117 STATIC void mvxpe_disable_intr(struct mvxpe_softc *); 118 STATIC void mvxpe_enable_intr(struct mvxpe_softc *); 119 STATIC int mvxpe_rxtxth_intr(void *); 120 STATIC int mvxpe_misc_intr(void *); 121 STATIC int mvxpe_rxtx_intr(void *); 122 STATIC void mvxpe_tick(void *); 123 124 /* struct ifnet and mii callbacks*/ 125 STATIC void mvxpe_start(struct ifnet *); 126 STATIC int mvxpe_ioctl(struct ifnet *, u_long, void *); 127 STATIC int mvxpe_init(struct ifnet *); 128 STATIC void mvxpe_stop(struct ifnet *, int); 129 STATIC void mvxpe_watchdog(struct ifnet *); 130 STATIC int mvxpe_ifflags_cb(struct ethercom *); 131 STATIC int mvxpe_mediachange(struct ifnet *); 132 STATIC void mvxpe_mediastatus(struct ifnet *, struct ifmediareq *); 133 134 /* Link State Notify */ 135 STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc); 136 STATIC void mvxpe_linkup(struct mvxpe_softc *); 137 STATIC void mvxpe_linkdown(struct mvxpe_softc *); 138 STATIC void mvxpe_linkreset(struct mvxpe_softc *); 139 140 /* Tx Subroutines */ 141 STATIC int mvxpe_tx_queue_select(struct mvxpe_softc *, struct mbuf *); 142 STATIC int mvxpe_tx_queue(struct mvxpe_softc *, struct mbuf *, int); 143 STATIC void mvxpe_tx_set_csumflag(struct ifnet *, 144 struct mvxpe_tx_desc *, struct mbuf *); 145 STATIC void mvxpe_tx_complete(struct mvxpe_softc *, uint32_t); 146 STATIC void mvxpe_tx_queue_complete(struct mvxpe_softc *, int); 147 148 /* Rx Subroutines */ 149 STATIC void mvxpe_rx(struct mvxpe_softc *, uint32_t); 150 STATIC void mvxpe_rx_queue(struct mvxpe_softc *, int, int); 151 STATIC int mvxpe_rx_queue_select(struct mvxpe_softc *, uint32_t, int *); 152 STATIC void mvxpe_rx_refill(struct mvxpe_softc *, uint32_t); 153 STATIC void mvxpe_rx_queue_refill(struct mvxpe_softc *, int); 154 STATIC int mvxpe_rx_queue_add(struct mvxpe_softc *, int); 155 STATIC void mvxpe_rx_set_csumflag(struct ifnet *, 156 struct mvxpe_rx_desc *, struct mbuf *); 157 158 /* MAC address filter */ 159 STATIC uint8_t mvxpe_crc8(const uint8_t *, size_t); 160 STATIC void mvxpe_filter_setup(struct mvxpe_softc *); 161 162 /* sysctl(9) */ 163 STATIC int sysctl_read_mib(SYSCTLFN_PROTO); 164 STATIC int sysctl_clear_mib(SYSCTLFN_PROTO); 165 STATIC int sysctl_set_queue_length(SYSCTLFN_PROTO); 166 STATIC int sysctl_set_queue_rxthtime(SYSCTLFN_PROTO); 167 STATIC void sysctl_mvxpe_init(struct mvxpe_softc *); 168 169 /* MIB */ 170 STATIC void mvxpe_clear_mib(struct mvxpe_softc *); 171 STATIC void mvxpe_update_mib(struct mvxpe_softc *); 172 173 /* for Debug */ 174 STATIC void mvxpe_dump_txdesc(struct mvxpe_tx_desc *, int) __attribute__((__unused__)); 175 STATIC void mvxpe_dump_rxdesc(struct mvxpe_rx_desc *, int) __attribute__((__unused__)); 176 177 STATIC int mvxpe_root_num; 178 STATIC kmutex_t mii_mutex; 179 STATIC int mii_init = 0; 180 #ifdef MVXPE_DEBUG 181 STATIC int mvxpe_debug = MVXPE_DEBUG; 182 #endif 183 184 /* 185 * List of MIB register and names 186 */ 187 STATIC struct mvxpe_mib_def { 188 uint32_t regnum; 189 int reg64; 190 const char *sysctl_name; 191 const char *desc; 192 int ext; 193 #define MVXPE_MIBEXT_IF_OERRORS 1 194 #define MVXPE_MIBEXT_IF_IERRORS 2 195 #define MVXPE_MIBEXT_IF_COLLISIONS 3 196 } mvxpe_mib_list[] = { 197 {MVXPE_MIB_RX_GOOD_OCT, 1, "rx_good_oct", 198 "Good Octets Rx", 0}, 199 {MVXPE_MIB_RX_BAD_OCT, 0, "rx_bad_oct", 200 "Bad Octets Rx", 0}, 201 {MVXPE_MIB_TX_MAC_TRNS_ERR, 0, "tx_mac_err", 202 "MAC Transmit Error", MVXPE_MIBEXT_IF_OERRORS}, 203 {MVXPE_MIB_RX_GOOD_FRAME, 0, "rx_good_frame", 204 "Good Frames Rx", 0}, 205 {MVXPE_MIB_RX_BAD_FRAME, 0, "rx_bad_frame", 206 "Bad Frames Rx", 0}, 207 {MVXPE_MIB_RX_BCAST_FRAME, 0, "rx_bcast_frame", 208 "Broadcast Frames Rx", 0}, 209 {MVXPE_MIB_RX_MCAST_FRAME, 0, "rx_mcast_frame", 210 "Multicast Frames Rx", 0}, 211 {MVXPE_MIB_RX_FRAME64_OCT, 0, "rx_frame_1_64", 212 "Frame Size 1 - 64", 0}, 213 {MVXPE_MIB_RX_FRAME127_OCT, 0, "rx_frame_65_127", 214 "Frame Size 65 - 127", 0}, 215 {MVXPE_MIB_RX_FRAME255_OCT, 0, "rx_frame_128_255", 216 "Frame Size 128 - 255", 0}, 217 {MVXPE_MIB_RX_FRAME511_OCT, 0, "rx_frame_256_511", 218 "Frame Size 256 - 511"}, 219 {MVXPE_MIB_RX_FRAME1023_OCT, 0, "rx_frame_512_1023", 220 "Frame Size 512 - 1023", 0}, 221 {MVXPE_MIB_RX_FRAMEMAX_OCT, 0, "rx_fame_1024_max", 222 "Frame Size 1024 - Max", 0}, 223 {MVXPE_MIB_TX_GOOD_OCT, 1, "tx_good_oct", 224 "Good Octets Tx", 0}, 225 {MVXPE_MIB_TX_GOOD_FRAME, 0, "tx_good_frame", 226 "Good Frames Tx", 0}, 227 {MVXPE_MIB_TX_EXCES_COL, 0, "tx_exces_collision", 228 "Excessive Collision", MVXPE_MIBEXT_IF_OERRORS}, 229 {MVXPE_MIB_TX_MCAST_FRAME, 0, "tx_mcast_frame", 230 "Multicast Frames Tx"}, 231 {MVXPE_MIB_TX_BCAST_FRAME, 0, "tx_bcast_frame", 232 "Broadcast Frames Tx"}, 233 {MVXPE_MIB_TX_MAC_CTL_ERR, 0, "tx_mac_err", 234 "Unknown MAC Control", 0}, 235 {MVXPE_MIB_FC_SENT, 0, "fc_tx", 236 "Flow Control Tx", 0}, 237 {MVXPE_MIB_FC_GOOD, 0, "fc_rx_good", 238 "Good Flow Control Rx", 0}, 239 {MVXPE_MIB_FC_BAD, 0, "fc_rx_bad", 240 "Bad Flow Control Rx", 0}, 241 {MVXPE_MIB_PKT_UNDERSIZE, 0, "pkt_undersize", 242 "Undersized Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 243 {MVXPE_MIB_PKT_FRAGMENT, 0, "pkt_fragment", 244 "Fragmented Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 245 {MVXPE_MIB_PKT_OVERSIZE, 0, "pkt_oversize", 246 "Oversized Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 247 {MVXPE_MIB_PKT_JABBER, 0, "pkt_jabber", 248 "Jabber Packets Rx", MVXPE_MIBEXT_IF_IERRORS}, 249 {MVXPE_MIB_MAC_RX_ERR, 0, "mac_rx_err", 250 "MAC Rx Errors", MVXPE_MIBEXT_IF_IERRORS}, 251 {MVXPE_MIB_MAC_CRC_ERR, 0, "mac_crc_err", 252 "MAC CRC Errors", MVXPE_MIBEXT_IF_IERRORS}, 253 {MVXPE_MIB_MAC_COL, 0, "mac_collision", 254 "MAC Collision", MVXPE_MIBEXT_IF_COLLISIONS}, 255 {MVXPE_MIB_MAC_LATE_COL, 0, "mac_late_collision", 256 "MAC Late Collision", MVXPE_MIBEXT_IF_OERRORS}, 257 }; 258 259 /* 260 * autoconf(9) 261 */ 262 /* ARGSUSED */ 263 STATIC int 264 mvxpe_match(device_t parent, cfdata_t match, void *aux) 265 { 266 struct marvell_attach_args *mva = aux; 267 bus_size_t pv_off; 268 uint32_t pv; 269 270 if (strcmp(mva->mva_name, match->cf_name) != 0) 271 return 0; 272 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 273 return 0; 274 275 /* check port version */ 276 pv_off = mva->mva_offset + MVXPE_PV; 277 pv = bus_space_read_4(mva->mva_iot, mva->mva_ioh, pv_off); 278 if (MVXPE_PV_GET_VERSION(pv) < 0x10) 279 return 0; /* old version is not supported */ 280 281 return 1; 282 } 283 284 /* ARGSUSED */ 285 STATIC void 286 mvxpe_attach(device_t parent, device_t self, void *aux) 287 { 288 struct mvxpe_softc *sc = device_private(self); 289 struct mii_softc *mii; 290 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 291 struct marvell_attach_args *mva = aux; 292 prop_dictionary_t dict; 293 prop_data_t enaddrp = NULL; 294 uint32_t phyaddr, maddrh, maddrl; 295 uint8_t enaddr[ETHER_ADDR_LEN]; 296 int q; 297 298 aprint_naive("\n"); 299 aprint_normal(": Marvell ARMADA GbE Controller\n"); 300 memset(sc, 0, sizeof(*sc)); 301 sc->sc_dev = self; 302 sc->sc_port = mva->mva_unit; 303 sc->sc_iot = mva->mva_iot; 304 sc->sc_dmat = mva->mva_dmat; 305 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 306 callout_init(&sc->sc_tick_ch, 0); 307 callout_setfunc(&sc->sc_tick_ch, mvxpe_tick, sc); 308 309 /* 310 * BUS space 311 */ 312 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 313 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 314 aprint_error_dev(self, "Cannot map registers\n"); 315 goto fail; 316 } 317 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 318 mva->mva_offset + MVXPE_PORTMIB_BASE, MVXPE_PORTMIB_SIZE, 319 &sc->sc_mibh)) { 320 aprint_error_dev(self, 321 "Cannot map destination address filter registers\n"); 322 goto fail; 323 } 324 sc->sc_version = MVXPE_READ(sc, MVXPE_PV); 325 aprint_normal_dev(self, "Port Version %#x\n", sc->sc_version); 326 327 /* 328 * Buffer Manager(BM) subsystem. 329 */ 330 sc->sc_bm = mvxpbm_device(mva); 331 if (sc->sc_bm == NULL) { 332 aprint_error_dev(self, "no Buffer Manager.\n"); 333 goto fail; 334 } 335 aprint_normal_dev(self, 336 "Using Buffer Manager: %s\n", mvxpbm_xname(sc->sc_bm)); 337 aprint_normal_dev(sc->sc_dev, 338 "%zu kbytes managed buffer, %zu bytes * %u entries allocated.\n", 339 mvxpbm_buf_size(sc->sc_bm) / 1024, 340 mvxpbm_chunk_size(sc->sc_bm), mvxpbm_chunk_count(sc->sc_bm)); 341 342 /* 343 * make sure DMA engines are in reset state 344 */ 345 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 346 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 347 348 /* 349 * Address decoding window 350 */ 351 mvxpe_wininit(sc, mva->mva_tags); 352 353 /* 354 * MAC address 355 */ 356 dict = device_properties(self); 357 if (dict) 358 enaddrp = prop_dictionary_get(dict, "mac-address"); 359 if (enaddrp) { 360 memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN); 361 maddrh = enaddr[0] << 24; 362 maddrh |= enaddr[1] << 16; 363 maddrh |= enaddr[2] << 8; 364 maddrh |= enaddr[3]; 365 maddrl = enaddr[4] << 8; 366 maddrl |= enaddr[5]; 367 MVXPE_WRITE(sc, MVXPE_MACAH, maddrh); 368 MVXPE_WRITE(sc, MVXPE_MACAL, maddrl); 369 } 370 else { 371 /* 372 * even if enaddr is not found in dictionary, 373 * the port may be initialized by IPL program such as U-BOOT. 374 */ 375 maddrh = MVXPE_READ(sc, MVXPE_MACAH); 376 maddrl = MVXPE_READ(sc, MVXPE_MACAL); 377 if ((maddrh | maddrl) == 0) { 378 aprint_error_dev(self, "No Ethernet address\n"); 379 return; 380 } 381 } 382 sc->sc_enaddr[0] = maddrh >> 24; 383 sc->sc_enaddr[1] = maddrh >> 16; 384 sc->sc_enaddr[2] = maddrh >> 8; 385 sc->sc_enaddr[3] = maddrh >> 0; 386 sc->sc_enaddr[4] = maddrl >> 8; 387 sc->sc_enaddr[5] = maddrl >> 0; 388 aprint_normal_dev(self, "Ethernet address %s\n", 389 ether_sprintf(sc->sc_enaddr)); 390 391 /* 392 * Register interrupt handlers 393 * XXX: handle Ethernet unit intr. and Error intr. 394 */ 395 mvxpe_disable_intr(sc); 396 marvell_intr_establish(mva->mva_irq, IPL_NET, mvxpe_rxtxth_intr, sc); 397 398 /* 399 * MIB buffer allocation 400 */ 401 sc->sc_sysctl_mib_size = 402 __arraycount(mvxpe_mib_list) * sizeof(struct mvxpe_sysctl_mib); 403 sc->sc_sysctl_mib = kmem_alloc(sc->sc_sysctl_mib_size, KM_NOSLEEP); 404 if (sc->sc_sysctl_mib == NULL) 405 goto fail; 406 memset(sc->sc_sysctl_mib, 0, sc->sc_sysctl_mib_size); 407 408 /* 409 * Device DMA Buffer allocation 410 */ 411 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 412 if (mvxpe_ring_alloc_queue(sc, q) != 0) 413 goto fail; 414 mvxpe_ring_init_queue(sc, q); 415 } 416 417 /* 418 * We can support 802.1Q VLAN-sized frames and jumbo 419 * Ethernet frames. 420 */ 421 sc->sc_ethercom.ec_capabilities |= 422 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 423 ifp->if_softc = sc; 424 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 425 ifp->if_start = mvxpe_start; 426 ifp->if_ioctl = mvxpe_ioctl; 427 ifp->if_init = mvxpe_init; 428 ifp->if_stop = mvxpe_stop; 429 ifp->if_watchdog = mvxpe_watchdog; 430 431 /* 432 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 433 */ 434 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx; 435 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx; 436 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 437 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 438 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx; 439 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx; 440 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx; 441 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Rx; 442 ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Tx; 443 ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Rx; 444 445 /* 446 * Initialize struct ifnet 447 */ 448 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVXPE_TX_RING_CNT - 1, IFQ_MAXLEN)); 449 IFQ_SET_READY(&ifp->if_snd); 450 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname)); 451 452 /* 453 * Enable DMA engines and Initiazlie Device Regisers. 454 */ 455 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 456 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 457 MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 458 mvxpe_sc_lock(sc); /* XXX */ 459 mvxpe_filter_setup(sc); 460 mvxpe_sc_unlock(sc); 461 mvxpe_initreg(ifp); 462 463 /* 464 * Now MAC is working, setup MII. 465 */ 466 if (mii_init == 0) { 467 /* 468 * MII bus is shared by all MACs and all PHYs in SoC. 469 * serializing the bus access should be safe. 470 */ 471 mutex_init(&mii_mutex, MUTEX_DEFAULT, IPL_NET); 472 mii_init = 1; 473 } 474 sc->sc_mii.mii_ifp = ifp; 475 sc->sc_mii.mii_readreg = mvxpe_miibus_readreg; 476 sc->sc_mii.mii_writereg = mvxpe_miibus_writereg; 477 sc->sc_mii.mii_statchg = mvxpe_miibus_statchg; 478 479 sc->sc_ethercom.ec_mii = &sc->sc_mii; 480 ifmedia_init(&sc->sc_mii.mii_media, 0, 481 mvxpe_mediachange, mvxpe_mediastatus); 482 /* 483 * XXX: phy addressing highly depends on Board Design. 484 * we assume phyaddress == MAC unit number here, 485 * but some boards may not. 486 */ 487 mii_attach(self, &sc->sc_mii, 0xffffffff, 488 MII_PHY_ANY, sc->sc_dev->dv_unit, 0); 489 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 490 if (mii == NULL) { 491 aprint_error_dev(self, "no PHY found!\n"); 492 ifmedia_add(&sc->sc_mii.mii_media, 493 IFM_ETHER|IFM_MANUAL, 0, NULL); 494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 495 } else { 496 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 497 phyaddr = MVXPE_PHYADDR_PHYAD(mii->mii_phy); 498 MVXPE_WRITE(sc, MVXPE_PHYADDR, phyaddr); 499 DPRINTSC(sc, 1, "PHYADDR: %#x\n", MVXPE_READ(sc, MVXPE_PHYADDR)); 500 } 501 502 /* 503 * Call MI attach routines. 504 */ 505 if_attach(ifp); 506 507 ether_ifattach(ifp, sc->sc_enaddr); 508 ether_set_ifflags_cb(&sc->sc_ethercom, mvxpe_ifflags_cb); 509 510 sysctl_mvxpe_init(sc); 511 mvxpe_evcnt_attach(sc); 512 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 513 RND_TYPE_NET, RND_FLAG_DEFAULT); 514 515 return; 516 517 fail: 518 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) 519 mvxpe_ring_dealloc_queue(sc, q); 520 if (sc->sc_sysctl_mib) 521 kmem_free(sc->sc_sysctl_mib, sc->sc_sysctl_mib_size); 522 523 return; 524 } 525 526 STATIC int 527 mvxpe_evcnt_attach(struct mvxpe_softc *sc) 528 { 529 #ifdef MVXPE_EVENT_COUNTERS 530 int q; 531 532 /* Master Interrupt Handler */ 533 evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtxth, EVCNT_TYPE_INTR, 534 NULL, device_xname(sc->sc_dev), "RxTxTH Intr."); 535 evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtx, EVCNT_TYPE_INTR, 536 NULL, device_xname(sc->sc_dev), "RxTx Intr."); 537 evcnt_attach_dynamic(&sc->sc_ev.ev_i_misc, EVCNT_TYPE_INTR, 538 NULL, device_xname(sc->sc_dev), "MISC Intr."); 539 540 /* RXTXTH Interrupt */ 541 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtxth_txerr, EVCNT_TYPE_INTR, 542 NULL, device_xname(sc->sc_dev), "RxTxTH Tx error summary"); 543 544 /* MISC Interrupt */ 545 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_phystatuschng, EVCNT_TYPE_INTR, 546 NULL, device_xname(sc->sc_dev), "MISC phy status changed"); 547 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_linkchange, EVCNT_TYPE_INTR, 548 NULL, device_xname(sc->sc_dev), "MISC link status changed"); 549 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_iae, EVCNT_TYPE_INTR, 550 NULL, device_xname(sc->sc_dev), "MISC internal address error"); 551 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxoverrun, EVCNT_TYPE_INTR, 552 NULL, device_xname(sc->sc_dev), "MISC Rx FIFO overrun"); 553 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxcrc, EVCNT_TYPE_INTR, 554 NULL, device_xname(sc->sc_dev), "MISC Rx CRC error"); 555 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxlargepacket, EVCNT_TYPE_INTR, 556 NULL, device_xname(sc->sc_dev), "MISC Rx too large frame"); 557 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txunderrun, EVCNT_TYPE_INTR, 558 NULL, device_xname(sc->sc_dev), "MISC Tx FIFO underrun"); 559 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_prbserr, EVCNT_TYPE_INTR, 560 NULL, device_xname(sc->sc_dev), "MISC SERDES loopback test err"); 561 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_srse, EVCNT_TYPE_INTR, 562 NULL, device_xname(sc->sc_dev), "MISC SERDES sync error"); 563 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txreq, EVCNT_TYPE_INTR, 564 NULL, device_xname(sc->sc_dev), "MISC Tx resource erorr"); 565 566 /* RxTx Interrupt */ 567 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rreq, EVCNT_TYPE_INTR, 568 NULL, device_xname(sc->sc_dev), "RxTx Rx resource erorr"); 569 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rpq, EVCNT_TYPE_INTR, 570 NULL, device_xname(sc->sc_dev), "RxTx Rx pakcet"); 571 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_tbrq, EVCNT_TYPE_INTR, 572 NULL, device_xname(sc->sc_dev), "RxTx Tx complete"); 573 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rxtxth, EVCNT_TYPE_INTR, 574 NULL, device_xname(sc->sc_dev), "RxTx RxTxTH summary"); 575 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_txerr, EVCNT_TYPE_INTR, 576 NULL, device_xname(sc->sc_dev), "RxTx Tx error summary"); 577 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_misc, EVCNT_TYPE_INTR, 578 NULL, device_xname(sc->sc_dev), "RxTx MISC summary"); 579 580 /* Link */ 581 evcnt_attach_dynamic(&sc->sc_ev.ev_link_up, EVCNT_TYPE_MISC, 582 NULL, device_xname(sc->sc_dev), "link up"); 583 evcnt_attach_dynamic(&sc->sc_ev.ev_link_down, EVCNT_TYPE_MISC, 584 NULL, device_xname(sc->sc_dev), "link down"); 585 586 /* Rx Descriptor */ 587 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_ce, EVCNT_TYPE_MISC, 588 NULL, device_xname(sc->sc_dev), "Rx CRC error counter"); 589 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_or, EVCNT_TYPE_MISC, 590 NULL, device_xname(sc->sc_dev), "Rx FIFO overrun counter"); 591 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_mf, EVCNT_TYPE_MISC, 592 NULL, device_xname(sc->sc_dev), "Rx too large frame counter"); 593 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_re, EVCNT_TYPE_MISC, 594 NULL, device_xname(sc->sc_dev), "Rx resource error counter"); 595 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_scat, EVCNT_TYPE_MISC, 596 NULL, device_xname(sc->sc_dev), "Rx unexpected scatter bufs"); 597 598 /* Tx Descriptor */ 599 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_lc, EVCNT_TYPE_MISC, 600 NULL, device_xname(sc->sc_dev), "Tx late collision counter"); 601 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_rl, EVCNT_TYPE_MISC, 602 NULL, device_xname(sc->sc_dev), "Tx excess. collision counter"); 603 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_ur, EVCNT_TYPE_MISC, 604 NULL, device_xname(sc->sc_dev), "Tx FIFO underrun counter"); 605 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_oth, EVCNT_TYPE_MISC, 606 NULL, device_xname(sc->sc_dev), "Tx unkonwn erorr counter"); 607 608 /* Status Registers */ 609 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pdfc, EVCNT_TYPE_MISC, 610 NULL, device_xname(sc->sc_dev), "Rx discard counter"); 611 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pofc, EVCNT_TYPE_MISC, 612 NULL, device_xname(sc->sc_dev), "Rx overrun counter"); 613 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txbadfcs, EVCNT_TYPE_MISC, 614 NULL, device_xname(sc->sc_dev), "Tx bad FCS counter"); 615 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txdropped, EVCNT_TYPE_MISC, 616 NULL, device_xname(sc->sc_dev), "Tx dorpped counter"); 617 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_lpic, EVCNT_TYPE_MISC, 618 NULL, device_xname(sc->sc_dev), "LP_IDLE counter"); 619 620 /* Device Driver Errors */ 621 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_wdogsoft, EVCNT_TYPE_MISC, 622 NULL, device_xname(sc->sc_dev), "watchdog timer expired"); 623 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txerr, EVCNT_TYPE_MISC, 624 NULL, device_xname(sc->sc_dev), "Tx descriptor alloc failed"); 625 #define MVXPE_QUEUE_DESC(q) "Rx success in queue " # q 626 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 627 static const char *rxq_desc[] = { 628 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 629 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 630 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 631 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 632 }; 633 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxq[q], EVCNT_TYPE_MISC, 634 NULL, device_xname(sc->sc_dev), rxq_desc[q]); 635 } 636 #undef MVXPE_QUEUE_DESC 637 #define MVXPE_QUEUE_DESC(q) "Tx success in queue " # q 638 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 639 static const char *txq_desc[] = { 640 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 641 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 642 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 643 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 644 }; 645 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txq[q], EVCNT_TYPE_MISC, 646 NULL, device_xname(sc->sc_dev), txq_desc[q]); 647 } 648 #undef MVXPE_QUEUE_DESC 649 #define MVXPE_QUEUE_DESC(q) "Rx error in queue " # q 650 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 651 static const char *rxqe_desc[] = { 652 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 653 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 654 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 655 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 656 }; 657 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxqe[q], EVCNT_TYPE_MISC, 658 NULL, device_xname(sc->sc_dev), rxqe_desc[q]); 659 } 660 #undef MVXPE_QUEUE_DESC 661 #define MVXPE_QUEUE_DESC(q) "Tx error in queue " # q 662 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 663 static const char *txqe_desc[] = { 664 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 665 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 666 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 667 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 668 }; 669 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txqe[q], EVCNT_TYPE_MISC, 670 NULL, device_xname(sc->sc_dev), txqe_desc[q]); 671 } 672 #undef MVXPE_QUEUE_DESC 673 674 #endif /* MVXPE_EVENT_COUNTERS */ 675 return 0; 676 } 677 678 STATIC void 679 mvxpe_sc_lock(struct mvxpe_softc *sc) 680 { 681 mutex_enter(&sc->sc_mtx); 682 } 683 684 STATIC void 685 mvxpe_sc_unlock(struct mvxpe_softc *sc) 686 { 687 mutex_exit(&sc->sc_mtx); 688 } 689 690 /* 691 * MII 692 */ 693 STATIC int 694 mvxpe_miibus_readreg(device_t dev, int phy, int reg) 695 { 696 struct mvxpe_softc *sc = device_private(dev); 697 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 698 uint32_t smi, val; 699 int i; 700 701 mutex_enter(&mii_mutex); 702 703 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 704 DELAY(1); 705 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 706 break; 707 } 708 if (i == MVXPE_PHY_TIMEOUT) { 709 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 710 mutex_exit(&mii_mutex); 711 return -1; 712 } 713 714 smi = 715 MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | MVXPE_SMI_OPCODE_READ; 716 MVXPE_WRITE(sc, MVXPE_SMI, smi); 717 718 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 719 DELAY(1); 720 smi = MVXPE_READ(sc, MVXPE_SMI); 721 if (smi & MVXPE_SMI_READVALID) 722 break; 723 } 724 725 mutex_exit(&mii_mutex); 726 727 DPRINTDEV(dev, 9, "i=%d, timeout=%d\n", i, MVXPE_PHY_TIMEOUT); 728 729 val = smi & MVXPE_SMI_DATA_MASK; 730 731 DPRINTDEV(dev, 9, "phy=%d, reg=%#x, val=%#x\n", phy, reg, val); 732 733 return val; 734 } 735 736 STATIC void 737 mvxpe_miibus_writereg(device_t dev, int phy, int reg, int val) 738 { 739 struct mvxpe_softc *sc = device_private(dev); 740 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 741 uint32_t smi; 742 int i; 743 744 DPRINTDEV(dev, 9, "phy=%d reg=%#x val=%#x\n", phy, reg, val); 745 746 mutex_enter(&mii_mutex); 747 748 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 749 DELAY(1); 750 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 751 break; 752 } 753 if (i == MVXPE_PHY_TIMEOUT) { 754 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 755 mutex_exit(&mii_mutex); 756 return; 757 } 758 759 smi = MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | 760 MVXPE_SMI_OPCODE_WRITE | (val & MVXPE_SMI_DATA_MASK); 761 MVXPE_WRITE(sc, MVXPE_SMI, smi); 762 763 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 764 DELAY(1); 765 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 766 break; 767 } 768 769 mutex_exit(&mii_mutex); 770 771 if (i == MVXPE_PHY_TIMEOUT) 772 aprint_error_ifnet(ifp, "phy write timed out\n"); 773 } 774 775 STATIC void 776 mvxpe_miibus_statchg(struct ifnet *ifp) 777 { 778 779 /* nothing to do */ 780 } 781 782 /* 783 * Address Decoding Window 784 */ 785 STATIC void 786 mvxpe_wininit(struct mvxpe_softc *sc, enum marvell_tags *tags) 787 { 788 device_t pdev = device_parent(sc->sc_dev); 789 uint64_t base; 790 uint32_t en, ac, size; 791 int window, target, attr, rv, i; 792 793 /* First disable all address decode windows */ 794 en = MVXPE_BARE_EN_MASK; 795 MVXPE_WRITE(sc, MVXPE_BARE, en); 796 797 ac = 0; 798 for (window = 0, i = 0; 799 tags[i] != MARVELL_TAG_UNDEFINED && window < MVXPE_NWINDOW; i++) { 800 rv = marvell_winparams_by_tag(pdev, tags[i], 801 &target, &attr, &base, &size); 802 if (rv != 0 || size == 0) 803 continue; 804 805 if (base > 0xffffffffULL) { 806 if (window >= MVXPE_NREMAP) { 807 aprint_error_dev(sc->sc_dev, 808 "can't remap window %d\n", window); 809 continue; 810 } 811 MVXPE_WRITE(sc, MVXPE_HA(window), 812 (base >> 32) & 0xffffffff); 813 } 814 815 MVXPE_WRITE(sc, MVXPE_BASEADDR(window), 816 MVXPE_BASEADDR_TARGET(target) | 817 MVXPE_BASEADDR_ATTR(attr) | 818 MVXPE_BASEADDR_BASE(base)); 819 MVXPE_WRITE(sc, MVXPE_S(window), MVXPE_S_SIZE(size)); 820 821 DPRINTSC(sc, 1, "Window %d Base 0x%016llx: Size 0x%08x\n", 822 window, base, size); 823 824 en &= ~(1 << window); 825 /* set full access (r/w) */ 826 ac |= MVXPE_EPAP_EPAR(window, MVXPE_EPAP_AC_FA); 827 window++; 828 } 829 /* allow to access decode window */ 830 MVXPE_WRITE(sc, MVXPE_EPAP, ac); 831 832 MVXPE_WRITE(sc, MVXPE_BARE, en); 833 } 834 835 /* 836 * Device Register Initialization 837 * reset device registers to device driver default value. 838 * the device is not enabled here. 839 */ 840 STATIC int 841 mvxpe_initreg(struct ifnet *ifp) 842 { 843 struct mvxpe_softc *sc = ifp->if_softc; 844 int serdes = 0; 845 uint32_t reg; 846 int q, i; 847 848 DPRINTIFNET(ifp, 1, "initializing device register\n"); 849 850 /* Init TX/RX Queue Registers */ 851 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 852 mvxpe_rx_lockq(sc, q); 853 if (mvxpe_rx_queue_init(ifp, q) != 0) { 854 aprint_error_ifnet(ifp, 855 "initialization failed: cannot initialize queue\n"); 856 mvxpe_rx_unlockq(sc, q); 857 return ENOBUFS; 858 } 859 mvxpe_rx_unlockq(sc, q); 860 861 mvxpe_tx_lockq(sc, q); 862 if (mvxpe_tx_queue_init(ifp, q) != 0) { 863 aprint_error_ifnet(ifp, 864 "initialization failed: cannot initialize queue\n"); 865 mvxpe_tx_unlockq(sc, q); 866 return ENOBUFS; 867 } 868 mvxpe_tx_unlockq(sc, q); 869 } 870 871 /* Tx MTU Limit */ 872 MVXPE_WRITE(sc, MVXPE_TXMTU, MVXPE_MTU); 873 874 /* Check SGMII or SERDES(asume IPL/U-BOOT initialize this) */ 875 reg = MVXPE_READ(sc, MVXPE_PMACC0); 876 if ((reg & MVXPE_PMACC0_PORTTYPE) != 0) 877 serdes = 1; 878 879 /* Ethernet Unit Control */ 880 reg = MVXPE_READ(sc, MVXPE_EUC); 881 reg |= MVXPE_EUC_POLLING; 882 MVXPE_WRITE(sc, MVXPE_EUC, reg); 883 884 /* Auto Negotiation */ 885 reg = MVXPE_PANC_MUSTSET; /* must write 0x1 */ 886 reg |= MVXPE_PANC_FORCELINKFAIL;/* force link state down */ 887 reg |= MVXPE_PANC_ANSPEEDEN; /* interface speed negotiation */ 888 reg |= MVXPE_PANC_ANDUPLEXEN; /* negotiate duplex mode */ 889 if (serdes) { 890 reg |= MVXPE_PANC_INBANDANEN; /* In Band negotiation */ 891 reg |= MVXPE_PANC_INBANDANBYPASSEN; /* bypass negotiation */ 892 reg |= MVXPE_PANC_SETFULLDX; /* set full-duplex on failure */ 893 } 894 MVXPE_WRITE(sc, MVXPE_PANC, reg); 895 896 /* EEE: Low Power Idle */ 897 reg = MVXPE_LPIC0_LILIMIT(MVXPE_LPI_LI); 898 reg |= MVXPE_LPIC0_TSLIMIT(MVXPE_LPI_TS); 899 MVXPE_WRITE(sc, MVXPE_LPIC0, reg); 900 901 reg = MVXPE_LPIC1_TWLIMIT(MVXPE_LPI_TS); 902 MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 903 904 reg = MVXPE_LPIC2_MUSTSET; 905 MVXPE_WRITE(sc, MVXPE_LPIC2, reg); 906 907 /* Port MAC Control set 0 */ 908 reg = MVXPE_PMACC0_MUSTSET; /* must write 0x1 */ 909 reg &= ~MVXPE_PMACC0_PORTEN; /* port is still disabled */ 910 reg |= MVXPE_PMACC0_FRAMESIZELIMIT(MVXPE_MRU); 911 if (serdes) 912 reg |= MVXPE_PMACC0_PORTTYPE; 913 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 914 915 /* Port MAC Control set 1 is only used for loop-back test */ 916 917 /* Port MAC Control set 2 */ 918 reg = MVXPE_READ(sc, MVXPE_PMACC2); 919 reg &= (MVXPE_PMACC2_PCSEN | MVXPE_PMACC2_RGMIIEN); 920 reg |= MVXPE_PMACC2_MUSTSET; 921 MVXPE_WRITE(sc, MVXPE_PMACC2, reg); 922 923 /* Port MAC Control set 3 is used for IPG tune */ 924 925 /* Port MAC Control set 4 is not used */ 926 927 /* Port Configuration Extended: enable Tx CRC generation */ 928 reg = MVXPE_READ(sc, MVXPE_PXCX); 929 reg &= ~MVXPE_PXCX_TXCRCDIS; 930 MVXPE_WRITE(sc, MVXPE_PXCX, reg); 931 932 /* clear MIB counter registers(clear by read) */ 933 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) 934 MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum)); 935 936 /* Set SDC register except IPGINT bits */ 937 reg = MVXPE_SDC_RXBSZ_16_64BITWORDS; 938 reg |= MVXPE_SDC_TXBSZ_16_64BITWORDS; 939 reg |= MVXPE_SDC_BLMR; 940 reg |= MVXPE_SDC_BLMT; 941 MVXPE_WRITE(sc, MVXPE_SDC, reg); 942 943 return 0; 944 } 945 946 /* 947 * Descriptor Ring Controls for each of queues 948 */ 949 STATIC void * 950 mvxpe_dma_memalloc(struct mvxpe_softc *sc, bus_dmamap_t *map, size_t size) 951 { 952 bus_dma_segment_t segs; 953 void *kva = NULL; 954 int nsegs; 955 956 /* 957 * Allocate the descriptor queues. 958 * struct mvxpe_ring_data contians array of descriptor per queue. 959 */ 960 if (bus_dmamem_alloc(sc->sc_dmat, 961 size, PAGE_SIZE, 0, &segs, 1, &nsegs, BUS_DMA_NOWAIT)) { 962 aprint_error_dev(sc->sc_dev, 963 "can't alloc device memory (%zu bytes)\n", size); 964 return NULL; 965 } 966 if (bus_dmamem_map(sc->sc_dmat, 967 &segs, nsegs, size, &kva, BUS_DMA_NOWAIT)) { 968 aprint_error_dev(sc->sc_dev, 969 "can't map dma buffers (%zu bytes)\n", size); 970 goto fail1; 971 } 972 973 if (bus_dmamap_create(sc->sc_dmat, 974 size, 1, size, 0, BUS_DMA_NOWAIT, map)) { 975 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 976 goto fail2; 977 } 978 if (bus_dmamap_load(sc->sc_dmat, 979 *map, kva, size, NULL, BUS_DMA_NOWAIT)) { 980 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 981 goto fail3; 982 } 983 memset(kva, 0, size); 984 return kva; 985 986 fail3: 987 bus_dmamap_destroy(sc->sc_dmat, *map); 988 memset(map, 0, sizeof(*map)); 989 fail2: 990 bus_dmamem_unmap(sc->sc_dmat, kva, size); 991 fail1: 992 bus_dmamem_free(sc->sc_dmat, &segs, nsegs); 993 return NULL; 994 } 995 996 STATIC int 997 mvxpe_ring_alloc_queue(struct mvxpe_softc *sc, int q) 998 { 999 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1000 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1001 1002 /* 1003 * MVXPE_RX_RING_CNT and MVXPE_TX_RING_CNT is a hard limit of 1004 * queue length. real queue length is limited by 1005 * sc->sc_rx_ring[q].rx_queue_len and sc->sc_tx_ring[q].tx_queue_len. 1006 * 1007 * because descriptor ring reallocation needs reprogramming of 1008 * DMA registers, we allocate enough descriptor for hard limit 1009 * of queue length. 1010 */ 1011 rx->rx_descriptors = 1012 mvxpe_dma_memalloc(sc, &rx->rx_descriptors_map, 1013 (sizeof(struct mvxpe_rx_desc) * MVXPE_RX_RING_CNT)); 1014 if (rx->rx_descriptors == NULL) 1015 goto fail; 1016 1017 tx->tx_descriptors = 1018 mvxpe_dma_memalloc(sc, &tx->tx_descriptors_map, 1019 (sizeof(struct mvxpe_tx_desc) * MVXPE_TX_RING_CNT)); 1020 if (tx->tx_descriptors == NULL) 1021 goto fail; 1022 1023 return 0; 1024 fail: 1025 mvxpe_ring_dealloc_queue(sc, q); 1026 aprint_error_dev(sc->sc_dev, "DMA Ring buffer allocation failure.\n"); 1027 return ENOMEM; 1028 } 1029 1030 STATIC void 1031 mvxpe_ring_dealloc_queue(struct mvxpe_softc *sc, int q) 1032 { 1033 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1034 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1035 bus_dma_segment_t *segs; 1036 bus_size_t size; 1037 void *kva; 1038 int nsegs; 1039 1040 /* Rx */ 1041 kva = (void *)MVXPE_RX_RING_MEM_VA(sc, q); 1042 if (kva) { 1043 segs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_segs; 1044 nsegs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_nsegs; 1045 size = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_mapsize; 1046 1047 bus_dmamap_unload(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1048 bus_dmamap_destroy(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1049 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1050 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1051 } 1052 1053 /* Tx */ 1054 kva = (void *)MVXPE_TX_RING_MEM_VA(sc, q); 1055 if (kva) { 1056 segs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_segs; 1057 nsegs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_nsegs; 1058 size = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_mapsize; 1059 1060 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1061 bus_dmamap_destroy(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1062 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1063 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1064 } 1065 1066 /* Clear doungling pointers all */ 1067 memset(rx, 0, sizeof(*rx)); 1068 memset(tx, 0, sizeof(*tx)); 1069 } 1070 1071 STATIC void 1072 mvxpe_ring_init_queue(struct mvxpe_softc *sc, int q) 1073 { 1074 struct mvxpe_rx_desc *rxd = MVXPE_RX_RING_MEM_VA(sc, q); 1075 struct mvxpe_tx_desc *txd = MVXPE_TX_RING_MEM_VA(sc, q); 1076 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1077 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1078 static const int rx_default_queue_len[] = { 1079 MVXPE_RX_QUEUE_LIMIT_0, MVXPE_RX_QUEUE_LIMIT_1, 1080 MVXPE_RX_QUEUE_LIMIT_2, MVXPE_RX_QUEUE_LIMIT_3, 1081 MVXPE_RX_QUEUE_LIMIT_4, MVXPE_RX_QUEUE_LIMIT_5, 1082 MVXPE_RX_QUEUE_LIMIT_6, MVXPE_RX_QUEUE_LIMIT_7, 1083 }; 1084 static const int tx_default_queue_len[] = { 1085 MVXPE_TX_QUEUE_LIMIT_0, MVXPE_TX_QUEUE_LIMIT_1, 1086 MVXPE_TX_QUEUE_LIMIT_2, MVXPE_TX_QUEUE_LIMIT_3, 1087 MVXPE_TX_QUEUE_LIMIT_4, MVXPE_TX_QUEUE_LIMIT_5, 1088 MVXPE_TX_QUEUE_LIMIT_6, MVXPE_TX_QUEUE_LIMIT_7, 1089 }; 1090 extern uint32_t mvTclk; 1091 int i; 1092 1093 /* Rx handle */ 1094 for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1095 MVXPE_RX_DESC(sc, q, i) = &rxd[i]; 1096 MVXPE_RX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_rx_desc) * i; 1097 MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1098 } 1099 mutex_init(&rx->rx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1100 rx->rx_dma = rx->rx_cpu = 0; 1101 rx->rx_queue_len = rx_default_queue_len[q]; 1102 if (rx->rx_queue_len > MVXPE_RX_RING_CNT) 1103 rx->rx_queue_len = MVXPE_RX_RING_CNT; 1104 rx->rx_queue_th_received = rx->rx_queue_len / MVXPE_RXTH_RATIO; 1105 rx->rx_queue_th_free = rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 1106 rx->rx_queue_th_time = (mvTclk / 1000) / 2; /* 0.5 [ms] */ 1107 1108 /* Tx handle */ 1109 for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1110 MVXPE_TX_DESC(sc, q, i) = &txd[i]; 1111 MVXPE_TX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_tx_desc) * i; 1112 MVXPE_TX_MBUF(sc, q, i) = NULL; 1113 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1114 if (bus_dmamap_create(sc->sc_dmat, 1115 mvxpbm_chunk_size(sc->sc_bm), 1116 MVXPE_TX_SEGLIMIT, mvxpbm_chunk_size(sc->sc_bm), 0, 1117 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 1118 &MVXPE_TX_MAP(sc, q, i))) { 1119 aprint_error_dev(sc->sc_dev, 1120 "can't create dma map (tx ring %d)\n", i); 1121 } 1122 } 1123 mutex_init(&tx->tx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1124 tx->tx_dma = tx->tx_cpu = 0; 1125 tx->tx_queue_len = tx_default_queue_len[q]; 1126 if (tx->tx_queue_len > MVXPE_TX_RING_CNT) 1127 tx->tx_queue_len = MVXPE_TX_RING_CNT; 1128 tx->tx_used = 0; 1129 tx->tx_queue_th_free = tx->tx_queue_len / MVXPE_TXTH_RATIO; 1130 } 1131 1132 STATIC void 1133 mvxpe_ring_flush_queue(struct mvxpe_softc *sc, int q) 1134 { 1135 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1136 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1137 int i; 1138 1139 KASSERT_RX_MTX(sc, q); 1140 KASSERT_TX_MTX(sc, q); 1141 1142 /* Rx handle */ 1143 for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1144 if (MVXPE_RX_PKTBUF(sc, q, i) == NULL) 1145 continue; 1146 mvxpbm_free_chunk(MVXPE_RX_PKTBUF(sc, q, i)); 1147 MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1148 } 1149 rx->rx_dma = rx->rx_cpu = 0; 1150 1151 /* Tx handle */ 1152 for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1153 if (MVXPE_TX_MBUF(sc, q, i) == NULL) 1154 continue; 1155 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, i)); 1156 m_freem(MVXPE_TX_MBUF(sc, q, i)); 1157 MVXPE_TX_MBUF(sc, q, i) = NULL; 1158 } 1159 tx->tx_dma = tx->tx_cpu = 0; 1160 tx->tx_used = 0; 1161 } 1162 1163 STATIC void 1164 mvxpe_ring_sync_rx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1165 { 1166 int wrap; 1167 1168 KASSERT_RX_MTX(sc, q); 1169 KASSERT(count > 0 && count <= MVXPE_RX_RING_CNT); 1170 KASSERT(idx >= 0 && idx < MVXPE_RX_RING_CNT); 1171 1172 wrap = (idx + count) - MVXPE_RX_RING_CNT; 1173 if (wrap > 0) { 1174 count -= wrap; 1175 KASSERT(count > 0); 1176 bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1177 0, sizeof(struct mvxpe_rx_desc) * wrap, ops); 1178 } 1179 bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1180 MVXPE_RX_DESC_OFF(sc, q, idx), 1181 sizeof(struct mvxpe_rx_desc) * count, ops); 1182 } 1183 1184 STATIC void 1185 mvxpe_ring_sync_tx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1186 { 1187 int wrap = 0; 1188 1189 KASSERT_TX_MTX(sc, q); 1190 KASSERT(count > 0 && count <= MVXPE_TX_RING_CNT); 1191 KASSERT(idx >= 0 && idx < MVXPE_TX_RING_CNT); 1192 1193 wrap = (idx + count) - MVXPE_TX_RING_CNT; 1194 if (wrap > 0) { 1195 count -= wrap; 1196 bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1197 0, sizeof(struct mvxpe_tx_desc) * wrap, ops); 1198 } 1199 bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1200 MVXPE_TX_DESC_OFF(sc, q, idx), 1201 sizeof(struct mvxpe_tx_desc) * count, ops); 1202 } 1203 1204 /* 1205 * Rx/Tx Queue Control 1206 */ 1207 STATIC int 1208 mvxpe_rx_queue_init(struct ifnet *ifp, int q) 1209 { 1210 struct mvxpe_softc *sc = ifp->if_softc; 1211 uint32_t reg; 1212 1213 KASSERT_RX_MTX(sc, q); 1214 KASSERT(MVXPE_RX_RING_MEM_PA(sc, q) != 0); 1215 1216 /* descriptor address */ 1217 MVXPE_WRITE(sc, MVXPE_PRXDQA(q), MVXPE_RX_RING_MEM_PA(sc, q)); 1218 1219 /* Rx buffer size and descriptor ring size */ 1220 reg = MVXPE_PRXDQS_BUFFERSIZE(mvxpbm_chunk_size(sc->sc_bm) >> 3); 1221 reg |= MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(MVXPE_RX_RING_CNT); 1222 MVXPE_WRITE(sc, MVXPE_PRXDQS(q), reg); 1223 DPRINTIFNET(ifp, 1, "PRXDQS(%d): %#x\n", 1224 q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 1225 1226 /* Rx packet offset address */ 1227 reg = MVXPE_PRXC_PACKETOFFSET(mvxpbm_packet_offset(sc->sc_bm) >> 3); 1228 MVXPE_WRITE(sc, MVXPE_PRXC(q), reg); 1229 DPRINTIFNET(ifp, 1, "PRXC(%d): %#x\n", 1230 q, MVXPE_READ(sc, MVXPE_PRXC(q))); 1231 1232 /* Rx DMA SNOOP */ 1233 reg = MVXPE_PRXSNP_SNOOPNOOFBYTES(MVXPE_MRU); 1234 reg |= MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(MVXPE_MRU); 1235 MVXPE_WRITE(sc, MVXPE_PRXSNP(q), reg); 1236 1237 /* if DMA is not working, register is not updated */ 1238 KASSERT(MVXPE_READ(sc, MVXPE_PRXDQA(q)) == MVXPE_RX_RING_MEM_PA(sc, q)); 1239 return 0; 1240 } 1241 1242 STATIC int 1243 mvxpe_tx_queue_init(struct ifnet *ifp, int q) 1244 { 1245 struct mvxpe_softc *sc = ifp->if_softc; 1246 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1247 uint32_t reg; 1248 1249 KASSERT_TX_MTX(sc, q); 1250 KASSERT(MVXPE_TX_RING_MEM_PA(sc, q) != 0); 1251 1252 /* descriptor address */ 1253 MVXPE_WRITE(sc, MVXPE_PTXDQA(q), MVXPE_TX_RING_MEM_PA(sc, q)); 1254 1255 /* Tx threshold, and descriptor ring size */ 1256 reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1257 reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 1258 MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1259 DPRINTIFNET(ifp, 1, "PTXDQS(%d): %#x\n", 1260 q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 1261 1262 /* if DMA is not working, register is not updated */ 1263 KASSERT(MVXPE_READ(sc, MVXPE_PTXDQA(q)) == MVXPE_TX_RING_MEM_PA(sc, q)); 1264 return 0; 1265 } 1266 1267 STATIC int 1268 mvxpe_rx_queue_enable(struct ifnet *ifp, int q) 1269 { 1270 struct mvxpe_softc *sc = ifp->if_softc; 1271 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1272 uint32_t reg; 1273 1274 KASSERT_RX_MTX(sc, q); 1275 1276 /* Set Rx interrupt threshold */ 1277 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1278 reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 1279 MVXPE_WRITE(sc, MVXPE_PRXDQTH(q), reg); 1280 1281 reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 1282 MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1283 1284 /* Unmask RXTX_TH Intr. */ 1285 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1286 reg |= MVXPE_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1287 reg |= MVXPE_PRXTXTI_RDTAQ(q); /* Rx Descriptor Alart */ 1288 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1289 1290 /* Enable Rx queue */ 1291 reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1292 reg |= MVXPE_RQC_ENQ(q); 1293 MVXPE_WRITE(sc, MVXPE_RQC, reg); 1294 1295 return 0; 1296 } 1297 1298 STATIC int 1299 mvxpe_tx_queue_enable(struct ifnet *ifp, int q) 1300 { 1301 struct mvxpe_softc *sc = ifp->if_softc; 1302 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1303 uint32_t reg; 1304 1305 KASSERT_TX_MTX(sc, q); 1306 1307 /* Set Tx interrupt threshold */ 1308 reg = MVXPE_READ(sc, MVXPE_PTXDQS(q)); 1309 reg &= ~MVXPE_PTXDQS_TBT_MASK; /* keep queue size */ 1310 reg |= MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1311 MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1312 1313 /* Unmask RXTX_TH Intr. */ 1314 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1315 reg |= MVXPE_PRXTXTI_TBTCQ(q); /* Tx Threshold cross */ 1316 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1317 1318 /* Don't update MVXPE_TQC here, there is no packet yet. */ 1319 return 0; 1320 } 1321 1322 STATIC void 1323 mvxpe_rx_lockq(struct mvxpe_softc *sc, int q) 1324 { 1325 KASSERT(q >= 0); 1326 KASSERT(q < MVXPE_QUEUE_SIZE); 1327 mutex_enter(&sc->sc_rx_ring[q].rx_ring_mtx); 1328 } 1329 1330 STATIC void 1331 mvxpe_rx_unlockq(struct mvxpe_softc *sc, int q) 1332 { 1333 KASSERT(q >= 0); 1334 KASSERT(q < MVXPE_QUEUE_SIZE); 1335 mutex_exit(&sc->sc_rx_ring[q].rx_ring_mtx); 1336 } 1337 1338 STATIC void 1339 mvxpe_tx_lockq(struct mvxpe_softc *sc, int q) 1340 { 1341 KASSERT(q >= 0); 1342 KASSERT(q < MVXPE_QUEUE_SIZE); 1343 mutex_enter(&sc->sc_tx_ring[q].tx_ring_mtx); 1344 } 1345 1346 STATIC void 1347 mvxpe_tx_unlockq(struct mvxpe_softc *sc, int q) 1348 { 1349 KASSERT(q >= 0); 1350 KASSERT(q < MVXPE_QUEUE_SIZE); 1351 mutex_exit(&sc->sc_tx_ring[q].tx_ring_mtx); 1352 } 1353 1354 /* 1355 * Interrupt Handlers 1356 */ 1357 STATIC void 1358 mvxpe_disable_intr(struct mvxpe_softc *sc) 1359 { 1360 MVXPE_WRITE(sc, MVXPE_EUIM, 0); 1361 MVXPE_WRITE(sc, MVXPE_EUIC, 0); 1362 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, 0); 1363 MVXPE_WRITE(sc, MVXPE_PRXTXTIC, 0); 1364 MVXPE_WRITE(sc, MVXPE_PRXTXIM, 0); 1365 MVXPE_WRITE(sc, MVXPE_PRXTXIC, 0); 1366 MVXPE_WRITE(sc, MVXPE_PMIM, 0); 1367 MVXPE_WRITE(sc, MVXPE_PMIC, 0); 1368 MVXPE_WRITE(sc, MVXPE_PIE, 0); 1369 } 1370 1371 STATIC void 1372 mvxpe_enable_intr(struct mvxpe_softc *sc) 1373 { 1374 uint32_t reg; 1375 1376 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1377 reg = MVXPE_READ(sc, MVXPE_PMIM); 1378 reg |= MVXPE_PMI_PHYSTATUSCHNG; 1379 reg |= MVXPE_PMI_LINKCHANGE; 1380 reg |= MVXPE_PMI_IAE; 1381 reg |= MVXPE_PMI_RXOVERRUN; 1382 reg |= MVXPE_PMI_RXCRCERROR; 1383 reg |= MVXPE_PMI_RXLARGEPACKET; 1384 reg |= MVXPE_PMI_TXUNDRN; 1385 #if 0 1386 /* 1387 * The device may raise false interrupts for SERDES even if the device 1388 * is not configured to use SERDES connection. 1389 */ 1390 reg |= MVXPE_PMI_PRBSERROR; 1391 reg |= MVXPE_PMI_SRSE; 1392 #else 1393 reg &= ~MVXPE_PMI_PRBSERROR; 1394 reg &= ~MVXPE_PMI_SRSE; 1395 #endif 1396 reg |= MVXPE_PMI_TREQ_MASK; 1397 MVXPE_WRITE(sc, MVXPE_PMIM, reg); 1398 1399 /* Enable Summary Bit to check all interrupt cause. */ 1400 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1401 reg |= MVXPE_PRXTXTI_PMISCICSUMMARY; 1402 reg |= MVXPE_PRXTXTI_PTXERRORSUMMARY; 1403 reg |= MVXPE_PRXTXTI_PRXTXICSUMMARY; 1404 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1405 1406 /* Enable All Queue Interrupt */ 1407 reg = MVXPE_READ(sc, MVXPE_PIE); 1408 reg |= MVXPE_PIE_RXPKTINTRPTENB_MASK; 1409 reg |= MVXPE_PIE_TXPKTINTRPTENB_MASK; 1410 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1411 } 1412 1413 STATIC int 1414 mvxpe_rxtxth_intr(void *arg) 1415 { 1416 struct mvxpe_softc *sc = arg; 1417 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1418 uint32_t ic, queues, datum = 0; 1419 1420 DPRINTSC(sc, 2, "got RXTX_TH_Intr\n"); 1421 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtxth); 1422 1423 mvxpe_sc_lock(sc); 1424 ic = MVXPE_READ(sc, MVXPE_PRXTXTIC); 1425 if (ic == 0) { 1426 mvxpe_sc_unlock(sc); 1427 return 0; 1428 } 1429 MVXPE_WRITE(sc, MVXPE_PRXTXTIC, ~ic); 1430 datum = datum ^ ic; 1431 1432 DPRINTIFNET(ifp, 2, "PRXTXTIC: %#x\n", ic); 1433 1434 /* ack maintance interrupt first */ 1435 if (ic & MVXPE_PRXTXTI_PTXERRORSUMMARY) { 1436 DPRINTIFNET(ifp, 1, "PRXTXTIC: +PTXERRORSUMMARY\n"); 1437 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtxth_txerr); 1438 } 1439 if ((ic & MVXPE_PRXTXTI_PMISCICSUMMARY)) { 1440 DPRINTIFNET(ifp, 2, "PTXTXTIC: +PMISCICSUMMARY\n"); 1441 mvxpe_misc_intr(sc); 1442 } 1443 if (ic & MVXPE_PRXTXTI_PRXTXICSUMMARY) { 1444 DPRINTIFNET(ifp, 2, "PTXTXTIC: +PRXTXICSUMMARY\n"); 1445 mvxpe_rxtx_intr(sc); 1446 } 1447 if (!(ifp->if_flags & IFF_RUNNING)) { 1448 mvxpe_sc_unlock(sc); 1449 return 1; 1450 } 1451 1452 /* RxTxTH interrupt */ 1453 queues = MVXPE_PRXTXTI_GET_RBICTAPQ(ic); 1454 if (queues) { 1455 DPRINTIFNET(ifp, 2, "PRXTXTIC: +RXEOF\n"); 1456 mvxpe_rx(sc, queues); 1457 } 1458 queues = MVXPE_PRXTXTI_GET_TBTCQ(ic); 1459 if (queues) { 1460 DPRINTIFNET(ifp, 2, "PRXTXTIC: +TBTCQ\n"); 1461 mvxpe_tx_complete(sc, queues); 1462 } 1463 queues = MVXPE_PRXTXTI_GET_RDTAQ(ic); 1464 if (queues) { 1465 DPRINTIFNET(ifp, 2, "PRXTXTIC: +RDTAQ\n"); 1466 mvxpe_rx_refill(sc, queues); 1467 } 1468 mvxpe_sc_unlock(sc); 1469 1470 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1471 mvxpe_start(ifp); 1472 1473 rnd_add_uint32(&sc->sc_rnd_source, datum); 1474 1475 return 1; 1476 } 1477 1478 STATIC int 1479 mvxpe_misc_intr(void *arg) 1480 { 1481 struct mvxpe_softc *sc = arg; 1482 #ifdef MVXPE_DEBUG 1483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1484 #endif 1485 uint32_t ic; 1486 uint32_t datum = 0; 1487 int claimed = 0; 1488 1489 DPRINTSC(sc, 2, "got MISC_INTR\n"); 1490 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_misc); 1491 1492 KASSERT_SC_MTX(sc); 1493 1494 for (;;) { 1495 ic = MVXPE_READ(sc, MVXPE_PMIC); 1496 ic &= MVXPE_READ(sc, MVXPE_PMIM); 1497 if (ic == 0) 1498 break; 1499 MVXPE_WRITE(sc, MVXPE_PMIC, ~ic); 1500 datum = datum ^ ic; 1501 claimed = 1; 1502 1503 DPRINTIFNET(ifp, 2, "PMIC=%#x\n", ic); 1504 if (ic & MVXPE_PMI_PHYSTATUSCHNG) { 1505 DPRINTIFNET(ifp, 2, "+PHYSTATUSCHNG\n"); 1506 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_phystatuschng); 1507 } 1508 if (ic & MVXPE_PMI_LINKCHANGE) { 1509 DPRINTIFNET(ifp, 2, "+LINKCHANGE\n"); 1510 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_linkchange); 1511 mvxpe_linkupdate(sc); 1512 } 1513 if (ic & MVXPE_PMI_IAE) { 1514 DPRINTIFNET(ifp, 2, "+IAE\n"); 1515 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_iae); 1516 } 1517 if (ic & MVXPE_PMI_RXOVERRUN) { 1518 DPRINTIFNET(ifp, 2, "+RXOVERRUN\n"); 1519 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxoverrun); 1520 } 1521 if (ic & MVXPE_PMI_RXCRCERROR) { 1522 DPRINTIFNET(ifp, 2, "+RXCRCERROR\n"); 1523 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxcrc); 1524 } 1525 if (ic & MVXPE_PMI_RXLARGEPACKET) { 1526 DPRINTIFNET(ifp, 2, "+RXLARGEPACKET\n"); 1527 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxlargepacket); 1528 } 1529 if (ic & MVXPE_PMI_TXUNDRN) { 1530 DPRINTIFNET(ifp, 2, "+TXUNDRN\n"); 1531 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txunderrun); 1532 } 1533 if (ic & MVXPE_PMI_PRBSERROR) { 1534 DPRINTIFNET(ifp, 2, "+PRBSERROR\n"); 1535 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_prbserr); 1536 } 1537 if (ic & MVXPE_PMI_TREQ_MASK) { 1538 DPRINTIFNET(ifp, 2, "+TREQ\n"); 1539 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txreq); 1540 } 1541 } 1542 if (datum) 1543 rnd_add_uint32(&sc->sc_rnd_source, datum); 1544 1545 return claimed; 1546 } 1547 1548 STATIC int 1549 mvxpe_rxtx_intr(void *arg) 1550 { 1551 struct mvxpe_softc *sc = arg; 1552 #ifdef MVXPE_DEBUG 1553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1554 #endif 1555 uint32_t datum = 0; 1556 uint32_t prxtxic; 1557 int claimed = 0; 1558 1559 DPRINTSC(sc, 2, "got RXTX_Intr\n"); 1560 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtx); 1561 1562 KASSERT_SC_MTX(sc); 1563 1564 for (;;) { 1565 prxtxic = MVXPE_READ(sc, MVXPE_PRXTXIC); 1566 prxtxic &= MVXPE_READ(sc, MVXPE_PRXTXIM); 1567 if (prxtxic == 0) 1568 break; 1569 MVXPE_WRITE(sc, MVXPE_PRXTXIC, ~prxtxic); 1570 datum = datum ^ prxtxic; 1571 claimed = 1; 1572 1573 DPRINTSC(sc, 2, "PRXTXIC: %#x\n", prxtxic); 1574 1575 if (prxtxic & MVXPE_PRXTXI_RREQ_MASK) { 1576 DPRINTIFNET(ifp, 1, "Rx Resource Error.\n"); 1577 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rreq); 1578 } 1579 if (prxtxic & MVXPE_PRXTXI_RPQ_MASK) { 1580 DPRINTIFNET(ifp, 1, "Rx Packet in Queue.\n"); 1581 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rpq); 1582 } 1583 if (prxtxic & MVXPE_PRXTXI_TBRQ_MASK) { 1584 DPRINTIFNET(ifp, 1, "Tx Buffer Return.\n"); 1585 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_tbrq); 1586 } 1587 if (prxtxic & MVXPE_PRXTXI_PRXTXTHICSUMMARY) { 1588 DPRINTIFNET(ifp, 1, "PRXTXTHIC Sumary\n"); 1589 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rxtxth); 1590 } 1591 if (prxtxic & MVXPE_PRXTXI_PTXERRORSUMMARY) { 1592 DPRINTIFNET(ifp, 1, "PTXERROR Sumary\n"); 1593 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_txerr); 1594 } 1595 if (prxtxic & MVXPE_PRXTXI_PMISCICSUMMARY) { 1596 DPRINTIFNET(ifp, 1, "PMISCIC Sumary\n"); 1597 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_misc); 1598 } 1599 } 1600 if (datum) 1601 rnd_add_uint32(&sc->sc_rnd_source, datum); 1602 1603 return claimed; 1604 } 1605 1606 STATIC void 1607 mvxpe_tick(void *arg) 1608 { 1609 struct mvxpe_softc *sc = arg; 1610 struct mii_data *mii = &sc->sc_mii; 1611 1612 mvxpe_sc_lock(sc); 1613 1614 mii_tick(mii); 1615 mii_pollstat(&sc->sc_mii); 1616 1617 /* read mib regisers(clear by read) */ 1618 mvxpe_update_mib(sc); 1619 1620 /* read counter registers(clear by read) */ 1621 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pdfc, 1622 MVXPE_READ(sc, MVXPE_PDFC)); 1623 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pofc, 1624 MVXPE_READ(sc, MVXPE_POFC)); 1625 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txbadfcs, 1626 MVXPE_READ(sc, MVXPE_TXBADFCS)); 1627 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txdropped, 1628 MVXPE_READ(sc, MVXPE_TXDROPPED)); 1629 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_lpic, 1630 MVXPE_READ(sc, MVXPE_LPIC)); 1631 1632 mvxpe_sc_unlock(sc); 1633 1634 callout_schedule(&sc->sc_tick_ch, hz); 1635 } 1636 1637 1638 /* 1639 * struct ifnet and mii callbacks 1640 */ 1641 STATIC void 1642 mvxpe_start(struct ifnet *ifp) 1643 { 1644 struct mvxpe_softc *sc = ifp->if_softc; 1645 struct mbuf *m; 1646 int q; 1647 1648 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1649 DPRINTIFNET(ifp, 1, "not running\n"); 1650 return; 1651 } 1652 1653 mvxpe_sc_lock(sc); 1654 if (!MVXPE_IS_LINKUP(sc)) { 1655 /* If Link is DOWN, can't start TX */ 1656 DPRINTIFNET(ifp, 1, "link fail\n"); 1657 for (;;) { 1658 /* 1659 * discard stale packets all. 1660 * these may confuse DAD, ARP or timer based protocols. 1661 */ 1662 IFQ_DEQUEUE(&ifp->if_snd, m); 1663 if (m == NULL) 1664 break; 1665 m_freem(m); 1666 } 1667 mvxpe_sc_unlock(sc); 1668 return; 1669 } 1670 for (;;) { 1671 /* 1672 * don't use IFQ_POLL(). 1673 * there is lock problem between IFQ_POLL and IFQ_DEQUEUE 1674 * on SMP enabled networking stack. 1675 */ 1676 IFQ_DEQUEUE(&ifp->if_snd, m); 1677 if (m == NULL) 1678 break; 1679 1680 q = mvxpe_tx_queue_select(sc, m); 1681 if (q < 0) 1682 break; 1683 /* mutex is held in mvxpe_tx_queue_select() */ 1684 1685 if (mvxpe_tx_queue(sc, m, q) != 0) { 1686 DPRINTIFNET(ifp, 1, "cannot add packet to tx ring\n"); 1687 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txerr); 1688 mvxpe_tx_unlockq(sc, q); 1689 break; 1690 } 1691 mvxpe_tx_unlockq(sc, q); 1692 KASSERT(sc->sc_tx_ring[q].tx_used >= 0); 1693 KASSERT(sc->sc_tx_ring[q].tx_used <= 1694 sc->sc_tx_ring[q].tx_queue_len); 1695 DPRINTIFNET(ifp, 1, "a packet is added to tx ring\n"); 1696 sc->sc_tx_pending++; 1697 ifp->if_opackets++; 1698 ifp->if_timer = 1; 1699 sc->sc_wdogsoft = 1; 1700 bpf_mtap(ifp, m); 1701 } 1702 mvxpe_sc_unlock(sc); 1703 1704 return; 1705 } 1706 1707 STATIC int 1708 mvxpe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1709 { 1710 struct mvxpe_softc *sc = ifp->if_softc; 1711 struct ifreq *ifr = data; 1712 int error = 0; 1713 int s; 1714 1715 switch (cmd) { 1716 case SIOCGIFMEDIA: 1717 case SIOCSIFMEDIA: 1718 DPRINTIFNET(ifp, 2, "mvxpe_ioctl MEDIA\n"); 1719 s = splnet(); /* XXX: is there suitable mutex? */ 1720 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1721 splx(s); 1722 break; 1723 default: 1724 DPRINTIFNET(ifp, 2, "mvxpe_ioctl ETHER\n"); 1725 error = ether_ioctl(ifp, cmd, data); 1726 if (error == ENETRESET) { 1727 if (ifp->if_flags & IFF_RUNNING) { 1728 mvxpe_sc_lock(sc); 1729 mvxpe_filter_setup(sc); 1730 mvxpe_sc_unlock(sc); 1731 } 1732 error = 0; 1733 } 1734 break; 1735 } 1736 1737 return error; 1738 } 1739 1740 STATIC int 1741 mvxpe_init(struct ifnet *ifp) 1742 { 1743 struct mvxpe_softc *sc = ifp->if_softc; 1744 struct mii_data *mii = &sc->sc_mii; 1745 uint32_t reg; 1746 int q; 1747 1748 mvxpe_sc_lock(sc); 1749 1750 /* Start DMA Engine */ 1751 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 1752 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 1753 MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 1754 1755 /* Enable port */ 1756 reg = MVXPE_READ(sc, MVXPE_PMACC0); 1757 reg |= MVXPE_PMACC0_PORTEN; 1758 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1759 1760 /* Link up */ 1761 mvxpe_linkup(sc); 1762 1763 /* Enable All Queue and interrupt of each Queue */ 1764 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1765 mvxpe_rx_lockq(sc, q); 1766 mvxpe_rx_queue_enable(ifp, q); 1767 mvxpe_rx_queue_refill(sc, q); 1768 mvxpe_rx_unlockq(sc, q); 1769 1770 mvxpe_tx_lockq(sc, q); 1771 mvxpe_tx_queue_enable(ifp, q); 1772 mvxpe_tx_unlockq(sc, q); 1773 } 1774 1775 /* Enable interrupt */ 1776 mvxpe_enable_intr(sc); 1777 1778 /* Set Counter */ 1779 callout_schedule(&sc->sc_tick_ch, hz); 1780 1781 /* Media check */ 1782 mii_mediachg(mii); 1783 1784 ifp->if_flags |= IFF_RUNNING; 1785 ifp->if_flags &= ~IFF_OACTIVE; 1786 1787 mvxpe_sc_unlock(sc); 1788 return 0; 1789 } 1790 1791 /* ARGSUSED */ 1792 STATIC void 1793 mvxpe_stop(struct ifnet *ifp, int disable) 1794 { 1795 struct mvxpe_softc *sc = ifp->if_softc; 1796 uint32_t reg; 1797 int q, cnt; 1798 1799 DPRINTIFNET(ifp, 1, "stop device dma and interrupts.\n"); 1800 1801 mvxpe_sc_lock(sc); 1802 1803 callout_stop(&sc->sc_tick_ch); 1804 1805 /* Link down */ 1806 mvxpe_linkdown(sc); 1807 1808 /* Disable Rx interrupt */ 1809 reg = MVXPE_READ(sc, MVXPE_PIE); 1810 reg &= ~MVXPE_PIE_RXPKTINTRPTENB_MASK; 1811 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1812 1813 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1814 reg &= ~MVXPE_PRXTXTI_RBICTAPQ_MASK; 1815 reg &= ~MVXPE_PRXTXTI_RDTAQ_MASK; 1816 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1817 1818 /* Wait for all Rx activity to terminate. */ 1819 reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1820 reg = MVXPE_RQC_DIS(reg); 1821 MVXPE_WRITE(sc, MVXPE_RQC, reg); 1822 cnt = 0; 1823 do { 1824 if (cnt >= RX_DISABLE_TIMEOUT) { 1825 aprint_error_ifnet(ifp, 1826 "timeout for RX stopped. rqc 0x%x\n", reg); 1827 break; 1828 } 1829 cnt++; 1830 reg = MVXPE_READ(sc, MVXPE_RQC); 1831 } while (reg & MVXPE_RQC_EN_MASK); 1832 1833 /* Wait for all Tx activety to terminate. */ 1834 reg = MVXPE_READ(sc, MVXPE_PIE); 1835 reg &= ~MVXPE_PIE_TXPKTINTRPTENB_MASK; 1836 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1837 1838 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1839 reg &= ~MVXPE_PRXTXTI_TBTCQ_MASK; 1840 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1841 1842 reg = MVXPE_READ(sc, MVXPE_TQC) & MVXPE_TQC_EN_MASK; 1843 reg = MVXPE_TQC_DIS(reg); 1844 MVXPE_WRITE(sc, MVXPE_TQC, reg); 1845 cnt = 0; 1846 do { 1847 if (cnt >= TX_DISABLE_TIMEOUT) { 1848 aprint_error_ifnet(ifp, 1849 "timeout for TX stopped. tqc 0x%x\n", reg); 1850 break; 1851 } 1852 cnt++; 1853 reg = MVXPE_READ(sc, MVXPE_TQC); 1854 } while (reg & MVXPE_TQC_EN_MASK); 1855 1856 /* Wait for all Tx FIFO is empty */ 1857 cnt = 0; 1858 do { 1859 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1860 aprint_error_ifnet(ifp, 1861 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1862 break; 1863 } 1864 cnt++; 1865 reg = MVXPE_READ(sc, MVXPE_PS0); 1866 } while (!(reg & MVXPE_PS0_TXFIFOEMP) && (reg & MVXPE_PS0_TXINPROG)); 1867 1868 /* Reset the MAC Port Enable bit */ 1869 reg = MVXPE_READ(sc, MVXPE_PMACC0); 1870 reg &= ~MVXPE_PMACC0_PORTEN; 1871 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1872 1873 /* Disable each of queue */ 1874 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1875 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1876 1877 mvxpe_rx_lockq(sc, q); 1878 mvxpe_tx_lockq(sc, q); 1879 1880 /* Disable Rx packet buffer refill request */ 1881 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1882 reg |= MVXPE_PRXDQTH_NODT(0); 1883 MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1884 1885 if (disable) { 1886 /* 1887 * Hold Reset state of DMA Engine 1888 * (must write 0x0 to restart it) 1889 */ 1890 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 1891 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 1892 mvxpe_ring_flush_queue(sc, q); 1893 } 1894 1895 mvxpe_tx_unlockq(sc, q); 1896 mvxpe_rx_unlockq(sc, q); 1897 } 1898 1899 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1900 1901 mvxpe_sc_unlock(sc); 1902 } 1903 1904 STATIC void 1905 mvxpe_watchdog(struct ifnet *ifp) 1906 { 1907 struct mvxpe_softc *sc = ifp->if_softc; 1908 int q; 1909 1910 mvxpe_sc_lock(sc); 1911 1912 /* 1913 * Reclaim first as there is a possibility of losing Tx completion 1914 * interrupts. 1915 */ 1916 mvxpe_tx_complete(sc, 0xff); 1917 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1918 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1919 1920 if (tx->tx_dma != tx->tx_cpu) { 1921 if (sc->sc_wdogsoft) { 1922 /* 1923 * There is race condition between CPU and DMA 1924 * engine. When DMA engine encounters queue end, 1925 * it clears MVXPE_TQC_ENQ bit. 1926 * XXX: how about enhanced mode? 1927 */ 1928 MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 1929 ifp->if_timer = 5; 1930 sc->sc_wdogsoft = 0; 1931 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_wdogsoft); 1932 } else { 1933 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1934 ifp->if_oerrors++; 1935 mvxpe_linkreset(sc); 1936 mvxpe_sc_unlock(sc); 1937 1938 /* trigger reinitialize sequence */ 1939 mvxpe_stop(ifp, 1); 1940 mvxpe_init(ifp); 1941 1942 mvxpe_sc_lock(sc); 1943 } 1944 } 1945 } 1946 mvxpe_sc_unlock(sc); 1947 } 1948 1949 STATIC int 1950 mvxpe_ifflags_cb(struct ethercom *ec) 1951 { 1952 struct ifnet *ifp = &ec->ec_if; 1953 struct mvxpe_softc *sc = ifp->if_softc; 1954 int change = ifp->if_flags ^ sc->sc_if_flags; 1955 1956 mvxpe_sc_lock(sc); 1957 1958 if (change != 0) 1959 sc->sc_if_flags = ifp->if_flags; 1960 1961 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) { 1962 mvxpe_sc_unlock(sc); 1963 return ENETRESET; 1964 } 1965 1966 if ((change & IFF_PROMISC) != 0) 1967 mvxpe_filter_setup(sc); 1968 1969 if ((change & IFF_UP) != 0) 1970 mvxpe_linkreset(sc); 1971 1972 mvxpe_sc_unlock(sc); 1973 return 0; 1974 } 1975 1976 STATIC int 1977 mvxpe_mediachange(struct ifnet *ifp) 1978 { 1979 return ether_mediachange(ifp); 1980 } 1981 1982 STATIC void 1983 mvxpe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1984 { 1985 ether_mediastatus(ifp, ifmr); 1986 } 1987 1988 /* 1989 * Link State Notify 1990 */ 1991 STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc) 1992 { 1993 int linkup; /* bool */ 1994 1995 KASSERT_SC_MTX(sc); 1996 1997 /* tell miibus */ 1998 mii_pollstat(&sc->sc_mii); 1999 2000 /* syslog */ 2001 linkup = MVXPE_IS_LINKUP(sc); 2002 if (sc->sc_linkstate == linkup) 2003 return; 2004 2005 #ifdef DEBUG 2006 log(LOG_DEBUG, 2007 "%s: link %s\n", device_xname(sc->sc_dev), linkup ? "up" : "down"); 2008 #endif 2009 if (linkup) 2010 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_up); 2011 else 2012 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_down); 2013 2014 sc->sc_linkstate = linkup; 2015 } 2016 2017 STATIC void 2018 mvxpe_linkup(struct mvxpe_softc *sc) 2019 { 2020 uint32_t reg; 2021 2022 KASSERT_SC_MTX(sc); 2023 2024 /* set EEE parameters */ 2025 reg = MVXPE_READ(sc, MVXPE_LPIC1); 2026 if (sc->sc_cf.cf_lpi) 2027 reg |= MVXPE_LPIC1_LPIRE; 2028 else 2029 reg &= ~MVXPE_LPIC1_LPIRE; 2030 MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 2031 2032 /* set auto-negotiation parameters */ 2033 reg = MVXPE_READ(sc, MVXPE_PANC); 2034 if (sc->sc_cf.cf_fc) { 2035 /* flow control negotiation */ 2036 reg |= MVXPE_PANC_PAUSEADV; 2037 reg |= MVXPE_PANC_ANFCEN; 2038 } 2039 else { 2040 reg &= ~MVXPE_PANC_PAUSEADV; 2041 reg &= ~MVXPE_PANC_ANFCEN; 2042 } 2043 reg &= ~MVXPE_PANC_FORCELINKFAIL; 2044 reg &= ~MVXPE_PANC_FORCELINKPASS; 2045 MVXPE_WRITE(sc, MVXPE_PANC, reg); 2046 2047 mii_mediachg(&sc->sc_mii); 2048 } 2049 2050 STATIC void 2051 mvxpe_linkdown(struct mvxpe_softc *sc) 2052 { 2053 struct mii_softc *mii; 2054 uint32_t reg; 2055 2056 KASSERT_SC_MTX(sc); 2057 return; 2058 2059 reg = MVXPE_READ(sc, MVXPE_PANC); 2060 reg |= MVXPE_PANC_FORCELINKFAIL; 2061 reg &= MVXPE_PANC_FORCELINKPASS; 2062 MVXPE_WRITE(sc, MVXPE_PANC, reg); 2063 2064 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2065 if (mii) 2066 mii_phy_down(mii); 2067 } 2068 2069 STATIC void 2070 mvxpe_linkreset(struct mvxpe_softc *sc) 2071 { 2072 struct mii_softc *mii; 2073 2074 KASSERT_SC_MTX(sc); 2075 2076 /* force reset PHY first */ 2077 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2078 if (mii) 2079 mii_phy_reset(mii); 2080 2081 /* reinit MAC and PHY */ 2082 mvxpe_linkdown(sc); 2083 if ((sc->sc_if_flags & IFF_UP) != 0) 2084 mvxpe_linkup(sc); 2085 } 2086 2087 /* 2088 * Tx Subroutines 2089 */ 2090 STATIC int 2091 mvxpe_tx_queue_select(struct mvxpe_softc *sc, struct mbuf *m) 2092 { 2093 int q = 0; 2094 2095 /* XXX: get attribute from ALTQ framework? */ 2096 mvxpe_tx_lockq(sc, q); 2097 return 0; 2098 } 2099 2100 STATIC int 2101 mvxpe_tx_queue(struct mvxpe_softc *sc, struct mbuf *m, int q) 2102 { 2103 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2104 bus_dma_segment_t *txsegs; 2105 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2106 struct mvxpe_tx_desc *t = NULL; 2107 uint32_t ptxsu; 2108 int txnsegs; 2109 int start, used; 2110 int i; 2111 2112 KASSERT_TX_MTX(sc, q); 2113 KASSERT(tx->tx_used >= 0); 2114 KASSERT(tx->tx_used <= tx->tx_queue_len); 2115 2116 /* load mbuf using dmamap of 1st descriptor */ 2117 if (bus_dmamap_load_mbuf(sc->sc_dmat, 2118 MVXPE_TX_MAP(sc, q, tx->tx_cpu), m, BUS_DMA_NOWAIT) != 0) { 2119 m_freem(m); 2120 return ENOBUFS; 2121 } 2122 txsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_segs; 2123 txnsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_nsegs; 2124 if (txnsegs <= 0 || (txnsegs + tx->tx_used) > tx->tx_queue_len) { 2125 /* we have no enough descriptors or mbuf is broken */ 2126 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, tx->tx_cpu)); 2127 m_freem(m); 2128 return ENOBUFS; 2129 } 2130 DPRINTSC(sc, 2, "send packet %p descriptor %d\n", m, tx->tx_cpu); 2131 KASSERT(MVXPE_TX_MBUF(sc, q, tx->tx_cpu) == NULL); 2132 2133 /* remember mbuf using 1st descriptor */ 2134 MVXPE_TX_MBUF(sc, q, tx->tx_cpu) = m; 2135 bus_dmamap_sync(sc->sc_dmat, 2136 MVXPE_TX_MAP(sc, q, tx->tx_cpu), 0, m->m_pkthdr.len, 2137 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2138 2139 /* load to tx descriptors */ 2140 start = tx->tx_cpu; 2141 used = 0; 2142 for (i = 0; i < txnsegs; i++) { 2143 if (__predict_false(txsegs[i].ds_len == 0)) 2144 continue; 2145 t = MVXPE_TX_DESC(sc, q, tx->tx_cpu); 2146 t->command = 0; 2147 t->l4ichk = 0; 2148 t->flags = 0; 2149 if (i == 0) { 2150 /* 1st descriptor */ 2151 t->command |= MVXPE_TX_CMD_W_PACKET_OFFSET(0); 2152 t->command |= MVXPE_TX_CMD_PADDING; 2153 t->command |= MVXPE_TX_CMD_F; 2154 mvxpe_tx_set_csumflag(ifp, t, m); 2155 } 2156 t->bufptr = txsegs[i].ds_addr; 2157 t->bytecnt = txsegs[i].ds_len; 2158 tx->tx_cpu = tx_counter_adv(tx->tx_cpu, 1); 2159 tx->tx_used++; 2160 used++; 2161 } 2162 /* t is last descriptor here */ 2163 KASSERT(t != NULL); 2164 t->command |= MVXPE_TX_CMD_L; 2165 2166 DPRINTSC(sc, 2, "queue %d, %d descriptors used\n", q, used); 2167 #ifdef MVXPE_DEBUG 2168 if (mvxpe_debug > 2) 2169 for (i = start; i <= tx->tx_cpu; i++) { 2170 t = MVXPE_TX_DESC(sc, q, i); 2171 mvxpe_dump_txdesc(t, i); 2172 } 2173 #endif 2174 mvxpe_ring_sync_tx(sc, q, start, used, 2175 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2176 2177 while (used > 255) { 2178 ptxsu = MVXPE_PTXSU_NOWD(255); 2179 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2180 used -= 255; 2181 } 2182 if (used > 0) { 2183 ptxsu = MVXPE_PTXSU_NOWD(used); 2184 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2185 } 2186 MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 2187 2188 DPRINTSC(sc, 2, 2189 "PTXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQA(q))); 2190 DPRINTSC(sc, 2, 2191 "PTXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 2192 DPRINTSC(sc, 2, 2193 "PTXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXS(q))); 2194 DPRINTSC(sc, 2, 2195 "PTXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PTXDI(q))); 2196 DPRINTSC(sc, 2, "TQC: %#x\n", MVXPE_READ(sc, MVXPE_TQC)); 2197 DPRINTIFNET(ifp, 2, 2198 "Tx: tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2199 tx->tx_cpu, tx->tx_dma, tx->tx_used); 2200 return 0; 2201 } 2202 2203 STATIC void 2204 mvxpe_tx_set_csumflag(struct ifnet *ifp, 2205 struct mvxpe_tx_desc *t, struct mbuf *m) 2206 { 2207 struct ether_header *eh; 2208 int csum_flags; 2209 uint32_t iphl = 0, ipoff = 0; 2210 2211 2212 csum_flags = ifp->if_csum_flags_tx & m->m_pkthdr.csum_flags; 2213 2214 eh = mtod(m, struct ether_header *); 2215 switch (htons(eh->ether_type)) { 2216 case ETHERTYPE_IP: 2217 case ETHERTYPE_IPV6: 2218 ipoff = ETHER_HDR_LEN; 2219 break; 2220 case ETHERTYPE_VLAN: 2221 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2222 break; 2223 } 2224 2225 if (csum_flags & (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 2226 iphl = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2227 t->command |= MVXPE_TX_CMD_L3_IP4; 2228 } 2229 else if (csum_flags & (M_CSUM_TCPv6|M_CSUM_UDPv6)) { 2230 iphl = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 2231 t->command |= MVXPE_TX_CMD_L3_IP6; 2232 } 2233 else { 2234 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2235 return; 2236 } 2237 2238 2239 /* L3 */ 2240 if (csum_flags & M_CSUM_IPv4) { 2241 t->command |= MVXPE_TX_CMD_IP4_CHECKSUM; 2242 } 2243 2244 /* L4 */ 2245 if ((csum_flags & 2246 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6)) == 0) { 2247 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2248 } 2249 else if (csum_flags & M_CSUM_TCPv4) { 2250 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2251 t->command |= MVXPE_TX_CMD_L4_TCP; 2252 } 2253 else if (csum_flags & M_CSUM_UDPv4) { 2254 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2255 t->command |= MVXPE_TX_CMD_L4_UDP; 2256 } 2257 else if (csum_flags & M_CSUM_TCPv6) { 2258 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2259 t->command |= MVXPE_TX_CMD_L4_TCP; 2260 } 2261 else if (csum_flags & M_CSUM_UDPv6) { 2262 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2263 t->command |= MVXPE_TX_CMD_L4_UDP; 2264 } 2265 2266 t->l4ichk = 0; 2267 t->command |= MVXPE_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2268 t->command |= MVXPE_TX_CMD_L3_OFFSET(ipoff); 2269 } 2270 2271 STATIC void 2272 mvxpe_tx_complete(struct mvxpe_softc *sc, uint32_t queues) 2273 { 2274 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2275 int q; 2276 2277 DPRINTSC(sc, 2, "tx completed.\n"); 2278 2279 KASSERT_SC_MTX(sc); 2280 2281 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2282 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2283 continue; 2284 mvxpe_tx_lockq(sc, q); 2285 mvxpe_tx_queue_complete(sc, q); 2286 mvxpe_tx_unlockq(sc, q); 2287 } 2288 KASSERT(sc->sc_tx_pending >= 0); 2289 if (sc->sc_tx_pending == 0) 2290 ifp->if_timer = 0; 2291 } 2292 2293 STATIC void 2294 mvxpe_tx_queue_complete(struct mvxpe_softc *sc, int q) 2295 { 2296 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2297 struct mvxpe_tx_desc *t; 2298 uint32_t ptxs, ptxsu, ndesc; 2299 int i; 2300 2301 KASSERT_TX_MTX(sc, q); 2302 2303 ptxs = MVXPE_READ(sc, MVXPE_PTXS(q)); 2304 ndesc = MVXPE_PTXS_GET_TBC(ptxs); 2305 if (ndesc == 0) 2306 return; 2307 2308 DPRINTSC(sc, 2, 2309 "tx complete queue %d, %d descriptors.\n", q, ndesc); 2310 2311 mvxpe_ring_sync_tx(sc, q, tx->tx_dma, ndesc, 2312 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2313 2314 for (i = 0; i < ndesc; i++) { 2315 int error = 0; 2316 2317 t = MVXPE_TX_DESC(sc, q, tx->tx_dma); 2318 if (t->flags & MVXPE_TX_F_ES) { 2319 DPRINTSC(sc, 1, 2320 "tx error queue %d desc %d\n", 2321 q, tx->tx_dma); 2322 switch (t->flags & MVXPE_TX_F_EC_MASK) { 2323 case MVXPE_TX_F_EC_LC: 2324 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_lc); 2325 break; 2326 case MVXPE_TX_F_EC_UR: 2327 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_ur); 2328 break; 2329 case MVXPE_TX_F_EC_RL: 2330 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_rl); 2331 break; 2332 default: 2333 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_oth); 2334 break; 2335 } 2336 error = 1; 2337 } 2338 if (MVXPE_TX_MBUF(sc, q, tx->tx_dma) != NULL) { 2339 KASSERT((t->command & MVXPE_TX_CMD_F) != 0); 2340 bus_dmamap_unload(sc->sc_dmat, 2341 MVXPE_TX_MAP(sc, q, tx->tx_dma)); 2342 m_freem(MVXPE_TX_MBUF(sc, q, tx->tx_dma)); 2343 MVXPE_TX_MBUF(sc, q, tx->tx_dma) = NULL; 2344 sc->sc_tx_pending--; 2345 } 2346 else 2347 KASSERT((t->flags & MVXPE_TX_CMD_F) == 0); 2348 tx->tx_dma = tx_counter_adv(tx->tx_dma, 1); 2349 tx->tx_used--; 2350 if (error) 2351 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txqe[q]); 2352 else 2353 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txq[q]); 2354 } 2355 KASSERT(tx->tx_used >= 0); 2356 KASSERT(tx->tx_used <= tx->tx_queue_len); 2357 while (ndesc > 255) { 2358 ptxsu = MVXPE_PTXSU_NORB(255); 2359 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2360 ndesc -= 255; 2361 } 2362 if (ndesc > 0) { 2363 ptxsu = MVXPE_PTXSU_NORB(ndesc); 2364 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2365 } 2366 DPRINTSC(sc, 2, 2367 "Tx complete q %d, tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2368 q, tx->tx_cpu, tx->tx_dma, tx->tx_used); 2369 } 2370 2371 /* 2372 * Rx Subroutines 2373 */ 2374 STATIC void 2375 mvxpe_rx(struct mvxpe_softc *sc, uint32_t queues) 2376 { 2377 int q, npkt; 2378 2379 KASSERT_SC_MTX(sc); 2380 2381 while ( (npkt = mvxpe_rx_queue_select(sc, queues, &q))) { 2382 /* mutex is held by rx_queue_select */ 2383 mvxpe_rx_queue(sc, q, npkt); 2384 mvxpe_rx_unlockq(sc, q); 2385 } 2386 } 2387 2388 STATIC void 2389 mvxpe_rx_queue(struct mvxpe_softc *sc, int q, int npkt) 2390 { 2391 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2392 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2393 struct mvxpe_rx_desc *r; 2394 struct mvxpbm_chunk *chunk; 2395 struct mbuf *m; 2396 uint32_t prxsu; 2397 int error = 0; 2398 int i; 2399 2400 KASSERT_RX_MTX(sc, q); 2401 2402 mvxpe_ring_sync_rx(sc, q, rx->rx_dma, npkt, 2403 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2404 2405 for (i = 0; i < npkt; i++) { 2406 /* get descriptor and packet */ 2407 chunk = MVXPE_RX_PKTBUF(sc, q, rx->rx_dma); 2408 MVXPE_RX_PKTBUF(sc, q, rx->rx_dma) = NULL; 2409 r = MVXPE_RX_DESC(sc, q, rx->rx_dma); 2410 mvxpbm_dmamap_sync(chunk, r->bytecnt, BUS_DMASYNC_POSTREAD); 2411 2412 /* check errors */ 2413 if (r->status & MVXPE_RX_ES) { 2414 switch (r->status & MVXPE_RX_EC_MASK) { 2415 case MVXPE_RX_EC_CE: 2416 DPRINTIFNET(ifp, 1, "CRC error\n"); 2417 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_ce); 2418 break; 2419 case MVXPE_RX_EC_OR: 2420 DPRINTIFNET(ifp, 1, "Rx FIFO overrun\n"); 2421 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_or); 2422 break; 2423 case MVXPE_RX_EC_MF: 2424 DPRINTIFNET(ifp, 1, "Rx too large frame\n"); 2425 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_mf); 2426 break; 2427 case MVXPE_RX_EC_RE: 2428 DPRINTIFNET(ifp, 1, "Rx resource error\n"); 2429 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_re); 2430 break; 2431 } 2432 error = 1; 2433 goto rx_done; 2434 } 2435 if (!(r->status & MVXPE_RX_F) || !(r->status & MVXPE_RX_L)) { 2436 DPRINTIFNET(ifp, 1, "not support scatter buf\n"); 2437 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_scat); 2438 error = 1; 2439 goto rx_done; 2440 } 2441 2442 if (chunk == NULL) { 2443 device_printf(sc->sc_dev, 2444 "got rx interrupt, but no chunk\n"); 2445 error = 1; 2446 goto rx_done; 2447 } 2448 2449 /* extract packet buffer */ 2450 if (mvxpbm_init_mbuf_hdr(chunk) != 0) { 2451 error = 1; 2452 goto rx_done; 2453 } 2454 m = chunk->m; 2455 m->m_pkthdr.rcvif = ifp; 2456 m->m_pkthdr.len = m->m_len = r->bytecnt - ETHER_CRC_LEN; 2457 m_adj(m, MVXPE_HWHEADER_SIZE); /* strip MH */ 2458 mvxpe_rx_set_csumflag(ifp, r, m); 2459 ifp->if_ipackets++; 2460 bpf_mtap(ifp, m); 2461 if_percpuq_enqueue(ifp->if_percpuq, m); 2462 chunk = NULL; /* the BM chunk goes to networking stack now */ 2463 rx_done: 2464 if (chunk) { 2465 /* rx error. just return the chunk to BM. */ 2466 mvxpbm_free_chunk(chunk); 2467 } 2468 if (error) 2469 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxqe[q]); 2470 else 2471 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxq[q]); 2472 rx->rx_dma = rx_counter_adv(rx->rx_dma, 1); 2473 } 2474 /* DMA status update */ 2475 DPRINTSC(sc, 2, "%d packets received from queue %d\n", npkt, q); 2476 while (npkt > 255) { 2477 prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2478 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2479 npkt -= 255; 2480 } 2481 if (npkt > 0) { 2482 prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(npkt); 2483 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2484 } 2485 2486 DPRINTSC(sc, 2, 2487 "PRXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQA(q))); 2488 DPRINTSC(sc, 2, 2489 "PRXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 2490 DPRINTSC(sc, 2, 2491 "PRXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXS(q))); 2492 DPRINTSC(sc, 2, 2493 "PRXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PRXDI(q))); 2494 DPRINTSC(sc, 2, "RQC: %#x\n", MVXPE_READ(sc, MVXPE_RQC)); 2495 DPRINTIFNET(ifp, 2, "Rx: rx_cpu = %d, rx_dma = %d\n", 2496 rx->rx_cpu, rx->rx_dma); 2497 } 2498 2499 STATIC int 2500 mvxpe_rx_queue_select(struct mvxpe_softc *sc, uint32_t queues, int *queue) 2501 { 2502 uint32_t prxs, npkt; 2503 int q; 2504 2505 KASSERT_SC_MTX(sc); 2506 KASSERT(queue != NULL); 2507 DPRINTSC(sc, 2, "selecting rx queue\n"); 2508 2509 for (q = MVXPE_QUEUE_SIZE - 1; q >= 0; q--) { 2510 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2511 continue; 2512 2513 prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2514 npkt = MVXPE_PRXS_GET_ODC(prxs); 2515 if (npkt == 0) 2516 continue; 2517 2518 DPRINTSC(sc, 2, 2519 "queue %d selected: prxs=%#x, %u pakcet received.\n", 2520 q, prxs, npkt); 2521 *queue = q; 2522 mvxpe_rx_lockq(sc, q); 2523 return npkt; 2524 } 2525 2526 return 0; 2527 } 2528 2529 STATIC void 2530 mvxpe_rx_refill(struct mvxpe_softc *sc, uint32_t queues) 2531 { 2532 int q; 2533 2534 KASSERT_SC_MTX(sc); 2535 2536 /* XXX: check rx bit array */ 2537 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2538 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2539 continue; 2540 2541 mvxpe_rx_lockq(sc, q); 2542 mvxpe_rx_queue_refill(sc, q); 2543 mvxpe_rx_unlockq(sc, q); 2544 } 2545 } 2546 2547 STATIC void 2548 mvxpe_rx_queue_refill(struct mvxpe_softc *sc, int q) 2549 { 2550 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2551 uint32_t prxs, prxsu, ndesc; 2552 int idx, refill = 0; 2553 int npkt; 2554 2555 KASSERT_RX_MTX(sc, q); 2556 2557 prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2558 ndesc = MVXPE_PRXS_GET_NODC(prxs) + MVXPE_PRXS_GET_ODC(prxs); 2559 refill = rx->rx_queue_len - ndesc; 2560 if (refill <= 0) 2561 return; 2562 DPRINTPRXS(2, q); 2563 DPRINTSC(sc, 2, "%d buffers to refill.\n", refill); 2564 2565 idx = rx->rx_cpu; 2566 for (npkt = 0; npkt < refill; npkt++) 2567 if (mvxpe_rx_queue_add(sc, q) != 0) 2568 break; 2569 DPRINTSC(sc, 2, "queue %d, %d buffer refilled.\n", q, npkt); 2570 if (npkt == 0) 2571 return; 2572 2573 mvxpe_ring_sync_rx(sc, q, idx, npkt, 2574 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2575 2576 while (npkt > 255) { 2577 prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(255); 2578 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2579 npkt -= 255; 2580 } 2581 if (npkt > 0) { 2582 prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(npkt); 2583 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2584 } 2585 DPRINTPRXS(2, q); 2586 return; 2587 } 2588 2589 STATIC int 2590 mvxpe_rx_queue_add(struct mvxpe_softc *sc, int q) 2591 { 2592 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2593 struct mvxpe_rx_desc *r; 2594 struct mvxpbm_chunk *chunk = NULL; 2595 2596 KASSERT_RX_MTX(sc, q); 2597 2598 /* Allocate the packet buffer */ 2599 chunk = mvxpbm_alloc(sc->sc_bm); 2600 if (chunk == NULL) { 2601 DPRINTSC(sc, 1, "BM chunk allocation failed.\n"); 2602 return ENOBUFS; 2603 } 2604 2605 /* Add the packet to descritor */ 2606 KASSERT(MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) == NULL); 2607 MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) = chunk; 2608 mvxpbm_dmamap_sync(chunk, BM_SYNC_ALL, BUS_DMASYNC_PREREAD); 2609 2610 r = MVXPE_RX_DESC(sc, q, rx->rx_cpu); 2611 r->bufptr = chunk->buf_pa; 2612 DPRINTSC(sc, 9, "chunk added to index %d\n", rx->rx_cpu); 2613 rx->rx_cpu = rx_counter_adv(rx->rx_cpu, 1); 2614 return 0; 2615 } 2616 2617 STATIC void 2618 mvxpe_rx_set_csumflag(struct ifnet *ifp, 2619 struct mvxpe_rx_desc *r, struct mbuf *m0) 2620 { 2621 uint32_t csum_flags = 0; 2622 2623 if ((r->status & (MVXPE_RX_IP_HEADER_OK|MVXPE_RX_L3_IP)) == 0) 2624 return; /* not a IP packet */ 2625 2626 /* L3 */ 2627 if (r->status & MVXPE_RX_L3_IP) { 2628 csum_flags |= M_CSUM_IPv4 & ifp->if_csum_flags_rx; 2629 if ((r->status & MVXPE_RX_IP_HEADER_OK) == 0 && 2630 (csum_flags & M_CSUM_IPv4) != 0) { 2631 csum_flags |= M_CSUM_IPv4_BAD; 2632 goto finish; 2633 } 2634 else if (r->status & MVXPE_RX_IPV4_FRAGMENT) { 2635 /* 2636 * r->l4chk has partial checksum of each framgment. 2637 * but there is no way to use it in NetBSD. 2638 */ 2639 return; 2640 } 2641 } 2642 2643 /* L4 */ 2644 switch (r->status & MVXPE_RX_L4_MASK) { 2645 case MVXPE_RX_L4_TCP: 2646 if (r->status & MVXPE_RX_L3_IP) 2647 csum_flags |= M_CSUM_TCPv4 & ifp->if_csum_flags_rx; 2648 else 2649 csum_flags |= M_CSUM_TCPv6 & ifp->if_csum_flags_rx; 2650 break; 2651 case MVXPE_RX_L4_UDP: 2652 if (r->status & MVXPE_RX_L3_IP) 2653 csum_flags |= M_CSUM_UDPv4 & ifp->if_csum_flags_rx; 2654 else 2655 csum_flags |= M_CSUM_UDPv6 & ifp->if_csum_flags_rx; 2656 break; 2657 case MVXPE_RX_L4_OTH: 2658 default: 2659 break; 2660 } 2661 if ((r->status & MVXPE_RX_L4_CHECKSUM_OK) == 0 && (csum_flags & 2662 (M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2663 csum_flags |= M_CSUM_TCP_UDP_BAD; 2664 finish: 2665 m0->m_pkthdr.csum_flags = csum_flags; 2666 } 2667 2668 /* 2669 * MAC address filter 2670 */ 2671 STATIC uint8_t 2672 mvxpe_crc8(const uint8_t *data, size_t size) 2673 { 2674 int bit; 2675 uint8_t byte; 2676 uint8_t crc = 0; 2677 const uint8_t poly = 0x07; 2678 2679 while(size--) 2680 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2681 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2682 2683 return crc; 2684 } 2685 2686 CTASSERT(MVXPE_NDFSMT == MVXPE_NDFOMT); 2687 2688 STATIC void 2689 mvxpe_filter_setup(struct mvxpe_softc *sc) 2690 { 2691 struct ethercom *ec = &sc->sc_ethercom; 2692 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2693 struct ether_multi *enm; 2694 struct ether_multistep step; 2695 uint32_t dfut[MVXPE_NDFUT], dfsmt[MVXPE_NDFSMT], dfomt[MVXPE_NDFOMT]; 2696 uint32_t pxc; 2697 int i; 2698 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2699 2700 KASSERT_SC_MTX(sc); 2701 2702 memset(dfut, 0, sizeof(dfut)); 2703 memset(dfsmt, 0, sizeof(dfsmt)); 2704 memset(dfomt, 0, sizeof(dfomt)); 2705 2706 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2707 goto allmulti; 2708 } 2709 2710 ETHER_FIRST_MULTI(step, ec, enm); 2711 while (enm != NULL) { 2712 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2713 /* ranges are complex and somewhat rare */ 2714 goto allmulti; 2715 } 2716 /* chip handles some IPv4 multicast specially */ 2717 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2718 i = enm->enm_addrlo[5]; 2719 dfsmt[i>>2] |= 2720 MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2721 } else { 2722 i = mvxpe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2723 dfomt[i>>2] |= 2724 MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2725 } 2726 2727 ETHER_NEXT_MULTI(step, enm); 2728 } 2729 goto set; 2730 2731 allmulti: 2732 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2733 for (i = 0; i < MVXPE_NDFSMT; i++) { 2734 dfsmt[i] = dfomt[i] = 2735 MVXPE_DF(0, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2736 MVXPE_DF(1, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2737 MVXPE_DF(2, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2738 MVXPE_DF(3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2739 } 2740 } 2741 2742 set: 2743 pxc = MVXPE_READ(sc, MVXPE_PXC); 2744 pxc &= ~MVXPE_PXC_UPM; 2745 pxc |= MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP; 2746 if (ifp->if_flags & IFF_BROADCAST) { 2747 pxc &= ~(MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP); 2748 } 2749 if (ifp->if_flags & IFF_PROMISC) { 2750 pxc |= MVXPE_PXC_UPM; 2751 } 2752 MVXPE_WRITE(sc, MVXPE_PXC, pxc); 2753 2754 /* Set Destination Address Filter Unicast Table */ 2755 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2756 dfut[i>>2] = MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2757 MVXPE_WRITE_REGION(sc, MVXPE_DFUT(0), dfut, MVXPE_NDFUT); 2758 2759 /* Set Destination Address Filter Multicast Tables */ 2760 MVXPE_WRITE_REGION(sc, MVXPE_DFSMT(0), dfsmt, MVXPE_NDFSMT); 2761 MVXPE_WRITE_REGION(sc, MVXPE_DFOMT(0), dfomt, MVXPE_NDFOMT); 2762 } 2763 2764 /* 2765 * sysctl(9) 2766 */ 2767 SYSCTL_SETUP(sysctl_mvxpe, "sysctl mvxpe subtree setup") 2768 { 2769 int rc; 2770 const struct sysctlnode *node; 2771 2772 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2773 0, CTLTYPE_NODE, "mvxpe", 2774 SYSCTL_DESCR("mvxpe interface controls"), 2775 NULL, 0, NULL, 0, 2776 CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2777 goto err; 2778 } 2779 2780 mvxpe_root_num = node->sysctl_num; 2781 return; 2782 2783 err: 2784 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2785 } 2786 2787 STATIC int 2788 sysctl_read_mib(SYSCTLFN_ARGS) 2789 { 2790 struct mvxpe_sysctl_mib *arg; 2791 struct mvxpe_softc *sc; 2792 struct sysctlnode node; 2793 uint64_t val; 2794 int err; 2795 2796 node = *rnode; 2797 arg = (struct mvxpe_sysctl_mib *)rnode->sysctl_data; 2798 if (arg == NULL) 2799 return EINVAL; 2800 2801 sc = arg->sc; 2802 if (sc == NULL) 2803 return EINVAL; 2804 if (arg->index < 0 || arg->index > __arraycount(mvxpe_mib_list)) 2805 return EINVAL; 2806 2807 mvxpe_sc_lock(sc); 2808 val = arg->counter; 2809 mvxpe_sc_unlock(sc); 2810 2811 node.sysctl_data = &val; 2812 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2813 if (err) 2814 return err; 2815 if (newp) 2816 return EINVAL; 2817 2818 return 0; 2819 } 2820 2821 2822 STATIC int 2823 sysctl_clear_mib(SYSCTLFN_ARGS) 2824 { 2825 struct mvxpe_softc *sc; 2826 struct sysctlnode node; 2827 int val; 2828 int err; 2829 2830 node = *rnode; 2831 sc = (struct mvxpe_softc *)rnode->sysctl_data; 2832 if (sc == NULL) 2833 return EINVAL; 2834 2835 val = 0; 2836 node.sysctl_data = &val; 2837 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2838 if (err || newp == NULL) 2839 return err; 2840 if (val < 0 || val > 1) 2841 return EINVAL; 2842 if (val == 1) { 2843 mvxpe_sc_lock(sc); 2844 mvxpe_clear_mib(sc); 2845 mvxpe_sc_unlock(sc); 2846 } 2847 2848 return 0; 2849 } 2850 2851 STATIC int 2852 sysctl_set_queue_length(SYSCTLFN_ARGS) 2853 { 2854 struct mvxpe_sysctl_queue *arg; 2855 struct mvxpe_rx_ring *rx = NULL; 2856 struct mvxpe_tx_ring *tx = NULL; 2857 struct mvxpe_softc *sc; 2858 struct sysctlnode node; 2859 uint32_t reg; 2860 int val; 2861 int err; 2862 2863 node = *rnode; 2864 2865 arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2866 if (arg == NULL) 2867 return EINVAL; 2868 if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2869 return EINVAL; 2870 if (arg->rxtx != MVXPE_SYSCTL_RX && arg->rxtx != MVXPE_SYSCTL_TX) 2871 return EINVAL; 2872 2873 sc = arg->sc; 2874 if (sc == NULL) 2875 return EINVAL; 2876 2877 /* read queue length */ 2878 mvxpe_sc_lock(sc); 2879 switch (arg->rxtx) { 2880 case MVXPE_SYSCTL_RX: 2881 mvxpe_rx_lockq(sc, arg->queue); 2882 rx = MVXPE_RX_RING(sc, arg->queue); 2883 val = rx->rx_queue_len; 2884 mvxpe_rx_unlockq(sc, arg->queue); 2885 break; 2886 case MVXPE_SYSCTL_TX: 2887 mvxpe_tx_lockq(sc, arg->queue); 2888 tx = MVXPE_TX_RING(sc, arg->queue); 2889 val = tx->tx_queue_len; 2890 mvxpe_tx_unlockq(sc, arg->queue); 2891 break; 2892 } 2893 2894 node.sysctl_data = &val; 2895 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2896 if (err || newp == NULL) { 2897 mvxpe_sc_unlock(sc); 2898 return err; 2899 } 2900 2901 /* update queue length */ 2902 if (val < 8 || val > MVXPE_RX_RING_CNT) { 2903 mvxpe_sc_unlock(sc); 2904 return EINVAL; 2905 } 2906 switch (arg->rxtx) { 2907 case MVXPE_SYSCTL_RX: 2908 mvxpe_rx_lockq(sc, arg->queue); 2909 rx->rx_queue_len = val; 2910 rx->rx_queue_th_received = 2911 rx->rx_queue_len / MVXPE_RXTH_RATIO; 2912 rx->rx_queue_th_free = 2913 rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 2914 2915 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 2916 reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 2917 MVXPE_WRITE(sc, MVXPE_PRXDQTH(arg->queue), reg); 2918 2919 mvxpe_rx_unlockq(sc, arg->queue); 2920 break; 2921 case MVXPE_SYSCTL_TX: 2922 mvxpe_tx_lockq(sc, arg->queue); 2923 tx->tx_queue_len = val; 2924 tx->tx_queue_th_free = 2925 tx->tx_queue_len / MVXPE_TXTH_RATIO; 2926 2927 reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 2928 reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 2929 MVXPE_WRITE(sc, MVXPE_PTXDQS(arg->queue), reg); 2930 2931 mvxpe_tx_unlockq(sc, arg->queue); 2932 break; 2933 } 2934 mvxpe_sc_unlock(sc); 2935 2936 return 0; 2937 } 2938 2939 STATIC int 2940 sysctl_set_queue_rxthtime(SYSCTLFN_ARGS) 2941 { 2942 struct mvxpe_sysctl_queue *arg; 2943 struct mvxpe_rx_ring *rx = NULL; 2944 struct mvxpe_softc *sc; 2945 struct sysctlnode node; 2946 extern uint32_t mvTclk; 2947 uint32_t reg, time_mvtclk; 2948 int time_us; 2949 int err; 2950 2951 node = *rnode; 2952 2953 arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2954 if (arg == NULL) 2955 return EINVAL; 2956 if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2957 return EINVAL; 2958 if (arg->rxtx != MVXPE_SYSCTL_RX) 2959 return EINVAL; 2960 2961 sc = arg->sc; 2962 if (sc == NULL) 2963 return EINVAL; 2964 2965 /* read queue length */ 2966 mvxpe_sc_lock(sc); 2967 mvxpe_rx_lockq(sc, arg->queue); 2968 rx = MVXPE_RX_RING(sc, arg->queue); 2969 time_mvtclk = rx->rx_queue_th_time; 2970 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvTclk; 2971 node.sysctl_data = &time_us; 2972 DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", 2973 arg->queue, MVXPE_READ(sc, MVXPE_PRXITTH(arg->queue))); 2974 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2975 if (err || newp == NULL) { 2976 mvxpe_rx_unlockq(sc, arg->queue); 2977 mvxpe_sc_unlock(sc); 2978 return err; 2979 } 2980 2981 /* update queue length (0[sec] - 1[sec]) */ 2982 if (time_us < 0 || time_us > (1000 * 1000)) { 2983 mvxpe_rx_unlockq(sc, arg->queue); 2984 mvxpe_sc_unlock(sc); 2985 return EINVAL; 2986 } 2987 time_mvtclk = 2988 (uint64_t)mvTclk * (uint64_t)time_us / (1000ULL * 1000ULL); 2989 rx->rx_queue_th_time = time_mvtclk; 2990 reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 2991 MVXPE_WRITE(sc, MVXPE_PRXITTH(arg->queue), reg); 2992 DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", arg->queue, reg); 2993 mvxpe_rx_unlockq(sc, arg->queue); 2994 mvxpe_sc_unlock(sc); 2995 2996 return 0; 2997 } 2998 2999 3000 STATIC void 3001 sysctl_mvxpe_init(struct mvxpe_softc *sc) 3002 { 3003 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3004 const struct sysctlnode *node; 3005 int mvxpe_nodenum; 3006 int mvxpe_mibnum; 3007 int mvxpe_rxqueuenum; 3008 int mvxpe_txqueuenum; 3009 int q, i; 3010 3011 /* hw.mvxpe.mvxpe[unit] */ 3012 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3013 0, CTLTYPE_NODE, ifp->if_xname, 3014 SYSCTL_DESCR("mvxpe per-controller controls"), 3015 NULL, 0, NULL, 0, 3016 CTL_HW, mvxpe_root_num, CTL_CREATE, 3017 CTL_EOL) != 0) { 3018 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3019 return; 3020 } 3021 mvxpe_nodenum = node->sysctl_num; 3022 3023 /* hw.mvxpe.mvxpe[unit].mib */ 3024 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3025 0, CTLTYPE_NODE, "mib", 3026 SYSCTL_DESCR("mvxpe per-controller MIB counters"), 3027 NULL, 0, NULL, 0, 3028 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3029 CTL_EOL) != 0) { 3030 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3031 return; 3032 } 3033 mvxpe_mibnum = node->sysctl_num; 3034 3035 /* hw.mvxpe.mvxpe[unit].rx */ 3036 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3037 0, CTLTYPE_NODE, "rx", 3038 SYSCTL_DESCR("Rx Queues"), 3039 NULL, 0, NULL, 0, 3040 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3041 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3042 return; 3043 } 3044 mvxpe_rxqueuenum = node->sysctl_num; 3045 3046 /* hw.mvxpe.mvxpe[unit].tx */ 3047 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3048 0, CTLTYPE_NODE, "tx", 3049 SYSCTL_DESCR("Tx Queues"), 3050 NULL, 0, NULL, 0, 3051 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3052 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3053 return; 3054 } 3055 mvxpe_txqueuenum = node->sysctl_num; 3056 3057 #ifdef MVXPE_DEBUG 3058 /* hw.mvxpe.debug */ 3059 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3060 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 3061 SYSCTL_DESCR("mvxpe device driver debug control"), 3062 NULL, 0, &mvxpe_debug, 0, 3063 CTL_HW, mvxpe_root_num, CTL_CREATE, CTL_EOL) != 0) { 3064 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3065 return; 3066 } 3067 #endif 3068 /* 3069 * MIB access 3070 */ 3071 /* hw.mvxpe.mvxpe[unit].mib.<mibs> */ 3072 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3073 const char *name = mvxpe_mib_list[i].sysctl_name; 3074 const char *desc = mvxpe_mib_list[i].desc; 3075 struct mvxpe_sysctl_mib *mib_arg = &sc->sc_sysctl_mib[i]; 3076 3077 mib_arg->sc = sc; 3078 mib_arg->index = i; 3079 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3080 CTLFLAG_READONLY, CTLTYPE_QUAD, name, desc, 3081 sysctl_read_mib, 0, (void *)mib_arg, 0, 3082 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_mibnum, 3083 CTL_CREATE, CTL_EOL) != 0) { 3084 aprint_normal_dev(sc->sc_dev, 3085 "couldn't create sysctl node\n"); 3086 break; 3087 } 3088 } 3089 3090 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 3091 struct mvxpe_sysctl_queue *rxarg = &sc->sc_sysctl_rx_queue[q]; 3092 struct mvxpe_sysctl_queue *txarg = &sc->sc_sysctl_tx_queue[q]; 3093 #define MVXPE_SYSCTL_NAME(num) "queue" # num 3094 static const char *sysctl_queue_names[] = { 3095 MVXPE_SYSCTL_NAME(0), MVXPE_SYSCTL_NAME(1), 3096 MVXPE_SYSCTL_NAME(2), MVXPE_SYSCTL_NAME(3), 3097 MVXPE_SYSCTL_NAME(4), MVXPE_SYSCTL_NAME(5), 3098 MVXPE_SYSCTL_NAME(6), MVXPE_SYSCTL_NAME(7), 3099 }; 3100 #undef MVXPE_SYSCTL_NAME 3101 #ifdef SYSCTL_INCLUDE_DESCR 3102 #define MVXPE_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3103 static const char *sysctl_queue_descrs[] = { 3104 MVXPE_SYSCTL_DESCR(0), MVXPE_SYSCTL_DESCR(1), 3105 MVXPE_SYSCTL_DESCR(2), MVXPE_SYSCTL_DESCR(3), 3106 MVXPE_SYSCTL_DESCR(4), MVXPE_SYSCTL_DESCR(5), 3107 MVXPE_SYSCTL_DESCR(6), MVXPE_SYSCTL_DESCR(7), 3108 }; 3109 #undef MVXPE_SYSCTL_DESCR 3110 #endif /* SYSCTL_INCLUDE_DESCR */ 3111 int mvxpe_curnum; 3112 3113 rxarg->sc = txarg->sc = sc; 3114 rxarg->queue = txarg->queue = q; 3115 rxarg->rxtx = MVXPE_SYSCTL_RX; 3116 txarg->rxtx = MVXPE_SYSCTL_TX; 3117 3118 /* hw.mvxpe.mvxpe[unit].rx.[queue] */ 3119 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3120 0, CTLTYPE_NODE, 3121 sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descrs[q]), 3122 NULL, 0, NULL, 0, 3123 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3124 CTL_CREATE, CTL_EOL) != 0) { 3125 aprint_normal_dev(sc->sc_dev, 3126 "couldn't create sysctl node\n"); 3127 break; 3128 } 3129 mvxpe_curnum = node->sysctl_num; 3130 3131 /* hw.mvxpe.mvxpe[unit].rx.[queue].length */ 3132 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3133 CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3134 SYSCTL_DESCR("maximum length of the queue"), 3135 sysctl_set_queue_length, 0, (void *)rxarg, 0, 3136 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3137 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3138 aprint_normal_dev(sc->sc_dev, 3139 "couldn't create sysctl node\n"); 3140 break; 3141 } 3142 3143 /* hw.mvxpe.mvxpe[unit].rx.[queue].threshold_timer_us */ 3144 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3145 CTLFLAG_READWRITE, CTLTYPE_INT, "threshold_timer_us", 3146 SYSCTL_DESCR("interrupt coalescing threshold timer [us]"), 3147 sysctl_set_queue_rxthtime, 0, (void *)rxarg, 0, 3148 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3149 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3150 aprint_normal_dev(sc->sc_dev, 3151 "couldn't create sysctl node\n"); 3152 break; 3153 } 3154 3155 /* hw.mvxpe.mvxpe[unit].tx.[queue] */ 3156 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3157 0, CTLTYPE_NODE, 3158 sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descs[q]), 3159 NULL, 0, NULL, 0, 3160 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3161 CTL_CREATE, CTL_EOL) != 0) { 3162 aprint_normal_dev(sc->sc_dev, 3163 "couldn't create sysctl node\n"); 3164 break; 3165 } 3166 mvxpe_curnum = node->sysctl_num; 3167 3168 /* hw.mvxpe.mvxpe[unit].tx.length[queue] */ 3169 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3170 CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3171 SYSCTL_DESCR("maximum length of the queue"), 3172 sysctl_set_queue_length, 0, (void *)txarg, 0, 3173 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3174 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3175 aprint_normal_dev(sc->sc_dev, 3176 "couldn't create sysctl node\n"); 3177 break; 3178 } 3179 } 3180 3181 /* hw.mvxpe.mvxpe[unit].clear_mib */ 3182 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3183 CTLFLAG_READWRITE, CTLTYPE_INT, "clear_mib", 3184 SYSCTL_DESCR("mvxpe device driver debug control"), 3185 sysctl_clear_mib, 0, (void *)sc, 0, 3186 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3187 CTL_EOL) != 0) { 3188 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3189 return; 3190 } 3191 3192 } 3193 3194 /* 3195 * MIB 3196 */ 3197 STATIC void 3198 mvxpe_clear_mib(struct mvxpe_softc *sc) 3199 { 3200 int i; 3201 3202 KASSERT_SC_MTX(sc); 3203 3204 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3205 if (mvxpe_mib_list[i].reg64) 3206 MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum + 4)); 3207 MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3208 sc->sc_sysctl_mib[i].counter = 0; 3209 } 3210 } 3211 3212 STATIC void 3213 mvxpe_update_mib(struct mvxpe_softc *sc) 3214 { 3215 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3216 int i; 3217 3218 KASSERT_SC_MTX(sc); 3219 3220 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3221 uint32_t val_hi; 3222 uint32_t val_lo; 3223 uint64_t val; 3224 3225 if (mvxpe_mib_list[i].reg64) { 3226 /* XXX: implement bus_space_read_8() */ 3227 val_lo = MVXPE_READ_MIB(sc, 3228 (mvxpe_mib_list[i].regnum + 4)); 3229 val_hi = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3230 } 3231 else { 3232 val_lo = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3233 val_hi = 0; 3234 } 3235 3236 if ((val_lo | val_hi) == 0) 3237 continue; 3238 3239 val = ((uint64_t)val_hi << 32) | (uint64_t)val_lo; 3240 sc->sc_sysctl_mib[i].counter += val; 3241 3242 switch (mvxpe_mib_list[i].ext) { 3243 case MVXPE_MIBEXT_IF_OERRORS: 3244 ifp->if_oerrors += val; 3245 break; 3246 case MVXPE_MIBEXT_IF_IERRORS: 3247 ifp->if_ierrors += val; 3248 break; 3249 case MVXPE_MIBEXT_IF_COLLISIONS: 3250 ifp->if_collisions += val; 3251 break; 3252 default: 3253 break; 3254 } 3255 3256 } 3257 } 3258 3259 /* 3260 * for Debug 3261 */ 3262 STATIC void 3263 mvxpe_dump_txdesc(struct mvxpe_tx_desc *desc, int idx) 3264 { 3265 #define DESC_PRINT(X) \ 3266 if (X) \ 3267 printf("txdesc[%d]." #X "=%#x\n", idx, X); 3268 3269 DESC_PRINT(desc->command); 3270 DESC_PRINT(desc->l4ichk); 3271 DESC_PRINT(desc->bytecnt); 3272 DESC_PRINT(desc->bufptr); 3273 DESC_PRINT(desc->flags); 3274 #undef DESC_PRINT 3275 } 3276 3277 STATIC void 3278 mvxpe_dump_rxdesc(struct mvxpe_rx_desc *desc, int idx) 3279 { 3280 #define DESC_PRINT(X) \ 3281 if (X) \ 3282 printf("rxdesc[%d]." #X "=%#x\n", idx, X); 3283 3284 DESC_PRINT(desc->status); 3285 DESC_PRINT(desc->bytecnt); 3286 DESC_PRINT(desc->bufptr); 3287 DESC_PRINT(desc->l4chk); 3288 #undef DESC_PRINT 3289 } 3290
Indexes created Tue Sep 30 20:09:53 GMT 2025