if_mvxpe.c revision 1.9
1 /* $NetBSD: if_mvxpe.c,v 1.9 2016/02/13 06:12:46 hikaru Exp $ */ 2 /* 3 * Copyright (c) 2015 Internet Initiative Japan Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvxpe.c,v 1.9 2016/02/13 06:12:46 hikaru Exp $"); 29 30 #include "opt_multiprocessor.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/callout.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 #include <sys/errno.h> 38 #include <sys/evcnt.h> 39 #include <sys/kernel.h> 40 #include <sys/kmem.h> 41 #include <sys/mutex.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/syslog.h> 45 #include <sys/rndsource.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 #include <net/bpf.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/ip.h> 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include <dev/marvell/marvellreg.h> 60 #include <dev/marvell/marvellvar.h> 61 #include <dev/marvell/mvxpbmvar.h> 62 #include <dev/marvell/if_mvxpereg.h> 63 #include <dev/marvell/if_mvxpevar.h> 64 65 #include "locators.h" 66 67 #if BYTE_ORDER == BIG_ENDIAN 68 #error "BIG ENDIAN not supported" 69 #endif 70 71 #ifdef MVXPE_DEBUG 72 #define STATIC /* nothing */ 73 #else 74 #define STATIC static 75 #endif 76 77 /* autoconf(9) */ 78 STATIC int mvxpe_match(device_t, struct cfdata *, void *); 79 STATIC void mvxpe_attach(device_t, device_t, void *); 80 STATIC int mvxpe_evcnt_attach(struct mvxpe_softc *); 81 CFATTACH_DECL_NEW(mvxpe_mbus, sizeof(struct mvxpe_softc), 82 mvxpe_match, mvxpe_attach, NULL, NULL); 83 STATIC void mvxpe_sc_lock(struct mvxpe_softc *); 84 STATIC void mvxpe_sc_unlock(struct mvxpe_softc *); 85 86 /* MII */ 87 STATIC int mvxpe_miibus_readreg(device_t, int, int); 88 STATIC void mvxpe_miibus_writereg(device_t, int, int, int); 89 STATIC void mvxpe_miibus_statchg(struct ifnet *); 90 91 /* Addres Decoding Window */ 92 STATIC void mvxpe_wininit(struct mvxpe_softc *, enum marvell_tags *); 93 94 /* Device Register Initialization */ 95 STATIC int mvxpe_initreg(struct ifnet *); 96 97 /* Descriptor Ring Control for each of queues */ 98 STATIC void *mvxpe_dma_memalloc(struct mvxpe_softc *, bus_dmamap_t *, size_t); 99 STATIC int mvxpe_ring_alloc_queue(struct mvxpe_softc *, int); 100 STATIC void mvxpe_ring_dealloc_queue(struct mvxpe_softc *, int); 101 STATIC void mvxpe_ring_init_queue(struct mvxpe_softc *, int); 102 STATIC void mvxpe_ring_flush_queue(struct mvxpe_softc *, int); 103 STATIC void mvxpe_ring_sync_rx(struct mvxpe_softc *, int, int, int, int); 104 STATIC void mvxpe_ring_sync_tx(struct mvxpe_softc *, int, int, int, int); 105 106 /* Rx/Tx Queue Control */ 107 STATIC int mvxpe_rx_queue_init(struct ifnet *, int); 108 STATIC int mvxpe_tx_queue_init(struct ifnet *, int); 109 STATIC int mvxpe_rx_queue_enable(struct ifnet *, int); 110 STATIC int mvxpe_tx_queue_enable(struct ifnet *, int); 111 STATIC void mvxpe_rx_lockq(struct mvxpe_softc *, int); 112 STATIC void mvxpe_rx_unlockq(struct mvxpe_softc *, int); 113 STATIC void mvxpe_tx_lockq(struct mvxpe_softc *, int); 114 STATIC void mvxpe_tx_unlockq(struct mvxpe_softc *, int); 115 116 /* Interrupt Handlers */ 117 STATIC void mvxpe_disable_intr(struct mvxpe_softc *); 118 STATIC void mvxpe_enable_intr(struct mvxpe_softc *); 119 STATIC int mvxpe_rxtxth_intr(void *); 120 STATIC int mvxpe_misc_intr(void *); 121 STATIC int mvxpe_rxtx_intr(void *); 122 STATIC void mvxpe_tick(void *); 123 124 /* struct ifnet and mii callbacks*/ 125 STATIC void mvxpe_start(struct ifnet *); 126 STATIC int mvxpe_ioctl(struct ifnet *, u_long, void *); 127 STATIC int mvxpe_init(struct ifnet *); 128 STATIC void mvxpe_stop(struct ifnet *, int); 129 STATIC void mvxpe_watchdog(struct ifnet *); 130 STATIC int mvxpe_ifflags_cb(struct ethercom *); 131 STATIC int mvxpe_mediachange(struct ifnet *); 132 STATIC void mvxpe_mediastatus(struct ifnet *, struct ifmediareq *); 133 134 /* Link State Notify */ 135 STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc); 136 STATIC void mvxpe_linkup(struct mvxpe_softc *); 137 STATIC void mvxpe_linkdown(struct mvxpe_softc *); 138 STATIC void mvxpe_linkreset(struct mvxpe_softc *); 139 140 /* Tx Subroutines */ 141 STATIC int mvxpe_tx_queue_select(struct mvxpe_softc *, struct mbuf *); 142 STATIC int mvxpe_tx_queue(struct mvxpe_softc *, struct mbuf *, int); 143 STATIC void mvxpe_tx_set_csumflag(struct ifnet *, 144 struct mvxpe_tx_desc *, struct mbuf *); 145 STATIC void mvxpe_tx_complete(struct mvxpe_softc *, uint32_t); 146 STATIC void mvxpe_tx_queue_complete(struct mvxpe_softc *, int); 147 148 /* Rx Subroutines */ 149 STATIC void mvxpe_rx(struct mvxpe_softc *, uint32_t); 150 STATIC void mvxpe_rx_queue(struct mvxpe_softc *, int, int); 151 STATIC int mvxpe_rx_queue_select(struct mvxpe_softc *, uint32_t, int *); 152 STATIC void mvxpe_rx_refill(struct mvxpe_softc *, uint32_t); 153 STATIC void mvxpe_rx_queue_refill(struct mvxpe_softc *, int); 154 STATIC int mvxpe_rx_queue_add(struct mvxpe_softc *, int); 155 STATIC void mvxpe_rx_set_csumflag(struct ifnet *, 156 struct mvxpe_rx_desc *, struct mbuf *); 157 158 /* MAC address filter */ 159 STATIC uint8_t mvxpe_crc8(const uint8_t *, size_t); 160 STATIC void mvxpe_filter_setup(struct mvxpe_softc *); 161 162 /* sysctl(9) */ 163 STATIC int sysctl_read_mib(SYSCTLFN_PROTO); 164 STATIC int sysctl_clear_mib(SYSCTLFN_PROTO); 165 STATIC int sysctl_set_queue_length(SYSCTLFN_PROTO); 166 STATIC int sysctl_set_queue_rxthtime(SYSCTLFN_PROTO); 167 STATIC void sysctl_mvxpe_init(struct mvxpe_softc *); 168 169 /* MIB */ 170 STATIC void mvxpe_clear_mib(struct mvxpe_softc *); 171 STATIC void mvxpe_update_mib(struct mvxpe_softc *); 172 173 /* for Debug */ 174 STATIC void mvxpe_dump_txdesc(struct mvxpe_tx_desc *, int) __attribute__((__unused__)); 175 STATIC void mvxpe_dump_rxdesc(struct mvxpe_rx_desc *, int) __attribute__((__unused__)); 176 177 STATIC int mvxpe_root_num; 178 STATIC kmutex_t mii_mutex; 179 STATIC int mii_init = 0; 180 #ifdef MVXPE_DEBUG 181 STATIC int mvxpe_debug = MVXPE_DEBUG; 182 #endif 183 184 /* 185 * List of MIB register and names 186 */ 187 STATIC struct mvxpe_mib_def { 188 uint32_t regnum; 189 int reg64; 190 const char *sysctl_name; 191 const char *desc; 192 } mvxpe_mib_list[] = { 193 {MVXPE_MIB_RX_GOOD_OCT, 1, "rx_good_oct", 194 "Good Octets Rx"}, 195 {MVXPE_MIB_RX_BAD_OCT, 0, "rx_bad_oct", 196 "Bad Octets Rx"}, 197 {MVXPE_MIB_RX_MAC_TRNS_ERR, 0, "rx_mac_err", 198 "MAC Transmit Error"}, 199 {MVXPE_MIB_RX_GOOD_FRAME, 0, "rx_good_frame", 200 "Good Frames Rx"}, 201 {MVXPE_MIB_RX_BAD_FRAME, 0, "rx_bad_frame", 202 "Bad Frames Rx"}, 203 {MVXPE_MIB_RX_BCAST_FRAME, 0, "rx_bcast_frame", 204 "Broadcast Frames Rx"}, 205 {MVXPE_MIB_RX_MCAST_FRAME, 0, "rx_mcast_frame", 206 "Multicast Frames Rx"}, 207 {MVXPE_MIB_RX_FRAME64_OCT, 0, "rx_frame_1_64", 208 "Frame Size 1 - 64"}, 209 {MVXPE_MIB_RX_FRAME127_OCT, 0, "rx_frame_65_127", 210 "Frame Size 65 - 127"}, 211 {MVXPE_MIB_RX_FRAME255_OCT, 0, "rx_frame_128_255", 212 "Frame Size 128 - 255"}, 213 {MVXPE_MIB_RX_FRAME511_OCT, 0, "rx_frame_256_511", 214 "Frame Size 256 - 511"}, 215 {MVXPE_MIB_RX_FRAME1023_OCT, 0, "rx_frame_512_1023", 216 "Frame Size 512 - 1023"}, 217 {MVXPE_MIB_RX_FRAMEMAX_OCT, 0, "rx_fame_1024_max", 218 "Frame Size 1024 - Max"}, 219 {MVXPE_MIB_TX_GOOD_OCT, 1, "tx_good_oct", 220 "Good Octets Tx"}, 221 {MVXPE_MIB_TX_GOOD_FRAME, 0, "tx_good_frame", 222 "Good Frames Tx"}, 223 {MVXPE_MIB_TX_EXCES_COL, 0, "tx_exces_collision", 224 "Excessive Collision"}, 225 {MVXPE_MIB_TX_MCAST_FRAME, 0, "tx_mcast_frame", 226 "Multicast Frames Tx"}, 227 {MVXPE_MIB_TX_BCAST_FRAME, 0, "tx_bcast_frame", 228 "Broadcast Frames Tx"}, 229 {MVXPE_MIB_TX_MAC_CTL_ERR, 0, "tx_mac_err", 230 "Unknown MAC Control"}, 231 {MVXPE_MIB_FC_SENT, 0, "fc_tx", 232 "Flow Control Tx"}, 233 {MVXPE_MIB_FC_GOOD, 0, "fc_rx_good", 234 "Good Flow Control Rx"}, 235 {MVXPE_MIB_FC_BAD, 0, "fc_rx_bad", 236 "Bad Flow Control Rx"}, 237 {MVXPE_MIB_PKT_UNDERSIZE, 0, "pkt_undersize", 238 "Undersized Packets Rx"}, 239 {MVXPE_MIB_PKT_FRAGMENT, 0, "pkt_fragment", 240 "Fragmented Packets Rx"}, 241 {MVXPE_MIB_PKT_OVERSIZE, 0, "pkt_oversize", 242 "Oversized Packets Rx"}, 243 {MVXPE_MIB_PKT_JABBER, 0, "pkt_jabber", 244 "Jabber Packets Rx"}, 245 {MVXPE_MIB_MAC_RX_ERR, 0, "mac_rx_err", 246 "MAC Rx Errors"}, 247 {MVXPE_MIB_MAC_CRC_ERR, 0, "mac_crc_err", 248 "MAC CRC Errors"}, 249 {MVXPE_MIB_MAC_COL, 0, "mac_collision", 250 "MAC Collision"}, 251 {MVXPE_MIB_MAC_LATE_COL, 0, "mac_late_collision", 252 "MAC Late Collision"}, 253 }; 254 255 /* 256 * autoconf(9) 257 */ 258 /* ARGSUSED */ 259 STATIC int 260 mvxpe_match(device_t parent, cfdata_t match, void *aux) 261 { 262 struct marvell_attach_args *mva = aux; 263 bus_size_t pv_off; 264 uint32_t pv; 265 266 if (strcmp(mva->mva_name, match->cf_name) != 0) 267 return 0; 268 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 269 return 0; 270 271 /* check port version */ 272 pv_off = mva->mva_offset + MVXPE_PV; 273 pv = bus_space_read_4(mva->mva_iot, mva->mva_ioh, pv_off); 274 if (MVXPE_PV_GET_VERSION(pv) < 0x10) 275 return 0; /* old version is not supported */ 276 277 return 1; 278 } 279 280 /* ARGSUSED */ 281 STATIC void 282 mvxpe_attach(device_t parent, device_t self, void *aux) 283 { 284 struct mvxpe_softc *sc = device_private(self); 285 struct mii_softc *mii; 286 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 287 struct marvell_attach_args *mva = aux; 288 prop_dictionary_t dict; 289 prop_data_t enaddrp = NULL; 290 uint32_t phyaddr, maddrh, maddrl; 291 uint8_t enaddr[ETHER_ADDR_LEN]; 292 int q; 293 294 aprint_naive("\n"); 295 aprint_normal(": Marvell ARMADA GbE Controller\n"); 296 memset(sc, 0, sizeof(*sc)); 297 sc->sc_dev = self; 298 sc->sc_port = mva->mva_unit; 299 sc->sc_iot = mva->mva_iot; 300 sc->sc_dmat = mva->mva_dmat; 301 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 302 callout_init(&sc->sc_tick_ch, 0); 303 callout_setfunc(&sc->sc_tick_ch, mvxpe_tick, sc); 304 305 /* 306 * BUS space 307 */ 308 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 309 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 310 aprint_error_dev(self, "Cannot map registers\n"); 311 goto fail; 312 } 313 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 314 mva->mva_offset + MVXPE_PORTMIB_BASE, MVXPE_PORTMIB_SIZE, 315 &sc->sc_mibh)) { 316 aprint_error_dev(self, 317 "Cannot map destination address filter registers\n"); 318 goto fail; 319 } 320 sc->sc_version = MVXPE_READ(sc, MVXPE_PV); 321 aprint_normal_dev(self, "Port Version %#x\n", sc->sc_version); 322 323 /* 324 * Buffer Manager(BM) subsystem. 325 */ 326 sc->sc_bm = mvxpbm_device(mva); 327 if (sc->sc_bm == NULL) { 328 aprint_error_dev(self, "no Buffer Manager.\n"); 329 goto fail; 330 } 331 aprint_normal_dev(self, 332 "Using Buffer Manager: %s\n", mvxpbm_xname(sc->sc_bm)); 333 aprint_normal_dev(sc->sc_dev, 334 "%zu kbytes managed buffer, %zu bytes * %u entries allocated.\n", 335 mvxpbm_buf_size(sc->sc_bm) / 1024, 336 mvxpbm_chunk_size(sc->sc_bm), mvxpbm_chunk_count(sc->sc_bm)); 337 338 /* 339 * make sure DMA engines are in reset state 340 */ 341 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 342 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 343 344 /* 345 * Address decoding window 346 */ 347 mvxpe_wininit(sc, mva->mva_tags); 348 349 /* 350 * MAC address 351 */ 352 dict = device_properties(self); 353 if (dict) 354 enaddrp = prop_dictionary_get(dict, "mac-address"); 355 if (enaddrp) { 356 memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN); 357 maddrh = enaddr[0] << 24; 358 maddrh |= enaddr[1] << 16; 359 maddrh |= enaddr[2] << 8; 360 maddrh |= enaddr[3]; 361 maddrl = enaddr[4] << 8; 362 maddrl |= enaddr[5]; 363 MVXPE_WRITE(sc, MVXPE_MACAH, maddrh); 364 MVXPE_WRITE(sc, MVXPE_MACAL, maddrl); 365 } 366 else { 367 /* 368 * even if enaddr is not found in dictionary, 369 * the port may be initialized by IPL program such as U-BOOT. 370 */ 371 maddrh = MVXPE_READ(sc, MVXPE_MACAH); 372 maddrl = MVXPE_READ(sc, MVXPE_MACAL); 373 if ((maddrh | maddrl) == 0) { 374 aprint_error_dev(self, "No Ethernet address\n"); 375 return; 376 } 377 } 378 sc->sc_enaddr[0] = maddrh >> 24; 379 sc->sc_enaddr[1] = maddrh >> 16; 380 sc->sc_enaddr[2] = maddrh >> 8; 381 sc->sc_enaddr[3] = maddrh >> 0; 382 sc->sc_enaddr[4] = maddrl >> 8; 383 sc->sc_enaddr[5] = maddrl >> 0; 384 aprint_normal_dev(self, "Ethernet address %s\n", 385 ether_sprintf(sc->sc_enaddr)); 386 387 /* 388 * Register interrupt handlers 389 * XXX: handle Ethernet unit intr. and Error intr. 390 */ 391 mvxpe_disable_intr(sc); 392 marvell_intr_establish(mva->mva_irq, IPL_NET, mvxpe_rxtxth_intr, sc); 393 394 /* 395 * MIB buffer allocation 396 */ 397 sc->sc_sysctl_mib_size = 398 __arraycount(mvxpe_mib_list) * sizeof(struct mvxpe_sysctl_mib); 399 sc->sc_sysctl_mib = kmem_alloc(sc->sc_sysctl_mib_size, KM_NOSLEEP); 400 if (sc->sc_sysctl_mib == NULL) 401 goto fail; 402 memset(sc->sc_sysctl_mib, 0, sc->sc_sysctl_mib_size); 403 404 /* 405 * Device DMA Buffer allocation 406 */ 407 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 408 if (mvxpe_ring_alloc_queue(sc, q) != 0) 409 goto fail; 410 mvxpe_ring_init_queue(sc, q); 411 } 412 413 /* 414 * We can support 802.1Q VLAN-sized frames and jumbo 415 * Ethernet frames. 416 */ 417 sc->sc_ethercom.ec_capabilities |= 418 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 419 ifp->if_softc = sc; 420 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 421 ifp->if_start = mvxpe_start; 422 ifp->if_ioctl = mvxpe_ioctl; 423 ifp->if_init = mvxpe_init; 424 ifp->if_stop = mvxpe_stop; 425 ifp->if_watchdog = mvxpe_watchdog; 426 427 /* 428 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 429 */ 430 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx; 431 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx; 432 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 433 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 434 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx; 435 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx; 436 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx; 437 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Rx; 438 ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Tx; 439 ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Rx; 440 441 /* 442 * Initialize struct ifnet 443 */ 444 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVXPE_TX_RING_CNT - 1, IFQ_MAXLEN)); 445 IFQ_SET_READY(&ifp->if_snd); 446 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname)); 447 448 /* 449 * Enable DMA engines and Initiazlie Device Regisers. 450 */ 451 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 452 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 453 MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 454 mvxpe_sc_lock(sc); /* XXX */ 455 mvxpe_filter_setup(sc); 456 mvxpe_sc_unlock(sc); 457 mvxpe_initreg(ifp); 458 459 /* 460 * Now MAC is working, setup MII. 461 */ 462 if (mii_init == 0) { 463 /* 464 * MII bus is shared by all MACs and all PHYs in SoC. 465 * serializing the bus access should be safe. 466 */ 467 mutex_init(&mii_mutex, MUTEX_DEFAULT, IPL_NET); 468 mii_init = 1; 469 } 470 sc->sc_mii.mii_ifp = ifp; 471 sc->sc_mii.mii_readreg = mvxpe_miibus_readreg; 472 sc->sc_mii.mii_writereg = mvxpe_miibus_writereg; 473 sc->sc_mii.mii_statchg = mvxpe_miibus_statchg; 474 475 sc->sc_ethercom.ec_mii = &sc->sc_mii; 476 ifmedia_init(&sc->sc_mii.mii_media, 0, 477 mvxpe_mediachange, mvxpe_mediastatus); 478 /* 479 * XXX: phy addressing highly depends on Board Design. 480 * we assume phyaddress == MAC unit number here, 481 * but some boards may not. 482 */ 483 mii_attach(self, &sc->sc_mii, 0xffffffff, 484 MII_PHY_ANY, sc->sc_dev->dv_unit, 0); 485 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 486 if (mii == NULL) { 487 aprint_error_dev(self, "no PHY found!\n"); 488 ifmedia_add(&sc->sc_mii.mii_media, 489 IFM_ETHER|IFM_MANUAL, 0, NULL); 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 491 } else { 492 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 493 phyaddr = MVXPE_PHYADDR_PHYAD(mii->mii_phy); 494 MVXPE_WRITE(sc, MVXPE_PHYADDR, phyaddr); 495 DPRINTSC(sc, 1, "PHYADDR: %#x\n", MVXPE_READ(sc, MVXPE_PHYADDR)); 496 } 497 498 /* 499 * Call MI attach routines. 500 */ 501 if_attach(ifp); 502 503 ether_ifattach(ifp, sc->sc_enaddr); 504 ether_set_ifflags_cb(&sc->sc_ethercom, mvxpe_ifflags_cb); 505 506 sysctl_mvxpe_init(sc); 507 mvxpe_evcnt_attach(sc); 508 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 509 RND_TYPE_NET, RND_FLAG_DEFAULT); 510 511 return; 512 513 fail: 514 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) 515 mvxpe_ring_dealloc_queue(sc, q); 516 if (sc->sc_sysctl_mib) 517 kmem_free(sc->sc_sysctl_mib, sc->sc_sysctl_mib_size); 518 519 return; 520 } 521 522 STATIC int 523 mvxpe_evcnt_attach(struct mvxpe_softc *sc) 524 { 525 #ifdef MVXPE_EVENT_COUNTERS 526 int q; 527 528 /* Master Interrupt Handler */ 529 evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtxth, EVCNT_TYPE_INTR, 530 NULL, device_xname(sc->sc_dev), "RxTxTH Intr."); 531 evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtx, EVCNT_TYPE_INTR, 532 NULL, device_xname(sc->sc_dev), "RxTx Intr."); 533 evcnt_attach_dynamic(&sc->sc_ev.ev_i_misc, EVCNT_TYPE_INTR, 534 NULL, device_xname(sc->sc_dev), "MISC Intr."); 535 536 /* RXTXTH Interrupt */ 537 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtxth_txerr, EVCNT_TYPE_INTR, 538 NULL, device_xname(sc->sc_dev), "RxTxTH Tx error summary"); 539 540 /* MISC Interrupt */ 541 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_phystatuschng, EVCNT_TYPE_INTR, 542 NULL, device_xname(sc->sc_dev), "MISC phy status changed"); 543 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_linkchange, EVCNT_TYPE_INTR, 544 NULL, device_xname(sc->sc_dev), "MISC link status changed"); 545 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_iae, EVCNT_TYPE_INTR, 546 NULL, device_xname(sc->sc_dev), "MISC internal address error"); 547 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxoverrun, EVCNT_TYPE_INTR, 548 NULL, device_xname(sc->sc_dev), "MISC Rx FIFO overrun"); 549 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxcrc, EVCNT_TYPE_INTR, 550 NULL, device_xname(sc->sc_dev), "MISC Rx CRC error"); 551 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxlargepacket, EVCNT_TYPE_INTR, 552 NULL, device_xname(sc->sc_dev), "MISC Rx too large frame"); 553 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txunderrun, EVCNT_TYPE_INTR, 554 NULL, device_xname(sc->sc_dev), "MISC Tx FIFO underrun"); 555 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_prbserr, EVCNT_TYPE_INTR, 556 NULL, device_xname(sc->sc_dev), "MISC SERDES loopback test err"); 557 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_srse, EVCNT_TYPE_INTR, 558 NULL, device_xname(sc->sc_dev), "MISC SERDES sync error"); 559 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txreq, EVCNT_TYPE_INTR, 560 NULL, device_xname(sc->sc_dev), "MISC Tx resource erorr"); 561 562 /* RxTx Interrupt */ 563 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rreq, EVCNT_TYPE_INTR, 564 NULL, device_xname(sc->sc_dev), "RxTx Rx resource erorr"); 565 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rpq, EVCNT_TYPE_INTR, 566 NULL, device_xname(sc->sc_dev), "RxTx Rx pakcet"); 567 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_tbrq, EVCNT_TYPE_INTR, 568 NULL, device_xname(sc->sc_dev), "RxTx Tx complete"); 569 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rxtxth, EVCNT_TYPE_INTR, 570 NULL, device_xname(sc->sc_dev), "RxTx RxTxTH summary"); 571 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_txerr, EVCNT_TYPE_INTR, 572 NULL, device_xname(sc->sc_dev), "RxTx Tx error summary"); 573 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_misc, EVCNT_TYPE_INTR, 574 NULL, device_xname(sc->sc_dev), "RxTx MISC summary"); 575 576 /* Link */ 577 evcnt_attach_dynamic(&sc->sc_ev.ev_link_up, EVCNT_TYPE_MISC, 578 NULL, device_xname(sc->sc_dev), "link up"); 579 evcnt_attach_dynamic(&sc->sc_ev.ev_link_down, EVCNT_TYPE_MISC, 580 NULL, device_xname(sc->sc_dev), "link down"); 581 582 /* Rx Descriptor */ 583 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_ce, EVCNT_TYPE_MISC, 584 NULL, device_xname(sc->sc_dev), "Rx CRC error counter"); 585 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_or, EVCNT_TYPE_MISC, 586 NULL, device_xname(sc->sc_dev), "Rx FIFO overrun counter"); 587 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_mf, EVCNT_TYPE_MISC, 588 NULL, device_xname(sc->sc_dev), "Rx too large frame counter"); 589 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_re, EVCNT_TYPE_MISC, 590 NULL, device_xname(sc->sc_dev), "Rx resource error counter"); 591 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_scat, EVCNT_TYPE_MISC, 592 NULL, device_xname(sc->sc_dev), "Rx unexpected scatter bufs"); 593 594 /* Tx Descriptor */ 595 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_lc, EVCNT_TYPE_MISC, 596 NULL, device_xname(sc->sc_dev), "Tx late collision counter"); 597 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_rl, EVCNT_TYPE_MISC, 598 NULL, device_xname(sc->sc_dev), "Tx excess. collision counter"); 599 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_ur, EVCNT_TYPE_MISC, 600 NULL, device_xname(sc->sc_dev), "Tx FIFO underrun counter"); 601 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_oth, EVCNT_TYPE_MISC, 602 NULL, device_xname(sc->sc_dev), "Tx unkonwn erorr counter"); 603 604 /* Status Registers */ 605 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pdfc, EVCNT_TYPE_MISC, 606 NULL, device_xname(sc->sc_dev), "Rx discard counter"); 607 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pofc, EVCNT_TYPE_MISC, 608 NULL, device_xname(sc->sc_dev), "Rx overrun counter"); 609 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txbadfcs, EVCNT_TYPE_MISC, 610 NULL, device_xname(sc->sc_dev), "Tx bad FCS counter"); 611 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txdropped, EVCNT_TYPE_MISC, 612 NULL, device_xname(sc->sc_dev), "Tx dorpped counter"); 613 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_lpic, EVCNT_TYPE_MISC, 614 NULL, device_xname(sc->sc_dev), "LP_IDLE counter"); 615 616 /* Device Driver Errors */ 617 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_wdogsoft, EVCNT_TYPE_MISC, 618 NULL, device_xname(sc->sc_dev), "watchdog timer expired"); 619 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txerr, EVCNT_TYPE_MISC, 620 NULL, device_xname(sc->sc_dev), "Tx descriptor alloc failed"); 621 #define MVXPE_QUEUE_DESC(q) "Rx success in queue " # q 622 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 623 static const char *rxq_desc[] = { 624 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 625 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 626 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 627 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 628 }; 629 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxq[q], EVCNT_TYPE_MISC, 630 NULL, device_xname(sc->sc_dev), rxq_desc[q]); 631 } 632 #undef MVXPE_QUEUE_DESC 633 #define MVXPE_QUEUE_DESC(q) "Tx success in queue " # q 634 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 635 static const char *txq_desc[] = { 636 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 637 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 638 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 639 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 640 }; 641 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txq[q], EVCNT_TYPE_MISC, 642 NULL, device_xname(sc->sc_dev), txq_desc[q]); 643 } 644 #undef MVXPE_QUEUE_DESC 645 #define MVXPE_QUEUE_DESC(q) "Rx error in queue " # q 646 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 647 static const char *rxqe_desc[] = { 648 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 649 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 650 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 651 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 652 }; 653 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxqe[q], EVCNT_TYPE_MISC, 654 NULL, device_xname(sc->sc_dev), rxqe_desc[q]); 655 } 656 #undef MVXPE_QUEUE_DESC 657 #define MVXPE_QUEUE_DESC(q) "Tx error in queue " # q 658 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 659 static const char *txqe_desc[] = { 660 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 661 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 662 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 663 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 664 }; 665 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txqe[q], EVCNT_TYPE_MISC, 666 NULL, device_xname(sc->sc_dev), txqe_desc[q]); 667 } 668 #undef MVXPE_QUEUE_DESC 669 670 #endif /* MVXPE_EVENT_COUNTERS */ 671 return 0; 672 } 673 674 STATIC void 675 mvxpe_sc_lock(struct mvxpe_softc *sc) 676 { 677 mutex_enter(&sc->sc_mtx); 678 } 679 680 STATIC void 681 mvxpe_sc_unlock(struct mvxpe_softc *sc) 682 { 683 mutex_exit(&sc->sc_mtx); 684 } 685 686 /* 687 * MII 688 */ 689 STATIC int 690 mvxpe_miibus_readreg(device_t dev, int phy, int reg) 691 { 692 struct mvxpe_softc *sc = device_private(dev); 693 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 694 uint32_t smi, val; 695 int i; 696 697 mutex_enter(&mii_mutex); 698 699 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 700 DELAY(1); 701 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 702 break; 703 } 704 if (i == MVXPE_PHY_TIMEOUT) { 705 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 706 mutex_exit(&mii_mutex); 707 return -1; 708 } 709 710 smi = 711 MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | MVXPE_SMI_OPCODE_READ; 712 MVXPE_WRITE(sc, MVXPE_SMI, smi); 713 714 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 715 DELAY(1); 716 smi = MVXPE_READ(sc, MVXPE_SMI); 717 if (smi & MVXPE_SMI_READVALID) 718 break; 719 } 720 721 mutex_exit(&mii_mutex); 722 723 DPRINTDEV(dev, 9, "i=%d, timeout=%d\n", i, MVXPE_PHY_TIMEOUT); 724 725 val = smi & MVXPE_SMI_DATA_MASK; 726 727 DPRINTDEV(dev, 9, "phy=%d, reg=%#x, val=%#x\n", phy, reg, val); 728 729 return val; 730 } 731 732 STATIC void 733 mvxpe_miibus_writereg(device_t dev, int phy, int reg, int val) 734 { 735 struct mvxpe_softc *sc = device_private(dev); 736 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 737 uint32_t smi; 738 int i; 739 740 DPRINTDEV(dev, 9, "phy=%d reg=%#x val=%#x\n", phy, reg, val); 741 742 mutex_enter(&mii_mutex); 743 744 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 745 DELAY(1); 746 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 747 break; 748 } 749 if (i == MVXPE_PHY_TIMEOUT) { 750 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 751 mutex_exit(&mii_mutex); 752 return; 753 } 754 755 smi = MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | 756 MVXPE_SMI_OPCODE_WRITE | (val & MVXPE_SMI_DATA_MASK); 757 MVXPE_WRITE(sc, MVXPE_SMI, smi); 758 759 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 760 DELAY(1); 761 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 762 break; 763 } 764 765 mutex_exit(&mii_mutex); 766 767 if (i == MVXPE_PHY_TIMEOUT) 768 aprint_error_ifnet(ifp, "phy write timed out\n"); 769 } 770 771 STATIC void 772 mvxpe_miibus_statchg(struct ifnet *ifp) 773 { 774 775 /* nothing to do */ 776 } 777 778 /* 779 * Address Decoding Window 780 */ 781 STATIC void 782 mvxpe_wininit(struct mvxpe_softc *sc, enum marvell_tags *tags) 783 { 784 device_t pdev = device_parent(sc->sc_dev); 785 uint64_t base; 786 uint32_t en, ac, size; 787 int window, target, attr, rv, i; 788 789 /* First disable all address decode windows */ 790 en = MVXPE_BARE_EN_MASK; 791 MVXPE_WRITE(sc, MVXPE_BARE, en); 792 793 ac = 0; 794 for (window = 0, i = 0; 795 tags[i] != MARVELL_TAG_UNDEFINED && window < MVXPE_NWINDOW; i++) { 796 rv = marvell_winparams_by_tag(pdev, tags[i], 797 &target, &attr, &base, &size); 798 if (rv != 0 || size == 0) 799 continue; 800 801 if (base > 0xffffffffULL) { 802 if (window >= MVXPE_NREMAP) { 803 aprint_error_dev(sc->sc_dev, 804 "can't remap window %d\n", window); 805 continue; 806 } 807 MVXPE_WRITE(sc, MVXPE_HA(window), 808 (base >> 32) & 0xffffffff); 809 } 810 811 MVXPE_WRITE(sc, MVXPE_BASEADDR(window), 812 MVXPE_BASEADDR_TARGET(target) | 813 MVXPE_BASEADDR_ATTR(attr) | 814 MVXPE_BASEADDR_BASE(base)); 815 MVXPE_WRITE(sc, MVXPE_S(window), MVXPE_S_SIZE(size)); 816 817 DPRINTSC(sc, 1, "Window %d Base 0x%016llx: Size 0x%08x\n", 818 window, base, size); 819 820 en &= ~(1 << window); 821 /* set full access (r/w) */ 822 ac |= MVXPE_EPAP_EPAR(window, MVXPE_EPAP_AC_FA); 823 window++; 824 } 825 /* allow to access decode window */ 826 MVXPE_WRITE(sc, MVXPE_EPAP, ac); 827 828 MVXPE_WRITE(sc, MVXPE_BARE, en); 829 } 830 831 /* 832 * Device Register Initialization 833 * reset device registers to device driver default value. 834 * the device is not enabled here. 835 */ 836 STATIC int 837 mvxpe_initreg(struct ifnet *ifp) 838 { 839 struct mvxpe_softc *sc = ifp->if_softc; 840 int serdes = 0; 841 uint32_t reg; 842 int q, i; 843 844 DPRINTIFNET(ifp, 1, "initializing device register\n"); 845 846 /* Init TX/RX Queue Registers */ 847 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 848 mvxpe_rx_lockq(sc, q); 849 if (mvxpe_rx_queue_init(ifp, q) != 0) { 850 aprint_error_ifnet(ifp, 851 "initialization failed: cannot initialize queue\n"); 852 mvxpe_rx_unlockq(sc, q); 853 return ENOBUFS; 854 } 855 mvxpe_rx_unlockq(sc, q); 856 857 mvxpe_tx_lockq(sc, q); 858 if (mvxpe_tx_queue_init(ifp, q) != 0) { 859 aprint_error_ifnet(ifp, 860 "initialization failed: cannot initialize queue\n"); 861 mvxpe_tx_unlockq(sc, q); 862 return ENOBUFS; 863 } 864 mvxpe_tx_unlockq(sc, q); 865 } 866 867 /* Tx MTU Limit */ 868 MVXPE_WRITE(sc, MVXPE_TXMTU, MVXPE_MTU); 869 870 /* Check SGMII or SERDES(asume IPL/U-BOOT initialize this) */ 871 reg = MVXPE_READ(sc, MVXPE_PMACC0); 872 if ((reg & MVXPE_PMACC0_PORTTYPE) != 0) 873 serdes = 1; 874 875 /* Ethernet Unit Control */ 876 reg = MVXPE_READ(sc, MVXPE_EUC); 877 reg |= MVXPE_EUC_POLLING; 878 MVXPE_WRITE(sc, MVXPE_EUC, reg); 879 880 /* Auto Negotiation */ 881 reg = MVXPE_PANC_MUSTSET; /* must write 0x1 */ 882 reg |= MVXPE_PANC_FORCELINKFAIL;/* force link state down */ 883 reg |= MVXPE_PANC_ANSPEEDEN; /* interface speed negotiation */ 884 reg |= MVXPE_PANC_ANDUPLEXEN; /* negotiate duplex mode */ 885 if (serdes) { 886 reg |= MVXPE_PANC_INBANDANEN; /* In Band negotiation */ 887 reg |= MVXPE_PANC_INBANDANBYPASSEN; /* bypass negotiation */ 888 reg |= MVXPE_PANC_SETFULLDX; /* set full-duplex on failure */ 889 } 890 MVXPE_WRITE(sc, MVXPE_PANC, reg); 891 892 /* EEE: Low Power Idle */ 893 reg = MVXPE_LPIC0_LILIMIT(MVXPE_LPI_LI); 894 reg |= MVXPE_LPIC0_TSLIMIT(MVXPE_LPI_TS); 895 MVXPE_WRITE(sc, MVXPE_LPIC0, reg); 896 897 reg = MVXPE_LPIC1_TWLIMIT(MVXPE_LPI_TS); 898 MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 899 900 reg = MVXPE_LPIC2_MUSTSET; 901 MVXPE_WRITE(sc, MVXPE_LPIC2, reg); 902 903 /* Port MAC Control set 0 */ 904 reg = MVXPE_PMACC0_MUSTSET; /* must write 0x1 */ 905 reg &= ~MVXPE_PMACC0_PORTEN; /* port is still disabled */ 906 reg |= MVXPE_PMACC0_FRAMESIZELIMIT(MVXPE_MRU); 907 if (serdes) 908 reg |= MVXPE_PMACC0_PORTTYPE; 909 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 910 911 /* Port MAC Control set 1 is only used for loop-back test */ 912 913 /* Port MAC Control set 2 */ 914 reg = MVXPE_READ(sc, MVXPE_PMACC2); 915 reg &= (MVXPE_PMACC2_PCSEN | MVXPE_PMACC2_RGMIIEN); 916 reg |= MVXPE_PMACC2_MUSTSET; 917 MVXPE_WRITE(sc, MVXPE_PMACC2, reg); 918 919 /* Port MAC Control set 3 is used for IPG tune */ 920 921 /* Port MAC Control set 4 is not used */ 922 923 /* Port Configuration Extended: enable Tx CRC generation */ 924 reg = MVXPE_READ(sc, MVXPE_PXCX); 925 reg &= ~MVXPE_PXCX_TXCRCDIS; 926 MVXPE_WRITE(sc, MVXPE_PXCX, reg); 927 928 /* clear MIB counter registers(clear by read) */ 929 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) 930 MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum)); 931 932 /* Set SDC register except IPGINT bits */ 933 reg = MVXPE_SDC_RXBSZ_16_64BITWORDS; 934 reg |= MVXPE_SDC_TXBSZ_16_64BITWORDS; 935 reg |= MVXPE_SDC_BLMR; 936 reg |= MVXPE_SDC_BLMT; 937 MVXPE_WRITE(sc, MVXPE_SDC, reg); 938 939 return 0; 940 } 941 942 /* 943 * Descriptor Ring Controls for each of queues 944 */ 945 STATIC void * 946 mvxpe_dma_memalloc(struct mvxpe_softc *sc, bus_dmamap_t *map, size_t size) 947 { 948 bus_dma_segment_t segs; 949 void *kva = NULL; 950 int nsegs; 951 952 /* 953 * Allocate the descriptor queues. 954 * struct mvxpe_ring_data contians array of descriptor per queue. 955 */ 956 if (bus_dmamem_alloc(sc->sc_dmat, 957 size, PAGE_SIZE, 0, &segs, 1, &nsegs, BUS_DMA_NOWAIT)) { 958 aprint_error_dev(sc->sc_dev, 959 "can't alloc device memory (%zu bytes)\n", size); 960 return NULL; 961 } 962 if (bus_dmamem_map(sc->sc_dmat, 963 &segs, nsegs, size, &kva, BUS_DMA_NOWAIT)) { 964 aprint_error_dev(sc->sc_dev, 965 "can't map dma buffers (%zu bytes)\n", size); 966 goto fail1; 967 } 968 969 if (bus_dmamap_create(sc->sc_dmat, 970 size, 1, size, 0, BUS_DMA_NOWAIT, map)) { 971 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 972 goto fail2; 973 } 974 if (bus_dmamap_load(sc->sc_dmat, 975 *map, kva, size, NULL, BUS_DMA_NOWAIT)) { 976 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 977 goto fail3; 978 } 979 memset(kva, 0, size); 980 return kva; 981 982 fail3: 983 bus_dmamap_destroy(sc->sc_dmat, *map); 984 memset(map, 0, sizeof(*map)); 985 fail2: 986 bus_dmamem_unmap(sc->sc_dmat, kva, size); 987 fail1: 988 bus_dmamem_free(sc->sc_dmat, &segs, nsegs); 989 return NULL; 990 } 991 992 STATIC int 993 mvxpe_ring_alloc_queue(struct mvxpe_softc *sc, int q) 994 { 995 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 996 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 997 998 /* 999 * MVXPE_RX_RING_CNT and MVXPE_TX_RING_CNT is a hard limit of 1000 * queue length. real queue length is limited by 1001 * sc->sc_rx_ring[q].rx_queue_len and sc->sc_tx_ring[q].tx_queue_len. 1002 * 1003 * because descriptor ring reallocation needs reprogramming of 1004 * DMA registers, we allocate enough descriptor for hard limit 1005 * of queue length. 1006 */ 1007 rx->rx_descriptors = 1008 mvxpe_dma_memalloc(sc, &rx->rx_descriptors_map, 1009 (sizeof(struct mvxpe_rx_desc) * MVXPE_RX_RING_CNT)); 1010 if (rx->rx_descriptors == NULL) 1011 goto fail; 1012 1013 tx->tx_descriptors = 1014 mvxpe_dma_memalloc(sc, &tx->tx_descriptors_map, 1015 (sizeof(struct mvxpe_tx_desc) * MVXPE_TX_RING_CNT)); 1016 if (tx->tx_descriptors == NULL) 1017 goto fail; 1018 1019 return 0; 1020 fail: 1021 mvxpe_ring_dealloc_queue(sc, q); 1022 aprint_error_dev(sc->sc_dev, "DMA Ring buffer allocation failure.\n"); 1023 return ENOMEM; 1024 } 1025 1026 STATIC void 1027 mvxpe_ring_dealloc_queue(struct mvxpe_softc *sc, int q) 1028 { 1029 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1030 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1031 bus_dma_segment_t *segs; 1032 bus_size_t size; 1033 void *kva; 1034 int nsegs; 1035 1036 /* Rx */ 1037 kva = (void *)MVXPE_RX_RING_MEM_VA(sc, q); 1038 if (kva) { 1039 segs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_segs; 1040 nsegs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_nsegs; 1041 size = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_mapsize; 1042 1043 bus_dmamap_unload(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1044 bus_dmamap_destroy(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1045 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1046 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1047 } 1048 1049 /* Tx */ 1050 kva = (void *)MVXPE_TX_RING_MEM_VA(sc, q); 1051 if (kva) { 1052 segs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_segs; 1053 nsegs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_nsegs; 1054 size = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_mapsize; 1055 1056 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1057 bus_dmamap_destroy(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1058 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1059 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1060 } 1061 1062 /* Clear doungling pointers all */ 1063 memset(rx, 0, sizeof(*rx)); 1064 memset(tx, 0, sizeof(*tx)); 1065 } 1066 1067 STATIC void 1068 mvxpe_ring_init_queue(struct mvxpe_softc *sc, int q) 1069 { 1070 struct mvxpe_rx_desc *rxd = MVXPE_RX_RING_MEM_VA(sc, q); 1071 struct mvxpe_tx_desc *txd = MVXPE_TX_RING_MEM_VA(sc, q); 1072 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1073 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1074 static const int rx_default_queue_len[] = { 1075 MVXPE_RX_QUEUE_LIMIT_0, MVXPE_RX_QUEUE_LIMIT_1, 1076 MVXPE_RX_QUEUE_LIMIT_2, MVXPE_RX_QUEUE_LIMIT_3, 1077 MVXPE_RX_QUEUE_LIMIT_4, MVXPE_RX_QUEUE_LIMIT_5, 1078 MVXPE_RX_QUEUE_LIMIT_6, MVXPE_RX_QUEUE_LIMIT_7, 1079 }; 1080 static const int tx_default_queue_len[] = { 1081 MVXPE_TX_QUEUE_LIMIT_0, MVXPE_TX_QUEUE_LIMIT_1, 1082 MVXPE_TX_QUEUE_LIMIT_2, MVXPE_TX_QUEUE_LIMIT_3, 1083 MVXPE_TX_QUEUE_LIMIT_4, MVXPE_TX_QUEUE_LIMIT_5, 1084 MVXPE_TX_QUEUE_LIMIT_6, MVXPE_TX_QUEUE_LIMIT_7, 1085 }; 1086 extern uint32_t mvTclk; 1087 int i; 1088 1089 /* Rx handle */ 1090 for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1091 MVXPE_RX_DESC(sc, q, i) = &rxd[i]; 1092 MVXPE_RX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_rx_desc) * i; 1093 MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1094 } 1095 mutex_init(&rx->rx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1096 rx->rx_dma = rx->rx_cpu = 0; 1097 rx->rx_queue_len = rx_default_queue_len[q]; 1098 if (rx->rx_queue_len > MVXPE_RX_RING_CNT) 1099 rx->rx_queue_len = MVXPE_RX_RING_CNT; 1100 rx->rx_queue_th_received = rx->rx_queue_len / MVXPE_RXTH_RATIO; 1101 rx->rx_queue_th_free = rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 1102 rx->rx_queue_th_time = (mvTclk / 1000) / 2; /* 0.5 [ms] */ 1103 1104 /* Tx handle */ 1105 for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1106 MVXPE_TX_DESC(sc, q, i) = &txd[i]; 1107 MVXPE_TX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_tx_desc) * i; 1108 MVXPE_TX_MBUF(sc, q, i) = NULL; 1109 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1110 if (bus_dmamap_create(sc->sc_dmat, 1111 mvxpbm_chunk_size(sc->sc_bm), 1112 MVXPE_TX_SEGLIMIT, mvxpbm_chunk_size(sc->sc_bm), 0, 1113 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 1114 &MVXPE_TX_MAP(sc, q, i))) { 1115 aprint_error_dev(sc->sc_dev, 1116 "can't create dma map (tx ring %d)\n", i); 1117 } 1118 } 1119 mutex_init(&tx->tx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1120 tx->tx_dma = tx->tx_cpu = 0; 1121 tx->tx_queue_len = tx_default_queue_len[q]; 1122 if (tx->tx_queue_len > MVXPE_TX_RING_CNT) 1123 tx->tx_queue_len = MVXPE_TX_RING_CNT; 1124 tx->tx_used = 0; 1125 tx->tx_queue_th_free = tx->tx_queue_len / MVXPE_TXTH_RATIO; 1126 } 1127 1128 STATIC void 1129 mvxpe_ring_flush_queue(struct mvxpe_softc *sc, int q) 1130 { 1131 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1132 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1133 int i; 1134 1135 KASSERT_RX_MTX(sc, q); 1136 KASSERT_TX_MTX(sc, q); 1137 1138 /* Rx handle */ 1139 for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1140 if (MVXPE_RX_PKTBUF(sc, q, i) == NULL) 1141 continue; 1142 mvxpbm_free_chunk(MVXPE_RX_PKTBUF(sc, q, i)); 1143 MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1144 } 1145 rx->rx_dma = rx->rx_cpu = 0; 1146 1147 /* Tx handle */ 1148 for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1149 if (MVXPE_TX_MBUF(sc, q, i) == NULL) 1150 continue; 1151 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, i)); 1152 m_freem(MVXPE_TX_MBUF(sc, q, i)); 1153 MVXPE_TX_MBUF(sc, q, i) = NULL; 1154 } 1155 tx->tx_dma = tx->tx_cpu = 0; 1156 tx->tx_used = 0; 1157 } 1158 1159 STATIC void 1160 mvxpe_ring_sync_rx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1161 { 1162 int wrap; 1163 1164 KASSERT_RX_MTX(sc, q); 1165 KASSERT(count > 0 && count <= MVXPE_RX_RING_CNT); 1166 KASSERT(idx >= 0 && idx < MVXPE_RX_RING_CNT); 1167 1168 wrap = (idx + count) - MVXPE_RX_RING_CNT; 1169 if (wrap > 0) { 1170 count -= wrap; 1171 KASSERT(count > 0); 1172 bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1173 0, sizeof(struct mvxpe_rx_desc) * wrap, ops); 1174 } 1175 bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1176 MVXPE_RX_DESC_OFF(sc, q, idx), 1177 sizeof(struct mvxpe_rx_desc) * count, ops); 1178 } 1179 1180 STATIC void 1181 mvxpe_ring_sync_tx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1182 { 1183 int wrap = 0; 1184 1185 KASSERT_TX_MTX(sc, q); 1186 KASSERT(count > 0 && count <= MVXPE_TX_RING_CNT); 1187 KASSERT(idx >= 0 && idx < MVXPE_TX_RING_CNT); 1188 1189 wrap = (idx + count) - MVXPE_TX_RING_CNT; 1190 if (wrap > 0) { 1191 count -= wrap; 1192 bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1193 0, sizeof(struct mvxpe_tx_desc) * wrap, ops); 1194 } 1195 bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1196 MVXPE_TX_DESC_OFF(sc, q, idx), 1197 sizeof(struct mvxpe_tx_desc) * count, ops); 1198 } 1199 1200 /* 1201 * Rx/Tx Queue Control 1202 */ 1203 STATIC int 1204 mvxpe_rx_queue_init(struct ifnet *ifp, int q) 1205 { 1206 struct mvxpe_softc *sc = ifp->if_softc; 1207 uint32_t reg; 1208 1209 KASSERT_RX_MTX(sc, q); 1210 KASSERT(MVXPE_RX_RING_MEM_PA(sc, q) != 0); 1211 1212 /* descriptor address */ 1213 MVXPE_WRITE(sc, MVXPE_PRXDQA(q), MVXPE_RX_RING_MEM_PA(sc, q)); 1214 1215 /* Rx buffer size and descriptor ring size */ 1216 reg = MVXPE_PRXDQS_BUFFERSIZE(mvxpbm_chunk_size(sc->sc_bm) >> 3); 1217 reg |= MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(MVXPE_RX_RING_CNT); 1218 MVXPE_WRITE(sc, MVXPE_PRXDQS(q), reg); 1219 DPRINTIFNET(ifp, 1, "PRXDQS(%d): %#x\n", 1220 q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 1221 1222 /* Rx packet offset address */ 1223 reg = MVXPE_PRXC_PACKETOFFSET(mvxpbm_packet_offset(sc->sc_bm) >> 3); 1224 MVXPE_WRITE(sc, MVXPE_PRXC(q), reg); 1225 DPRINTIFNET(ifp, 1, "PRXC(%d): %#x\n", 1226 q, MVXPE_READ(sc, MVXPE_PRXC(q))); 1227 1228 /* Rx DMA SNOOP */ 1229 reg = MVXPE_PRXSNP_SNOOPNOOFBYTES(MVXPE_MRU); 1230 reg |= MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(MVXPE_MRU); 1231 MVXPE_WRITE(sc, MVXPE_PRXSNP(q), reg); 1232 1233 /* if DMA is not working, register is not updated */ 1234 KASSERT(MVXPE_READ(sc, MVXPE_PRXDQA(q)) == MVXPE_RX_RING_MEM_PA(sc, q)); 1235 return 0; 1236 } 1237 1238 STATIC int 1239 mvxpe_tx_queue_init(struct ifnet *ifp, int q) 1240 { 1241 struct mvxpe_softc *sc = ifp->if_softc; 1242 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1243 uint32_t reg; 1244 1245 KASSERT_TX_MTX(sc, q); 1246 KASSERT(MVXPE_TX_RING_MEM_PA(sc, q) != 0); 1247 1248 /* descriptor address */ 1249 MVXPE_WRITE(sc, MVXPE_PTXDQA(q), MVXPE_TX_RING_MEM_PA(sc, q)); 1250 1251 /* Tx threshold, and descriptor ring size */ 1252 reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1253 reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 1254 MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1255 DPRINTIFNET(ifp, 1, "PTXDQS(%d): %#x\n", 1256 q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 1257 1258 /* if DMA is not working, register is not updated */ 1259 KASSERT(MVXPE_READ(sc, MVXPE_PTXDQA(q)) == MVXPE_TX_RING_MEM_PA(sc, q)); 1260 return 0; 1261 } 1262 1263 STATIC int 1264 mvxpe_rx_queue_enable(struct ifnet *ifp, int q) 1265 { 1266 struct mvxpe_softc *sc = ifp->if_softc; 1267 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1268 uint32_t reg; 1269 1270 KASSERT_RX_MTX(sc, q); 1271 1272 /* Set Rx interrupt threshold */ 1273 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1274 reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 1275 MVXPE_WRITE(sc, MVXPE_PRXDQTH(q), reg); 1276 1277 reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 1278 MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1279 1280 /* Unmask RXTX_TH Intr. */ 1281 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1282 reg |= MVXPE_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1283 reg |= MVXPE_PRXTXTI_RDTAQ(q); /* Rx Descriptor Alart */ 1284 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1285 1286 /* Enable Rx queue */ 1287 reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1288 reg |= MVXPE_RQC_ENQ(q); 1289 MVXPE_WRITE(sc, MVXPE_RQC, reg); 1290 1291 return 0; 1292 } 1293 1294 STATIC int 1295 mvxpe_tx_queue_enable(struct ifnet *ifp, int q) 1296 { 1297 struct mvxpe_softc *sc = ifp->if_softc; 1298 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1299 uint32_t reg; 1300 1301 KASSERT_TX_MTX(sc, q); 1302 1303 /* Set Tx interrupt threshold */ 1304 reg = MVXPE_READ(sc, MVXPE_PTXDQS(q)); 1305 reg &= ~MVXPE_PTXDQS_TBT_MASK; /* keep queue size */ 1306 reg |= MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1307 MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1308 1309 /* Unmask RXTX_TH Intr. */ 1310 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1311 reg |= MVXPE_PRXTXTI_TBTCQ(q); /* Tx Threshold cross */ 1312 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1313 1314 /* Don't update MVXPE_TQC here, there is no packet yet. */ 1315 return 0; 1316 } 1317 1318 STATIC void 1319 mvxpe_rx_lockq(struct mvxpe_softc *sc, int q) 1320 { 1321 KASSERT(q >= 0); 1322 KASSERT(q < MVXPE_QUEUE_SIZE); 1323 mutex_enter(&sc->sc_rx_ring[q].rx_ring_mtx); 1324 } 1325 1326 STATIC void 1327 mvxpe_rx_unlockq(struct mvxpe_softc *sc, int q) 1328 { 1329 KASSERT(q >= 0); 1330 KASSERT(q < MVXPE_QUEUE_SIZE); 1331 mutex_exit(&sc->sc_rx_ring[q].rx_ring_mtx); 1332 } 1333 1334 STATIC void 1335 mvxpe_tx_lockq(struct mvxpe_softc *sc, int q) 1336 { 1337 KASSERT(q >= 0); 1338 KASSERT(q < MVXPE_QUEUE_SIZE); 1339 mutex_enter(&sc->sc_tx_ring[q].tx_ring_mtx); 1340 } 1341 1342 STATIC void 1343 mvxpe_tx_unlockq(struct mvxpe_softc *sc, int q) 1344 { 1345 KASSERT(q >= 0); 1346 KASSERT(q < MVXPE_QUEUE_SIZE); 1347 mutex_exit(&sc->sc_tx_ring[q].tx_ring_mtx); 1348 } 1349 1350 /* 1351 * Interrupt Handlers 1352 */ 1353 STATIC void 1354 mvxpe_disable_intr(struct mvxpe_softc *sc) 1355 { 1356 MVXPE_WRITE(sc, MVXPE_EUIM, 0); 1357 MVXPE_WRITE(sc, MVXPE_EUIC, 0); 1358 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, 0); 1359 MVXPE_WRITE(sc, MVXPE_PRXTXTIC, 0); 1360 MVXPE_WRITE(sc, MVXPE_PRXTXIM, 0); 1361 MVXPE_WRITE(sc, MVXPE_PRXTXIC, 0); 1362 MVXPE_WRITE(sc, MVXPE_PMIM, 0); 1363 MVXPE_WRITE(sc, MVXPE_PMIC, 0); 1364 MVXPE_WRITE(sc, MVXPE_PIE, 0); 1365 } 1366 1367 STATIC void 1368 mvxpe_enable_intr(struct mvxpe_softc *sc) 1369 { 1370 uint32_t reg; 1371 1372 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1373 reg = MVXPE_READ(sc, MVXPE_PMIM); 1374 reg |= MVXPE_PMI_PHYSTATUSCHNG; 1375 reg |= MVXPE_PMI_LINKCHANGE; 1376 reg |= MVXPE_PMI_IAE; 1377 reg |= MVXPE_PMI_RXOVERRUN; 1378 reg |= MVXPE_PMI_RXCRCERROR; 1379 reg |= MVXPE_PMI_RXLARGEPACKET; 1380 reg |= MVXPE_PMI_TXUNDRN; 1381 #if 0 1382 /* 1383 * The device may raise false interrupts for SERDES even if the device 1384 * is not configured to use SERDES connection. 1385 */ 1386 reg |= MVXPE_PMI_PRBSERROR; 1387 reg |= MVXPE_PMI_SRSE; 1388 #else 1389 reg &= ~MVXPE_PMI_PRBSERROR; 1390 reg &= ~MVXPE_PMI_SRSE; 1391 #endif 1392 reg |= MVXPE_PMI_TREQ_MASK; 1393 MVXPE_WRITE(sc, MVXPE_PMIM, reg); 1394 1395 /* Enable Summary Bit to check all interrupt cause. */ 1396 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1397 reg |= MVXPE_PRXTXTI_PMISCICSUMMARY; 1398 reg |= MVXPE_PRXTXTI_PTXERRORSUMMARY; 1399 reg |= MVXPE_PRXTXTI_PRXTXICSUMMARY; 1400 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1401 1402 /* Enable All Queue Interrupt */ 1403 reg = MVXPE_READ(sc, MVXPE_PIE); 1404 reg |= MVXPE_PIE_RXPKTINTRPTENB_MASK; 1405 reg |= MVXPE_PIE_TXPKTINTRPTENB_MASK; 1406 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1407 } 1408 1409 STATIC int 1410 mvxpe_rxtxth_intr(void *arg) 1411 { 1412 struct mvxpe_softc *sc = arg; 1413 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1414 uint32_t ic, queues, datum = 0; 1415 1416 DPRINTSC(sc, 2, "got RXTX_TH_Intr\n"); 1417 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtxth); 1418 1419 mvxpe_sc_lock(sc); 1420 ic = MVXPE_READ(sc, MVXPE_PRXTXTIC); 1421 if (ic == 0) { 1422 mvxpe_sc_unlock(sc); 1423 return 0; 1424 } 1425 MVXPE_WRITE(sc, MVXPE_PRXTXTIC, ~ic); 1426 datum = datum ^ ic; 1427 1428 DPRINTIFNET(ifp, 2, "PRXTXTIC: %#x\n", ic); 1429 1430 /* ack maintance interrupt first */ 1431 if (ic & MVXPE_PRXTXTI_PTXERRORSUMMARY) { 1432 DPRINTIFNET(ifp, 1, "PRXTXTIC: +PTXERRORSUMMARY\n"); 1433 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtxth_txerr); 1434 } 1435 if ((ic & MVXPE_PRXTXTI_PMISCICSUMMARY)) { 1436 DPRINTIFNET(ifp, 2, "PTXTXTIC: +PMISCICSUMMARY\n"); 1437 mvxpe_misc_intr(sc); 1438 } 1439 if (ic & MVXPE_PRXTXTI_PRXTXICSUMMARY) { 1440 DPRINTIFNET(ifp, 2, "PTXTXTIC: +PRXTXICSUMMARY\n"); 1441 mvxpe_rxtx_intr(sc); 1442 } 1443 if (!(ifp->if_flags & IFF_RUNNING)) { 1444 mvxpe_sc_unlock(sc); 1445 return 1; 1446 } 1447 1448 /* RxTxTH interrupt */ 1449 queues = MVXPE_PRXTXTI_GET_RBICTAPQ(ic); 1450 if (queues) { 1451 DPRINTIFNET(ifp, 2, "PRXTXTIC: +RXEOF\n"); 1452 mvxpe_rx(sc, queues); 1453 } 1454 queues = MVXPE_PRXTXTI_GET_TBTCQ(ic); 1455 if (queues) { 1456 DPRINTIFNET(ifp, 2, "PRXTXTIC: +TBTCQ\n"); 1457 mvxpe_tx_complete(sc, queues); 1458 } 1459 queues = MVXPE_PRXTXTI_GET_RDTAQ(ic); 1460 if (queues) { 1461 DPRINTIFNET(ifp, 2, "PRXTXTIC: +RDTAQ\n"); 1462 mvxpe_rx_refill(sc, queues); 1463 } 1464 mvxpe_sc_unlock(sc); 1465 1466 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1467 mvxpe_start(ifp); 1468 1469 rnd_add_uint32(&sc->sc_rnd_source, datum); 1470 1471 return 1; 1472 } 1473 1474 STATIC int 1475 mvxpe_misc_intr(void *arg) 1476 { 1477 struct mvxpe_softc *sc = arg; 1478 #ifdef MVXPE_DEBUG 1479 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1480 #endif 1481 uint32_t ic; 1482 uint32_t datum = 0; 1483 int claimed = 0; 1484 1485 DPRINTSC(sc, 2, "got MISC_INTR\n"); 1486 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_misc); 1487 1488 KASSERT_SC_MTX(sc); 1489 1490 for (;;) { 1491 ic = MVXPE_READ(sc, MVXPE_PMIC); 1492 ic &= MVXPE_READ(sc, MVXPE_PMIM); 1493 if (ic == 0) 1494 break; 1495 MVXPE_WRITE(sc, MVXPE_PMIC, ~ic); 1496 datum = datum ^ ic; 1497 claimed = 1; 1498 1499 DPRINTIFNET(ifp, 2, "PMIC=%#x\n", ic); 1500 if (ic & MVXPE_PMI_PHYSTATUSCHNG) { 1501 DPRINTIFNET(ifp, 2, "+PHYSTATUSCHNG\n"); 1502 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_phystatuschng); 1503 } 1504 if (ic & MVXPE_PMI_LINKCHANGE) { 1505 DPRINTIFNET(ifp, 2, "+LINKCHANGE\n"); 1506 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_linkchange); 1507 mvxpe_linkupdate(sc); 1508 } 1509 if (ic & MVXPE_PMI_IAE) { 1510 DPRINTIFNET(ifp, 2, "+IAE\n"); 1511 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_iae); 1512 } 1513 if (ic & MVXPE_PMI_RXOVERRUN) { 1514 DPRINTIFNET(ifp, 2, "+RXOVERRUN\n"); 1515 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxoverrun); 1516 } 1517 if (ic & MVXPE_PMI_RXCRCERROR) { 1518 DPRINTIFNET(ifp, 2, "+RXCRCERROR\n"); 1519 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxcrc); 1520 } 1521 if (ic & MVXPE_PMI_RXLARGEPACKET) { 1522 DPRINTIFNET(ifp, 2, "+RXLARGEPACKET\n"); 1523 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxlargepacket); 1524 } 1525 if (ic & MVXPE_PMI_TXUNDRN) { 1526 DPRINTIFNET(ifp, 2, "+TXUNDRN\n"); 1527 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txunderrun); 1528 } 1529 if (ic & MVXPE_PMI_PRBSERROR) { 1530 DPRINTIFNET(ifp, 2, "+PRBSERROR\n"); 1531 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_prbserr); 1532 } 1533 if (ic & MVXPE_PMI_TREQ_MASK) { 1534 DPRINTIFNET(ifp, 2, "+TREQ\n"); 1535 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txreq); 1536 } 1537 } 1538 if (datum) 1539 rnd_add_uint32(&sc->sc_rnd_source, datum); 1540 1541 return claimed; 1542 } 1543 1544 STATIC int 1545 mvxpe_rxtx_intr(void *arg) 1546 { 1547 struct mvxpe_softc *sc = arg; 1548 #ifdef MVXPE_DEBUG 1549 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1550 #endif 1551 uint32_t datum = 0; 1552 uint32_t prxtxic; 1553 int claimed = 0; 1554 1555 DPRINTSC(sc, 2, "got RXTX_Intr\n"); 1556 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtx); 1557 1558 KASSERT_SC_MTX(sc); 1559 1560 for (;;) { 1561 prxtxic = MVXPE_READ(sc, MVXPE_PRXTXIC); 1562 prxtxic &= MVXPE_READ(sc, MVXPE_PRXTXIM); 1563 if (prxtxic == 0) 1564 break; 1565 MVXPE_WRITE(sc, MVXPE_PRXTXIC, ~prxtxic); 1566 datum = datum ^ prxtxic; 1567 claimed = 1; 1568 1569 DPRINTSC(sc, 2, "PRXTXIC: %#x\n", prxtxic); 1570 1571 if (prxtxic & MVXPE_PRXTXI_RREQ_MASK) { 1572 DPRINTIFNET(ifp, 1, "Rx Resource Error.\n"); 1573 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rreq); 1574 } 1575 if (prxtxic & MVXPE_PRXTXI_RPQ_MASK) { 1576 DPRINTIFNET(ifp, 1, "Rx Packet in Queue.\n"); 1577 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rpq); 1578 } 1579 if (prxtxic & MVXPE_PRXTXI_TBRQ_MASK) { 1580 DPRINTIFNET(ifp, 1, "Tx Buffer Return.\n"); 1581 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_tbrq); 1582 } 1583 if (prxtxic & MVXPE_PRXTXI_PRXTXTHICSUMMARY) { 1584 DPRINTIFNET(ifp, 1, "PRXTXTHIC Sumary\n"); 1585 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rxtxth); 1586 } 1587 if (prxtxic & MVXPE_PRXTXI_PTXERRORSUMMARY) { 1588 DPRINTIFNET(ifp, 1, "PTXERROR Sumary\n"); 1589 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_txerr); 1590 } 1591 if (prxtxic & MVXPE_PRXTXI_PMISCICSUMMARY) { 1592 DPRINTIFNET(ifp, 1, "PMISCIC Sumary\n"); 1593 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_misc); 1594 } 1595 } 1596 if (datum) 1597 rnd_add_uint32(&sc->sc_rnd_source, datum); 1598 1599 return claimed; 1600 } 1601 1602 STATIC void 1603 mvxpe_tick(void *arg) 1604 { 1605 struct mvxpe_softc *sc = arg; 1606 struct mii_data *mii = &sc->sc_mii; 1607 1608 mvxpe_sc_lock(sc); 1609 1610 mii_tick(mii); 1611 mii_pollstat(&sc->sc_mii); 1612 1613 /* read mib regisers(clear by read) */ 1614 mvxpe_update_mib(sc); 1615 1616 /* read counter registers(clear by read) */ 1617 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pdfc, 1618 MVXPE_READ(sc, MVXPE_PDFC)); 1619 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pofc, 1620 MVXPE_READ(sc, MVXPE_POFC)); 1621 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txbadfcs, 1622 MVXPE_READ(sc, MVXPE_TXBADFCS)); 1623 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txdropped, 1624 MVXPE_READ(sc, MVXPE_TXDROPPED)); 1625 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_lpic, 1626 MVXPE_READ(sc, MVXPE_LPIC)); 1627 1628 mvxpe_sc_unlock(sc); 1629 1630 callout_schedule(&sc->sc_tick_ch, hz); 1631 } 1632 1633 1634 /* 1635 * struct ifnet and mii callbacks 1636 */ 1637 STATIC void 1638 mvxpe_start(struct ifnet *ifp) 1639 { 1640 struct mvxpe_softc *sc = ifp->if_softc; 1641 struct mbuf *m; 1642 int q; 1643 1644 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1645 DPRINTIFNET(ifp, 1, "not running\n"); 1646 return; 1647 } 1648 1649 mvxpe_sc_lock(sc); 1650 if (!MVXPE_IS_LINKUP(sc)) { 1651 /* If Link is DOWN, can't start TX */ 1652 DPRINTIFNET(ifp, 1, "link fail\n"); 1653 for (;;) { 1654 /* 1655 * discard stale packets all. 1656 * these may confuse DAD, ARP or timer based protocols. 1657 */ 1658 IFQ_DEQUEUE(&ifp->if_snd, m); 1659 if (m == NULL) 1660 break; 1661 m_freem(m); 1662 } 1663 mvxpe_sc_unlock(sc); 1664 return; 1665 } 1666 for (;;) { 1667 /* 1668 * don't use IFQ_POLL(). 1669 * there is lock problem between IFQ_POLL and IFQ_DEQUEUE 1670 * on SMP enabled networking stack. 1671 */ 1672 IFQ_DEQUEUE(&ifp->if_snd, m); 1673 if (m == NULL) 1674 break; 1675 1676 q = mvxpe_tx_queue_select(sc, m); 1677 if (q < 0) 1678 break; 1679 /* mutex is held in mvxpe_tx_queue_select() */ 1680 1681 if (mvxpe_tx_queue(sc, m, q) != 0) { 1682 DPRINTIFNET(ifp, 1, "cannot add packet to tx ring\n"); 1683 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txerr); 1684 mvxpe_tx_unlockq(sc, q); 1685 break; 1686 } 1687 mvxpe_tx_unlockq(sc, q); 1688 KASSERT(sc->sc_tx_ring[q].tx_used >= 0); 1689 KASSERT(sc->sc_tx_ring[q].tx_used <= 1690 sc->sc_tx_ring[q].tx_queue_len); 1691 DPRINTIFNET(ifp, 1, "a packet is added to tx ring\n"); 1692 sc->sc_tx_pending++; 1693 ifp->if_timer = 1; 1694 sc->sc_wdogsoft = 1; 1695 bpf_mtap(ifp, m); 1696 } 1697 mvxpe_sc_unlock(sc); 1698 1699 return; 1700 } 1701 1702 STATIC int 1703 mvxpe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1704 { 1705 struct mvxpe_softc *sc = ifp->if_softc; 1706 struct ifreq *ifr = data; 1707 int error = 0; 1708 int s; 1709 1710 switch (cmd) { 1711 case SIOCGIFMEDIA: 1712 case SIOCSIFMEDIA: 1713 DPRINTIFNET(ifp, 2, "mvxpe_ioctl MEDIA\n"); 1714 s = splnet(); /* XXX: is there suitable mutex? */ 1715 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1716 splx(s); 1717 break; 1718 default: 1719 DPRINTIFNET(ifp, 2, "mvxpe_ioctl ETHER\n"); 1720 error = ether_ioctl(ifp, cmd, data); 1721 if (error == ENETRESET) { 1722 if (ifp->if_flags & IFF_RUNNING) { 1723 mvxpe_sc_lock(sc); 1724 mvxpe_filter_setup(sc); 1725 mvxpe_sc_unlock(sc); 1726 } 1727 error = 0; 1728 } 1729 break; 1730 } 1731 1732 return error; 1733 } 1734 1735 STATIC int 1736 mvxpe_init(struct ifnet *ifp) 1737 { 1738 struct mvxpe_softc *sc = ifp->if_softc; 1739 struct mii_data *mii = &sc->sc_mii; 1740 uint32_t reg; 1741 int q; 1742 1743 mvxpe_sc_lock(sc); 1744 1745 /* Start DMA Engine */ 1746 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 1747 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 1748 MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 1749 1750 /* Enable port */ 1751 reg = MVXPE_READ(sc, MVXPE_PMACC0); 1752 reg |= MVXPE_PMACC0_PORTEN; 1753 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1754 1755 /* Link up */ 1756 mvxpe_linkup(sc); 1757 1758 /* Enable All Queue and interrupt of each Queue */ 1759 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1760 mvxpe_rx_lockq(sc, q); 1761 mvxpe_rx_queue_enable(ifp, q); 1762 mvxpe_rx_queue_refill(sc, q); 1763 mvxpe_rx_unlockq(sc, q); 1764 1765 mvxpe_tx_lockq(sc, q); 1766 mvxpe_tx_queue_enable(ifp, q); 1767 mvxpe_tx_unlockq(sc, q); 1768 } 1769 1770 /* Enable interrupt */ 1771 mvxpe_enable_intr(sc); 1772 1773 /* Set Counter */ 1774 callout_schedule(&sc->sc_tick_ch, hz); 1775 1776 /* Media check */ 1777 mii_mediachg(mii); 1778 1779 ifp->if_flags |= IFF_RUNNING; 1780 ifp->if_flags &= ~IFF_OACTIVE; 1781 1782 mvxpe_sc_unlock(sc); 1783 return 0; 1784 } 1785 1786 /* ARGSUSED */ 1787 STATIC void 1788 mvxpe_stop(struct ifnet *ifp, int disable) 1789 { 1790 struct mvxpe_softc *sc = ifp->if_softc; 1791 uint32_t reg; 1792 int q, cnt; 1793 1794 DPRINTIFNET(ifp, 1, "stop device dma and interrupts.\n"); 1795 1796 mvxpe_sc_lock(sc); 1797 1798 callout_stop(&sc->sc_tick_ch); 1799 1800 /* Link down */ 1801 mvxpe_linkdown(sc); 1802 1803 /* Disable Rx interrupt */ 1804 reg = MVXPE_READ(sc, MVXPE_PIE); 1805 reg &= ~MVXPE_PIE_RXPKTINTRPTENB_MASK; 1806 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1807 1808 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1809 reg &= ~MVXPE_PRXTXTI_RBICTAPQ_MASK; 1810 reg &= ~MVXPE_PRXTXTI_RDTAQ_MASK; 1811 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1812 1813 /* Wait for all Rx activity to terminate. */ 1814 reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1815 reg = MVXPE_RQC_DIS(reg); 1816 MVXPE_WRITE(sc, MVXPE_RQC, reg); 1817 cnt = 0; 1818 do { 1819 if (cnt >= RX_DISABLE_TIMEOUT) { 1820 aprint_error_ifnet(ifp, 1821 "timeout for RX stopped. rqc 0x%x\n", reg); 1822 break; 1823 } 1824 cnt++; 1825 reg = MVXPE_READ(sc, MVXPE_RQC); 1826 } while (reg & MVXPE_RQC_EN_MASK); 1827 1828 /* Wait for all Tx activety to terminate. */ 1829 reg = MVXPE_READ(sc, MVXPE_PIE); 1830 reg &= ~MVXPE_PIE_TXPKTINTRPTENB_MASK; 1831 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1832 1833 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1834 reg &= ~MVXPE_PRXTXTI_TBTCQ_MASK; 1835 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1836 1837 reg = MVXPE_READ(sc, MVXPE_TQC) & MVXPE_TQC_EN_MASK; 1838 reg = MVXPE_TQC_DIS(reg); 1839 MVXPE_WRITE(sc, MVXPE_TQC, reg); 1840 cnt = 0; 1841 do { 1842 if (cnt >= TX_DISABLE_TIMEOUT) { 1843 aprint_error_ifnet(ifp, 1844 "timeout for TX stopped. tqc 0x%x\n", reg); 1845 break; 1846 } 1847 cnt++; 1848 reg = MVXPE_READ(sc, MVXPE_TQC); 1849 } while (reg & MVXPE_TQC_EN_MASK); 1850 1851 /* Wait for all Tx FIFO is empty */ 1852 cnt = 0; 1853 do { 1854 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1855 aprint_error_ifnet(ifp, 1856 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1857 break; 1858 } 1859 cnt++; 1860 reg = MVXPE_READ(sc, MVXPE_PS0); 1861 } while (!(reg & MVXPE_PS0_TXFIFOEMP) && (reg & MVXPE_PS0_TXINPROG)); 1862 1863 /* Reset the MAC Port Enable bit */ 1864 reg = MVXPE_READ(sc, MVXPE_PMACC0); 1865 reg &= ~MVXPE_PMACC0_PORTEN; 1866 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1867 1868 /* Disable each of queue */ 1869 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1870 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1871 1872 mvxpe_rx_lockq(sc, q); 1873 mvxpe_tx_lockq(sc, q); 1874 1875 /* Disable Rx packet buffer refill request */ 1876 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1877 reg |= MVXPE_PRXDQTH_NODT(0); 1878 MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1879 1880 if (disable) { 1881 /* 1882 * Hold Reset state of DMA Engine 1883 * (must write 0x0 to restart it) 1884 */ 1885 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 1886 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 1887 mvxpe_ring_flush_queue(sc, q); 1888 } 1889 1890 mvxpe_tx_unlockq(sc, q); 1891 mvxpe_rx_unlockq(sc, q); 1892 } 1893 1894 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1895 1896 mvxpe_sc_unlock(sc); 1897 } 1898 1899 STATIC void 1900 mvxpe_watchdog(struct ifnet *ifp) 1901 { 1902 struct mvxpe_softc *sc = ifp->if_softc; 1903 int q; 1904 1905 mvxpe_sc_lock(sc); 1906 1907 /* 1908 * Reclaim first as there is a possibility of losing Tx completion 1909 * interrupts. 1910 */ 1911 mvxpe_tx_complete(sc, 0xff); 1912 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1913 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1914 1915 if (tx->tx_dma != tx->tx_cpu) { 1916 if (sc->sc_wdogsoft) { 1917 /* 1918 * There is race condition between CPU and DMA 1919 * engine. When DMA engine encounters queue end, 1920 * it clears MVXPE_TQC_ENQ bit. 1921 * XXX: how about enhanced mode? 1922 */ 1923 MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 1924 ifp->if_timer = 5; 1925 sc->sc_wdogsoft = 0; 1926 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_wdogsoft); 1927 } else { 1928 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1929 ifp->if_oerrors++; 1930 mvxpe_linkreset(sc); 1931 mvxpe_sc_unlock(sc); 1932 1933 /* trigger reinitialize sequence */ 1934 mvxpe_stop(ifp, 1); 1935 mvxpe_init(ifp); 1936 1937 mvxpe_sc_lock(sc); 1938 } 1939 } 1940 } 1941 mvxpe_sc_unlock(sc); 1942 } 1943 1944 STATIC int 1945 mvxpe_ifflags_cb(struct ethercom *ec) 1946 { 1947 struct ifnet *ifp = &ec->ec_if; 1948 struct mvxpe_softc *sc = ifp->if_softc; 1949 int change = ifp->if_flags ^ sc->sc_if_flags; 1950 1951 mvxpe_sc_lock(sc); 1952 1953 if (change != 0) 1954 sc->sc_if_flags = ifp->if_flags; 1955 1956 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) { 1957 mvxpe_sc_unlock(sc); 1958 return ENETRESET; 1959 } 1960 1961 if ((change & IFF_PROMISC) != 0) 1962 mvxpe_filter_setup(sc); 1963 1964 if ((change & IFF_UP) != 0) 1965 mvxpe_linkreset(sc); 1966 1967 mvxpe_sc_unlock(sc); 1968 return 0; 1969 } 1970 1971 STATIC int 1972 mvxpe_mediachange(struct ifnet *ifp) 1973 { 1974 return ether_mediachange(ifp); 1975 } 1976 1977 STATIC void 1978 mvxpe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1979 { 1980 ether_mediastatus(ifp, ifmr); 1981 } 1982 1983 /* 1984 * Link State Notify 1985 */ 1986 STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc) 1987 { 1988 int linkup; /* bool */ 1989 1990 KASSERT_SC_MTX(sc); 1991 1992 /* tell miibus */ 1993 mii_pollstat(&sc->sc_mii); 1994 1995 /* syslog */ 1996 linkup = MVXPE_IS_LINKUP(sc); 1997 if (sc->sc_linkstate == linkup) 1998 return; 1999 2000 #ifdef DEBUG 2001 log(LOG_DEBUG, 2002 "%s: link %s\n", device_xname(sc->sc_dev), linkup ? "up" : "down"); 2003 #endif 2004 if (linkup) 2005 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_up); 2006 else 2007 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_down); 2008 2009 sc->sc_linkstate = linkup; 2010 } 2011 2012 STATIC void 2013 mvxpe_linkup(struct mvxpe_softc *sc) 2014 { 2015 uint32_t reg; 2016 2017 KASSERT_SC_MTX(sc); 2018 2019 /* set EEE parameters */ 2020 reg = MVXPE_READ(sc, MVXPE_LPIC1); 2021 if (sc->sc_cf.cf_lpi) 2022 reg |= MVXPE_LPIC1_LPIRE; 2023 else 2024 reg &= ~MVXPE_LPIC1_LPIRE; 2025 MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 2026 2027 /* set auto-negotiation parameters */ 2028 reg = MVXPE_READ(sc, MVXPE_PANC); 2029 if (sc->sc_cf.cf_fc) { 2030 /* flow control negotiation */ 2031 reg |= MVXPE_PANC_PAUSEADV; 2032 reg |= MVXPE_PANC_ANFCEN; 2033 } 2034 else { 2035 reg &= ~MVXPE_PANC_PAUSEADV; 2036 reg &= ~MVXPE_PANC_ANFCEN; 2037 } 2038 reg &= ~MVXPE_PANC_FORCELINKFAIL; 2039 reg &= ~MVXPE_PANC_FORCELINKPASS; 2040 MVXPE_WRITE(sc, MVXPE_PANC, reg); 2041 2042 mii_mediachg(&sc->sc_mii); 2043 } 2044 2045 STATIC void 2046 mvxpe_linkdown(struct mvxpe_softc *sc) 2047 { 2048 struct mii_softc *mii; 2049 uint32_t reg; 2050 2051 KASSERT_SC_MTX(sc); 2052 return; 2053 2054 reg = MVXPE_READ(sc, MVXPE_PANC); 2055 reg |= MVXPE_PANC_FORCELINKFAIL; 2056 reg &= MVXPE_PANC_FORCELINKPASS; 2057 MVXPE_WRITE(sc, MVXPE_PANC, reg); 2058 2059 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2060 if (mii) 2061 mii_phy_down(mii); 2062 } 2063 2064 STATIC void 2065 mvxpe_linkreset(struct mvxpe_softc *sc) 2066 { 2067 struct mii_softc *mii; 2068 2069 KASSERT_SC_MTX(sc); 2070 2071 /* force reset PHY first */ 2072 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2073 if (mii) 2074 mii_phy_reset(mii); 2075 2076 /* reinit MAC and PHY */ 2077 mvxpe_linkdown(sc); 2078 if ((sc->sc_if_flags & IFF_UP) != 0) 2079 mvxpe_linkup(sc); 2080 } 2081 2082 /* 2083 * Tx Subroutines 2084 */ 2085 STATIC int 2086 mvxpe_tx_queue_select(struct mvxpe_softc *sc, struct mbuf *m) 2087 { 2088 int q = 0; 2089 2090 /* XXX: get attribute from ALTQ framework? */ 2091 mvxpe_tx_lockq(sc, q); 2092 return 0; 2093 } 2094 2095 STATIC int 2096 mvxpe_tx_queue(struct mvxpe_softc *sc, struct mbuf *m, int q) 2097 { 2098 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2099 bus_dma_segment_t *txsegs; 2100 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2101 struct mvxpe_tx_desc *t = NULL; 2102 uint32_t ptxsu; 2103 int txnsegs; 2104 int start, used; 2105 int i; 2106 2107 KASSERT_TX_MTX(sc, q); 2108 KASSERT(tx->tx_used >= 0); 2109 KASSERT(tx->tx_used <= tx->tx_queue_len); 2110 2111 /* load mbuf using dmamap of 1st descriptor */ 2112 if (bus_dmamap_load_mbuf(sc->sc_dmat, 2113 MVXPE_TX_MAP(sc, q, tx->tx_cpu), m, BUS_DMA_NOWAIT) != 0) { 2114 m_freem(m); 2115 return ENOBUFS; 2116 } 2117 txsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_segs; 2118 txnsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_nsegs; 2119 if (txnsegs <= 0 || (txnsegs + tx->tx_used) > tx->tx_queue_len) { 2120 /* we have no enough descriptors or mbuf is broken */ 2121 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, tx->tx_cpu)); 2122 m_freem(m); 2123 return ENOBUFS; 2124 } 2125 DPRINTSC(sc, 2, "send packet %p descriptor %d\n", m, tx->tx_cpu); 2126 KASSERT(MVXPE_TX_MBUF(sc, q, tx->tx_cpu) == NULL); 2127 2128 /* remember mbuf using 1st descriptor */ 2129 MVXPE_TX_MBUF(sc, q, tx->tx_cpu) = m; 2130 bus_dmamap_sync(sc->sc_dmat, 2131 MVXPE_TX_MAP(sc, q, tx->tx_cpu), 0, m->m_pkthdr.len, 2132 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2133 2134 /* load to tx descriptors */ 2135 start = tx->tx_cpu; 2136 used = 0; 2137 for (i = 0; i < txnsegs; i++) { 2138 if (__predict_false(txsegs[i].ds_len == 0)) 2139 continue; 2140 t = MVXPE_TX_DESC(sc, q, tx->tx_cpu); 2141 t->command = 0; 2142 t->l4ichk = 0; 2143 t->flags = 0; 2144 if (i == 0) { 2145 /* 1st descriptor */ 2146 t->command |= MVXPE_TX_CMD_W_PACKET_OFFSET(0); 2147 t->command |= MVXPE_TX_CMD_PADDING; 2148 t->command |= MVXPE_TX_CMD_F; 2149 mvxpe_tx_set_csumflag(ifp, t, m); 2150 } 2151 t->bufptr = txsegs[i].ds_addr; 2152 t->bytecnt = txsegs[i].ds_len; 2153 tx->tx_cpu = tx_counter_adv(tx->tx_cpu, 1); 2154 tx->tx_used++; 2155 used++; 2156 } 2157 /* t is last descriptor here */ 2158 KASSERT(t != NULL); 2159 t->command |= MVXPE_TX_CMD_L; 2160 2161 DPRINTSC(sc, 2, "queue %d, %d descriptors used\n", q, used); 2162 #ifdef MVXPE_DEBUG 2163 if (mvxpe_debug > 2) 2164 for (i = start; i <= tx->tx_cpu; i++) { 2165 t = MVXPE_TX_DESC(sc, q, i); 2166 mvxpe_dump_txdesc(t, i); 2167 } 2168 #endif 2169 mvxpe_ring_sync_tx(sc, q, start, used, 2170 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2171 2172 while (used > 255) { 2173 ptxsu = MVXPE_PTXSU_NOWD(255); 2174 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2175 used -= 255; 2176 } 2177 if (used > 0) { 2178 ptxsu = MVXPE_PTXSU_NOWD(used); 2179 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2180 } 2181 MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 2182 2183 DPRINTSC(sc, 2, 2184 "PTXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQA(q))); 2185 DPRINTSC(sc, 2, 2186 "PTXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 2187 DPRINTSC(sc, 2, 2188 "PTXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXS(q))); 2189 DPRINTSC(sc, 2, 2190 "PTXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PTXDI(q))); 2191 DPRINTSC(sc, 2, "TQC: %#x\n", MVXPE_READ(sc, MVXPE_TQC)); 2192 DPRINTIFNET(ifp, 2, 2193 "Tx: tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2194 tx->tx_cpu, tx->tx_dma, tx->tx_used); 2195 return 0; 2196 } 2197 2198 STATIC void 2199 mvxpe_tx_set_csumflag(struct ifnet *ifp, 2200 struct mvxpe_tx_desc *t, struct mbuf *m) 2201 { 2202 struct ether_header *eh; 2203 int csum_flags; 2204 uint32_t iphl = 0, ipoff = 0; 2205 2206 2207 csum_flags = ifp->if_csum_flags_tx & m->m_pkthdr.csum_flags; 2208 2209 eh = mtod(m, struct ether_header *); 2210 switch (htons(eh->ether_type)) { 2211 case ETHERTYPE_IP: 2212 case ETHERTYPE_IPV6: 2213 ipoff = ETHER_HDR_LEN; 2214 break; 2215 case ETHERTYPE_VLAN: 2216 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2217 break; 2218 } 2219 2220 if (csum_flags & (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 2221 iphl = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2222 t->command |= MVXPE_TX_CMD_L3_IP4; 2223 } 2224 else if (csum_flags & (M_CSUM_TCPv6|M_CSUM_UDPv6)) { 2225 iphl = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 2226 t->command |= MVXPE_TX_CMD_L3_IP6; 2227 } 2228 else { 2229 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2230 return; 2231 } 2232 2233 2234 /* L3 */ 2235 if (csum_flags & M_CSUM_IPv4) { 2236 t->command |= MVXPE_TX_CMD_IP4_CHECKSUM; 2237 } 2238 2239 /* L4 */ 2240 if ((csum_flags & 2241 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6)) == 0) { 2242 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2243 } 2244 else if (csum_flags & M_CSUM_TCPv4) { 2245 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2246 t->command |= MVXPE_TX_CMD_L4_TCP; 2247 } 2248 else if (csum_flags & M_CSUM_UDPv4) { 2249 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2250 t->command |= MVXPE_TX_CMD_L4_UDP; 2251 } 2252 else if (csum_flags & M_CSUM_TCPv6) { 2253 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2254 t->command |= MVXPE_TX_CMD_L4_TCP; 2255 } 2256 else if (csum_flags & M_CSUM_UDPv6) { 2257 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2258 t->command |= MVXPE_TX_CMD_L4_UDP; 2259 } 2260 2261 t->l4ichk = 0; 2262 t->command |= MVXPE_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2263 t->command |= MVXPE_TX_CMD_L3_OFFSET(ipoff); 2264 } 2265 2266 STATIC void 2267 mvxpe_tx_complete(struct mvxpe_softc *sc, uint32_t queues) 2268 { 2269 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2270 int q; 2271 2272 DPRINTSC(sc, 2, "tx completed.\n"); 2273 2274 KASSERT_SC_MTX(sc); 2275 2276 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2277 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2278 continue; 2279 mvxpe_tx_lockq(sc, q); 2280 mvxpe_tx_queue_complete(sc, q); 2281 mvxpe_tx_unlockq(sc, q); 2282 } 2283 KASSERT(sc->sc_tx_pending >= 0); 2284 if (sc->sc_tx_pending == 0) 2285 ifp->if_timer = 0; 2286 } 2287 2288 STATIC void 2289 mvxpe_tx_queue_complete(struct mvxpe_softc *sc, int q) 2290 { 2291 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2292 struct mvxpe_tx_desc *t; 2293 uint32_t ptxs, ptxsu, ndesc; 2294 int i; 2295 2296 KASSERT_TX_MTX(sc, q); 2297 2298 ptxs = MVXPE_READ(sc, MVXPE_PTXS(q)); 2299 ndesc = MVXPE_PTXS_GET_TBC(ptxs); 2300 if (ndesc == 0) 2301 return; 2302 2303 DPRINTSC(sc, 2, 2304 "tx complete queue %d, %d descriptors.\n", q, ndesc); 2305 2306 mvxpe_ring_sync_tx(sc, q, tx->tx_dma, ndesc, 2307 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2308 2309 for (i = 0; i < ndesc; i++) { 2310 int error = 0; 2311 2312 t = MVXPE_TX_DESC(sc, q, tx->tx_dma); 2313 if (t->flags & MVXPE_TX_F_ES) { 2314 DPRINTSC(sc, 1, 2315 "tx error queue %d desc %d\n", 2316 q, tx->tx_dma); 2317 switch (t->flags & MVXPE_TX_F_EC_MASK) { 2318 case MVXPE_TX_F_EC_LC: 2319 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_lc); 2320 break; 2321 case MVXPE_TX_F_EC_UR: 2322 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_ur); 2323 break; 2324 case MVXPE_TX_F_EC_RL: 2325 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_rl); 2326 break; 2327 default: 2328 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_oth); 2329 break; 2330 } 2331 error = 1; 2332 } 2333 if (MVXPE_TX_MBUF(sc, q, tx->tx_dma) != NULL) { 2334 KASSERT((t->command & MVXPE_TX_CMD_F) != 0); 2335 bus_dmamap_unload(sc->sc_dmat, 2336 MVXPE_TX_MAP(sc, q, tx->tx_dma)); 2337 m_freem(MVXPE_TX_MBUF(sc, q, tx->tx_dma)); 2338 MVXPE_TX_MBUF(sc, q, tx->tx_dma) = NULL; 2339 sc->sc_tx_pending--; 2340 } 2341 else 2342 KASSERT((t->flags & MVXPE_TX_CMD_F) == 0); 2343 tx->tx_dma = tx_counter_adv(tx->tx_dma, 1); 2344 tx->tx_used--; 2345 if (error) 2346 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txqe[q]); 2347 else 2348 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txq[q]); 2349 } 2350 KASSERT(tx->tx_used >= 0); 2351 KASSERT(tx->tx_used <= tx->tx_queue_len); 2352 while (ndesc > 255) { 2353 ptxsu = MVXPE_PTXSU_NORB(255); 2354 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2355 ndesc -= 255; 2356 } 2357 if (ndesc > 0) { 2358 ptxsu = MVXPE_PTXSU_NORB(ndesc); 2359 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2360 } 2361 DPRINTSC(sc, 2, 2362 "Tx complete q %d, tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2363 q, tx->tx_cpu, tx->tx_dma, tx->tx_used); 2364 } 2365 2366 /* 2367 * Rx Subroutines 2368 */ 2369 STATIC void 2370 mvxpe_rx(struct mvxpe_softc *sc, uint32_t queues) 2371 { 2372 int q, npkt; 2373 2374 KASSERT_SC_MTX(sc); 2375 2376 while ( (npkt = mvxpe_rx_queue_select(sc, queues, &q))) { 2377 /* mutex is held by rx_queue_select */ 2378 mvxpe_rx_queue(sc, q, npkt); 2379 mvxpe_rx_unlockq(sc, q); 2380 } 2381 } 2382 2383 STATIC void 2384 mvxpe_rx_queue(struct mvxpe_softc *sc, int q, int npkt) 2385 { 2386 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2387 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2388 struct mvxpe_rx_desc *r; 2389 struct mvxpbm_chunk *chunk; 2390 struct mbuf *m; 2391 uint32_t prxsu; 2392 int error = 0; 2393 int i; 2394 2395 KASSERT_RX_MTX(sc, q); 2396 2397 mvxpe_ring_sync_rx(sc, q, rx->rx_dma, npkt, 2398 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2399 2400 for (i = 0; i < npkt; i++) { 2401 /* get descriptor and packet */ 2402 chunk = MVXPE_RX_PKTBUF(sc, q, rx->rx_dma); 2403 MVXPE_RX_PKTBUF(sc, q, rx->rx_dma) = NULL; 2404 r = MVXPE_RX_DESC(sc, q, rx->rx_dma); 2405 mvxpbm_dmamap_sync(chunk, r->bytecnt, BUS_DMASYNC_POSTREAD); 2406 2407 /* check errors */ 2408 if (r->status & MVXPE_RX_ES) { 2409 switch (r->status & MVXPE_RX_EC_MASK) { 2410 case MVXPE_RX_EC_CE: 2411 DPRINTIFNET(ifp, 1, "CRC error\n"); 2412 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_ce); 2413 break; 2414 case MVXPE_RX_EC_OR: 2415 DPRINTIFNET(ifp, 1, "Rx FIFO overrun\n"); 2416 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_or); 2417 break; 2418 case MVXPE_RX_EC_MF: 2419 DPRINTIFNET(ifp, 1, "Rx too large frame\n"); 2420 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_mf); 2421 break; 2422 case MVXPE_RX_EC_RE: 2423 DPRINTIFNET(ifp, 1, "Rx resource error\n"); 2424 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_re); 2425 break; 2426 } 2427 error = 1; 2428 goto rx_done; 2429 } 2430 if (!(r->status & MVXPE_RX_F) || !(r->status & MVXPE_RX_L)) { 2431 DPRINTIFNET(ifp, 1, "not support scatter buf\n"); 2432 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_scat); 2433 error = 1; 2434 goto rx_done; 2435 } 2436 2437 if (chunk == NULL) { 2438 device_printf(sc->sc_dev, 2439 "got rx interrupt, but no chunk\n"); 2440 error = 1; 2441 goto rx_done; 2442 } 2443 2444 /* extract packet buffer */ 2445 if (mvxpbm_init_mbuf_hdr(chunk) != 0) { 2446 error = 1; 2447 goto rx_done; 2448 } 2449 m = chunk->m; 2450 m->m_pkthdr.rcvif = ifp; 2451 m->m_pkthdr.len = m->m_len = r->bytecnt - ETHER_CRC_LEN; 2452 m_adj(m, MVXPE_HWHEADER_SIZE); /* strip MH */ 2453 mvxpe_rx_set_csumflag(ifp, r, m); 2454 ifp->if_ipackets++; 2455 bpf_mtap(ifp, m); 2456 if_percpuq_enqueue(ifp->if_percpuq, m); 2457 chunk = NULL; /* the BM chunk goes to networking stack now */ 2458 rx_done: 2459 if (chunk) { 2460 /* rx error. just return the chunk to BM. */ 2461 mvxpbm_free_chunk(chunk); 2462 } 2463 if (error) 2464 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxqe[q]); 2465 else 2466 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxq[q]); 2467 rx->rx_dma = rx_counter_adv(rx->rx_dma, 1); 2468 } 2469 /* DMA status update */ 2470 DPRINTSC(sc, 2, "%d packets received from queue %d\n", npkt, q); 2471 while (npkt > 255) { 2472 prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2473 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2474 npkt -= 255; 2475 } 2476 if (npkt > 0) { 2477 prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(npkt); 2478 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2479 } 2480 2481 DPRINTSC(sc, 2, 2482 "PRXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQA(q))); 2483 DPRINTSC(sc, 2, 2484 "PRXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 2485 DPRINTSC(sc, 2, 2486 "PRXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXS(q))); 2487 DPRINTSC(sc, 2, 2488 "PRXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PRXDI(q))); 2489 DPRINTSC(sc, 2, "RQC: %#x\n", MVXPE_READ(sc, MVXPE_RQC)); 2490 DPRINTIFNET(ifp, 2, "Rx: rx_cpu = %d, rx_dma = %d\n", 2491 rx->rx_cpu, rx->rx_dma); 2492 } 2493 2494 STATIC int 2495 mvxpe_rx_queue_select(struct mvxpe_softc *sc, uint32_t queues, int *queue) 2496 { 2497 uint32_t prxs, npkt; 2498 int q; 2499 2500 KASSERT_SC_MTX(sc); 2501 KASSERT(queue != NULL); 2502 DPRINTSC(sc, 2, "selecting rx queue\n"); 2503 2504 for (q = MVXPE_QUEUE_SIZE - 1; q >= 0; q--) { 2505 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2506 continue; 2507 2508 prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2509 npkt = MVXPE_PRXS_GET_ODC(prxs); 2510 if (npkt == 0) 2511 continue; 2512 2513 DPRINTSC(sc, 2, 2514 "queue %d selected: prxs=%#x, %u pakcet received.\n", 2515 q, prxs, npkt); 2516 *queue = q; 2517 mvxpe_rx_lockq(sc, q); 2518 return npkt; 2519 } 2520 2521 return 0; 2522 } 2523 2524 STATIC void 2525 mvxpe_rx_refill(struct mvxpe_softc *sc, uint32_t queues) 2526 { 2527 int q; 2528 2529 KASSERT_SC_MTX(sc); 2530 2531 /* XXX: check rx bit array */ 2532 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2533 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2534 continue; 2535 2536 mvxpe_rx_lockq(sc, q); 2537 mvxpe_rx_queue_refill(sc, q); 2538 mvxpe_rx_unlockq(sc, q); 2539 } 2540 } 2541 2542 STATIC void 2543 mvxpe_rx_queue_refill(struct mvxpe_softc *sc, int q) 2544 { 2545 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2546 uint32_t prxs, prxsu, ndesc; 2547 int idx, refill = 0; 2548 int npkt; 2549 2550 KASSERT_RX_MTX(sc, q); 2551 2552 prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2553 ndesc = MVXPE_PRXS_GET_NODC(prxs) + MVXPE_PRXS_GET_ODC(prxs); 2554 refill = rx->rx_queue_len - ndesc; 2555 if (refill <= 0) 2556 return; 2557 DPRINTPRXS(2, q); 2558 DPRINTSC(sc, 2, "%d buffers to refill.\n", refill); 2559 2560 idx = rx->rx_cpu; 2561 for (npkt = 0; npkt < refill; npkt++) 2562 if (mvxpe_rx_queue_add(sc, q) != 0) 2563 break; 2564 DPRINTSC(sc, 2, "queue %d, %d buffer refilled.\n", q, npkt); 2565 if (npkt == 0) 2566 return; 2567 2568 mvxpe_ring_sync_rx(sc, q, idx, npkt, 2569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2570 2571 while (npkt > 255) { 2572 prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(255); 2573 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2574 npkt -= 255; 2575 } 2576 if (npkt > 0) { 2577 prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(npkt); 2578 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2579 } 2580 DPRINTPRXS(2, q); 2581 return; 2582 } 2583 2584 STATIC int 2585 mvxpe_rx_queue_add(struct mvxpe_softc *sc, int q) 2586 { 2587 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2588 struct mvxpe_rx_desc *r; 2589 struct mvxpbm_chunk *chunk = NULL; 2590 2591 KASSERT_RX_MTX(sc, q); 2592 2593 /* Allocate the packet buffer */ 2594 chunk = mvxpbm_alloc(sc->sc_bm); 2595 if (chunk == NULL) { 2596 DPRINTSC(sc, 1, "BM chunk allocation failed.\n"); 2597 return ENOBUFS; 2598 } 2599 2600 /* Add the packet to descritor */ 2601 KASSERT(MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) == NULL); 2602 MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) = chunk; 2603 mvxpbm_dmamap_sync(chunk, BM_SYNC_ALL, BUS_DMASYNC_PREREAD); 2604 2605 r = MVXPE_RX_DESC(sc, q, rx->rx_cpu); 2606 r->bufptr = chunk->buf_pa; 2607 DPRINTSC(sc, 9, "chunk added to index %d\n", rx->rx_cpu); 2608 rx->rx_cpu = rx_counter_adv(rx->rx_cpu, 1); 2609 return 0; 2610 } 2611 2612 STATIC void 2613 mvxpe_rx_set_csumflag(struct ifnet *ifp, 2614 struct mvxpe_rx_desc *r, struct mbuf *m0) 2615 { 2616 uint32_t csum_flags = 0; 2617 2618 if ((r->status & (MVXPE_RX_IP_HEADER_OK|MVXPE_RX_L3_IP)) == 0) 2619 return; /* not a IP packet */ 2620 2621 /* L3 */ 2622 if (r->status & MVXPE_RX_L3_IP) { 2623 csum_flags |= M_CSUM_IPv4 & ifp->if_csum_flags_rx; 2624 if ((r->status & MVXPE_RX_IP_HEADER_OK) == 0 && 2625 (csum_flags & M_CSUM_IPv4) != 0) { 2626 csum_flags |= M_CSUM_IPv4_BAD; 2627 goto finish; 2628 } 2629 else if (r->status & MVXPE_RX_IPV4_FRAGMENT) { 2630 /* 2631 * r->l4chk has partial checksum of each framgment. 2632 * but there is no way to use it in NetBSD. 2633 */ 2634 return; 2635 } 2636 } 2637 2638 /* L4 */ 2639 switch (r->status & MVXPE_RX_L4_MASK) { 2640 case MVXPE_RX_L4_TCP: 2641 if (r->status & MVXPE_RX_L3_IP) 2642 csum_flags |= M_CSUM_TCPv4 & ifp->if_csum_flags_rx; 2643 else 2644 csum_flags |= M_CSUM_TCPv6 & ifp->if_csum_flags_rx; 2645 break; 2646 case MVXPE_RX_L4_UDP: 2647 if (r->status & MVXPE_RX_L3_IP) 2648 csum_flags |= M_CSUM_UDPv4 & ifp->if_csum_flags_rx; 2649 else 2650 csum_flags |= M_CSUM_UDPv6 & ifp->if_csum_flags_rx; 2651 break; 2652 case MVXPE_RX_L4_OTH: 2653 default: 2654 break; 2655 } 2656 if ((r->status & MVXPE_RX_L4_CHECKSUM_OK) == 0 && (csum_flags & 2657 (M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2658 csum_flags |= M_CSUM_TCP_UDP_BAD; 2659 finish: 2660 m0->m_pkthdr.csum_flags = csum_flags; 2661 } 2662 2663 /* 2664 * MAC address filter 2665 */ 2666 STATIC uint8_t 2667 mvxpe_crc8(const uint8_t *data, size_t size) 2668 { 2669 int bit; 2670 uint8_t byte; 2671 uint8_t crc = 0; 2672 const uint8_t poly = 0x07; 2673 2674 while(size--) 2675 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2676 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2677 2678 return crc; 2679 } 2680 2681 CTASSERT(MVXPE_NDFSMT == MVXPE_NDFOMT); 2682 2683 STATIC void 2684 mvxpe_filter_setup(struct mvxpe_softc *sc) 2685 { 2686 struct ethercom *ec = &sc->sc_ethercom; 2687 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2688 struct ether_multi *enm; 2689 struct ether_multistep step; 2690 uint32_t dfut[MVXPE_NDFUT], dfsmt[MVXPE_NDFSMT], dfomt[MVXPE_NDFOMT]; 2691 uint32_t pxc; 2692 int i; 2693 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2694 2695 KASSERT_SC_MTX(sc); 2696 2697 memset(dfut, 0, sizeof(dfut)); 2698 memset(dfsmt, 0, sizeof(dfsmt)); 2699 memset(dfomt, 0, sizeof(dfomt)); 2700 2701 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2702 goto allmulti; 2703 } 2704 2705 ETHER_FIRST_MULTI(step, ec, enm); 2706 while (enm != NULL) { 2707 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2708 /* ranges are complex and somewhat rare */ 2709 goto allmulti; 2710 } 2711 /* chip handles some IPv4 multicast specially */ 2712 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2713 i = enm->enm_addrlo[5]; 2714 dfsmt[i>>2] |= 2715 MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2716 } else { 2717 i = mvxpe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2718 dfomt[i>>2] |= 2719 MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2720 } 2721 2722 ETHER_NEXT_MULTI(step, enm); 2723 } 2724 goto set; 2725 2726 allmulti: 2727 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2728 for (i = 0; i < MVXPE_NDFSMT; i++) { 2729 dfsmt[i] = dfomt[i] = 2730 MVXPE_DF(0, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2731 MVXPE_DF(1, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2732 MVXPE_DF(2, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2733 MVXPE_DF(3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2734 } 2735 } 2736 2737 set: 2738 pxc = MVXPE_READ(sc, MVXPE_PXC); 2739 pxc &= ~MVXPE_PXC_UPM; 2740 pxc |= MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP; 2741 if (ifp->if_flags & IFF_BROADCAST) { 2742 pxc &= ~(MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP); 2743 } 2744 if (ifp->if_flags & IFF_PROMISC) { 2745 pxc |= MVXPE_PXC_UPM; 2746 } 2747 MVXPE_WRITE(sc, MVXPE_PXC, pxc); 2748 2749 /* Set Destination Address Filter Unicast Table */ 2750 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2751 dfut[i>>2] = MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2752 MVXPE_WRITE_REGION(sc, MVXPE_DFUT(0), dfut, MVXPE_NDFUT); 2753 2754 /* Set Destination Address Filter Multicast Tables */ 2755 MVXPE_WRITE_REGION(sc, MVXPE_DFSMT(0), dfsmt, MVXPE_NDFSMT); 2756 MVXPE_WRITE_REGION(sc, MVXPE_DFOMT(0), dfomt, MVXPE_NDFOMT); 2757 } 2758 2759 /* 2760 * sysctl(9) 2761 */ 2762 SYSCTL_SETUP(sysctl_mvxpe, "sysctl mvxpe subtree setup") 2763 { 2764 int rc; 2765 const struct sysctlnode *node; 2766 2767 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2768 0, CTLTYPE_NODE, "mvxpe", 2769 SYSCTL_DESCR("mvxpe interface controls"), 2770 NULL, 0, NULL, 0, 2771 CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2772 goto err; 2773 } 2774 2775 mvxpe_root_num = node->sysctl_num; 2776 return; 2777 2778 err: 2779 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2780 } 2781 2782 STATIC int 2783 sysctl_read_mib(SYSCTLFN_ARGS) 2784 { 2785 struct mvxpe_sysctl_mib *arg; 2786 struct mvxpe_softc *sc; 2787 struct sysctlnode node; 2788 uint64_t val; 2789 int err; 2790 2791 node = *rnode; 2792 arg = (struct mvxpe_sysctl_mib *)rnode->sysctl_data; 2793 if (arg == NULL) 2794 return EINVAL; 2795 2796 sc = arg->sc; 2797 if (sc == NULL) 2798 return EINVAL; 2799 if (arg->index < 0 || arg->index > __arraycount(mvxpe_mib_list)) 2800 return EINVAL; 2801 2802 mvxpe_sc_lock(sc); 2803 val = arg->counter; 2804 mvxpe_sc_unlock(sc); 2805 2806 node.sysctl_data = &val; 2807 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2808 if (err) 2809 return err; 2810 if (newp) 2811 return EINVAL; 2812 2813 return 0; 2814 } 2815 2816 2817 STATIC int 2818 sysctl_clear_mib(SYSCTLFN_ARGS) 2819 { 2820 struct mvxpe_softc *sc; 2821 struct sysctlnode node; 2822 int val; 2823 int err; 2824 2825 node = *rnode; 2826 sc = (struct mvxpe_softc *)rnode->sysctl_data; 2827 if (sc == NULL) 2828 return EINVAL; 2829 2830 val = 0; 2831 node.sysctl_data = &val; 2832 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2833 if (err || newp == NULL) 2834 return err; 2835 if (val < 0 || val > 1) 2836 return EINVAL; 2837 if (val == 1) { 2838 mvxpe_sc_lock(sc); 2839 mvxpe_clear_mib(sc); 2840 mvxpe_sc_unlock(sc); 2841 } 2842 2843 return 0; 2844 } 2845 2846 STATIC int 2847 sysctl_set_queue_length(SYSCTLFN_ARGS) 2848 { 2849 struct mvxpe_sysctl_queue *arg; 2850 struct mvxpe_rx_ring *rx = NULL; 2851 struct mvxpe_tx_ring *tx = NULL; 2852 struct mvxpe_softc *sc; 2853 struct sysctlnode node; 2854 uint32_t reg; 2855 int val; 2856 int err; 2857 2858 node = *rnode; 2859 2860 arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2861 if (arg == NULL) 2862 return EINVAL; 2863 if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2864 return EINVAL; 2865 if (arg->rxtx != MVXPE_SYSCTL_RX && arg->rxtx != MVXPE_SYSCTL_TX) 2866 return EINVAL; 2867 2868 sc = arg->sc; 2869 if (sc == NULL) 2870 return EINVAL; 2871 2872 /* read queue length */ 2873 mvxpe_sc_lock(sc); 2874 switch (arg->rxtx) { 2875 case MVXPE_SYSCTL_RX: 2876 mvxpe_rx_lockq(sc, arg->queue); 2877 rx = MVXPE_RX_RING(sc, arg->queue); 2878 val = rx->rx_queue_len; 2879 mvxpe_rx_unlockq(sc, arg->queue); 2880 break; 2881 case MVXPE_SYSCTL_TX: 2882 mvxpe_tx_lockq(sc, arg->queue); 2883 tx = MVXPE_TX_RING(sc, arg->queue); 2884 val = tx->tx_queue_len; 2885 mvxpe_tx_unlockq(sc, arg->queue); 2886 break; 2887 } 2888 2889 node.sysctl_data = &val; 2890 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2891 if (err || newp == NULL) { 2892 mvxpe_sc_unlock(sc); 2893 return err; 2894 } 2895 2896 /* update queue length */ 2897 if (val < 8 || val > MVXPE_RX_RING_CNT) { 2898 mvxpe_sc_unlock(sc); 2899 return EINVAL; 2900 } 2901 switch (arg->rxtx) { 2902 case MVXPE_SYSCTL_RX: 2903 mvxpe_rx_lockq(sc, arg->queue); 2904 rx->rx_queue_len = val; 2905 rx->rx_queue_th_received = 2906 rx->rx_queue_len / MVXPE_RXTH_RATIO; 2907 rx->rx_queue_th_free = 2908 rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 2909 2910 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 2911 reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 2912 MVXPE_WRITE(sc, MVXPE_PRXDQTH(arg->queue), reg); 2913 2914 mvxpe_rx_unlockq(sc, arg->queue); 2915 break; 2916 case MVXPE_SYSCTL_TX: 2917 mvxpe_tx_lockq(sc, arg->queue); 2918 tx->tx_queue_len = val; 2919 tx->tx_queue_th_free = 2920 tx->tx_queue_len / MVXPE_TXTH_RATIO; 2921 2922 reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 2923 reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 2924 MVXPE_WRITE(sc, MVXPE_PTXDQS(arg->queue), reg); 2925 2926 mvxpe_tx_unlockq(sc, arg->queue); 2927 break; 2928 } 2929 mvxpe_sc_unlock(sc); 2930 2931 return 0; 2932 } 2933 2934 STATIC int 2935 sysctl_set_queue_rxthtime(SYSCTLFN_ARGS) 2936 { 2937 struct mvxpe_sysctl_queue *arg; 2938 struct mvxpe_rx_ring *rx = NULL; 2939 struct mvxpe_softc *sc; 2940 struct sysctlnode node; 2941 extern uint32_t mvTclk; 2942 uint32_t reg, time_mvtclk; 2943 int time_us; 2944 int err; 2945 2946 node = *rnode; 2947 2948 arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2949 if (arg == NULL) 2950 return EINVAL; 2951 if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2952 return EINVAL; 2953 if (arg->rxtx != MVXPE_SYSCTL_RX) 2954 return EINVAL; 2955 2956 sc = arg->sc; 2957 if (sc == NULL) 2958 return EINVAL; 2959 2960 /* read queue length */ 2961 mvxpe_sc_lock(sc); 2962 mvxpe_rx_lockq(sc, arg->queue); 2963 rx = MVXPE_RX_RING(sc, arg->queue); 2964 time_mvtclk = rx->rx_queue_th_time; 2965 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvTclk; 2966 node.sysctl_data = &time_us; 2967 DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", 2968 arg->queue, MVXPE_READ(sc, MVXPE_PRXITTH(arg->queue))); 2969 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2970 if (err || newp == NULL) { 2971 mvxpe_rx_unlockq(sc, arg->queue); 2972 mvxpe_sc_unlock(sc); 2973 return err; 2974 } 2975 2976 /* update queue length (0[sec] - 1[sec]) */ 2977 if (time_us < 0 || time_us > (1000 * 1000)) { 2978 mvxpe_rx_unlockq(sc, arg->queue); 2979 mvxpe_sc_unlock(sc); 2980 return EINVAL; 2981 } 2982 time_mvtclk = 2983 (uint64_t)mvTclk * (uint64_t)time_us / (1000ULL * 1000ULL); 2984 rx->rx_queue_th_time = time_mvtclk; 2985 reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 2986 MVXPE_WRITE(sc, MVXPE_PRXITTH(arg->queue), reg); 2987 DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", arg->queue, reg); 2988 mvxpe_rx_unlockq(sc, arg->queue); 2989 mvxpe_sc_unlock(sc); 2990 2991 return 0; 2992 } 2993 2994 2995 STATIC void 2996 sysctl_mvxpe_init(struct mvxpe_softc *sc) 2997 { 2998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2999 const struct sysctlnode *node; 3000 int mvxpe_nodenum; 3001 int mvxpe_mibnum; 3002 int mvxpe_rxqueuenum; 3003 int mvxpe_txqueuenum; 3004 int q, i; 3005 3006 /* hw.mvxpe.mvxpe[unit] */ 3007 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3008 0, CTLTYPE_NODE, ifp->if_xname, 3009 SYSCTL_DESCR("mvxpe per-controller controls"), 3010 NULL, 0, NULL, 0, 3011 CTL_HW, mvxpe_root_num, CTL_CREATE, 3012 CTL_EOL) != 0) { 3013 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3014 return; 3015 } 3016 mvxpe_nodenum = node->sysctl_num; 3017 3018 /* hw.mvxpe.mvxpe[unit].mib */ 3019 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3020 0, CTLTYPE_NODE, "mib", 3021 SYSCTL_DESCR("mvxpe per-controller MIB counters"), 3022 NULL, 0, NULL, 0, 3023 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3024 CTL_EOL) != 0) { 3025 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3026 return; 3027 } 3028 mvxpe_mibnum = node->sysctl_num; 3029 3030 /* hw.mvxpe.mvxpe[unit].rx */ 3031 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3032 0, CTLTYPE_NODE, "rx", 3033 SYSCTL_DESCR("Rx Queues"), 3034 NULL, 0, NULL, 0, 3035 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3036 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3037 return; 3038 } 3039 mvxpe_rxqueuenum = node->sysctl_num; 3040 3041 /* hw.mvxpe.mvxpe[unit].tx */ 3042 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3043 0, CTLTYPE_NODE, "tx", 3044 SYSCTL_DESCR("Tx Queues"), 3045 NULL, 0, NULL, 0, 3046 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3047 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3048 return; 3049 } 3050 mvxpe_txqueuenum = node->sysctl_num; 3051 3052 #ifdef MVXPE_DEBUG 3053 /* hw.mvxpe.debug */ 3054 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3055 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 3056 SYSCTL_DESCR("mvgbe device driver debug control"), 3057 NULL, 0, &mvxpe_debug, 0, 3058 CTL_HW, mvxpe_root_num, CTL_CREATE, CTL_EOL) != 0) { 3059 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3060 return; 3061 } 3062 #endif 3063 /* 3064 * MIB access 3065 */ 3066 /* hw.mvxpe.mvxpe[unit].mib.<mibs> */ 3067 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3068 const char *name = mvxpe_mib_list[i].sysctl_name; 3069 const char *desc = mvxpe_mib_list[i].desc; 3070 struct mvxpe_sysctl_mib *mib_arg = &sc->sc_sysctl_mib[i]; 3071 3072 mib_arg->sc = sc; 3073 mib_arg->index = i; 3074 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3075 CTLFLAG_READONLY, CTLTYPE_QUAD, name, desc, 3076 sysctl_read_mib, 0, (void *)mib_arg, 0, 3077 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_mibnum, 3078 CTL_CREATE, CTL_EOL) != 0) { 3079 aprint_normal_dev(sc->sc_dev, 3080 "couldn't create sysctl node\n"); 3081 break; 3082 } 3083 } 3084 3085 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 3086 struct mvxpe_sysctl_queue *rxarg = &sc->sc_sysctl_rx_queue[q]; 3087 struct mvxpe_sysctl_queue *txarg = &sc->sc_sysctl_tx_queue[q]; 3088 #define MVXPE_SYSCTL_NAME(num) "queue" # num 3089 static const char *sysctl_queue_names[] = { 3090 MVXPE_SYSCTL_NAME(0), MVXPE_SYSCTL_NAME(1), 3091 MVXPE_SYSCTL_NAME(2), MVXPE_SYSCTL_NAME(3), 3092 MVXPE_SYSCTL_NAME(4), MVXPE_SYSCTL_NAME(5), 3093 MVXPE_SYSCTL_NAME(6), MVXPE_SYSCTL_NAME(7), 3094 }; 3095 #undef MVXPE_SYSCTL_NAME 3096 #ifdef SYSCTL_INCLUDE_DESCR 3097 #define MVXPE_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3098 static const char *sysctl_queue_descrs[] = { 3099 MVXPE_SYSCTL_DESC(0), MVXPE_SYSCTL_DESC(1), 3100 MVXPE_SYSCTL_DESC(2), MVXPE_SYSCTL_DESC(3), 3101 MVXPE_SYSCTL_DESC(4), MVXPE_SYSCTL_DESC(5), 3102 MVXPE_SYSCTL_DESC(6), MVXPE_SYSCTL_DESC(7), 3103 }; 3104 #undef MVXPE_SYSCTL_DESCR 3105 #endif /* SYSCTL_INCLUDE_DESCR */ 3106 int mvxpe_curnum; 3107 3108 rxarg->sc = txarg->sc = sc; 3109 rxarg->queue = txarg->queue = q; 3110 rxarg->rxtx = MVXPE_SYSCTL_RX; 3111 txarg->rxtx = MVXPE_SYSCTL_TX; 3112 3113 /* hw.mvxpe.mvxpe[unit].rx.[queue] */ 3114 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3115 0, CTLTYPE_NODE, 3116 sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descrs[q]), 3117 NULL, 0, NULL, 0, 3118 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3119 CTL_CREATE, CTL_EOL) != 0) { 3120 aprint_normal_dev(sc->sc_dev, 3121 "couldn't create sysctl node\n"); 3122 break; 3123 } 3124 mvxpe_curnum = node->sysctl_num; 3125 3126 /* hw.mvxpe.mvxpe[unit].rx.[queue].length */ 3127 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3128 CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3129 SYSCTL_DESCR("maximum length of the queue"), 3130 sysctl_set_queue_length, 0, (void *)rxarg, 0, 3131 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3132 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3133 aprint_normal_dev(sc->sc_dev, 3134 "couldn't create sysctl node\n"); 3135 break; 3136 } 3137 3138 /* hw.mvxpe.mvxpe[unit].rx.[queue].threshold_timer_us */ 3139 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3140 CTLFLAG_READWRITE, CTLTYPE_INT, "threshold_timer_us", 3141 SYSCTL_DESCR("interrupt coalescing threshold timer [us]"), 3142 sysctl_set_queue_rxthtime, 0, (void *)rxarg, 0, 3143 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3144 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3145 aprint_normal_dev(sc->sc_dev, 3146 "couldn't create sysctl node\n"); 3147 break; 3148 } 3149 3150 /* hw.mvxpe.mvxpe[unit].tx.[queue] */ 3151 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3152 0, CTLTYPE_NODE, 3153 sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descs[q]), 3154 NULL, 0, NULL, 0, 3155 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3156 CTL_CREATE, CTL_EOL) != 0) { 3157 aprint_normal_dev(sc->sc_dev, 3158 "couldn't create sysctl node\n"); 3159 break; 3160 } 3161 mvxpe_curnum = node->sysctl_num; 3162 3163 /* hw.mvxpe.mvxpe[unit].tx.length[queue] */ 3164 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3165 CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3166 SYSCTL_DESCR("maximum length of the queue"), 3167 sysctl_set_queue_length, 0, (void *)txarg, 0, 3168 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3169 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3170 aprint_normal_dev(sc->sc_dev, 3171 "couldn't create sysctl node\n"); 3172 break; 3173 } 3174 } 3175 3176 /* hw.mvxpe.mvxpe[unit].clear_mib */ 3177 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3178 CTLFLAG_READWRITE, CTLTYPE_INT, "clear_mib", 3179 SYSCTL_DESCR("mvgbe device driver debug control"), 3180 sysctl_clear_mib, 0, (void *)sc, 0, 3181 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3182 CTL_EOL) != 0) { 3183 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3184 return; 3185 } 3186 3187 } 3188 3189 /* 3190 * MIB 3191 */ 3192 STATIC void 3193 mvxpe_clear_mib(struct mvxpe_softc *sc) 3194 { 3195 int i; 3196 3197 KASSERT_SC_MTX(sc); 3198 3199 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3200 if (mvxpe_mib_list[i].reg64) 3201 MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum + 4)); 3202 MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3203 sc->sc_sysctl_mib[i].counter = 0; 3204 } 3205 } 3206 3207 STATIC void 3208 mvxpe_update_mib(struct mvxpe_softc *sc) 3209 { 3210 int i; 3211 3212 KASSERT_SC_MTX(sc); 3213 3214 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3215 uint32_t val_hi; 3216 uint32_t val_lo; 3217 3218 if (mvxpe_mib_list[i].reg64) { 3219 /* XXX: implement bus_space_read_8() */ 3220 val_lo = MVXPE_READ_MIB(sc, 3221 (mvxpe_mib_list[i].regnum + 4)); 3222 val_hi = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3223 } 3224 else { 3225 val_lo = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3226 val_hi = 0; 3227 } 3228 3229 if ((val_lo | val_hi) == 0) 3230 continue; 3231 3232 sc->sc_sysctl_mib[i].counter += 3233 ((uint64_t)val_hi << 32) | (uint64_t)val_lo; 3234 } 3235 } 3236 3237 /* 3238 * for Debug 3239 */ 3240 STATIC void 3241 mvxpe_dump_txdesc(struct mvxpe_tx_desc *desc, int idx) 3242 { 3243 #define DESC_PRINT(X) \ 3244 if (X) \ 3245 printf("txdesc[%d]." #X "=%#x\n", idx, X); 3246 3247 DESC_PRINT(desc->command); 3248 DESC_PRINT(desc->l4ichk); 3249 DESC_PRINT(desc->bytecnt); 3250 DESC_PRINT(desc->bufptr); 3251 DESC_PRINT(desc->flags); 3252 #undef DESC_PRINT 3253 } 3254 3255 STATIC void 3256 mvxpe_dump_rxdesc(struct mvxpe_rx_desc *desc, int idx) 3257 { 3258 #define DESC_PRINT(X) \ 3259 if (X) \ 3260 printf("rxdesc[%d]." #X "=%#x\n", idx, X); 3261 3262 DESC_PRINT(desc->status); 3263 DESC_PRINT(desc->bytecnt); 3264 DESC_PRINT(desc->bufptr); 3265 DESC_PRINT(desc->l4chk); 3266 #undef DESC_PRINT 3267 } 3268
Indexes created Tue Sep 30 20:09:53 GMT 2025