if_mvxpevar.h revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: if_mvxpevar.h,v 1.2.2.2 2015/06/06 14:40:08 skrll Exp $ */ 2 1.2.2.2 skrll /* 3 1.2.2.2 skrll * Copyright (c) 2015 Internet Initiative Japan Inc. 4 1.2.2.2 skrll * All rights reserved. 5 1.2.2.2 skrll * 6 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll * modification, are permitted provided that the following conditions 8 1.2.2.2 skrll * are met: 9 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.2.2.2 skrll * 15 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.2.2.2 skrll * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.2.2.2 skrll * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.2.2.2 skrll * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.2.2.2 skrll * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.2.2.2 skrll * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.2.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.2.2.2 skrll * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.2.2.2 skrll * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.2.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 26 1.2.2.2 skrll */ 27 1.2.2.2 skrll #ifndef _IF_MVXPEVAR_H_ 28 1.2.2.2 skrll #define _IF_MVXPEVAR_H_ 29 1.2.2.2 skrll #include <net/if.h> 30 1.2.2.2 skrll #include <dev/marvell/mvxpbmvar.h> 31 1.2.2.2 skrll 32 1.2.2.2 skrll /* 33 1.2.2.2 skrll * Limit of packet sizes. 34 1.2.2.2 skrll */ 35 1.2.2.2 skrll #define MVXPE_HWHEADER_SIZE 2 /* Marvell Header */ 36 1.2.2.2 skrll #define MVXPE_MRU 2000 /* Max Receive Unit */ 37 1.2.2.2 skrll #define MVXPE_MTU MVXPE_MRU /* Max Transmit Unit */ 38 1.2.2.2 skrll 39 1.2.2.2 skrll /* 40 1.2.2.2 skrll * Default limit of queue length 41 1.2.2.2 skrll * 42 1.2.2.2 skrll * queue 0 is lowest priority and queue 7 is highest priority. 43 1.2.2.2 skrll * IP packet is received on queue 7 by default. 44 1.2.2.2 skrll * 45 1.2.2.2 skrll * XXX: packet classifier is not implement yet 46 1.2.2.2 skrll */ 47 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_0 8 48 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_1 8 49 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_2 8 50 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_3 8 51 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_4 8 52 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_5 8 53 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_6 8 54 1.2.2.2 skrll #define MVXPE_RX_QUEUE_LIMIT_7 IFQ_MAXLEN 55 1.2.2.2 skrll 56 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_0 IFQ_MAXLEN 57 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_1 8 58 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_2 8 59 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_3 8 60 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_4 8 61 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_5 8 62 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_6 8 63 1.2.2.2 skrll #define MVXPE_TX_QUEUE_LIMIT_7 8 64 1.2.2.2 skrll 65 1.2.2.2 skrll /* interrupt is triggered when corossing (queuelen / RATIO) */ 66 1.2.2.2 skrll #define MVXPE_RXTH_RATIO 8 67 1.2.2.2 skrll #define MVXPE_RXTH_REFILL_RATIO 2 68 1.2.2.2 skrll #define MVXPE_TXTH_RATIO 8 69 1.2.2.2 skrll 70 1.2.2.2 skrll /* 71 1.2.2.2 skrll * Device Register access 72 1.2.2.2 skrll */ 73 1.2.2.2 skrll #define MVXPE_READ(sc, reg) \ 74 1.2.2.2 skrll bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 75 1.2.2.2 skrll #define MVXPE_WRITE(sc, reg, val) \ 76 1.2.2.2 skrll bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 77 1.2.2.2 skrll 78 1.2.2.2 skrll #define MVXPE_READ_REGION(sc, reg, val, c) \ 79 1.2.2.2 skrll bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c)) 80 1.2.2.2 skrll #define MVXPE_WRITE_REGION(sc, reg, val, c) \ 81 1.2.2.2 skrll bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c)) 82 1.2.2.2 skrll 83 1.2.2.2 skrll #define MVXPE_READ_MIB(sc, reg) \ 84 1.2.2.2 skrll bus_space_read_4((sc)->sc_iot, (sc)->sc_mibh, (reg)) 85 1.2.2.2 skrll 86 1.2.2.2 skrll #define MVXPE_IS_LINKUP(sc) \ 87 1.2.2.2 skrll (MVXPE_READ((sc), MVXPE_PSR) & MVXPE_PSR_LINKUP) 88 1.2.2.2 skrll 89 1.2.2.2 skrll #define MVXPE_IS_QUEUE_BUSY(queues, q) \ 90 1.2.2.2 skrll ((((queues) >> (q)) & 0x1)) 91 1.2.2.2 skrll 92 1.2.2.2 skrll /* 93 1.2.2.2 skrll * EEE: Lower Power Idle config 94 1.2.2.2 skrll * Default timer is duration of MTU sized frame transmission. 95 1.2.2.2 skrll * The timer can be negotiated by LLDP protocol, but we have no 96 1.2.2.2 skrll * support. 97 1.2.2.2 skrll */ 98 1.2.2.2 skrll #define MVXPE_LPI_TS (MVXPE_MRU * 8 / 1000) /* [us] */ 99 1.2.2.2 skrll #define MVXPE_LPI_TW (MVXPE_MRU * 8 / 1000) /* [us] */ 100 1.2.2.2 skrll #define MVXPE_LPI_LI (MVXPE_MRU * 8 / 1000) /* [us] */ 101 1.2.2.2 skrll 102 1.2.2.2 skrll /* 103 1.2.2.2 skrll * DMA Descriptor 104 1.2.2.2 skrll * 105 1.2.2.2 skrll * the ethernet device has 8 rx/tx DMA queues. each of queue has its own 106 1.2.2.2 skrll * decriptor list. descriptors are simply index by counter inside the device. 107 1.2.2.2 skrll */ 108 1.2.2.2 skrll #define MVXPE_TX_RING_CNT IFQ_MAXLEN 109 1.2.2.2 skrll #define MVXPE_TX_RING_MSK (MVXPE_TX_RING_CNT - 1) 110 1.2.2.2 skrll #define MVXPE_TX_RING_NEXT(x) (((x) + 1) & MVXPE_TX_RING_MSK) 111 1.2.2.2 skrll #define MVXPE_RX_RING_CNT IFQ_MAXLEN 112 1.2.2.2 skrll #define MVXPE_RX_RING_MSK (MVXPE_RX_RING_CNT - 1) 113 1.2.2.2 skrll #define MVXPE_RX_RING_NEXT(x) (((x) + 1) & MVXPE_RX_RING_MSK) 114 1.2.2.2 skrll #define MVXPE_TX_SEGLIMIT 32 115 1.2.2.2 skrll 116 1.2.2.2 skrll struct mvxpe_rx_ring { 117 1.2.2.2 skrll /* Real descriptors array. shared by RxDMA */ 118 1.2.2.2 skrll struct mvxpe_rx_desc *rx_descriptors; 119 1.2.2.2 skrll bus_dmamap_t rx_descriptors_map; 120 1.2.2.2 skrll 121 1.2.2.2 skrll /* Managment entries for each of descritors */ 122 1.2.2.2 skrll struct mvxpe_rx_handle { 123 1.2.2.2 skrll struct mvxpe_rx_desc *rxdesc_va; 124 1.2.2.2 skrll off_t rxdesc_off; /* from rx_descriptors[0] */ 125 1.2.2.2 skrll struct mvxpbm_chunk *chunk; 126 1.2.2.2 skrll } rx_handle[MVXPE_RX_RING_CNT]; 127 1.2.2.2 skrll 128 1.2.2.2 skrll /* locks */ 129 1.2.2.2 skrll kmutex_t rx_ring_mtx; 130 1.2.2.2 skrll 131 1.2.2.2 skrll /* Index */ 132 1.2.2.2 skrll int rx_dma; 133 1.2.2.2 skrll int rx_cpu; 134 1.2.2.2 skrll 135 1.2.2.2 skrll /* Limit */ 136 1.2.2.2 skrll int rx_queue_len; 137 1.2.2.2 skrll int rx_queue_th_received; 138 1.2.2.2 skrll int rx_queue_th_free; 139 1.2.2.2 skrll int rx_queue_th_time; /* [Tclk] */ 140 1.2.2.2 skrll }; 141 1.2.2.2 skrll 142 1.2.2.2 skrll struct mvxpe_tx_ring { 143 1.2.2.2 skrll /* Real descriptors array. shared by TxDMA */ 144 1.2.2.2 skrll struct mvxpe_tx_desc *tx_descriptors; 145 1.2.2.2 skrll bus_dmamap_t tx_descriptors_map; 146 1.2.2.2 skrll 147 1.2.2.2 skrll /* Managment entries for each of descritors */ 148 1.2.2.2 skrll struct mvxpe_tx_handle { 149 1.2.2.2 skrll struct mvxpe_tx_desc *txdesc_va; 150 1.2.2.2 skrll off_t txdesc_off; /* from tx_descriptors[0] */ 151 1.2.2.2 skrll struct mbuf *txdesc_mbuf; 152 1.2.2.2 skrll bus_dmamap_t txdesc_mbuf_map; 153 1.2.2.2 skrll } tx_handle[MVXPE_TX_RING_CNT]; 154 1.2.2.2 skrll 155 1.2.2.2 skrll /* locks */ 156 1.2.2.2 skrll kmutex_t tx_ring_mtx; 157 1.2.2.2 skrll 158 1.2.2.2 skrll /* Index */ 159 1.2.2.2 skrll int tx_used; 160 1.2.2.2 skrll int tx_dma; 161 1.2.2.2 skrll int tx_cpu; 162 1.2.2.2 skrll 163 1.2.2.2 skrll /* Limit */ 164 1.2.2.2 skrll int tx_queue_len; 165 1.2.2.2 skrll int tx_queue_th_free; 166 1.2.2.2 skrll }; 167 1.2.2.2 skrll 168 1.2.2.2 skrll static inline int 169 1.2.2.2 skrll tx_counter_adv(int ctr, int n) 170 1.2.2.2 skrll { 171 1.2.2.2 skrll /* XXX: lock or atomic */ 172 1.2.2.2 skrll ctr += n; 173 1.2.2.2 skrll while (ctr >= MVXPE_TX_RING_CNT) 174 1.2.2.2 skrll ctr -= MVXPE_TX_RING_CNT; 175 1.2.2.2 skrll 176 1.2.2.2 skrll return ctr; 177 1.2.2.2 skrll } 178 1.2.2.2 skrll 179 1.2.2.2 skrll static inline int 180 1.2.2.2 skrll rx_counter_adv(int ctr, int n) 181 1.2.2.2 skrll { 182 1.2.2.2 skrll /* XXX: lock or atomic */ 183 1.2.2.2 skrll ctr += n; 184 1.2.2.2 skrll while (ctr >= MVXPE_TX_RING_CNT) 185 1.2.2.2 skrll ctr -= MVXPE_TX_RING_CNT; 186 1.2.2.2 skrll 187 1.2.2.2 skrll return ctr; 188 1.2.2.2 skrll } 189 1.2.2.2 skrll 190 1.2.2.2 skrll /* 191 1.2.2.2 skrll * Timeout control 192 1.2.2.2 skrll */ 193 1.2.2.2 skrll #define MVXPE_PHY_TIMEOUT 10000 /* msec */ 194 1.2.2.2 skrll #define RX_DISABLE_TIMEOUT 0x1000000 /* times */ 195 1.2.2.2 skrll #define TX_DISABLE_TIMEOUT 0x1000000 /* times */ 196 1.2.2.2 skrll #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 /* times */ 197 1.2.2.2 skrll 198 1.2.2.2 skrll /* 199 1.2.2.2 skrll * Event counter 200 1.2.2.2 skrll */ 201 1.2.2.2 skrll #ifdef MVXPE_EVENT_COUNTERS 202 1.2.2.2 skrll #define MVXPE_EVCNT_INCR(ev) (ev)->ev_count++ 203 1.2.2.2 skrll #define MVXPE_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 204 1.2.2.2 skrll #else 205 1.2.2.2 skrll #define MVXPE_EVCNT_INCR(ev) /* nothing */ 206 1.2.2.2 skrll #define MVXPE_EVCNT_ADD(ev, val) /* nothing */ 207 1.2.2.2 skrll #endif 208 1.2.2.2 skrll struct mvxpe_evcnt { 209 1.2.2.2 skrll /* 210 1.2.2.2 skrll * Master Interrupt Handler 211 1.2.2.2 skrll */ 212 1.2.2.2 skrll struct evcnt ev_i_rxtxth; 213 1.2.2.2 skrll struct evcnt ev_i_rxtx; 214 1.2.2.2 skrll struct evcnt ev_i_misc; 215 1.2.2.2 skrll 216 1.2.2.2 skrll /* 217 1.2.2.2 skrll * RXTXTH Interrupt 218 1.2.2.2 skrll */ 219 1.2.2.2 skrll struct evcnt ev_rxtxth_txerr; 220 1.2.2.2 skrll 221 1.2.2.2 skrll /* 222 1.2.2.2 skrll * MISC Interrupt 223 1.2.2.2 skrll */ 224 1.2.2.2 skrll struct evcnt ev_misc_phystatuschng; 225 1.2.2.2 skrll struct evcnt ev_misc_linkchange; 226 1.2.2.2 skrll struct evcnt ev_misc_iae; 227 1.2.2.2 skrll struct evcnt ev_misc_rxoverrun; 228 1.2.2.2 skrll struct evcnt ev_misc_rxcrc; 229 1.2.2.2 skrll struct evcnt ev_misc_rxlargepacket; 230 1.2.2.2 skrll struct evcnt ev_misc_txunderrun; 231 1.2.2.2 skrll struct evcnt ev_misc_prbserr; 232 1.2.2.2 skrll struct evcnt ev_misc_srse; 233 1.2.2.2 skrll struct evcnt ev_misc_txreq; 234 1.2.2.2 skrll 235 1.2.2.2 skrll /* 236 1.2.2.2 skrll * RxTx Interrupt 237 1.2.2.2 skrll */ 238 1.2.2.2 skrll struct evcnt ev_rxtx_rreq; 239 1.2.2.2 skrll struct evcnt ev_rxtx_rpq; 240 1.2.2.2 skrll struct evcnt ev_rxtx_tbrq; 241 1.2.2.2 skrll struct evcnt ev_rxtx_rxtxth; 242 1.2.2.2 skrll struct evcnt ev_rxtx_txerr; 243 1.2.2.2 skrll struct evcnt ev_rxtx_misc; 244 1.2.2.2 skrll 245 1.2.2.2 skrll /* 246 1.2.2.2 skrll * Link 247 1.2.2.2 skrll */ 248 1.2.2.2 skrll struct evcnt ev_link_up; 249 1.2.2.2 skrll struct evcnt ev_link_down; 250 1.2.2.2 skrll 251 1.2.2.2 skrll /* 252 1.2.2.2 skrll * Rx Descriptor 253 1.2.2.2 skrll */ 254 1.2.2.2 skrll struct evcnt ev_rxd_ce; 255 1.2.2.2 skrll struct evcnt ev_rxd_or; 256 1.2.2.2 skrll struct evcnt ev_rxd_mf; 257 1.2.2.2 skrll struct evcnt ev_rxd_re; 258 1.2.2.2 skrll struct evcnt ev_rxd_scat; 259 1.2.2.2 skrll 260 1.2.2.2 skrll /* 261 1.2.2.2 skrll * Tx Descriptor 262 1.2.2.2 skrll */ 263 1.2.2.2 skrll struct evcnt ev_txd_lc; 264 1.2.2.2 skrll struct evcnt ev_txd_ur; 265 1.2.2.2 skrll struct evcnt ev_txd_rl; 266 1.2.2.2 skrll struct evcnt ev_txd_oth; 267 1.2.2.2 skrll 268 1.2.2.2 skrll /* 269 1.2.2.2 skrll * Status Registers 270 1.2.2.2 skrll */ 271 1.2.2.2 skrll struct evcnt ev_reg_pdfc; /* Rx Port Discard Frame Counter */ 272 1.2.2.2 skrll struct evcnt ev_reg_pofc; /* Rx Port Overrun Frame Counter */ 273 1.2.2.2 skrll struct evcnt ev_reg_txbadfcs; /* Tx BAD FCS Counter */ 274 1.2.2.2 skrll struct evcnt ev_reg_txdropped; /* Tx Dropped Counter */ 275 1.2.2.2 skrll struct evcnt ev_reg_lpic; 276 1.2.2.2 skrll 277 1.2.2.2 skrll 278 1.2.2.2 skrll /* Device Driver Errors */ 279 1.2.2.2 skrll struct evcnt ev_drv_wdogsoft; 280 1.2.2.2 skrll struct evcnt ev_drv_txerr; 281 1.2.2.2 skrll struct evcnt ev_drv_rxq[MVXPE_QUEUE_SIZE]; 282 1.2.2.2 skrll struct evcnt ev_drv_rxqe[MVXPE_QUEUE_SIZE]; 283 1.2.2.2 skrll struct evcnt ev_drv_txq[MVXPE_QUEUE_SIZE]; 284 1.2.2.2 skrll struct evcnt ev_drv_txqe[MVXPE_QUEUE_SIZE]; 285 1.2.2.2 skrll }; 286 1.2.2.2 skrll 287 1.2.2.2 skrll /* 288 1.2.2.2 skrll * Debug 289 1.2.2.2 skrll */ 290 1.2.2.2 skrll #ifdef MVXPE_DEBUG 291 1.2.2.2 skrll #define DPRINTF(fmt, ...) \ 292 1.2.2.2 skrll do { \ 293 1.2.2.2 skrll if (mvxpe_debug >= 1) { \ 294 1.2.2.2 skrll printf("%s: ", __func__); \ 295 1.2.2.2 skrll printf((fmt), ##__VA_ARGS__); \ 296 1.2.2.2 skrll } \ 297 1.2.2.2 skrll } while (/*CONSTCOND*/0) 298 1.2.2.2 skrll #define DPRINTFN(level , fmt, ...) \ 299 1.2.2.2 skrll do { \ 300 1.2.2.2 skrll if (mvxpe_debug >= (level)) { \ 301 1.2.2.2 skrll printf("%s: ", __func__); \ 302 1.2.2.2 skrll printf((fmt), ##__VA_ARGS__); \ 303 1.2.2.2 skrll } \ 304 1.2.2.2 skrll } while (/*CONSTCOND*/0) 305 1.2.2.2 skrll #define DPRINTDEV(dev, level, fmt, ...) \ 306 1.2.2.2 skrll do { \ 307 1.2.2.2 skrll if (mvxpe_debug >= (level)) { \ 308 1.2.2.2 skrll device_printf((dev), \ 309 1.2.2.2 skrll "%s: "fmt , __func__, ##__VA_ARGS__); \ 310 1.2.2.2 skrll } \ 311 1.2.2.2 skrll } while (/*CONSTCOND*/0) 312 1.2.2.2 skrll #define DPRINTSC(sc, level, fmt, ...) \ 313 1.2.2.2 skrll do { \ 314 1.2.2.2 skrll device_t dev = (sc)->sc_dev; \ 315 1.2.2.2 skrll if (mvxpe_debug >= (level)) { \ 316 1.2.2.2 skrll device_printf(dev, \ 317 1.2.2.2 skrll "%s: " fmt, __func__, ##__VA_ARGS__); \ 318 1.2.2.2 skrll } \ 319 1.2.2.2 skrll } while (/*CONSTCOND*/0) 320 1.2.2.2 skrll #define DPRINTIFNET(ifp, level, fmt, ...) \ 321 1.2.2.2 skrll do { \ 322 1.2.2.2 skrll const char *xname = (ifp)->if_xname; \ 323 1.2.2.2 skrll if (mvxpe_debug >= (level)) { \ 324 1.2.2.2 skrll printf("%s: %s: " fmt, xname, __func__, ##__VA_ARGS__);\ 325 1.2.2.2 skrll } \ 326 1.2.2.2 skrll } while (/*CONSTCOND*/0) 327 1.2.2.2 skrll #define DPRINTIFNET(ifp, level, fmt, ...) \ 328 1.2.2.2 skrll do { \ 329 1.2.2.2 skrll const char *xname = (ifp)->if_xname; \ 330 1.2.2.2 skrll if (mvxpe_debug >= (level)) { \ 331 1.2.2.2 skrll printf("%s: %s: " fmt, xname, __func__, ##__VA_ARGS__);\ 332 1.2.2.2 skrll } \ 333 1.2.2.2 skrll } while (/*CONSTCOND*/0) 334 1.2.2.2 skrll #define DPRINTPRXS(level, q) \ 335 1.2.2.2 skrll do { \ 336 1.2.2.2 skrll uint32_t _reg = MVXPE_READ(sc, MVXPE_PRXS(q)); \ 337 1.2.2.2 skrll if (mvxpe_debug >= (level)) { \ 338 1.2.2.2 skrll printf("PRXS(queue %d) %#x: Occupied %d, NoOccupied %d.\n", \ 339 1.2.2.2 skrll q, _reg, MVXPE_PRXS_GET_ODC(_reg), \ 340 1.2.2.2 skrll MVXPE_PRXS_GET_NODC(_reg)); \ 341 1.2.2.2 skrll } \ 342 1.2.2.2 skrll } while (/*CONSTCOND*/0) 343 1.2.2.2 skrll #else 344 1.2.2.2 skrll #define DPRINTF(fmt, ...) 345 1.2.2.2 skrll #define DPRINTFN(level, fmt, ...) 346 1.2.2.2 skrll #define DPRINTDEV(dev, level, fmt, ...) 347 1.2.2.2 skrll #define DPRINTSC(sc, level, fmt, ...) 348 1.2.2.2 skrll #define DPRINTIFNET(ifp, level, fmt, ...) 349 1.2.2.2 skrll #define DPRINTPRXS(level, reg) 350 1.2.2.2 skrll #endif 351 1.2.2.2 skrll 352 1.2.2.2 skrll #define KASSERT_SC_MTX(sc) \ 353 1.2.2.2 skrll KASSERT(mutex_owned(&(sc)->sc_mtx)) 354 1.2.2.2 skrll #define KASSERT_BM_MTX(sc) \ 355 1.2.2.2 skrll KASSERT(mutex_owned(&(sc)->sc_bm.bm_mtx)) 356 1.2.2.2 skrll #define KASSERT_RX_MTX(sc, q) \ 357 1.2.2.2 skrll KASSERT(mutex_owned(&(sc)->sc_rx_ring[(q)].rx_ring_mtx)) 358 1.2.2.2 skrll #define KASSERT_TX_MTX(sc, q) \ 359 1.2.2.2 skrll KASSERT(mutex_owned(&(sc)->sc_tx_ring[(q)].tx_ring_mtx)) 360 1.2.2.2 skrll 361 1.2.2.2 skrll /* 362 1.2.2.2 skrll * Configuration parameters 363 1.2.2.2 skrll */ 364 1.2.2.2 skrll struct mvxpe_conf { 365 1.2.2.2 skrll int cf_lpi; /* EEE Low Power IDLE enable */ 366 1.2.2.2 skrll int cf_fc; /* Flow Control enable */ 367 1.2.2.2 skrll }; 368 1.2.2.2 skrll 369 1.2.2.2 skrll /* 370 1.2.2.2 skrll * sysctl(9) parameters 371 1.2.2.2 skrll */ 372 1.2.2.2 skrll struct mvxpe_softc; 373 1.2.2.2 skrll struct mvxpe_sysctl_queue { 374 1.2.2.2 skrll struct mvxpe_softc *sc; 375 1.2.2.2 skrll int rxtx; 376 1.2.2.2 skrll int queue; 377 1.2.2.2 skrll }; 378 1.2.2.2 skrll #define MVXPE_SYSCTL_RX 0 379 1.2.2.2 skrll #define MVXPE_SYSCTL_TX 1 380 1.2.2.2 skrll 381 1.2.2.2 skrll struct mvxpe_sysctl_mib { 382 1.2.2.2 skrll struct mvxpe_softc *sc; 383 1.2.2.2 skrll int index; 384 1.2.2.2 skrll uint64_t counter; 385 1.2.2.2 skrll }; 386 1.2.2.2 skrll 387 1.2.2.2 skrll /* 388 1.2.2.2 skrll * Ethernet Device main context 389 1.2.2.2 skrll */ 390 1.2.2.2 skrll struct mvxpe_softc { 391 1.2.2.2 skrll device_t sc_dev; 392 1.2.2.2 skrll int sc_port; 393 1.2.2.2 skrll uint32_t sc_version; 394 1.2.2.2 skrll 395 1.2.2.2 skrll /* 396 1.2.2.2 skrll * sc_mtx must be held by interface functions to/from 397 1.2.2.2 skrll * other frameworks. interrupt hander, sysctl hander, 398 1.2.2.2 skrll * ioctl hander, and so on. 399 1.2.2.2 skrll */ 400 1.2.2.2 skrll kmutex_t sc_mtx; 401 1.2.2.2 skrll 402 1.2.2.2 skrll /* 403 1.2.2.2 skrll * Ethernet facilities 404 1.2.2.2 skrll */ 405 1.2.2.2 skrll struct ethercom sc_ethercom; 406 1.2.2.2 skrll struct mii_data sc_mii; 407 1.2.2.2 skrll u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 408 1.2.2.2 skrll int sc_if_flags; 409 1.2.2.2 skrll int sc_wdogsoft; 410 1.2.2.2 skrll 411 1.2.2.2 skrll /* 412 1.2.2.2 skrll * Configuration Parameters 413 1.2.2.2 skrll */ 414 1.2.2.2 skrll struct mvxpe_conf sc_cf; 415 1.2.2.2 skrll 416 1.2.2.2 skrll /* 417 1.2.2.2 skrll * I/O Spaces 418 1.2.2.2 skrll */ 419 1.2.2.2 skrll bus_space_tag_t sc_iot; 420 1.2.2.2 skrll bus_space_handle_t sc_ioh; /* all registers handle */ 421 1.2.2.2 skrll bus_space_handle_t sc_mibh; /* mib counter handle */ 422 1.2.2.2 skrll 423 1.2.2.2 skrll /* 424 1.2.2.2 skrll * DMA Spaces 425 1.2.2.2 skrll */ 426 1.2.2.2 skrll bus_dma_tag_t sc_dmat; 427 1.2.2.2 skrll struct mvxpe_rx_ring sc_rx_ring[MVXPE_QUEUE_SIZE]; 428 1.2.2.2 skrll struct mvxpe_tx_ring sc_tx_ring[MVXPE_QUEUE_SIZE]; 429 1.2.2.2 skrll int sc_tx_pending; /* total number of tx pkt */ 430 1.2.2.2 skrll 431 1.2.2.2 skrll /* 432 1.2.2.2 skrll * Software Buffer Manager 433 1.2.2.2 skrll */ 434 1.2.2.2 skrll struct mvxpbm_softc *sc_bm; 435 1.2.2.2 skrll 436 1.2.2.2 skrll /* 437 1.2.2.2 skrll * Maintance clock 438 1.2.2.2 skrll */ 439 1.2.2.2 skrll callout_t sc_tick_ch; /* tick callout */ 440 1.2.2.2 skrll 441 1.2.2.2 skrll /* 442 1.2.2.2 skrll * Link State control 443 1.2.2.2 skrll */ 444 1.2.2.2 skrll uint32_t sc_linkstate; 445 1.2.2.2 skrll 446 1.2.2.2 skrll /* 447 1.2.2.2 skrll * Act as Rndom source 448 1.2.2.2 skrll */ 449 1.2.2.2 skrll krndsource_t sc_rnd_source; 450 1.2.2.2 skrll 451 1.2.2.2 skrll /* 452 1.2.2.2 skrll * Sysctl interfaces 453 1.2.2.2 skrll */ 454 1.2.2.2 skrll struct sysctllog *sc_mvxpe_clog; 455 1.2.2.2 skrll struct mvxpe_sysctl_queue sc_sysctl_rx_queue[MVXPE_QUEUE_SIZE]; 456 1.2.2.2 skrll struct mvxpe_sysctl_queue sc_sysctl_tx_queue[MVXPE_QUEUE_SIZE]; 457 1.2.2.2 skrll 458 1.2.2.2 skrll /* 459 1.2.2.2 skrll * MIB counter 460 1.2.2.2 skrll */ 461 1.2.2.2 skrll size_t sc_sysctl_mib_size; 462 1.2.2.2 skrll struct mvxpe_sysctl_mib *sc_sysctl_mib; 463 1.2.2.2 skrll 464 1.2.2.2 skrll #ifdef MVXPE_EVENT_COUNTERS 465 1.2.2.2 skrll /* 466 1.2.2.2 skrll * Event counter 467 1.2.2.2 skrll */ 468 1.2.2.2 skrll struct mvxpe_evcnt sc_ev; 469 1.2.2.2 skrll #endif 470 1.2.2.2 skrll }; 471 1.2.2.2 skrll #define MVXPE_RX_RING_MEM_VA(sc, q) \ 472 1.2.2.2 skrll ((sc)->sc_rx_ring[(q)].rx_descriptors) 473 1.2.2.2 skrll #define MVXPE_RX_RING_MEM_PA(sc, q) \ 474 1.2.2.2 skrll ((sc)->sc_rx_ring[(q)].rx_descriptors_map->dm_segs[0].ds_addr) 475 1.2.2.2 skrll #define MVXPE_RX_RING_MEM_MAP(sc, q) \ 476 1.2.2.2 skrll ((sc)->sc_rx_ring[(q)].rx_descriptors_map) 477 1.2.2.2 skrll #define MVXPE_RX_RING(sc, q) \ 478 1.2.2.2 skrll (&(sc)->sc_rx_ring[(q)]) 479 1.2.2.2 skrll #define MVXPE_RX_HANDLE(sc, q, i) \ 480 1.2.2.2 skrll (&(sc)->sc_rx_ring[(q)].rx_handle[(i)]) 481 1.2.2.2 skrll #define MVXPE_RX_DESC(sc, q, i) \ 482 1.2.2.2 skrll ((sc)->sc_rx_ring[(q)].rx_handle[(i)].rxdesc_va) 483 1.2.2.2 skrll #define MVXPE_RX_DESC_OFF(sc, q, i) \ 484 1.2.2.2 skrll ((sc)->sc_rx_ring[(q)].rx_handle[(i)].rxdesc_off) 485 1.2.2.2 skrll #define MVXPE_RX_PKTBUF(sc, q, i) \ 486 1.2.2.2 skrll ((sc)->sc_rx_ring[(q)].rx_handle[(i)].chunk) 487 1.2.2.2 skrll 488 1.2.2.2 skrll #define MVXPE_TX_RING_MEM_VA(sc, q) \ 489 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_descriptors) 490 1.2.2.2 skrll #define MVXPE_TX_RING_MEM_PA(sc, q) \ 491 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_descriptors_map->dm_segs[0].ds_addr) 492 1.2.2.2 skrll #define MVXPE_TX_RING_MEM_MAP(sc, q) \ 493 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_descriptors_map) 494 1.2.2.2 skrll #define MVXPE_TX_RING(sc, q) \ 495 1.2.2.2 skrll (&(sc)->sc_tx_ring[(q)]) 496 1.2.2.2 skrll #define MVXPE_TX_HANDLE(sc, q, i) \ 497 1.2.2.2 skrll (&(sc)->sc_tx_ring[(q)].tx_handle[(i)]) 498 1.2.2.2 skrll #define MVXPE_TX_DESC(sc, q, i) \ 499 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_va) 500 1.2.2.2 skrll #define MVXPE_TX_DESC_OFF(sc, q, i) \ 501 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_off) 502 1.2.2.2 skrll #define MVXPE_TX_MBUF(sc, q, i) \ 503 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_mbuf) 504 1.2.2.2 skrll #define MVXPE_TX_MAP(sc, q, i) \ 505 1.2.2.2 skrll ((sc)->sc_tx_ring[(q)].tx_handle[(i)].txdesc_mbuf_map) 506 1.2.2.2 skrll 507 1.2.2.2 skrll #endif /* _IF_MVXPEVAR_H_ */ 508
Indexes created Thu Oct 23 22:10:10 GMT 2025