mvpex.c revision 1.1
1 /* $NetBSD: mvpex.c,v 1.1 2010/07/13 11:16:02 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.1 2010/07/13 11:16:02 kiyohara Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/evcnt.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 43 #include <prop/proplib.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <dev/marvell/mvpexreg.h> 50 #include <dev/marvell/mvpexvar.h> 51 #include <dev/marvell/marvellreg.h> 52 #include <dev/marvell/marvellvar.h> 53 54 #include <machine/pci_machdep.h> 55 56 #include "locators.h" 57 58 59 static int mvpex_match(device_t, struct cfdata *, void *); 60 static void mvpex_attach(device_t, device_t, void *); 61 62 static int mvpex_intr(void *); 63 64 static void mvpex_init(struct mvpex_softc *); 65 #if 0 /* shall move to pchb(4)? */ 66 static void mvpex_barinit(struct mvpex_softc *); 67 static int mvpex_wininit(struct mvpex_softc *, int, int, int, int, uint32_t *, 68 uint32_t *); 69 #else 70 static void mvpex_wininit(struct mvpex_softc *); 71 #endif 72 #if NPCI > 0 73 static void mvpex_pci_config(struct mvpex_softc *, bus_space_tag_t, 74 bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t, 75 u_long, u_long, u_long, u_long, int); 76 #endif 77 78 CFATTACH_DECL_NEW(mvpex_gt, sizeof(struct mvpex_softc), 79 mvpex_match, mvpex_attach, NULL, NULL); 80 CFATTACH_DECL_NEW(mvpex_mbus, sizeof(struct mvpex_softc), 81 mvpex_match, mvpex_attach, NULL, NULL); 82 83 84 /* ARGSUSED */ 85 static int 86 mvpex_match(device_t parent, struct cfdata *match, void *aux) 87 { 88 struct marvell_attach_args *mva = aux; 89 90 switch (mva->mva_model) { 91 #if 0 92 case MARVELL_DISCOVERY_V: 93 case MARVELL_DISCOVERY_VI: 94 #endif 95 case MARVELL_ORION_1_88F1181: 96 case MARVELL_ORION_1_88F5082: 97 case MARVELL_ORION_1_88F5180N: 98 case MARVELL_ORION_1_88F5181: 99 case MARVELL_ORION_1_88F5182: 100 case MARVELL_ORION_1_88F6082: 101 case MARVELL_ORION_1_88W8660: 102 case MARVELL_ORION_2_88F1281: 103 case MARVELL_ORION_2_88F5281: 104 break; 105 106 default: 107 return 0; 108 } 109 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 110 mva->mva_irq == MVA_IRQ_DEFAULT) 111 return 0; 112 113 mva->mva_size = MVPEX_SIZE; 114 return 1; 115 } 116 117 /* ARGSUSED */ 118 static void 119 mvpex_attach(device_t parent, device_t self, void *aux) 120 { 121 struct mvpex_softc *sc = device_private(self); 122 struct marvell_attach_args *mva = aux; 123 #if NPCI > 0 124 prop_dictionary_t dict = device_properties(self); 125 prop_object_t pc, iot, memt; 126 pci_chipset_tag_t mvpex_chipset; 127 bus_space_tag_t mvpex_io_bs_tag, mvpex_mem_bs_tag; 128 uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0; 129 uint32_t cl_size; 130 int i; 131 #endif 132 133 aprint_normal(": Marvell PCI Express Interface\n"); 134 aprint_naive("\n"); 135 136 #if NPCI > 0 137 iot = prop_dictionary_get(dict, "io-bus-tag"); 138 if (iot == NULL) { 139 aprint_error_dev(self, "no io-bus-tag property\n"); 140 return; 141 } 142 KASSERT(prop_object_type(iot) == PROP_TYPE_DATA); 143 mvpex_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot)); 144 memt = prop_dictionary_get(dict, "mem-bus-tag"); 145 if (memt == NULL) { 146 aprint_error_dev(self, "no mem-bus-tag property\n"); 147 return; 148 } 149 KASSERT(prop_object_type(memt) == PROP_TYPE_DATA); 150 mvpex_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt)); 151 pc = prop_dictionary_get(dict, "pci-chipset"); 152 if (pc == NULL) { 153 aprint_error_dev(self, "no pci-chipset property\n"); 154 return; 155 } 156 KASSERT(prop_object_type(pc) == PROP_TYPE_DATA); 157 mvpex_chipset = __UNCONST(prop_data_data_nocopy(pc)); 158 #ifdef PCI_NETBSD_CONFIGURE 159 if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) { 160 aprint_error_dev(self, "no iostart property\n"); 161 return; 162 } 163 if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) { 164 aprint_error_dev(self, "no ioend property\n"); 165 return; 166 } 167 if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) { 168 aprint_error_dev(self, "no memstart property\n"); 169 return; 170 } 171 if (!prop_dictionary_get_uint64(dict, "memend", &memend)) { 172 aprint_error_dev(self, "no memend property\n"); 173 return; 174 } 175 if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) { 176 aprint_error_dev(self, "no cache-line-size property\n"); 177 return; 178 } 179 #endif 180 #endif 181 182 sc->sc_dev = self; 183 sc->sc_model = mva->mva_model; 184 sc->sc_rev = mva->mva_revision; 185 sc->sc_offset = mva->mva_offset; 186 sc->sc_iot = mva->mva_iot; 187 188 /* Map I/O registers for mvpex */ 189 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 190 mva->mva_size, &sc->sc_ioh)) { 191 aprint_error_dev(self, "can't map registers\n"); 192 return; 193 } 194 mvpex_init(sc); 195 196 /* XXX: looks seem good to specify level IPL_VM. */ 197 marvell_intr_establish(mva->mva_irq, IPL_VM, mvpex_intr, sc); 198 199 #if NPCI > 0 200 for (i = 0; i < PCI_INTERRUPT_PIN_MAX; i++) { 201 sc->sc_intrtab[i].intr_pin = PCI_INTERRUPT_PIN_A + i; 202 sc->sc_intrtab[i].intr_refcnt = 0; 203 LIST_INIT(&sc->sc_intrtab[i].intr_list); 204 } 205 206 mvpex_pci_config(sc, mvpex_io_bs_tag, mvpex_mem_bs_tag, mva->mva_dmat, 207 mvpex_chipset, iostart, ioend, memstart, memend, cl_size); 208 #endif 209 } 210 211 static int 212 mvpex_intr(void *arg) 213 { 214 struct mvpex_softc *sc = (struct mvpex_softc *)arg; 215 struct mvpex_intrhand *ih; 216 struct mvpex_intrtab *intrtab; 217 uint32_t ic, im; 218 int handled = 0, pin, rv, i, s; 219 220 for (;;) { 221 ic = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC); 222 im = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 223 ic &= im; 224 225 if (!ic) 226 break; 227 228 for (i = 0, pin = PCI_INTERRUPT_PIN_A; 229 i < PCI_INTERRUPT_PIN_MAX; pin++, i++) { 230 if ((ic & MVPEX_I_PIN(pin)) == 0) 231 continue; 232 233 intrtab = &sc->sc_intrtab[i]; 234 LIST_FOREACH(ih, &intrtab->intr_list, ih_q) { 235 s = _splraise(ih->ih_type); 236 rv = (*ih->ih_func)(ih->ih_arg); 237 splx(s); 238 if (rv) { 239 ih->ih_evcnt.ev_count++; 240 handled++; 241 } 242 } 243 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 244 ~MVPEX_I_PIN(pin)); 245 } 246 } 247 248 return handled; 249 } 250 251 252 static void 253 mvpex_init(struct mvpex_softc *sc) 254 { 255 uint32_t reg; 256 int window; 257 258 /* 259 * First implement Guideline (GL# PCI Express-2) Wrong Default Value 260 * to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 261 * and 88F5281-B0 262 */ 263 /* Write the read command */ 264 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, 0x80820000); 265 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x1b00); 266 /* Prepare new data for write */ 267 reg &= ~0x7; /* Clear bits [2:0] */ 268 reg |= 0x4; /* Set the new value */ 269 reg &= ~0x80000000; /* Set "write" command */ 270 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, reg); 271 272 for (window = 0; window < MVPEX_NWINDOW; window++) 273 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0); 274 275 #if 0 /* shall move to pchb(4)? */ 276 mvpex_barinit(sc); 277 #else 278 mvpex_wininit(sc); 279 #endif 280 281 /* Clear Interrupt Cause and Mask registers */ 282 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 0); 283 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, 0); 284 285 /* now wait 60 ns to be sure the link is valid (spec compliant) */ 286 delay(1); 287 } 288 289 #if 0 290 static int 291 mvpex_wininit(struct mvpex_softc *sc, int window, int tbegin, int tend, 292 int barmap, uint32_t *barbase, uint32_t *barsize) 293 { 294 uint32_t target, attr, base, size; 295 int targetid; 296 297 for (targetid = tbegin; targetid <= tend && window < MVPEX_NWINDOW; 298 targetid++) { 299 if (orion_target(targetid, &target, &attr, &base, &size) == -1) 300 continue; 301 if (size == 0) 302 continue; 303 304 if (base < *barbase) 305 *barbase = base; 306 *barsize += size; 307 308 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 309 MVPEX_WC_WINEN | 310 barmap | 311 MVPEX_WC_TARGET(target) | 312 MVPEX_WC_ATTR(attr) | 313 MVPEX_WC_SIZE(size)); 314 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window), 315 MVPEX_WB_BASE(base)); 316 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0); 317 window++; 318 } 319 320 return window; 321 } 322 323 /* shall move to pchb(4)? */ 324 static void 325 mvpex_barinit(struct mvpex_softc *sc) 326 { 327 const uint32_t barflag = 328 PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT; 329 uint32_t base, size; 330 int window = 0; 331 332 marvell_winparams_by_tag(device_parent(sc->sc_dev), 333 ORION_TARGETID_INTERNALREG, NULL, NULL, &base, &size); 334 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNAL, 335 barflag | (base & MVPEX_BAR0INTERNAL_MASK)); 336 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNALH, 0); 337 338 base = size = 0; 339 window = mvpex_wininit(sc, window, ORION_TARGETID_SDRAM_CS0, 340 ORION_TARGETID_SDRAM_CS3, MVPEX_WC_BARMAP_BAR1, &base, &size); 341 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1, 342 barflag | (base & MVPEX_BAR_MASK)); 343 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1H, 0); 344 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1C, 345 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN); 346 347 #if 0 348 base = size = 0; 349 if (sc->sc_model == MARVELL_ORION_1_88F1181) 350 window = mvpex_wininit(sc, window, ORION_TARGETID_FLASH_CS, 351 ORION_TARGETID_DEVICE_BOOTCS, 352 MVPEX_WC_BARMAP_BAR2, &base, &size); 353 else { 354 window = mvpex_wininit(sc, window, 355 ORION_TARGETID_DEVICE_CS0, ORION_TARGETID_DEVICE_CS2, 356 MVPEX_WC_BARMAP_BAR2, &base, &size); 357 window = mvpex_wininit(sc, window, 358 ORION_TARGETID_DEVICE_BOOTCS, ORION_TARGETID_DEVICE_BOOTCS, 359 MVPEX_WC_BARMAP_BAR2, &base, &size); 360 } 361 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2, 362 barflag | (base & MVPEX_BAR_MASK)); 363 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2H, 0); 364 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 365 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN); 366 #else 367 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 0); 368 #endif 369 } 370 #else 371 static void 372 mvpex_wininit(struct mvpex_softc *sc) 373 { 374 device_t pdev = device_parent(sc->sc_dev); 375 uint64_t base; 376 uint32_t size; 377 int target, attr, window, rv, i; 378 static struct { 379 int tag; 380 int bar; 381 } tags[] = { 382 { MARVELL_TAG_SDRAM_CS0, MVPEX_WC_BARMAP_BAR1 }, 383 { MARVELL_TAG_SDRAM_CS1, MVPEX_WC_BARMAP_BAR1 }, 384 { MARVELL_TAG_SDRAM_CS2, MVPEX_WC_BARMAP_BAR1 }, 385 { MARVELL_TAG_SDRAM_CS3, MVPEX_WC_BARMAP_BAR1 }, 386 387 { MARVELL_TAG_UNDEFINED, 0 }, 388 }; 389 390 for (window = 0, i = 0; 391 tags[i].tag != MARVELL_TAG_UNDEFINED && window < MVPEX_NWINDOW; 392 i++) { 393 rv = marvell_winparams_by_tag(pdev, tags[i].tag, 394 &target, &attr, &base, &size); 395 if (rv != 0 || size == 0) 396 continue; 397 398 if (base > 0xffffffffULL) { 399 aprint_error_dev(sc->sc_dev, 400 "tag %d address 0x%llx not support\n", 401 tags[i].tag, base); 402 continue; 403 } 404 405 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 406 MVPEX_WC_WINEN | 407 tags[i].bar | 408 MVPEX_WC_TARGET(target) | 409 MVPEX_WC_ATTR(attr) | 410 MVPEX_WC_SIZE(size)); 411 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window), 412 MVPEX_WB_BASE(base)); 413 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0); 414 window++; 415 } 416 for ( ; window < MVPEX_NWINDOW; window++) 417 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0); 418 } 419 #endif 420 421 #if NPCI > 0 422 static void 423 mvpex_pci_config(struct mvpex_softc *sc, bus_space_tag_t iot, 424 bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc, 425 u_long iostart, u_long ioend, u_long memstart, u_long memend, 426 int cacheline_size) 427 { 428 struct pcibus_attach_args pba; 429 #ifdef PCI_NETBSD_CONFIGURE 430 struct extent *ioext = NULL, *memext = NULL; 431 #endif 432 uint32_t stat; 433 434 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 435 436 #ifdef PCI_NETBSD_CONFIGURE 437 ioext = extent_create("pexio", iostart, ioend, M_DEVBUF, NULL, 0, 438 EX_NOWAIT); 439 memext = extent_create("pexmem", memstart, memend, M_DEVBUF, NULL, 0, 440 EX_NOWAIT); 441 if (ioext != NULL && memext != NULL) 442 pci_configure_bus(pc, ioext, memext, NULL, 443 MVPEX_STAT_PEXBUSNUM(stat), cacheline_size); 444 else 445 aprint_error_dev(sc->sc_dev, "can't create extent %s%s%s\n", 446 ioext == NULL ? "io" : "", 447 ioext == NULL && memext == NULL ? " and " : "", 448 memext == NULL ? "mem" : ""); 449 if (ioext != NULL) 450 extent_destroy(ioext); 451 if (memext != NULL) 452 extent_destroy(memext); 453 #endif 454 455 pba.pba_iot = iot; 456 pba.pba_memt = memt; 457 pba.pba_dmat = dmat; 458 pba.pba_dmat64 = NULL; 459 pba.pba_pc = pc; 460 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 461 pba.pba_bus = MVPEX_STAT_PEXBUSNUM(stat); 462 pba.pba_bridgetag = NULL; 463 config_found_ia(sc->sc_dev, "pcibus", &pba, NULL); 464 } 465 466 467 /* 468 * PCI-Express CPU dependent code 469 */ 470 471 /* ARGSUSED */ 472 void 473 mvpex_attach_hook(device_t parent, device_t self, 474 struct pcibus_attach_args *pba) 475 { 476 477 /* Nothing */ 478 } 479 480 /* 481 * Bit map for configuration register: 482 * [31] ConfigEn 483 * [30:28] Reserved 484 * [27:24] ExtRegNum (PCI Express only) 485 * [23:16] BusNum 486 * [15:11] DevNum 487 * [10: 8] FunctNum 488 * [ 7: 2] RegNum 489 * [ 1: 0] reserved 490 */ 491 492 /* ARGSUSED */ 493 int 494 mvpex_bus_maxdevs(void *v, int busno) 495 { 496 497 return 32; /* 32 device/bus */ 498 } 499 500 /* ARGSUSED */ 501 pcitag_t 502 mvpex_make_tag(void *v, int bus, int dev, int func) 503 { 504 505 return (bus << 16) | (dev << 11) | (func << 8); 506 } 507 508 /* ARGSUSED */ 509 void 510 mvpex_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 511 { 512 513 if (bp != NULL) 514 *bp = (tag >> 16) & 0xff; 515 if (dp != NULL) 516 *dp = (tag >> 11) & 0x1f; 517 if (fp != NULL) 518 *fp = (tag >> 8) & 0x07; 519 } 520 521 pcireg_t 522 mvpex_conf_read(void *v, pcitag_t tag, int reg) 523 { 524 struct mvpex_softc *sc = v; 525 pcireg_t addr, pci_cs; 526 uint32_t stat; 527 int bus, dev, func, pexbus, pexdev; 528 529 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 530 531 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 532 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 533 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 534 if (bus != pexbus || dev != pexdev) 535 if (stat & MVPEX_STAT_DLDOWN) 536 return -1; 537 538 if (bus == pexbus) { 539 if (pexdev == 0) { 540 if (dev != 1 && dev != pexdev) 541 return -1; 542 } else { 543 if (dev != 0 && dev != pexdev) 544 return -1; 545 } 546 if (func != 0) 547 return -1; 548 } 549 550 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 551 552 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 553 addr | MVPEX_CA_CONFIGEN); 554 if ((addr | MVPEX_CA_CONFIGEN) != 555 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 556 return -1; 557 558 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 559 PCI_COMMAND_STATUS_REG); 560 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 561 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 562 563 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 564 } 565 566 void 567 mvpex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 568 { 569 struct mvpex_softc *sc = v; 570 pcireg_t addr; 571 uint32_t stat; 572 int bus, dev, func, pexbus, pexdev; 573 574 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 575 576 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 577 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 578 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 579 if (bus != pexbus || dev != pexdev) 580 if (stat & MVPEX_STAT_DLDOWN) 581 return; 582 583 if (bus == pexbus) { 584 if (pexdev == 0) { 585 if (dev != 1 && dev != pexdev) 586 return; 587 } else { 588 if (dev != 0 && dev != pexdev) 589 return; 590 } 591 if (func != 0) 592 return; 593 } 594 595 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 596 597 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 598 addr | MVPEX_CA_CONFIGEN); 599 if ((addr | MVPEX_CA_CONFIGEN) != 600 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 601 return; 602 603 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD, data); 604 } 605 606 /* ARGSUSED */ 607 int 608 mvpex_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id) 609 { 610 611 if (bus == 0 && dev == 0) /* don't configure GT */ 612 return 0; 613 614 return PCI_CONF_DEFAULT; 615 } 616 617 int 618 mvpex_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 619 { 620 621 switch (pa->pa_intrpin) { 622 case PCI_INTERRUPT_PIN_A: 623 case PCI_INTERRUPT_PIN_B: 624 case PCI_INTERRUPT_PIN_C: 625 case PCI_INTERRUPT_PIN_D: 626 *ihp = pa->pa_intrpin; 627 return 0; 628 } 629 return -1; 630 } 631 632 /* ARGSUSED */ 633 const char * 634 mvpex_intr_string(void *v, pci_intr_handle_t pin) 635 { 636 static char intrstr[32]; 637 638 switch (pin) { 639 case PCI_INTERRUPT_PIN_A: 640 case PCI_INTERRUPT_PIN_B: 641 case PCI_INTERRUPT_PIN_C: 642 case PCI_INTERRUPT_PIN_D: 643 break; 644 645 default: 646 return NULL; 647 } 648 snprintf(intrstr, sizeof(intrstr), "interrupt pin INT%c#", 649 (char)('A' - 1 + pin)); 650 651 return intrstr; 652 } 653 654 /* ARGSUSED */ 655 const struct evcnt * 656 mvpex_intr_evcnt(void *v, pci_intr_handle_t pin) 657 { 658 659 return NULL; 660 } 661 662 /* 663 * XXXX: Shall these functions use mutex(9) instead of spl(9)? 664 * MV78200 and MV64360 and after supports SMP. 665 */ 666 667 /* ARGSUSED */ 668 void * 669 mvpex_intr_establish(void *v, pci_intr_handle_t pin, int ipl, 670 int (*intrhand)(void *), void *intrarg) 671 { 672 struct mvpex_softc *sc = (struct mvpex_softc *)v; 673 struct mvpex_intrtab *intrtab; 674 struct mvpex_intrhand *pexih; 675 uint32_t mask; 676 int ih = pin - 1, s; 677 678 intrtab = &sc->sc_intrtab[ih]; 679 680 KASSERT(pin == intrtab->intr_pin); 681 682 pexih = malloc(sizeof(*pexih), M_DEVBUF, M_NOWAIT); 683 if (pexih == NULL) 684 return NULL; 685 686 pexih->ih_func = intrhand; 687 pexih->ih_arg = intrarg; 688 pexih->ih_type = ipl; 689 pexih->ih_intrtab = intrtab; 690 evcnt_attach_dynamic(&pexih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "mvpex", 691 mvpex_intr_string(v, pin)); 692 693 s = splhigh(); 694 695 /* First, link it into the tables. */ 696 LIST_INSERT_HEAD(&intrtab->intr_list, pexih, ih_q); 697 698 /* Now enable it. */ 699 if (intrtab->intr_refcnt++ == 0) { 700 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 701 mask |= MVPEX_I_PIN(intrtab->intr_pin); 702 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask); 703 } 704 705 splx(s); 706 707 return pexih; 708 } 709 710 void 711 mvpex_intr_disestablish(void *v, void *ih) 712 { 713 struct mvpex_softc *sc = (struct mvpex_softc *)v; 714 struct mvpex_intrtab *intrtab; 715 struct mvpex_intrhand *pexih = ih; 716 uint32_t mask; 717 int s; 718 719 intrtab = pexih->ih_intrtab; 720 721 s = splhigh(); 722 723 /* 724 * First, remove it from the table. 725 */ 726 LIST_REMOVE(pexih, ih_q); 727 728 /* Now, disable it, if there is nothing remaining on the list. */ 729 if (intrtab->intr_refcnt-- == 1) { 730 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 731 mask &= ~MVPEX_I_PIN(intrtab->intr_pin); 732 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask); 733 } 734 splx(s); 735 736 free(pexih, M_DEVBUF); 737 } 738 #endif /* NPCI > 0 */ 739
Indexes created Fri Sep 26 08:10:20 GMT 2025