mvpex.c revision 1.14
1 /* $NetBSD: mvpex.c,v 1.14 2015/07/28 01:57:55 knakahara Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.14 2015/07/28 01:57:55 knakahara Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/evcnt.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 43 #include <prop/proplib.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pciconf.h> 48 49 #include <dev/marvell/mvpexreg.h> 50 #include <dev/marvell/mvpexvar.h> 51 #include <dev/marvell/marvellreg.h> 52 #include <dev/marvell/marvellvar.h> 53 54 #include <machine/pci_machdep.h> 55 56 #include "locators.h" 57 58 59 static int mvpex_match(device_t, struct cfdata *, void *); 60 static void mvpex_attach(device_t, device_t, void *); 61 62 static int mvpex_intr(void *); 63 64 static void mvpex_init(struct mvpex_softc *, enum marvell_tags *); 65 #if 0 /* shall move to pchb(4)? */ 66 static void mvpex_barinit(struct mvpex_softc *); 67 static int mvpex_wininit(struct mvpex_softc *, int, int, int, int, uint32_t *, 68 uint32_t *); 69 #else 70 static void mvpex_wininit(struct mvpex_softc *, enum marvell_tags *); 71 #endif 72 #if NPCI > 0 73 static void mvpex_pci_config(struct mvpex_softc *, bus_space_tag_t, 74 bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t, 75 u_long, u_long, u_long, u_long, int); 76 #endif 77 78 enum marvell_tags *mvpex_bar2_tags; 79 80 CFATTACH_DECL_NEW(mvpex_gt, sizeof(struct mvpex_softc), 81 mvpex_match, mvpex_attach, NULL, NULL); 82 CFATTACH_DECL_NEW(mvpex_mbus, sizeof(struct mvpex_softc), 83 mvpex_match, mvpex_attach, NULL, NULL); 84 85 86 /* ARGSUSED */ 87 static int 88 mvpex_match(device_t parent, struct cfdata *match, void *aux) 89 { 90 struct marvell_attach_args *mva = aux; 91 92 if (strcmp(mva->mva_name, match->cf_name) != 0) 93 return 0; 94 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 95 mva->mva_irq == MVA_IRQ_DEFAULT) 96 return 0; 97 98 mva->mva_size = MVPEX_SIZE; 99 return 1; 100 } 101 102 /* ARGSUSED */ 103 static void 104 mvpex_attach(device_t parent, device_t self, void *aux) 105 { 106 struct mvpex_softc *sc = device_private(self); 107 struct marvell_attach_args *mva = aux; 108 #if NPCI > 0 109 prop_dictionary_t dict = device_properties(self); 110 prop_object_t pc, iot, memt; 111 pci_chipset_tag_t mvpex_chipset; 112 bus_space_tag_t mvpex_io_bs_tag, mvpex_mem_bs_tag; 113 uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0; 114 uint32_t cl_size = 0; 115 int i; 116 #endif 117 118 aprint_normal(": Marvell PCI Express Interface\n"); 119 aprint_naive("\n"); 120 121 #if NPCI > 0 122 iot = prop_dictionary_get(dict, "io-bus-tag"); 123 if (iot == NULL) { 124 aprint_error_dev(self, "no io-bus-tag property\n"); 125 return; 126 } 127 KASSERT(prop_object_type(iot) == PROP_TYPE_DATA); 128 mvpex_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot)); 129 memt = prop_dictionary_get(dict, "mem-bus-tag"); 130 if (memt == NULL) { 131 aprint_error_dev(self, "no mem-bus-tag property\n"); 132 return; 133 } 134 KASSERT(prop_object_type(memt) == PROP_TYPE_DATA); 135 mvpex_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt)); 136 pc = prop_dictionary_get(dict, "pci-chipset"); 137 if (pc == NULL) { 138 aprint_error_dev(self, "no pci-chipset property\n"); 139 return; 140 } 141 KASSERT(prop_object_type(pc) == PROP_TYPE_DATA); 142 mvpex_chipset = __UNCONST(prop_data_data_nocopy(pc)); 143 #ifdef PCI_NETBSD_CONFIGURE 144 if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) { 145 aprint_error_dev(self, "no iostart property\n"); 146 return; 147 } 148 if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) { 149 aprint_error_dev(self, "no ioend property\n"); 150 return; 151 } 152 if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) { 153 aprint_error_dev(self, "no memstart property\n"); 154 return; 155 } 156 if (!prop_dictionary_get_uint64(dict, "memend", &memend)) { 157 aprint_error_dev(self, "no memend property\n"); 158 return; 159 } 160 if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) { 161 aprint_error_dev(self, "no cache-line-size property\n"); 162 return; 163 } 164 #endif 165 #endif 166 167 sc->sc_dev = self; 168 sc->sc_model = mva->mva_model; 169 sc->sc_rev = mva->mva_revision; 170 sc->sc_offset = mva->mva_offset; 171 sc->sc_iot = mva->mva_iot; 172 173 /* Map I/O registers for mvpex */ 174 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 175 mva->mva_size, &sc->sc_ioh)) { 176 aprint_error_dev(self, "can't map registers\n"); 177 return; 178 } 179 mvpex_init(sc, mva->mva_tags); 180 181 /* XXX: looks seem good to specify level IPL_VM. */ 182 marvell_intr_establish(mva->mva_irq, IPL_VM, mvpex_intr, sc); 183 184 #if NPCI > 0 185 for (i = 0; i < PCI_INTERRUPT_PIN_MAX; i++) { 186 sc->sc_intrtab[i].intr_pin = PCI_INTERRUPT_PIN_A + i; 187 sc->sc_intrtab[i].intr_refcnt = 0; 188 LIST_INIT(&sc->sc_intrtab[i].intr_list); 189 } 190 191 mvpex_pci_config(sc, mvpex_io_bs_tag, mvpex_mem_bs_tag, mva->mva_dmat, 192 mvpex_chipset, iostart, ioend, memstart, memend, cl_size); 193 #endif 194 } 195 196 static int 197 mvpex_intr(void *arg) 198 { 199 struct mvpex_softc *sc = (struct mvpex_softc *)arg; 200 struct mvpex_intrhand *ih; 201 struct mvpex_intrtab *intrtab; 202 uint32_t ic, im; 203 int handled = 0, pin, rv, i, s; 204 205 for (;;) { 206 ic = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC); 207 im = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 208 ic &= im; 209 210 if (!ic) 211 break; 212 213 for (i = 0, pin = PCI_INTERRUPT_PIN_A; 214 i < PCI_INTERRUPT_PIN_MAX; pin++, i++) { 215 if ((ic & MVPEX_I_PIN(pin)) == 0) 216 continue; 217 218 intrtab = &sc->sc_intrtab[i]; 219 LIST_FOREACH(ih, &intrtab->intr_list, ih_q) { 220 s = _splraise(ih->ih_type); 221 rv = (*ih->ih_func)(ih->ih_arg); 222 splx(s); 223 if (rv) { 224 ih->ih_evcnt.ev_count++; 225 handled++; 226 } 227 } 228 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 229 ~MVPEX_I_PIN(pin)); 230 } 231 } 232 233 return handled; 234 } 235 236 237 static void 238 mvpex_init(struct mvpex_softc *sc, enum marvell_tags *tags) 239 { 240 uint32_t reg; 241 int window; 242 243 /* 244 * First implement Guideline (GL# PCI Express-2) Wrong Default Value 245 * to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 246 * and 88F5281-B0 247 */ 248 /* Write the read command */ 249 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, 0x80820000); 250 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x1b00); 251 /* Prepare new data for write */ 252 reg &= ~0x7; /* Clear bits [2:0] */ 253 reg |= 0x4; /* Set the new value */ 254 reg &= ~0x80000000; /* Set "write" command */ 255 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, reg); 256 257 for (window = 0; window < MVPEX_NWINDOW; window++) 258 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0); 259 260 #if 0 /* shall move to pchb(4)? */ 261 mvpex_barinit(sc); 262 #else 263 mvpex_wininit(sc, tags); 264 #endif 265 266 /* Clear Interrupt Cause and Mask registers */ 267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 0); 268 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, 0); 269 270 /* now wait 60 ns to be sure the link is valid (spec compliant) */ 271 delay(1); 272 } 273 274 #if 0 275 static int 276 mvpex_wininit(struct mvpex_softc *sc, int window, int tbegin, int tend, 277 int barmap, uint32_t *barbase, uint32_t *barsize) 278 { 279 uint32_t target, attr, base, size; 280 int targetid; 281 282 for (targetid = tbegin; targetid <= tend && window < MVPEX_NWINDOW; 283 targetid++) { 284 if (orion_target(targetid, &target, &attr, &base, &size) == -1) 285 continue; 286 if (size == 0) 287 continue; 288 289 if (base < *barbase) 290 *barbase = base; 291 *barsize += size; 292 293 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 294 MVPEX_WC_WINEN | 295 barmap | 296 MVPEX_WC_TARGET(target) | 297 MVPEX_WC_ATTR(attr) | 298 MVPEX_WC_SIZE(size)); 299 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window), 300 MVPEX_WB_BASE(base)); 301 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0); 302 window++; 303 } 304 305 return window; 306 } 307 308 /* shall move to pchb(4)? */ 309 static void 310 mvpex_barinit(struct mvpex_softc *sc) 311 { 312 const uint32_t barflag = 313 PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT; 314 uint32_t base, size; 315 int window = 0; 316 317 marvell_winparams_by_tag(device_parent(sc->sc_dev), 318 ORION_TARGETID_INTERNALREG, NULL, NULL, &base, &size); 319 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNAL, 320 barflag | (base & MVPEX_BAR0INTERNAL_MASK)); 321 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNALH, 0); 322 323 base = size = 0; 324 window = mvpex_wininit(sc, window, ORION_TARGETID_SDRAM_CS0, 325 ORION_TARGETID_SDRAM_CS3, MVPEX_WC_BARMAP_BAR1, &base, &size); 326 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1, 327 barflag | (base & MVPEX_BAR_MASK)); 328 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1H, 0); 329 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1C, 330 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN); 331 332 #if 0 333 base = size = 0; 334 if (sc->sc_model == MARVELL_ORION_1_88F1181) 335 window = mvpex_wininit(sc, window, ORION_TARGETID_FLASH_CS, 336 ORION_TARGETID_DEVICE_BOOTCS, 337 MVPEX_WC_BARMAP_BAR2, &base, &size); 338 else { 339 window = mvpex_wininit(sc, window, 340 ORION_TARGETID_DEVICE_CS0, ORION_TARGETID_DEVICE_CS2, 341 MVPEX_WC_BARMAP_BAR2, &base, &size); 342 window = mvpex_wininit(sc, window, 343 ORION_TARGETID_DEVICE_BOOTCS, ORION_TARGETID_DEVICE_BOOTCS, 344 MVPEX_WC_BARMAP_BAR2, &base, &size); 345 } 346 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2, 347 barflag | (base & MVPEX_BAR_MASK)); 348 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2H, 0); 349 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 350 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN); 351 #else 352 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 0); 353 #endif 354 } 355 #else 356 static void 357 mvpex_wininit(struct mvpex_softc *sc, enum marvell_tags *tags) 358 { 359 device_t pdev = device_parent(sc->sc_dev); 360 uint64_t base; 361 uint32_t size, bar; 362 int target, attr, window, rv, i, j; 363 364 for (window = 0, i = 0; 365 tags[i] != MARVELL_TAG_UNDEFINED && window < MVPEX_NWINDOW; i++) { 366 rv = marvell_winparams_by_tag(pdev, tags[i], 367 &target, &attr, &base, &size); 368 if (rv != 0 || size == 0) 369 continue; 370 371 if (base > 0xffffffffULL) { 372 aprint_error_dev(sc->sc_dev, 373 "tag %d address 0x%llx not support\n", 374 tags[i], base); 375 continue; 376 } 377 378 bar = MVPEX_WC_BARMAP_BAR1; 379 if (mvpex_bar2_tags != NULL) 380 for (j = 0; mvpex_bar2_tags[j] != MARVELL_TAG_UNDEFINED; 381 j++) { 382 if (mvpex_bar2_tags[j] != tags[i]) 383 continue; 384 bar = MVPEX_WC_BARMAP_BAR2; 385 break; 386 } 387 388 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 389 MVPEX_WC_WINEN | 390 bar | 391 MVPEX_WC_TARGET(target) | 392 MVPEX_WC_ATTR(attr) | 393 MVPEX_WC_SIZE(size)); 394 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window), 395 MVPEX_WB_BASE(base)); 396 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0); 397 window++; 398 } 399 for ( ; window < MVPEX_NWINDOW; window++) 400 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0); 401 } 402 #endif 403 404 #if NPCI > 0 405 static void 406 mvpex_pci_config(struct mvpex_softc *sc, bus_space_tag_t iot, 407 bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc, 408 u_long iostart, u_long ioend, u_long memstart, u_long memend, 409 int cacheline_size) 410 { 411 struct pcibus_attach_args pba; 412 #ifdef PCI_NETBSD_CONFIGURE 413 struct extent *ioext = NULL, *memext = NULL; 414 #endif 415 uint32_t stat; 416 417 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 418 419 #ifdef PCI_NETBSD_CONFIGURE 420 ioext = extent_create("pexio", iostart, ioend, NULL, 0, EX_NOWAIT); 421 memext = extent_create("pexmem", memstart, memend, NULL, 0, EX_NOWAIT); 422 if (ioext != NULL && memext != NULL) 423 pci_configure_bus(pc, ioext, memext, NULL, 424 MVPEX_STAT_PEXBUSNUM(stat), cacheline_size); 425 else 426 aprint_error_dev(sc->sc_dev, "can't create extent %s%s%s\n", 427 ioext == NULL ? "io" : "", 428 ioext == NULL && memext == NULL ? " and " : "", 429 memext == NULL ? "mem" : ""); 430 if (ioext != NULL) 431 extent_destroy(ioext); 432 if (memext != NULL) 433 extent_destroy(memext); 434 #endif 435 436 pba.pba_iot = iot; 437 pba.pba_memt = memt; 438 pba.pba_dmat = dmat; 439 pba.pba_dmat64 = NULL; 440 pba.pba_pc = pc; 441 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 442 pba.pba_bus = MVPEX_STAT_PEXBUSNUM(stat); 443 pba.pba_bridgetag = NULL; 444 config_found_ia(sc->sc_dev, "pcibus", &pba, NULL); 445 } 446 447 448 /* 449 * PCI-Express CPU dependent code 450 */ 451 452 /* ARGSUSED */ 453 void 454 mvpex_attach_hook(device_t parent, device_t self, 455 struct pcibus_attach_args *pba) 456 { 457 458 /* Nothing */ 459 } 460 461 /* 462 * Bit map for configuration register: 463 * [31] ConfigEn 464 * [30:28] Reserved 465 * [27:24] ExtRegNum (PCI Express only) 466 * [23:16] BusNum 467 * [15:11] DevNum 468 * [10: 8] FunctNum 469 * [ 7: 2] RegNum 470 * [ 1: 0] reserved 471 */ 472 473 /* ARGSUSED */ 474 int 475 mvpex_bus_maxdevs(void *v, int busno) 476 { 477 478 return 32; /* 32 device/bus */ 479 } 480 481 /* ARGSUSED */ 482 pcitag_t 483 mvpex_make_tag(void *v, int bus, int dev, int func) 484 { 485 486 return (bus << 16) | (dev << 11) | (func << 8); 487 } 488 489 /* ARGSUSED */ 490 void 491 mvpex_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 492 { 493 494 if (bp != NULL) 495 *bp = (tag >> 16) & 0xff; 496 if (dp != NULL) 497 *dp = (tag >> 11) & 0x1f; 498 if (fp != NULL) 499 *fp = (tag >> 8) & 0x07; 500 } 501 502 pcireg_t 503 mvpex_conf_read(void *v, pcitag_t tag, int reg) 504 { 505 struct mvpex_softc *sc = v; 506 pcireg_t addr, pci_cs; 507 uint32_t stat; 508 int bus, dev, func, pexbus, pexdev; 509 510 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 511 512 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 513 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 514 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 515 if (bus != pexbus || dev != pexdev) 516 if (stat & MVPEX_STAT_DLDOWN) 517 return -1; 518 519 if (bus == pexbus) { 520 if (pexdev == 0) { 521 if (dev != 1 && dev != pexdev) 522 return -1; 523 } else { 524 if (dev != 0 && dev != pexdev) 525 return -1; 526 } 527 if (func != 0) 528 return -1; 529 } 530 531 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 532 533 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 534 addr | MVPEX_CA_CONFIGEN); 535 if ((addr | MVPEX_CA_CONFIGEN) != 536 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 537 return -1; 538 539 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 540 PCI_COMMAND_STATUS_REG); 541 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 542 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT); 543 544 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD); 545 } 546 547 void 548 mvpex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 549 { 550 struct mvpex_softc *sc = v; 551 pcireg_t addr; 552 uint32_t stat; 553 int bus, dev, func, pexbus, pexdev; 554 555 mvpex_decompose_tag(v, tag, &bus, &dev, &func); 556 557 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT); 558 pexbus = MVPEX_STAT_PEXBUSNUM(stat); 559 pexdev = MVPEX_STAT_PEXDEVNUM(stat); 560 if (bus != pexbus || dev != pexdev) 561 if (stat & MVPEX_STAT_DLDOWN) 562 return; 563 564 if (bus == pexbus) { 565 if (pexdev == 0) { 566 if (dev != 1 && dev != pexdev) 567 return; 568 } else { 569 if (dev != 0 && dev != pexdev) 570 return; 571 } 572 if (func != 0) 573 return; 574 } 575 576 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc); 577 578 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA, 579 addr | MVPEX_CA_CONFIGEN); 580 if ((addr | MVPEX_CA_CONFIGEN) != 581 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA)) 582 return; 583 584 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD, data); 585 } 586 587 /* ARGSUSED */ 588 int 589 mvpex_conf_hook(void *v, int bus, int dev, int func, pcireg_t id) 590 { 591 592 if (bus == 0 && dev == 0) /* don't configure GT */ 593 return 0; 594 595 /* 596 * Do not configure PCI Express root complex on MV78460 - avoid 597 * setting up IO and memory windows. 598 * XXX: should also avoid that other Aramadas. 599 */ 600 else if ((dev == 0) && (PCI_PRODUCT(id) == MARVELL_ARMADAXP_MV78460)) 601 return 0; 602 603 return PCI_CONF_DEFAULT; 604 } 605 606 int 607 mvpex_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 608 { 609 610 switch (pa->pa_intrpin) { 611 case PCI_INTERRUPT_PIN_A: 612 case PCI_INTERRUPT_PIN_B: 613 case PCI_INTERRUPT_PIN_C: 614 case PCI_INTERRUPT_PIN_D: 615 *ihp = pa->pa_intrpin; 616 return 0; 617 } 618 return -1; 619 } 620 621 /* ARGSUSED */ 622 const char * 623 mvpex_intr_string(void *v, pci_intr_handle_t pin, char *buf, size_t len) 624 { 625 switch (pin) { 626 case PCI_INTERRUPT_PIN_A: 627 case PCI_INTERRUPT_PIN_B: 628 case PCI_INTERRUPT_PIN_C: 629 case PCI_INTERRUPT_PIN_D: 630 break; 631 632 default: 633 return NULL; 634 } 635 snprintf(buf, len, "interrupt pin INT%c#", (char)('A' - 1 + pin)); 636 637 return buf; 638 } 639 640 /* ARGSUSED */ 641 const struct evcnt * 642 mvpex_intr_evcnt(void *v, pci_intr_handle_t pin) 643 { 644 645 return NULL; 646 } 647 648 /* 649 * XXXX: Shall these functions use mutex(9) instead of spl(9)? 650 * MV78200 and MV64360 and after supports SMP. 651 */ 652 653 /* ARGSUSED */ 654 void * 655 mvpex_intr_establish(void *v, pci_intr_handle_t pin, int ipl, 656 int (*intrhand)(void *), void *intrarg) 657 { 658 struct mvpex_softc *sc = (struct mvpex_softc *)v; 659 struct mvpex_intrtab *intrtab; 660 struct mvpex_intrhand *pexih; 661 uint32_t mask; 662 int ih = pin - 1, s; 663 664 intrtab = &sc->sc_intrtab[ih]; 665 666 KASSERT(pin == intrtab->intr_pin); 667 668 pexih = malloc(sizeof(*pexih), M_DEVBUF, M_NOWAIT); 669 if (pexih == NULL) 670 return NULL; 671 672 pexih->ih_func = intrhand; 673 pexih->ih_arg = intrarg; 674 pexih->ih_type = ipl; 675 pexih->ih_intrtab = intrtab; 676 mvpex_intr_string(v, pin, pexih->ih_evname, sizeof(pexih->ih_evname)); 677 evcnt_attach_dynamic(&pexih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "mvpex", 678 pexih->ih_evname); 679 680 s = splhigh(); 681 682 /* First, link it into the tables. */ 683 LIST_INSERT_HEAD(&intrtab->intr_list, pexih, ih_q); 684 685 /* Now enable it. */ 686 if (intrtab->intr_refcnt++ == 0) { 687 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 688 mask |= MVPEX_I_PIN(intrtab->intr_pin); 689 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask); 690 } 691 692 splx(s); 693 694 return pexih; 695 } 696 697 void 698 mvpex_intr_disestablish(void *v, void *ih) 699 { 700 struct mvpex_softc *sc = (struct mvpex_softc *)v; 701 struct mvpex_intrtab *intrtab; 702 struct mvpex_intrhand *pexih = ih; 703 uint32_t mask; 704 int s; 705 706 evcnt_detach(&pexih->ih_evcnt); 707 708 intrtab = pexih->ih_intrtab; 709 710 s = splhigh(); 711 712 /* 713 * First, remove it from the table. 714 */ 715 LIST_REMOVE(pexih, ih_q); 716 717 /* Now, disable it, if there is nothing remaining on the list. */ 718 if (intrtab->intr_refcnt-- == 1) { 719 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM); 720 mask &= ~MVPEX_I_PIN(intrtab->intr_pin); 721 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask); 722 } 723 splx(s); 724 725 free(pexih, M_DEVBUF); 726 } 727 #endif /* NPCI > 0 */ 728
Indexes created Thu Sep 25 16:09:42 GMT 2025