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mvsata_mv.c revision 1.4.2.1
      1 /*	$NetBSD: mvsata_mv.c,v 1.4.2.1 2013/06/23 06:20:17 tls Exp $	*/
      2 /*
      3  * Copyright (c) 2008 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: mvsata_mv.c,v 1.4.2.1 2013/06/23 06:20:17 tls Exp $");
     30 
     31 #include <sys/param.h>
     32 #include <sys/bus.h>
     33 #include <sys/device.h>
     34 #include <sys/errno.h>
     35 
     36 #include <dev/ata/atareg.h>
     37 #include <dev/ata/atavar.h>
     38 #include <dev/ic/wdcvar.h>
     39 
     40 #include <dev/ic/mvsatareg.h>
     41 #include <dev/ic/mvsatavar.h>
     42 
     43 #include <dev/marvell/marvellreg.h>
     44 #include <dev/marvell/marvellvar.h>
     45 
     46 #include "locators.h"
     47 
     48 
     49 #define MVSATAHC_SIZE			0x8000
     50 
     51 #define MVSATAHC_NWINDOW		4
     52 
     53 #define MVSATAHC_MICR			0x20 /* Main Interrupt Cause */
     54 #define MVSATAHC_MIMR			0x24 /* Main Interrupt Mask */
     55 #define MVSATAHC_MI_SATAERR(p)			(1 << ((p) * 2))
     56 #define MVSATAHC_MI_SATADONE(p)			(1 << (((p) * 2) + 1))
     57 #define MVSATAHC_MI_SATADMADONE(p)		(1 << ((p) + 4))
     58 #define MVSATAHC_MI_SATACOALDONE		(1 << 8)
     59 #define MVSATAHC_WCR(n)			(0x30 + (n) * 0x10) /* WinN Control */
     60 #define MVSATAHC_WCR_WINEN			(1 << 0)
     61 #define MVSATAHC_WCR_TARGET(t)			(((t) & 0xf) << 4)
     62 #define MVSATAHC_WCR_ATTR(a)			(((a) & 0xff) << 8)
     63 #define MVSATAHC_WCR_SIZE(s)			(((s) - 1) & 0xffff0000)
     64 #define MVSATAHC_WBR(n)			(0x34 + (n) * 0x10) /* WinN Base */
     65 #define MVSATAHC_WBR_BASE(b)			((b) & 0xffff0000)
     66 
     67 
     68 static int mvsatahc_match(device_t, cfdata_t, void *);
     69 static void mvsatahc_attach(device_t, device_t, void *);
     70 
     71 static int mvsatahc_intr(void *);
     72 
     73 static void mvsatahc_enable_intr(struct mvsata_port *, int);
     74 static void mvsatahc_wininit(struct mvsata_softc *);
     75 
     76 CFATTACH_DECL_NEW(mvsata_gt, sizeof(struct mvsata_softc),
     77     mvsatahc_match, mvsatahc_attach, NULL, NULL);
     78 CFATTACH_DECL_NEW(mvsata_mbus, sizeof(struct mvsata_softc),
     79     mvsatahc_match, mvsatahc_attach, NULL, NULL);
     80 
     81 
     82 struct mvsata_product mvsata_products[] = {
     83 #if 0
     84 	/* Discovery VI */
     85 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV64660, ?, ?, gen2?, 0 },
     86 #endif
     87 
     88 	/* Orion */
     89 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5082, 1, 1, gen2e, 0 },
     90 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5182, 1, 2, gen2e, 0 },
     91 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6082, 1, 1, gen2e, 0 },
     92 
     93 	/* Kirkwood */
     94 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6192, 1, 2, gen2e, 0 },
     95 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6281, 1, 2, gen2e, 0 },
     96 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F6282, 1, 2, gen2e, 0 },
     97 
     98 	/* Discovery Innovation */
     99 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78100, 1, 2, gen2e, 0 },
    100 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78200, 1, 2, gen2e, 0 },
    101 
    102 	/* Armada XP */
    103 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_MV78460, 1, 2, gen2e, 0 },
    104 };
    105 
    106 
    107 /* ARGSUSED */
    108 static int
    109 mvsatahc_match(device_t parent, cfdata_t match, void *aux)
    110 {
    111 	struct marvell_attach_args *mva = aux;
    112 	int i;
    113 
    114 	if (strcmp(mva->mva_name, match->cf_name) != 0)
    115 		return 0;
    116 	if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
    117 	    mva->mva_irq == MVA_IRQ_DEFAULT)
    118 		    return 0;
    119 
    120 	for (i = 0; i < __arraycount(mvsata_products); i++)
    121 		if (mva->mva_model == mvsata_products[i].model) {
    122 			mva->mva_size = MVSATAHC_SIZE;
    123 			return 1;
    124 		}
    125 	return 0;
    126 }
    127 
    128 /* ARGSUSED */
    129 static void
    130 mvsatahc_attach(device_t parent, device_t self, void *aux)
    131 {
    132 	struct mvsata_softc *sc = device_private(self);
    133 	struct marvell_attach_args *mva = aux;
    134 	uint32_t mask;
    135 	int port, i;
    136 
    137 	aprint_normal(": Marvell Serial-ATA Host Controller (SATAHC)\n");
    138 	aprint_naive("\n");
    139 
    140 	sc->sc_wdcdev.sc_atac.atac_dev = self;
    141 	sc->sc_model = mva->mva_model;
    142 	sc->sc_iot = mva->mva_iot;
    143         if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
    144 	    mva->mva_size, &sc->sc_ioh)) {
    145 		aprint_error_dev(self, "can't map registers\n");
    146 		return;
    147 	}
    148 	sc->sc_dmat = mva->mva_dmat;
    149 	sc->sc_enable_intr = mvsatahc_enable_intr;
    150 
    151 	mvsatahc_wininit(sc);
    152 
    153 	for (i = 0; i < __arraycount(mvsata_products); i++)
    154 		if (mva->mva_model == mvsata_products[i].model)
    155 			break;
    156 	KASSERT(i < __arraycount(mvsata_products));
    157 
    158 	if (mvsata_attach(sc, &mvsata_products[i], NULL, NULL, 0) != 0)
    159 		return;
    160 
    161 	marvell_intr_establish(mva->mva_irq, IPL_BIO, mvsatahc_intr, sc);
    162 	mask = 0;
    163 	for (port = 0; port < sc->sc_port; port++)
    164 		mask |=
    165 		    MVSATAHC_MI_SATAERR(port) |
    166 		    MVSATAHC_MI_SATADONE(port);
    167 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR, mask);
    168 }
    169 
    170 static int
    171 mvsatahc_intr(void *arg)
    172 {
    173 	struct mvsata_softc *sc = (struct mvsata_softc *)arg;
    174 	struct mvsata_hc *mvhc = &sc->sc_hcs[0];
    175 	uint32_t cause, handled = 0;
    176 
    177 	cause = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MICR);
    178 	if (cause & MVSATAHC_MI_SATAERR(0))
    179 		handled |= mvsata_error(mvhc->hc_ports[0]);
    180 	if (cause & MVSATAHC_MI_SATAERR(1))
    181 		handled |= mvsata_error(mvhc->hc_ports[1]);
    182 	if (cause & (MVSATAHC_MI_SATADONE(0) | MVSATAHC_MI_SATADONE(1)))
    183 		handled |= mvsata_intr(mvhc);
    184 
    185 	return handled;
    186 }
    187 
    188 
    189 static void
    190 mvsatahc_enable_intr(struct mvsata_port *mvport, int on)
    191 {
    192 	struct mvsata_softc *sc =
    193 	    device_private(mvport->port_ata_channel.ch_atac->atac_dev);
    194 	uint32_t mask;
    195 
    196 	mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR);
    197 	if (on)
    198 		mask |= MVSATAHC_MI_SATADONE(mvport->port);
    199 	else
    200 		mask &= ~MVSATAHC_MI_SATADONE(mvport->port);
    201 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR, mask);
    202 }
    203 
    204 static void
    205 mvsatahc_wininit(struct mvsata_softc *sc)
    206 {
    207 	device_t pdev = device_parent(sc->sc_wdcdev.sc_atac.atac_dev);
    208 	uint64_t base;
    209 	uint32_t size;
    210 	int window, target, attr, rv, i;
    211 	static int tags[] = {
    212 		MARVELL_TAG_SDRAM_CS0,
    213 		MARVELL_TAG_SDRAM_CS1,
    214 		MARVELL_TAG_SDRAM_CS2,
    215 		MARVELL_TAG_SDRAM_CS3,
    216 
    217 		MARVELL_TAG_UNDEFINED,
    218 	};
    219 
    220 	for (window = 0, i = 0;
    221 	    tags[i] != MARVELL_TAG_UNDEFINED && window < MVSATAHC_NWINDOW;
    222 	    i++) {
    223 		rv = marvell_winparams_by_tag(pdev, tags[i],
    224 		    &target, &attr, &base, &size);
    225 		if (rv != 0 || size == 0)
    226 			continue;
    227 		if (base > 0xffffffffULL) {
    228 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    229 			    "tag %d address 0x%llx not support\n",
    230 			    tags[i], base);
    231 			continue;
    232 		}
    233 
    234 		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
    235 		    MVSATAHC_WCR(window),
    236 		    MVSATAHC_WCR_WINEN |
    237 		    MVSATAHC_WCR_TARGET(target) |
    238 		    MVSATAHC_WCR_ATTR(attr) |
    239 		    MVSATAHC_WCR_SIZE(size));
    240 		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
    241 		    MVSATAHC_WBR(window), MVSATAHC_WBR_BASE(base));
    242 		window++;
    243 	}
    244 	for (; window < MVSATAHC_NWINDOW; window++)
    245 		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
    246 		    MVSATAHC_WCR(window), 0);
    247 }
    248