mvspireg.h revision 1.2.2.3
1 1.2.2.2 tls /******************************************************************************* 2 1.2.2.2 tls Copyright (C) Marvell International Ltd. and its affiliates 3 1.2.2.2 tls 4 1.2.2.2 tls Developed by Semihalf 5 1.2.2.2 tls 6 1.2.2.2 tls ******************************************************************************** 7 1.2.2.2 tls Marvell BSD License 8 1.2.2.2 tls 9 1.2.2.2 tls If you received this File from Marvell, you may opt to use, redistribute and/or 10 1.2.2.2 tls modify this File under the following licensing terms. 11 1.2.2.2 tls Redistribution and use in source and binary forms, with or without modification, 12 1.2.2.2 tls are permitted provided that the following conditions are met: 13 1.2.2.2 tls 14 1.2.2.2 tls * Redistributions of source code must retain the above copyright notice, 15 1.2.2.2 tls this list of conditions and the following disclaimer. 16 1.2.2.2 tls 17 1.2.2.2 tls * Redistributions in binary form must reproduce the above copyright 18 1.2.2.2 tls notice, this list of conditions and the following disclaimer in the 19 1.2.2.2 tls documentation and/or other materials provided with the distribution. 20 1.2.2.2 tls 21 1.2.2.2 tls * Neither the name of Marvell nor the names of its contributors may be 22 1.2.2.2 tls used to endorse or promote products derived from this software without 23 1.2.2.2 tls specific prior written permission. 24 1.2.2.2 tls 25 1.2.2.2 tls THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 26 1.2.2.2 tls ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 1.2.2.2 tls WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 1.2.2.2 tls DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 29 1.2.2.2 tls ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 1.2.2.2 tls (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 1.2.2.2 tls LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 32 1.2.2.2 tls ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 1.2.2.2 tls (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 1.2.2.2 tls SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 1.2.2.2 tls 36 1.2.2.2 tls *******************************************************************************/ 37 1.2.2.2 tls 38 1.2.2.2 tls #ifndef _MVSPIREG_H_ 39 1.2.2.2 tls #define _MVSPIREG_H_ 40 1.2.2.2 tls 41 1.2.2.3 jdolecek #define MVSPI_SIZE 0x80 /* Size of MVSPI */ 42 1.2.2.2 tls 43 1.2.2.2 tls /* Definition of registers */ 44 1.2.2.2 tls #define MVSPI_CTRL_REG 0x00 /* MVSPI Control Register */ 45 1.2.2.2 tls #define MVSPI_INTCONF_REG 0x04 /* MVSPI Interface Configuration Register */ 46 1.2.2.2 tls #define MVSPI_DATAOUT_REG 0x08 /* MVSPI Data Out Register */ 47 1.2.2.2 tls #define MVSPI_DATAIN_REG 0x0C /* MVSPI Data In Register */ 48 1.2.2.2 tls #define MVSPI_IRQCAUSE_REG 0x10 /* MVSPI Interrupt Cause Register */ 49 1.2.2.2 tls #define MVSPI_IRQMASK_REG 0x14 /* MVSPI Interrupt Mask Register */ 50 1.2.2.2 tls #define MVSPI_TIMEPAR1_REG 0x18 /* MVSPI Timing Parameters 1 Register*/ 51 1.2.2.2 tls #define MVSPI_TIMEPAR2_REG 0x1C /* MVSPI Timing Parameters 2 Register */ 52 1.2.2.2 tls #define MVSPI_DIRWRITE_REG 0x20 /* MVSPI Direct Write Configuration Register*/ 53 1.2.2.2 tls #define MVSPI_DIRWRITEHD_REG 0x24 /* MVSPI Direct Write Header Register */ 54 1.2.2.2 tls #define MVSPI_DIRREADHD_REG 0x28 /* MVSPI Direct Read Header Register */ 55 1.2.2.2 tls #define MVSPI_CSADRDEC_REG 0x2C /* MVSPI CS Address Decode Register */ 56 1.2.2.2 tls #define MVSPI_CSnTIMPAR_REG 0x30 /* MVSPI CSn Timing Parameters Register */ 57 1.2.2.2 tls #define MVSPI_CNTVER_REG 0x50 /* MVSPI Controller Version Register */ 58 1.2.2.2 tls 59 1.2.2.2 tls /* Masks */ 60 1.2.2.2 tls #define MVSPI_CPOL_MASK 0x0800 /* CPOL bit = 1 */ 61 1.2.2.2 tls #define MVSPI_CPHA_MASK 0x1000 /* CPHA bit = 1 */ 62 1.2.2.2 tls #define MVSPI_DIRHS_MASK 0xFBFF /* SPI Direct Read High Speed Transaction Mask */ 63 1.2.2.2 tls #define MVSPI_1BYTE_MASK 0xFFDF /* Number of bits in each I/O transfer Mask */ 64 1.2.2.2 tls #define MVSPI_SPR_MASK 0x0007 /* SPR field mask */ 65 1.2.2.2 tls #define MVSPI_SPPR_MASK 0x00D0 /* SPPR field mask */ 66 1.2.2.2 tls #define MVSPI_SPPRHI_MASK 0x00C0 /* SPPR_HI field mask */ 67 1.2.2.2 tls #define MVSPI_SPPR0_MASK 0x0010 /* SPPR0 field mask */ 68 1.2.2.2 tls #define MVSPI_CSNACT_MASK 0x0001 /* CSn transfer acknowledge bit */ 69 1.2.2.2 tls 70 1.2.2.2 tls #define MVSPI_CR_SMEMRDY 0x0002 /* MVSPI Control Register Serial Memory Data Transfer Ready */ 71 1.2.2.2 tls 72 1.2.2.2 tls #define MVSPI_DUMMY_BYTE 0xFF /* Dummy byte */ 73 1.2.2.2 tls 74 1.2.2.2 tls #define MVSPI_WAIT_RDY_MAX_LOOP 100000 /* Transfer timeout threshold */ 75 1.2.2.2 tls #define MVSPI_SPR_MAXVALUE 15 /* Maximum value for SPR coeficient */ 76 1.2.2.2 tls #define MVSPI_SPPR_MAXVALUE 7 /* Maximum value for SPPR coeficient */ 77 1.2.2.2 tls 78 1.2.2.2 tls #endif /* _MVSPIREG_H_ */ 79
Indexes created Wed Oct 22 13:09:56 GMT 2025