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mvxpbmvar.h revision 1.4
      1  1.4    andvar /*	$NetBSD: mvxpbmvar.h,v 1.4 2022/03/13 17:50:55 andvar Exp $	*/
      2  1.1  hsuenaga /*
      3  1.1  hsuenaga  * Copyright (c) 2015 Internet Initiative Japan Inc.
      4  1.1  hsuenaga  * All rights reserved.
      5  1.1  hsuenaga  *
      6  1.1  hsuenaga  * Redistribution and use in source and binary forms, with or without
      7  1.1  hsuenaga  * modification, are permitted provided that the following conditions
      8  1.1  hsuenaga  * are met:
      9  1.1  hsuenaga  * 1. Redistributions of source code must retain the above copyright
     10  1.1  hsuenaga  *    notice, this list of conditions and the following disclaimer.
     11  1.1  hsuenaga  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.1  hsuenaga  *    notice, this list of conditions and the following disclaimer in the
     13  1.1  hsuenaga  *    documentation and/or other materials provided with the distribution.
     14  1.1  hsuenaga  *
     15  1.1  hsuenaga  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  1.1  hsuenaga  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  1.1  hsuenaga  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  1.1  hsuenaga  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  1.1  hsuenaga  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  1.1  hsuenaga  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  1.1  hsuenaga  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  1.1  hsuenaga  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  1.1  hsuenaga  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  1.1  hsuenaga  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  1.1  hsuenaga  * POSSIBILITY OF SUCH DAMAGE.
     26  1.1  hsuenaga  */
     27  1.1  hsuenaga #ifndef _MVXPBMVAR_H_
     28  1.1  hsuenaga #define _MVXPBMVAR_H_
     29  1.1  hsuenaga #include <dev/marvell/marvellvar.h>
     30  1.1  hsuenaga 
     31  1.1  hsuenaga /*
     32  1.1  hsuenaga  * Max number of unit.
     33  1.1  hsuenaga  */
     34  1.1  hsuenaga #define MVXPBM_UNIT_MAX		1
     35  1.1  hsuenaga 
     36  1.1  hsuenaga /*
     37  1.3    andvar  * Buffer alignment
     38  1.1  hsuenaga  */
     39  1.1  hsuenaga #define MVXPBM_NUM_SLOTS	2048	/* minimum number of slots */
     40  1.1  hsuenaga #define MVXPBM_PACKET_SIZE	2000	/* minimum packet size */
     41  1.1  hsuenaga 
     42  1.1  hsuenaga #define MVXPBM_BUF_ALIGN	65536	/* Mbus window size granularity */
     43  1.1  hsuenaga #define MVXPBM_BUF_MASK		(MVXPBM_BUF_ALIGN - 1)
     44  1.1  hsuenaga #define MVXPBM_CHUNK_ALIGN	32	/* Cache line size */
     45  1.1  hsuenaga #define MVXPBM_CHUNK_MASK	(MVXPBM_CHUNK_ALIGN - 1)
     46  1.1  hsuenaga #define MVXPBM_DATA_ALIGN	32	/* Cache line size */
     47  1.1  hsuenaga #define MVXPBM_DATA_MASK	(MVXPBM_DATA_ALIGN - 1)
     48  1.1  hsuenaga #define MVXPBM_DATA_UNIT	8
     49  1.1  hsuenaga 
     50  1.1  hsuenaga /*
     51  1.1  hsuenaga  * Packet Buffer Header
     52  1.1  hsuenaga  *
     53  1.1  hsuenaga  * this chunks may be managed by H/W Buffer Manger(BM) device,
     54  1.1  hsuenaga  * but there is no device driver yet.
     55  1.1  hsuenaga  *
     56  1.1  hsuenaga  *                            +----------------+ bm_buf
     57  1.1  hsuenaga  *                            |chunk header    | |
     58  1.1  hsuenaga  * +----------------+         |                | |chunk->buf_off
     59  1.1  hsuenaga  * |mbuf (M_EXT set)|<--------|struct mbuf *m  | V
     60  1.1  hsuenaga  * +----------------+         +----------------+ chunk->buf_va/buf_pa
     61  1.1  hsuenaga  * |   m_ext.ext_buf|-------->|packet buffer   | |
     62  1.1  hsuenaga  * +----------------+         |                | |chunk->buf_size
     63  1.1  hsuenaga  *                            |                | V
     64  1.1  hsuenaga  *                            +----------------+
     65  1.1  hsuenaga  *                            |chunk header    |
     66  1.1  hsuenaga  *                            |....            |
     67  1.1  hsuenaga  */
     68  1.1  hsuenaga 
     69  1.1  hsuenaga struct mvxpbm_chunk {
     70  1.1  hsuenaga 	struct mbuf	*m;		/* back pointer to  mbuf header */
     71  1.1  hsuenaga 	void		*sc;		/* back pointer to softc */
     72  1.1  hsuenaga 	off_t		off;		/* offset of chunk */
     73  1.1  hsuenaga 	paddr_t		pa;		/* physical address of chunk */
     74  1.1  hsuenaga 
     75  1.1  hsuenaga 	off_t		buf_off;	/* offset of packet from sc_bm_buf */
     76  1.1  hsuenaga 	paddr_t		buf_pa;		/* physical address of packet */
     77  1.2    andvar 	vaddr_t		buf_va;		/* virtual address of packet */
     78  1.1  hsuenaga 	size_t		buf_size;	/* size of buffer (exclude hdr) */
     79  1.1  hsuenaga 
     80  1.1  hsuenaga 	LIST_ENTRY(mvxpbm_chunk) link;
     81  1.1  hsuenaga 	/* followed by packet buffer */
     82  1.1  hsuenaga };
     83  1.1  hsuenaga 
     84  1.1  hsuenaga struct mvxpbm_softc {
     85  1.1  hsuenaga 	device_t	sc_dev;
     86  1.1  hsuenaga 	bus_dma_tag_t	sc_dmat;
     87  1.1  hsuenaga 	bus_space_tag_t sc_iot;
     88  1.1  hsuenaga 	kmutex_t	sc_mtx;
     89  1.1  hsuenaga 
     90  1.1  hsuenaga 	/* software emulated */
     91  1.1  hsuenaga 	int		sc_emul;
     92  1.1  hsuenaga 
     93  1.1  hsuenaga 	/* DMA MAP for entire buffer */
     94  1.1  hsuenaga 	bus_dmamap_t	sc_buf_map;
     95  1.1  hsuenaga 	char		*sc_buf;
     96  1.1  hsuenaga 	paddr_t		sc_buf_pa;
     97  1.1  hsuenaga 	size_t		sc_buf_size;
     98  1.1  hsuenaga 
     99  1.1  hsuenaga 	/* memory chunk properties */
    100  1.1  hsuenaga 	size_t		sc_slotsize;		/* size of bm_slots include header */
    101  1.1  hsuenaga 	uint32_t	sc_chunk_count;		/* number of chunks */
    102  1.1  hsuenaga 	size_t		sc_chunk_size;		/* size of packet buffer */
    103  1.4    andvar 	size_t		sc_chunk_header_size;	/* size of header + padding */
    104  1.1  hsuenaga 	off_t		sc_chunk_packet_offset;	/* allocate m_leading_space */
    105  1.1  hsuenaga 
    106  1.1  hsuenaga 	/* for software based management */
    107  1.1  hsuenaga 	LIST_HEAD(__mvxpbm_freehead, mvxpbm_chunk) sc_free;
    108  1.1  hsuenaga 	LIST_HEAD(__mvxpbm_inusehead, mvxpbm_chunk) sc_inuse;
    109  1.1  hsuenaga };
    110  1.1  hsuenaga 
    111  1.1  hsuenaga #define BM_SYNC_ALL	0
    112  1.1  hsuenaga 
    113  1.1  hsuenaga /* get mvxpbm device context */
    114  1.1  hsuenaga struct mvxpbm_softc *mvxpbm_device(struct marvell_attach_args *);
    115  1.1  hsuenaga 
    116  1.1  hsuenaga /* allocate new memory chunk */
    117  1.1  hsuenaga struct mvxpbm_chunk *mvxpbm_alloc(struct mvxpbm_softc *);
    118  1.1  hsuenaga 
    119  1.1  hsuenaga /* free memory chunk */
    120  1.1  hsuenaga void mvxpbm_free_chunk(struct mvxpbm_chunk *);
    121  1.1  hsuenaga 
    122  1.1  hsuenaga /* prepare mbuf header after Rx */
    123  1.1  hsuenaga int mvxpbm_init_mbuf_hdr(struct mvxpbm_chunk *);
    124  1.1  hsuenaga 
    125  1.1  hsuenaga /* sync DMA seguments */
    126  1.1  hsuenaga void mvxpbm_dmamap_sync(struct mvxpbm_chunk *, size_t, int);
    127  1.1  hsuenaga 
    128  1.1  hsuenaga /* lock */
    129  1.1  hsuenaga void mvxpbm_lock(struct mvxpbm_softc *);
    130  1.1  hsuenaga void mvxpbm_unlock(struct mvxpbm_softc *);
    131  1.1  hsuenaga 
    132  1.1  hsuenaga /* get params */
    133  1.1  hsuenaga const char *mvxpbm_xname(struct mvxpbm_softc *);
    134  1.1  hsuenaga size_t mvxpbm_chunk_size(struct mvxpbm_softc *);
    135  1.1  hsuenaga uint32_t mvxpbm_chunk_count(struct mvxpbm_softc *);
    136  1.1  hsuenaga off_t mvxpbm_packet_offset(struct mvxpbm_softc *);
    137  1.1  hsuenaga paddr_t mvxpbm_buf_pbase(struct mvxpbm_softc *);
    138  1.1  hsuenaga size_t mvxpbm_buf_size(struct mvxpbm_softc *);
    139  1.1  hsuenaga #endif /* _MVXPBMVAR_H_ */
    140