edc_mca.c revision 1.9.2.5 1 1.9.2.5 nathanw /* $NetBSD: edc_mca.c,v 1.9.2.5 2002/04/17 00:05:58 nathanw Exp $ */
2 1.9.2.2 nathanw
3 1.9.2.2 nathanw /*
4 1.9.2.2 nathanw * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.9.2.2 nathanw *
6 1.9.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
7 1.9.2.2 nathanw * by Jaromir Dolecek.
8 1.9.2.2 nathanw *
9 1.9.2.2 nathanw * Redistribution and use in source and binary forms, with or without
10 1.9.2.2 nathanw * modification, are permitted provided that the following conditions
11 1.9.2.2 nathanw * are met:
12 1.9.2.2 nathanw * 1. Redistributions of source code must retain the above copyright
13 1.9.2.2 nathanw * notice, this list of conditions and the following disclaimer.
14 1.9.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
15 1.9.2.2 nathanw * notice, this list of conditions and the following disclaimer in the
16 1.9.2.2 nathanw * documentation and/or other materials provided with the distribution.
17 1.9.2.2 nathanw * 3. All advertising materials mentioning features or use of this software
18 1.9.2.2 nathanw * must display the following acknowledgement:
19 1.9.2.2 nathanw * This product includes software developed by the NetBSD
20 1.9.2.2 nathanw * Foundation, Inc. and its contributors.
21 1.9.2.2 nathanw * 4. The name of the author may not be used to endorse or promote products
22 1.9.2.2 nathanw * derived from this software without specific prior written permission.
23 1.9.2.2 nathanw *
24 1.9.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 1.9.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 1.9.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 1.9.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 1.9.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 1.9.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 1.9.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 1.9.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 1.9.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 1.9.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 1.9.2.2 nathanw */
35 1.9.2.2 nathanw
36 1.9.2.2 nathanw /*
37 1.9.2.2 nathanw * Driver for MCA ESDI controllers and disks conforming to IBM DASD
38 1.9.2.2 nathanw * spec.
39 1.9.2.2 nathanw *
40 1.9.2.2 nathanw * The driver was written with DASD Storage Interface Specification
41 1.9.2.2 nathanw * for MCA rev. 2.2 in hands, thanks to Scott Telford <st (at) epcc.ed.ac.uk>.
42 1.9.2.2 nathanw *
43 1.9.2.2 nathanw * TODO:
44 1.9.2.2 nathanw * - improve error recovery
45 1.9.2.4 nathanw * Issue soft reset on error or timeout?
46 1.9.2.4 nathanw * - test with > 1 disk (this is supported by some controllers)
47 1.9.2.2 nathanw * - test with > 1 ESDI controller in machine; shared interrupts
48 1.9.2.2 nathanw * necessary for this to work should be supported - edc_intr() specifically
49 1.9.2.2 nathanw * checks if the interrupt is for this controller
50 1.9.2.2 nathanw */
51 1.9.2.2 nathanw
52 1.9.2.3 nathanw #include <sys/cdefs.h>
53 1.9.2.5 nathanw __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.9.2.5 2002/04/17 00:05:58 nathanw Exp $");
54 1.9.2.3 nathanw
55 1.9.2.2 nathanw #include "rnd.h"
56 1.9.2.2 nathanw
57 1.9.2.2 nathanw #include <sys/param.h>
58 1.9.2.2 nathanw #include <sys/systm.h>
59 1.9.2.2 nathanw #include <sys/errno.h>
60 1.9.2.2 nathanw #include <sys/device.h>
61 1.9.2.2 nathanw #include <sys/malloc.h>
62 1.9.2.2 nathanw #include <sys/endian.h>
63 1.9.2.2 nathanw #include <sys/disklabel.h>
64 1.9.2.2 nathanw #include <sys/disk.h>
65 1.9.2.2 nathanw #include <sys/syslog.h>
66 1.9.2.2 nathanw #include <sys/proc.h>
67 1.9.2.2 nathanw #include <sys/vnode.h>
68 1.9.2.2 nathanw #include <sys/kernel.h>
69 1.9.2.4 nathanw #include <sys/kthread.h>
70 1.9.2.2 nathanw #if NRND > 0
71 1.9.2.2 nathanw #include <sys/rnd.h>
72 1.9.2.2 nathanw #endif
73 1.9.2.2 nathanw
74 1.9.2.2 nathanw #include <machine/bus.h>
75 1.9.2.2 nathanw #include <machine/intr.h>
76 1.9.2.2 nathanw
77 1.9.2.2 nathanw #include <dev/mca/mcareg.h>
78 1.9.2.2 nathanw #include <dev/mca/mcavar.h>
79 1.9.2.2 nathanw #include <dev/mca/mcadevs.h>
80 1.9.2.2 nathanw
81 1.9.2.2 nathanw #include <dev/mca/edcreg.h>
82 1.9.2.2 nathanw #include <dev/mca/edvar.h>
83 1.9.2.2 nathanw #include <dev/mca/edcvar.h>
84 1.9.2.2 nathanw
85 1.9.2.2 nathanw #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */
86 1.9.2.4 nathanw #define EDC_MAX_CMD_RES_LEN 8
87 1.9.2.2 nathanw
88 1.9.2.2 nathanw struct edc_mca_softc {
89 1.9.2.2 nathanw struct device sc_dev;
90 1.9.2.2 nathanw
91 1.9.2.2 nathanw bus_space_tag_t sc_iot;
92 1.9.2.2 nathanw bus_space_handle_t sc_ioh;
93 1.9.2.2 nathanw
94 1.9.2.4 nathanw /* DMA related stuff */
95 1.9.2.2 nathanw bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */
96 1.9.2.4 nathanw bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */
97 1.9.2.2 nathanw
98 1.9.2.2 nathanw void *sc_ih; /* interrupt handle */
99 1.9.2.2 nathanw
100 1.9.2.2 nathanw int sc_flags;
101 1.9.2.2 nathanw #define DASD_QUIET 0x01 /* don't dump cmd error info */
102 1.9.2.4 nathanw
103 1.9.2.2 nathanw #define DASD_MAXDEVS 8
104 1.9.2.2 nathanw struct ed_softc *sc_ed[DASD_MAXDEVS];
105 1.9.2.4 nathanw int sc_maxdevs; /* max number of disks attached to this
106 1.9.2.4 nathanw * controller */
107 1.9.2.4 nathanw
108 1.9.2.4 nathanw /* I/O results variables */
109 1.9.2.5 nathanw volatile int sc_stat;
110 1.9.2.5 nathanw #define STAT_START 0
111 1.9.2.5 nathanw #define STAT_ERROR 1
112 1.9.2.5 nathanw #define STAT_DONE 2
113 1.9.2.4 nathanw volatile int sc_resblk; /* residual block count */
114 1.9.2.5 nathanw
115 1.9.2.5 nathanw /* CMD status block - only set & used in edc_intr() */
116 1.9.2.5 nathanw u_int16_t status_block[EDC_MAX_CMD_RES_LEN];
117 1.9.2.2 nathanw };
118 1.9.2.2 nathanw
119 1.9.2.2 nathanw int edc_mca_probe __P((struct device *, struct cfdata *, void *));
120 1.9.2.2 nathanw void edc_mca_attach __P((struct device *, struct device *, void *));
121 1.9.2.2 nathanw
122 1.9.2.2 nathanw struct cfattach edc_mca_ca = {
123 1.9.2.2 nathanw sizeof(struct edc_mca_softc), edc_mca_probe, edc_mca_attach
124 1.9.2.2 nathanw };
125 1.9.2.2 nathanw
126 1.9.2.2 nathanw static int edc_intr __P((void *));
127 1.9.2.4 nathanw static void edc_dump_status_block __P((struct edc_mca_softc *,
128 1.9.2.4 nathanw u_int16_t *, int));
129 1.9.2.2 nathanw static int edc_do_attn __P((struct edc_mca_softc *, int, int, int));
130 1.9.2.5 nathanw static void edc_cmd_wait __P((struct edc_mca_softc *, int, int));
131 1.9.2.4 nathanw static void edcworker __P((void *));
132 1.9.2.4 nathanw static void edc_spawn_worker __P((void *));
133 1.9.2.2 nathanw
134 1.9.2.2 nathanw int
135 1.9.2.2 nathanw edc_mca_probe(parent, match, aux)
136 1.9.2.2 nathanw struct device *parent;
137 1.9.2.2 nathanw struct cfdata *match;
138 1.9.2.2 nathanw void *aux;
139 1.9.2.2 nathanw {
140 1.9.2.2 nathanw struct mca_attach_args *ma = aux;
141 1.9.2.2 nathanw
142 1.9.2.2 nathanw switch (ma->ma_id) {
143 1.9.2.2 nathanw case MCA_PRODUCT_IBM_ESDIC:
144 1.9.2.2 nathanw case MCA_PRODUCT_IBM_ESDIC_IG:
145 1.9.2.2 nathanw return (1);
146 1.9.2.2 nathanw default:
147 1.9.2.2 nathanw return (0);
148 1.9.2.2 nathanw }
149 1.9.2.2 nathanw }
150 1.9.2.2 nathanw
151 1.9.2.2 nathanw void
152 1.9.2.2 nathanw edc_mca_attach(parent, self, aux)
153 1.9.2.2 nathanw struct device *parent, *self;
154 1.9.2.2 nathanw void *aux;
155 1.9.2.2 nathanw {
156 1.9.2.2 nathanw struct edc_mca_softc *sc = (void *) self;
157 1.9.2.2 nathanw struct mca_attach_args *ma = aux;
158 1.9.2.4 nathanw struct ed_attach_args eda;
159 1.9.2.2 nathanw int pos2, pos3, pos4;
160 1.9.2.2 nathanw int irq, drq, iobase;
161 1.9.2.2 nathanw const char *typestr;
162 1.9.2.4 nathanw int devno, error;
163 1.9.2.2 nathanw
164 1.9.2.2 nathanw pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2);
165 1.9.2.2 nathanw pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3);
166 1.9.2.2 nathanw pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4);
167 1.9.2.2 nathanw
168 1.9.2.2 nathanw /*
169 1.9.2.2 nathanw * POS register 2: (adf pos0)
170 1.9.2.2 nathanw *
171 1.9.2.2 nathanw * 7 6 5 4 3 2 1 0
172 1.9.2.2 nathanw * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled
173 1.9.2.2 nathanw * \ \ \___ Primary/Alternate Port Adresses:
174 1.9.2.2 nathanw * \ \ 0=0x3510-3517 1=0x3518-0x351f
175 1.9.2.2 nathanw * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7
176 1.9.2.2 nathanw * \ 0000=0 0001=1 0011=3 0100=4
177 1.9.2.2 nathanw * \_________ Fairness On/Off: 1=On 0=Off
178 1.9.2.2 nathanw *
179 1.9.2.2 nathanw * POS register 3: (adf pos1)
180 1.9.2.2 nathanw *
181 1.9.2.2 nathanw * 7 6 5 4 3 2 1 0
182 1.9.2.2 nathanw * 0 0 \_/
183 1.9.2.2 nathanw * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms
184 1.9.2.2 nathanw * 01=16ms 00=Burst Disabled
185 1.9.2.2 nathanw *
186 1.9.2.2 nathanw * POS register 4: (adf pos2)
187 1.9.2.2 nathanw *
188 1.9.2.2 nathanw * 7 6 5 4 3 2 1 0
189 1.9.2.2 nathanw * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled
190 1.9.2.2 nathanw * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate
191 1.9.2.2 nathanw *
192 1.9.2.2 nathanw * IRQ is fixed to 14 (0x0e).
193 1.9.2.2 nathanw */
194 1.9.2.2 nathanw
195 1.9.2.2 nathanw switch (ma->ma_id) {
196 1.9.2.2 nathanw case MCA_PRODUCT_IBM_ESDIC:
197 1.9.2.2 nathanw typestr = "IBM ESDI Fixed Disk Controller";
198 1.9.2.2 nathanw break;
199 1.9.2.2 nathanw case MCA_PRODUCT_IBM_ESDIC_IG:
200 1.9.2.2 nathanw typestr = "IBM Integ. ESDI Fixed Disk & Controller";
201 1.9.2.2 nathanw break;
202 1.9.2.2 nathanw default:
203 1.9.2.4 nathanw /* never reached */ ;
204 1.9.2.2 nathanw }
205 1.9.2.2 nathanw
206 1.9.2.2 nathanw irq = ESDIC_IRQ;
207 1.9.2.2 nathanw iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM;
208 1.9.2.2 nathanw drq = (pos2 & DRQ_MASK) >> 2;
209 1.9.2.2 nathanw
210 1.9.2.2 nathanw printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1,
211 1.9.2.2 nathanw irq, drq, typestr);
212 1.9.2.2 nathanw
213 1.9.2.2 nathanw #ifdef DIAGNOSTIC
214 1.9.2.2 nathanw /*
215 1.9.2.2 nathanw * It's not strictly necessary to check this, machine configuration
216 1.9.2.2 nathanw * utility uses only valid adresses.
217 1.9.2.2 nathanw */
218 1.9.2.2 nathanw if (drq == 2 || drq >= 8) {
219 1.9.2.2 nathanw printf("%s: invalid DMA Arbitration Level %d\n",
220 1.9.2.2 nathanw sc->sc_dev.dv_xname, drq);
221 1.9.2.2 nathanw return;
222 1.9.2.2 nathanw }
223 1.9.2.2 nathanw #endif
224 1.9.2.2 nathanw
225 1.9.2.2 nathanw printf("%s: Fairness %s, Release %s, ",
226 1.9.2.2 nathanw sc->sc_dev.dv_xname,
227 1.9.2.2 nathanw (pos2 & FAIRNESS_ENABLE) ? "On" : "Off",
228 1.9.2.2 nathanw (pos4 & RELEASE_1) ? "6ms"
229 1.9.2.2 nathanw : ((pos4 & RELEASE_2) ? "3ms" : "Immediate")
230 1.9.2.2 nathanw );
231 1.9.2.2 nathanw if ((pos4 & PACING_CTRL_DISABLE) == 0) {
232 1.9.2.2 nathanw static const char * const pacint[] =
233 1.9.2.2 nathanw { "disabled", "16ms", "24ms", "31ms"};
234 1.9.2.2 nathanw printf("DMA burst pacing interval %s\n",
235 1.9.2.2 nathanw pacint[(pos3 & PACING_INT_MASK) >> 4]);
236 1.9.2.2 nathanw } else
237 1.9.2.2 nathanw printf("DMA pacing control disabled\n");
238 1.9.2.2 nathanw
239 1.9.2.2 nathanw sc->sc_iot = ma->ma_iot;
240 1.9.2.2 nathanw
241 1.9.2.2 nathanw if (bus_space_map(sc->sc_iot, iobase,
242 1.9.2.2 nathanw ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) {
243 1.9.2.2 nathanw printf("%s: couldn't map registers\n",
244 1.9.2.2 nathanw sc->sc_dev.dv_xname);
245 1.9.2.2 nathanw return;
246 1.9.2.2 nathanw }
247 1.9.2.2 nathanw
248 1.9.2.2 nathanw sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc);
249 1.9.2.2 nathanw if (sc->sc_ih == NULL) {
250 1.9.2.2 nathanw printf("%s: couldn't establish interrupt handler\n",
251 1.9.2.2 nathanw sc->sc_dev.dv_xname);
252 1.9.2.2 nathanw return;
253 1.9.2.2 nathanw }
254 1.9.2.2 nathanw
255 1.9.2.4 nathanw /* Create a MCA DMA map, used for data transfer */
256 1.9.2.4 nathanw sc->sc_dmat = ma->ma_dmat;
257 1.9.2.4 nathanw if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS,
258 1.9.2.4 nathanw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT,
259 1.9.2.4 nathanw &sc->sc_dmamap_xfer, drq)) != 0){
260 1.9.2.4 nathanw printf("%s: couldn't create DMA map - error %d\n",
261 1.9.2.4 nathanw sc->sc_dev.dv_xname, error);
262 1.9.2.4 nathanw return;
263 1.9.2.4 nathanw }
264 1.9.2.4 nathanw
265 1.9.2.2 nathanw /*
266 1.9.2.2 nathanw * Integrated ESDI controller supports only one disk, other
267 1.9.2.2 nathanw * controllers support two disks.
268 1.9.2.2 nathanw */
269 1.9.2.2 nathanw if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG)
270 1.9.2.4 nathanw sc->sc_maxdevs = 1;
271 1.9.2.2 nathanw else
272 1.9.2.4 nathanw sc->sc_maxdevs = 2;
273 1.9.2.2 nathanw
274 1.9.2.2 nathanw /*
275 1.9.2.2 nathanw * Reset controller and attach individual disks. ed attach routine
276 1.9.2.2 nathanw * uses polling so that this works with interrupts disabled.
277 1.9.2.2 nathanw */
278 1.9.2.2 nathanw
279 1.9.2.2 nathanw /* Do a reset to ensure sane state after warm boot. */
280 1.9.2.2 nathanw if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) {
281 1.9.2.2 nathanw /* hard reset */
282 1.9.2.2 nathanw printf("%s: controller busy, performing hardware reset ...\n",
283 1.9.2.2 nathanw sc->sc_dev.dv_xname);
284 1.9.2.2 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR,
285 1.9.2.2 nathanw BCR_INT_ENABLE|BCR_RESET);
286 1.9.2.2 nathanw } else {
287 1.9.2.2 nathanw /* "SOFT" reset */
288 1.9.2.2 nathanw edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0);
289 1.9.2.2 nathanw }
290 1.9.2.2 nathanw
291 1.9.2.2 nathanw /*
292 1.9.2.5 nathanw * Since interrupts are disabled, it's necessary
293 1.9.2.2 nathanw * to detect the interrupt request and call edc_intr()
294 1.9.2.2 nathanw * explicitly. See also edc_run_cmd().
295 1.9.2.2 nathanw */
296 1.9.2.2 nathanw while(bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) {
297 1.9.2.2 nathanw if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR)
298 1.9.2.2 nathanw edc_intr(sc);
299 1.9.2.2 nathanw
300 1.9.2.2 nathanw delay(100);
301 1.9.2.2 nathanw }
302 1.9.2.2 nathanw
303 1.9.2.4 nathanw /* be quiet during probes */
304 1.9.2.2 nathanw sc->sc_flags |= DASD_QUIET;
305 1.9.2.2 nathanw
306 1.9.2.2 nathanw /* check for attached disks */
307 1.9.2.4 nathanw for(devno=0; devno < sc->sc_maxdevs; devno++) {
308 1.9.2.4 nathanw eda.edc_drive = devno;
309 1.9.2.4 nathanw sc->sc_ed[devno] =
310 1.9.2.4 nathanw (void *) config_found_sm(self, &eda, NULL, NULL);
311 1.9.2.4 nathanw
312 1.9.2.4 nathanw /* If initialization did not succeed, NULL the pointer. */
313 1.9.2.4 nathanw if (sc->sc_ed[devno]
314 1.9.2.4 nathanw && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0)
315 1.9.2.4 nathanw sc->sc_ed[devno] = NULL;
316 1.9.2.2 nathanw }
317 1.9.2.2 nathanw
318 1.9.2.2 nathanw /* enable full error dumps again */
319 1.9.2.2 nathanw sc->sc_flags &= ~DASD_QUIET;
320 1.9.2.2 nathanw
321 1.9.2.2 nathanw /*
322 1.9.2.2 nathanw * Check if there are any disks attached. If not, disestablish
323 1.9.2.2 nathanw * the interrupt.
324 1.9.2.2 nathanw */
325 1.9.2.4 nathanw for(devno=0; devno < sc->sc_maxdevs; devno++) {
326 1.9.2.4 nathanw if (sc->sc_ed[devno])
327 1.9.2.2 nathanw break;
328 1.9.2.2 nathanw }
329 1.9.2.4 nathanw
330 1.9.2.4 nathanw if (devno == sc->sc_maxdevs) {
331 1.9.2.2 nathanw printf("%s: disabling controller (no drives attached)\n",
332 1.9.2.2 nathanw sc->sc_dev.dv_xname);
333 1.9.2.2 nathanw mca_intr_disestablish(ma->ma_mc, sc->sc_ih);
334 1.9.2.4 nathanw return;
335 1.9.2.2 nathanw }
336 1.9.2.4 nathanw
337 1.9.2.4 nathanw /*
338 1.9.2.4 nathanw * Run the worker thread.
339 1.9.2.4 nathanw */
340 1.9.2.4 nathanw config_pending_incr();
341 1.9.2.4 nathanw kthread_create(edc_spawn_worker, (void *) sc);
342 1.9.2.2 nathanw }
343 1.9.2.2 nathanw
344 1.9.2.2 nathanw void
345 1.9.2.4 nathanw edc_add_disk(sc, ed)
346 1.9.2.2 nathanw struct edc_mca_softc *sc;
347 1.9.2.2 nathanw struct ed_softc *ed;
348 1.9.2.2 nathanw {
349 1.9.2.4 nathanw sc->sc_ed[ed->sc_devno] = ed;
350 1.9.2.2 nathanw }
351 1.9.2.2 nathanw
352 1.9.2.2 nathanw static int
353 1.9.2.2 nathanw edc_intr(arg)
354 1.9.2.2 nathanw void *arg;
355 1.9.2.2 nathanw {
356 1.9.2.2 nathanw struct edc_mca_softc *sc = arg;
357 1.9.2.2 nathanw u_int8_t isr, intr_id;
358 1.9.2.2 nathanw u_int16_t sifr;
359 1.9.2.5 nathanw int cmd=-1, devno;
360 1.9.2.2 nathanw
361 1.9.2.2 nathanw /*
362 1.9.2.2 nathanw * Check if the interrupt was for us.
363 1.9.2.2 nathanw */
364 1.9.2.2 nathanw if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0)
365 1.9.2.2 nathanw return (0);
366 1.9.2.2 nathanw
367 1.9.2.2 nathanw /*
368 1.9.2.2 nathanw * Read ISR to find out interrupt type. This also clears the interrupt
369 1.9.2.2 nathanw * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2
370 1.9.2.2 nathanw * and 4 are reserved and not used.
371 1.9.2.2 nathanw */
372 1.9.2.2 nathanw isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR);
373 1.9.2.2 nathanw intr_id = isr & ISR_INTR_ID_MASK;
374 1.9.2.2 nathanw
375 1.9.2.5 nathanw #ifdef EDC_DEBUG
376 1.9.2.2 nathanw if (intr_id == 0 || intr_id == 2 || intr_id == 4) {
377 1.9.2.2 nathanw printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname,
378 1.9.2.2 nathanw (int) intr_id);
379 1.9.2.2 nathanw return (0);
380 1.9.2.2 nathanw }
381 1.9.2.2 nathanw #endif
382 1.9.2.2 nathanw
383 1.9.2.2 nathanw /* Get number of device whose intr this was */
384 1.9.2.2 nathanw devno = (isr & 0xe0) >> 5;
385 1.9.2.2 nathanw
386 1.9.2.2 nathanw /*
387 1.9.2.2 nathanw * Get Status block. Higher byte always says how long the status
388 1.9.2.2 nathanw * block is, rest is device number and command code.
389 1.9.2.2 nathanw * Check the status block length against our supported maximum length
390 1.9.2.2 nathanw * and fetch the data.
391 1.9.2.2 nathanw */
392 1.9.2.2 nathanw if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) {
393 1.9.2.2 nathanw size_t len;
394 1.9.2.2 nathanw int i;
395 1.9.2.2 nathanw
396 1.9.2.2 nathanw sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR));
397 1.9.2.2 nathanw len = (sifr & 0xff00) >> 8;
398 1.9.2.2 nathanw #ifdef DEBUG
399 1.9.2.4 nathanw if (len > EDC_MAX_CMD_RES_LEN)
400 1.9.2.2 nathanw panic("%s: maximum Status Length exceeded: %d > %d",
401 1.9.2.2 nathanw sc->sc_dev.dv_xname,
402 1.9.2.4 nathanw len, EDC_MAX_CMD_RES_LEN);
403 1.9.2.2 nathanw #endif
404 1.9.2.2 nathanw
405 1.9.2.2 nathanw /* Get command code */
406 1.9.2.2 nathanw cmd = sifr & SIFR_CMD_MASK;
407 1.9.2.2 nathanw
408 1.9.2.2 nathanw /* Read whole status block */
409 1.9.2.5 nathanw sc->status_block[0] = sifr;
410 1.9.2.2 nathanw for(i=1; i < len; i++) {
411 1.9.2.2 nathanw while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
412 1.9.2.2 nathanw & BSR_SIFR_FULL) == 0)
413 1.9.2.5 nathanw ;
414 1.9.2.2 nathanw
415 1.9.2.5 nathanw sc->status_block[i] = le16toh(
416 1.9.2.2 nathanw bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR));
417 1.9.2.2 nathanw }
418 1.9.2.5 nathanw /* zero out rest */
419 1.9.2.5 nathanw if (i < EDC_MAX_CMD_RES_LEN) {
420 1.9.2.5 nathanw memset(&sc->status_block[i], 0,
421 1.9.2.5 nathanw (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t));
422 1.9.2.5 nathanw }
423 1.9.2.2 nathanw }
424 1.9.2.2 nathanw
425 1.9.2.2 nathanw switch (intr_id) {
426 1.9.2.2 nathanw case ISR_DATA_TRANSFER_RDY:
427 1.9.2.2 nathanw /*
428 1.9.2.4 nathanw * Ready to do DMA. The DMA controller has already been
429 1.9.2.4 nathanw * setup, now just kick disk controller to do the transfer.
430 1.9.2.2 nathanw */
431 1.9.2.4 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR,
432 1.9.2.4 nathanw BCR_INT_ENABLE|BCR_DMA_ENABLE);
433 1.9.2.2 nathanw break;
434 1.9.2.5 nathanw
435 1.9.2.2 nathanw case ISR_COMPLETED:
436 1.9.2.2 nathanw case ISR_COMPLETED_WITH_ECC:
437 1.9.2.2 nathanw case ISR_COMPLETED_RETRIES:
438 1.9.2.2 nathanw case ISR_COMPLETED_WARNING:
439 1.9.2.4 nathanw /*
440 1.9.2.4 nathanw * Copy device config data if appropriate. sc->sc_ed[]
441 1.9.2.4 nathanw * entry might be NULL during probe.
442 1.9.2.4 nathanw */
443 1.9.2.4 nathanw if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) {
444 1.9.2.5 nathanw memcpy(sc->sc_ed[devno]->sense_data, sc->status_block,
445 1.9.2.4 nathanw sizeof(sc->sc_ed[devno]->sense_data));
446 1.9.2.4 nathanw }
447 1.9.2.4 nathanw
448 1.9.2.5 nathanw sc->sc_stat = STAT_DONE;
449 1.9.2.2 nathanw break;
450 1.9.2.5 nathanw
451 1.9.2.2 nathanw case ISR_RESET_COMPLETED:
452 1.9.2.2 nathanw case ISR_ABORT_COMPLETED:
453 1.9.2.2 nathanw /* nothing to do */
454 1.9.2.2 nathanw break;
455 1.9.2.5 nathanw
456 1.9.2.5 nathanw case ISR_ATTN_ERROR:
457 1.9.2.5 nathanw /*
458 1.9.2.5 nathanw * Basically, this means driver bug or something seriously
459 1.9.2.5 nathanw * hosed. panic rather than extending the lossage.
460 1.9.2.5 nathanw * No status block available, so no further info.
461 1.9.2.5 nathanw */
462 1.9.2.5 nathanw panic("%s: dev %d: attention error",
463 1.9.2.5 nathanw sc->sc_dev.dv_xname,
464 1.9.2.5 nathanw devno);
465 1.9.2.5 nathanw /* NOTREACHED */
466 1.9.2.5 nathanw break;
467 1.9.2.5 nathanw
468 1.9.2.2 nathanw default:
469 1.9.2.2 nathanw if ((sc->sc_flags & DASD_QUIET) == 0)
470 1.9.2.5 nathanw edc_dump_status_block(sc, sc->status_block, intr_id);
471 1.9.2.2 nathanw
472 1.9.2.5 nathanw sc->sc_stat = STAT_ERROR;
473 1.9.2.2 nathanw break;
474 1.9.2.2 nathanw }
475 1.9.2.2 nathanw
476 1.9.2.2 nathanw /*
477 1.9.2.2 nathanw * Unless the interrupt is for Data Transfer Ready or
478 1.9.2.2 nathanw * Attention Error, finish by assertion EOI. This makes
479 1.9.2.2 nathanw * attachment aware the interrupt is processed and system
480 1.9.2.2 nathanw * is ready to accept another one.
481 1.9.2.2 nathanw */
482 1.9.2.2 nathanw if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR)
483 1.9.2.2 nathanw edc_do_attn(sc, ATN_END_INT, devno, intr_id);
484 1.9.2.2 nathanw
485 1.9.2.2 nathanw /* If Read or Write Data, wakeup worker thread to finish it */
486 1.9.2.5 nathanw if (intr_id != ISR_DATA_TRANSFER_RDY) {
487 1.9.2.5 nathanw if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA)
488 1.9.2.5 nathanw sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX];
489 1.9.2.4 nathanw wakeup_one(sc);
490 1.9.2.2 nathanw }
491 1.9.2.2 nathanw
492 1.9.2.2 nathanw return (1);
493 1.9.2.2 nathanw }
494 1.9.2.2 nathanw
495 1.9.2.2 nathanw /*
496 1.9.2.2 nathanw * This follows the exact order for Attention Request as
497 1.9.2.2 nathanw * written in DASD Storage Interface Specification MC (Rev 2.2).
498 1.9.2.2 nathanw */
499 1.9.2.2 nathanw static int
500 1.9.2.2 nathanw edc_do_attn(sc, attn_type, devno, intr_id)
501 1.9.2.2 nathanw struct edc_mca_softc *sc;
502 1.9.2.2 nathanw int attn_type, devno, intr_id;
503 1.9.2.2 nathanw {
504 1.9.2.2 nathanw int tries;
505 1.9.2.2 nathanw
506 1.9.2.2 nathanw /* 1. Disable interrupts in BCR. */
507 1.9.2.2 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0);
508 1.9.2.2 nathanw
509 1.9.2.2 nathanw /*
510 1.9.2.2 nathanw * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging
511 1.9.2.2 nathanw * a RESET COMPLETED interrupt.
512 1.9.2.2 nathanw */
513 1.9.2.2 nathanw if (intr_id != ISR_RESET_COMPLETED) {
514 1.9.2.5 nathanw #ifdef EDC_DEBUG
515 1.9.2.5 nathanw if (attn_type == ATN_CMD_REQ
516 1.9.2.5 nathanw && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
517 1.9.2.5 nathanw & BSR_INT_PENDING))
518 1.9.2.5 nathanw panic("%s: edc int pending", sc->sc_dev.dv_xname);
519 1.9.2.5 nathanw #endif
520 1.9.2.5 nathanw
521 1.9.2.2 nathanw for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) {
522 1.9.2.2 nathanw if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
523 1.9.2.5 nathanw & BSR_BUSY) == 0)
524 1.9.2.2 nathanw break;
525 1.9.2.2 nathanw }
526 1.9.2.2 nathanw
527 1.9.2.2 nathanw if (tries == EDC_ATTN_MAXTRIES) {
528 1.9.2.2 nathanw printf("%s: edc_do_attn: timeout waiting for attachment to become available\n",
529 1.9.2.2 nathanw sc->sc_ed[devno]->sc_dev.dv_xname);
530 1.9.2.5 nathanw return (EIO);
531 1.9.2.2 nathanw }
532 1.9.2.2 nathanw }
533 1.9.2.2 nathanw
534 1.9.2.2 nathanw /*
535 1.9.2.2 nathanw * 3. Write proper DEVICE NUMBER and Attention number to ATN.
536 1.9.2.2 nathanw */
537 1.9.2.5 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5));
538 1.9.2.2 nathanw
539 1.9.2.2 nathanw /*
540 1.9.2.2 nathanw * 4. Enable interrupts via BCR.
541 1.9.2.2 nathanw */
542 1.9.2.2 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE);
543 1.9.2.2 nathanw
544 1.9.2.2 nathanw return (0);
545 1.9.2.2 nathanw }
546 1.9.2.2 nathanw
547 1.9.2.2 nathanw /*
548 1.9.2.2 nathanw * Wait until command is processed, timeout after 'secs' seconds.
549 1.9.2.2 nathanw * We use mono_time, since we don't need actual RTC, just time
550 1.9.2.2 nathanw * interval.
551 1.9.2.2 nathanw */
552 1.9.2.5 nathanw static void
553 1.9.2.4 nathanw edc_cmd_wait(sc, secs, poll)
554 1.9.2.2 nathanw struct edc_mca_softc *sc;
555 1.9.2.4 nathanw int secs, poll;
556 1.9.2.2 nathanw {
557 1.9.2.5 nathanw int val;
558 1.9.2.2 nathanw
559 1.9.2.4 nathanw if (!poll) {
560 1.9.2.5 nathanw int s;
561 1.9.2.4 nathanw
562 1.9.2.4 nathanw /* Not polling, can sleep. Sleep until we are awakened,
563 1.9.2.4 nathanw * but maximum secs seconds.
564 1.9.2.4 nathanw */
565 1.9.2.5 nathanw s = splbio();
566 1.9.2.5 nathanw if (sc->sc_stat != STAT_DONE)
567 1.9.2.5 nathanw (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz);
568 1.9.2.5 nathanw splx(s);
569 1.9.2.4 nathanw }
570 1.9.2.4 nathanw
571 1.9.2.5 nathanw /* Wait until the command is completely finished */
572 1.9.2.5 nathanw while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR))
573 1.9.2.5 nathanw & BSR_CMD_INPROGRESS) {
574 1.9.2.5 nathanw if (poll && (val & BSR_INTR))
575 1.9.2.5 nathanw edc_intr(sc);
576 1.9.2.2 nathanw }
577 1.9.2.2 nathanw }
578 1.9.2.5 nathanw
579 1.9.2.5 nathanw /*
580 1.9.2.5 nathanw * Command controller to execute specified command on a device.
581 1.9.2.5 nathanw */
582 1.9.2.2 nathanw int
583 1.9.2.4 nathanw edc_run_cmd(sc, cmd, devno, cmd_args, cmd_len, poll)
584 1.9.2.2 nathanw struct edc_mca_softc *sc;
585 1.9.2.2 nathanw int cmd;
586 1.9.2.2 nathanw int devno;
587 1.9.2.2 nathanw u_int16_t cmd_args[];
588 1.9.2.4 nathanw int cmd_len, poll;
589 1.9.2.2 nathanw {
590 1.9.2.2 nathanw int i, error, tries;
591 1.9.2.2 nathanw u_int16_t cmd0;
592 1.9.2.2 nathanw
593 1.9.2.5 nathanw sc->sc_stat = STAT_START;
594 1.9.2.2 nathanw
595 1.9.2.2 nathanw /* Do Attention Request for Command Request. */
596 1.9.2.2 nathanw if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0)))
597 1.9.2.2 nathanw return (error);
598 1.9.2.2 nathanw
599 1.9.2.2 nathanw /*
600 1.9.2.2 nathanw * Construct the command. The bits are like this:
601 1.9.2.2 nathanw *
602 1.9.2.2 nathanw * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
603 1.9.2.2 nathanw * \_/ 0 0 1 0 \__/ \_____/
604 1.9.2.2 nathanw * \ \__________/ \ \_ Command Code (see CMD_*)
605 1.9.2.2 nathanw * \ \ \__ Device: 0 common, 7 controller
606 1.9.2.2 nathanw * \ \__ Options: reserved, bit 10=cache bypass bit
607 1.9.2.2 nathanw * \_ Type: 00=2B, 01=4B, 10 and 11 reserved
608 1.9.2.2 nathanw *
609 1.9.2.2 nathanw * We always use device 0 or 1, so difference is made only by Command
610 1.9.2.2 nathanw * Code, Command Options and command length.
611 1.9.2.2 nathanw */
612 1.9.2.2 nathanw cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0)
613 1.9.2.2 nathanw | (devno << 5)
614 1.9.2.2 nathanw | (cmd_args[0] << 8) | cmd;
615 1.9.2.2 nathanw cmd_args[0] = cmd0;
616 1.9.2.2 nathanw
617 1.9.2.2 nathanw /*
618 1.9.2.2 nathanw * Write word of CMD to the CIFR. This sets "Command
619 1.9.2.2 nathanw * Interface Register Full (CMD IN)" in BSR. Once the attachment
620 1.9.2.4 nathanw * detects it, it reads the word and clears CMD IN. This all should
621 1.9.2.5 nathanw * be quite fast, so don't sleep in !poll case neither.
622 1.9.2.2 nathanw */
623 1.9.2.2 nathanw for(i=0; i < cmd_len; i++) {
624 1.9.2.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR,
625 1.9.2.2 nathanw htole16(cmd_args[i]));
626 1.9.2.2 nathanw
627 1.9.2.5 nathanw /* Wait until CMD IN is cleared. */
628 1.9.2.2 nathanw tries = 0;
629 1.9.2.4 nathanw for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
630 1.9.2.5 nathanw & BSR_CIFR_FULL) && tries < 10000 ; tries++)
631 1.9.2.2 nathanw delay(poll ? 1000 : 1);
632 1.9.2.5 nathanw ;
633 1.9.2.2 nathanw
634 1.9.2.5 nathanw if (tries == 10000
635 1.9.2.5 nathanw && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
636 1.9.2.5 nathanw & BSR_CIFR_FULL) {
637 1.9.2.4 nathanw printf("%s: device too slow to accept command %d\n",
638 1.9.2.4 nathanw sc->sc_dev.dv_xname, cmd);
639 1.9.2.5 nathanw return (EIO);
640 1.9.2.4 nathanw }
641 1.9.2.2 nathanw }
642 1.9.2.2 nathanw
643 1.9.2.2 nathanw /* Wait for command to complete, but maximum 15 seconds. */
644 1.9.2.5 nathanw edc_cmd_wait(sc, 15, poll);
645 1.9.2.2 nathanw
646 1.9.2.5 nathanw return ((sc->sc_stat != STAT_DONE) ? EIO : 0);
647 1.9.2.2 nathanw }
648 1.9.2.2 nathanw
649 1.9.2.4 nathanw #ifdef EDC_DEBUG
650 1.9.2.2 nathanw static const char * const edc_commands[] = {
651 1.9.2.2 nathanw "Invalid Command",
652 1.9.2.2 nathanw "Read Data",
653 1.9.2.2 nathanw "Write Data",
654 1.9.2.2 nathanw "Read Verify",
655 1.9.2.2 nathanw "Write with Verify",
656 1.9.2.2 nathanw "Seek",
657 1.9.2.2 nathanw "Park Head",
658 1.9.2.2 nathanw "Get Command Complete Status",
659 1.9.2.2 nathanw "Get Device Status",
660 1.9.2.2 nathanw "Get Device Configuration",
661 1.9.2.2 nathanw "Get POS Information",
662 1.9.2.2 nathanw "Translate RBA",
663 1.9.2.2 nathanw "Write Attachment Buffer",
664 1.9.2.2 nathanw "Read Attachment Buffer",
665 1.9.2.2 nathanw "Run Diagnostic Test",
666 1.9.2.2 nathanw "Get Diagnostic Status Block",
667 1.9.2.2 nathanw "Get MFG Header",
668 1.9.2.2 nathanw "Format Unit",
669 1.9.2.2 nathanw "Format Prepare",
670 1.9.2.2 nathanw "Set MAX RBA",
671 1.9.2.2 nathanw "Set Power Saving Mode",
672 1.9.2.2 nathanw "Power Conservation Command",
673 1.9.2.2 nathanw };
674 1.9.2.2 nathanw
675 1.9.2.2 nathanw static const char * const edc_cmd_status[256] = {
676 1.9.2.2 nathanw "Reserved",
677 1.9.2.2 nathanw "Command completed successfully",
678 1.9.2.2 nathanw "Reserved",
679 1.9.2.2 nathanw "Command completed successfully with ECC applied",
680 1.9.2.2 nathanw "Reserved",
681 1.9.2.2 nathanw "Command completed successfully with retries",
682 1.9.2.2 nathanw "Format Command partially completed", /* Status available */
683 1.9.2.2 nathanw "Command completed successfully with ECC and retries",
684 1.9.2.2 nathanw "Command completed with Warning", /* Command Error is available */
685 1.9.2.2 nathanw "Aborted",
686 1.9.2.2 nathanw "Reset completed",
687 1.9.2.2 nathanw "Data Transfer Ready", /* No Status Block available */
688 1.9.2.2 nathanw "Command terminated with failure", /* Device Error is available */
689 1.9.2.2 nathanw "DMA Error", /* Retry entire command as recovery */
690 1.9.2.2 nathanw "Command Block Error",
691 1.9.2.2 nathanw "Attention Error (Illegal Attention Code)",
692 1.9.2.2 nathanw /* 0x14 - 0xff reserved */
693 1.9.2.2 nathanw };
694 1.9.2.2 nathanw
695 1.9.2.2 nathanw static const char * const edc_cmd_error[256] = {
696 1.9.2.2 nathanw "No Error",
697 1.9.2.2 nathanw "Invalid parameter in the command block",
698 1.9.2.2 nathanw "Reserved",
699 1.9.2.2 nathanw "Command not supported",
700 1.9.2.2 nathanw "Command Aborted per request",
701 1.9.2.2 nathanw "Reserved",
702 1.9.2.2 nathanw "Command rejected", /* Attachment diagnostic failure */
703 1.9.2.2 nathanw "Format Rejected", /* Prepare Format command is required */
704 1.9.2.2 nathanw "Format Error (Primary Map is not readable)",
705 1.9.2.2 nathanw "Format Error (Secondary map is not readable)",
706 1.9.2.2 nathanw "Format Error (Diagnostic Failure)",
707 1.9.2.2 nathanw "Format Warning (Secondary Map Overflow)",
708 1.9.2.2 nathanw "Reserved"
709 1.9.2.2 nathanw "Format Error (Host Checksum Error)",
710 1.9.2.2 nathanw "Reserved",
711 1.9.2.2 nathanw "Format Warning (Push table overflow)",
712 1.9.2.2 nathanw "Format Warning (More pushes than allowed)",
713 1.9.2.2 nathanw "Reserved",
714 1.9.2.2 nathanw "Format Warning (Error during verifying)",
715 1.9.2.2 nathanw "Invalid device number for the command",
716 1.9.2.2 nathanw /* 0x14-0xff reserved */
717 1.9.2.2 nathanw };
718 1.9.2.2 nathanw
719 1.9.2.2 nathanw static const char * const edc_dev_errors[] = {
720 1.9.2.2 nathanw "No Error",
721 1.9.2.2 nathanw "Seek Fault", /* Device report */
722 1.9.2.2 nathanw "Interface Fault (Parity, Attn, or Cmd Complete Error)",
723 1.9.2.2 nathanw "Block not found (ID not found)",
724 1.9.2.2 nathanw "Block not found (AM not found)",
725 1.9.2.2 nathanw "Data ECC Error (hard error)",
726 1.9.2.2 nathanw "ID CRC Error",
727 1.9.2.2 nathanw "RBA Out of Range",
728 1.9.2.2 nathanw "Reserved",
729 1.9.2.2 nathanw "Defective Block",
730 1.9.2.2 nathanw "Reserved",
731 1.9.2.2 nathanw "Selection Error",
732 1.9.2.2 nathanw "Reserved",
733 1.9.2.2 nathanw "Write Fault",
734 1.9.2.2 nathanw "No index or sector pulse",
735 1.9.2.2 nathanw "Device Not Ready",
736 1.9.2.2 nathanw "Seek Error", /* Attachment report */
737 1.9.2.2 nathanw "Bad Format",
738 1.9.2.2 nathanw "Volume Overflow",
739 1.9.2.2 nathanw "No Data AM Found",
740 1.9.2.2 nathanw "Block not found (No ID AM or ID CRC error occurred)",
741 1.9.2.2 nathanw "Reserved",
742 1.9.2.2 nathanw "Reserved",
743 1.9.2.2 nathanw "No ID found on track (ID search)",
744 1.9.2.2 nathanw /* 0x19 - 0xff reserved */
745 1.9.2.2 nathanw };
746 1.9.2.4 nathanw #endif /* EDC_DEBUG */
747 1.9.2.2 nathanw
748 1.9.2.2 nathanw static void
749 1.9.2.4 nathanw edc_dump_status_block(sc, status_block, intr_id)
750 1.9.2.2 nathanw struct edc_mca_softc *sc;
751 1.9.2.4 nathanw u_int16_t *status_block;
752 1.9.2.4 nathanw int intr_id;
753 1.9.2.2 nathanw {
754 1.9.2.4 nathanw #ifdef EDC_DEBUG
755 1.9.2.5 nathanw printf("%s: Command: %s, Status: %s (intr %d)\n",
756 1.9.2.4 nathanw sc->sc_dev.dv_xname,
757 1.9.2.4 nathanw edc_commands[status_block[0] & 0x1f],
758 1.9.2.5 nathanw edc_cmd_status[SB_GET_CMD_STATUS(status_block)],
759 1.9.2.5 nathanw intr_id
760 1.9.2.2 nathanw );
761 1.9.2.4 nathanw #else
762 1.9.2.5 nathanw printf("%s: Command: %d, Status: %d (intr %d)\n",
763 1.9.2.4 nathanw sc->sc_dev.dv_xname,
764 1.9.2.4 nathanw status_block[0] & 0x1f,
765 1.9.2.5 nathanw SB_GET_CMD_STATUS(status_block),
766 1.9.2.5 nathanw intr_id
767 1.9.2.5 nathanw );
768 1.9.2.4 nathanw #endif
769 1.9.2.2 nathanw printf("%s: # left blocks: %u, last processed RBA: %u\n",
770 1.9.2.4 nathanw sc->sc_dev.dv_xname,
771 1.9.2.4 nathanw status_block[SB_RESBLKCNT_IDX],
772 1.9.2.4 nathanw (status_block[5] << 16) | status_block[4]);
773 1.9.2.2 nathanw
774 1.9.2.2 nathanw if (intr_id == ISR_COMPLETED_WARNING) {
775 1.9.2.4 nathanw #ifdef EDC_DEBUG
776 1.9.2.2 nathanw printf("%s: Command Error Code: %s\n",
777 1.9.2.4 nathanw sc->sc_dev.dv_xname,
778 1.9.2.4 nathanw edc_cmd_error[status_block[1] & 0xff]);
779 1.9.2.4 nathanw #else
780 1.9.2.4 nathanw printf("%s: Command Error Code: %d\n",
781 1.9.2.4 nathanw sc->sc_dev.dv_xname,
782 1.9.2.4 nathanw status_block[1] & 0xff);
783 1.9.2.4 nathanw #endif
784 1.9.2.2 nathanw }
785 1.9.2.2 nathanw
786 1.9.2.2 nathanw if (intr_id == ISR_CMD_FAILED) {
787 1.9.2.4 nathanw #ifdef EDC_DEBUG
788 1.9.2.2 nathanw char buf[100];
789 1.9.2.2 nathanw
790 1.9.2.2 nathanw printf("%s: Device Error Code: %s\n",
791 1.9.2.4 nathanw sc->sc_dev.dv_xname,
792 1.9.2.4 nathanw edc_dev_errors[status_block[2] & 0xff]);
793 1.9.2.4 nathanw bitmask_snprintf((status_block[2] & 0xff00) >> 8,
794 1.9.2.2 nathanw "\20"
795 1.9.2.2 nathanw "\01SeekOrCmdComplete"
796 1.9.2.2 nathanw "\02Track0Flag"
797 1.9.2.2 nathanw "\03WriteFault"
798 1.9.2.2 nathanw "\04Selected"
799 1.9.2.2 nathanw "\05Ready"
800 1.9.2.2 nathanw "\06Reserved0"
801 1.9.2.2 nathanw "\07STANDBY"
802 1.9.2.2 nathanw "\010Reserved0",
803 1.9.2.2 nathanw buf, sizeof(buf));
804 1.9.2.2 nathanw printf("%s: Device Status: %s\n",
805 1.9.2.4 nathanw sc->sc_dev.dv_xname, buf);
806 1.9.2.4 nathanw #else
807 1.9.2.4 nathanw printf("%s: Device Error Code: %d, Device Status: %d\n",
808 1.9.2.4 nathanw sc->sc_dev.dv_xname,
809 1.9.2.4 nathanw status_block[2] & 0xff,
810 1.9.2.4 nathanw (status_block[2] & 0xff00) >> 8);
811 1.9.2.4 nathanw #endif
812 1.9.2.4 nathanw }
813 1.9.2.4 nathanw }
814 1.9.2.4 nathanw
815 1.9.2.4 nathanw static void
816 1.9.2.4 nathanw edc_spawn_worker(arg)
817 1.9.2.4 nathanw void *arg;
818 1.9.2.4 nathanw {
819 1.9.2.4 nathanw struct edc_mca_softc *sc = (struct edc_mca_softc *) arg;
820 1.9.2.4 nathanw int error;
821 1.9.2.4 nathanw struct proc *wrk;
822 1.9.2.4 nathanw
823 1.9.2.4 nathanw /* Now, everything is ready, start a kthread */
824 1.9.2.4 nathanw if ((error = kthread_create1(edcworker, sc, &wrk,
825 1.9.2.4 nathanw "%s", sc->sc_dev.dv_xname))) {
826 1.9.2.4 nathanw printf("%s: cannot spawn worker thread: errno=%d\n",
827 1.9.2.4 nathanw sc->sc_dev.dv_xname, error);
828 1.9.2.4 nathanw panic("edc_spawn_worker");
829 1.9.2.2 nathanw }
830 1.9.2.2 nathanw }
831 1.9.2.4 nathanw
832 1.9.2.4 nathanw /*
833 1.9.2.4 nathanw * Main worker thread function.
834 1.9.2.4 nathanw */
835 1.9.2.4 nathanw void
836 1.9.2.4 nathanw edcworker(arg)
837 1.9.2.4 nathanw void *arg;
838 1.9.2.4 nathanw {
839 1.9.2.4 nathanw struct edc_mca_softc *sc = (struct edc_mca_softc *) arg;
840 1.9.2.4 nathanw struct ed_softc *ed;
841 1.9.2.4 nathanw struct buf *bp;
842 1.9.2.5 nathanw int i, error;
843 1.9.2.4 nathanw
844 1.9.2.4 nathanw config_pending_decr();
845 1.9.2.4 nathanw
846 1.9.2.4 nathanw for(;;) {
847 1.9.2.4 nathanw /* Wait until awakened */
848 1.9.2.4 nathanw (void) tsleep(sc, PRIBIO, "edcidle", 0);
849 1.9.2.4 nathanw
850 1.9.2.4 nathanw for(i=0; i<sc->sc_maxdevs; ) {
851 1.9.2.4 nathanw if ((ed = sc->sc_ed[i]) == NULL) {
852 1.9.2.4 nathanw i++;
853 1.9.2.4 nathanw continue;
854 1.9.2.4 nathanw }
855 1.9.2.4 nathanw
856 1.9.2.4 nathanw /* Is there a buf for us ? */
857 1.9.2.4 nathanw simple_lock(&ed->sc_q_lock);
858 1.9.2.4 nathanw if ((bp = BUFQ_FIRST(&ed->sc_q)) == NULL) {
859 1.9.2.4 nathanw simple_unlock(&ed->sc_q_lock);
860 1.9.2.4 nathanw i++;
861 1.9.2.4 nathanw continue;
862 1.9.2.4 nathanw }
863 1.9.2.4 nathanw BUFQ_REMOVE(&ed->sc_q, bp);
864 1.9.2.4 nathanw simple_unlock(&ed->sc_q_lock);
865 1.9.2.4 nathanw
866 1.9.2.4 nathanw /* Instrumentation. */
867 1.9.2.4 nathanw disk_busy(&ed->sc_dk);
868 1.9.2.4 nathanw
869 1.9.2.4 nathanw error = edc_bio(sc, ed, bp->b_data, bp->b_bcount,
870 1.9.2.4 nathanw bp->b_rawblkno, (bp->b_flags & B_READ), 0);
871 1.9.2.4 nathanw
872 1.9.2.4 nathanw if (error) {
873 1.9.2.4 nathanw bp->b_error = error;
874 1.9.2.4 nathanw bp->b_flags |= B_ERROR;
875 1.9.2.4 nathanw } else {
876 1.9.2.4 nathanw /* Set resid, most commonly to zero. */
877 1.9.2.4 nathanw bp->b_resid = sc->sc_resblk * DEV_BSIZE;
878 1.9.2.4 nathanw }
879 1.9.2.4 nathanw
880 1.9.2.4 nathanw disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid));
881 1.9.2.4 nathanw #if NRND > 0
882 1.9.2.4 nathanw rnd_add_uint32(&ed->rnd_source, bp->b_blkno);
883 1.9.2.4 nathanw #endif
884 1.9.2.4 nathanw biodone(bp);
885 1.9.2.4 nathanw }
886 1.9.2.4 nathanw }
887 1.9.2.4 nathanw }
888 1.9.2.4 nathanw
889 1.9.2.4 nathanw int
890 1.9.2.4 nathanw edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data,
891 1.9.2.4 nathanw size_t bcount, daddr_t rawblkno, int isread, int poll)
892 1.9.2.4 nathanw {
893 1.9.2.4 nathanw u_int16_t cmd_args[4];
894 1.9.2.4 nathanw int error=0, fl;
895 1.9.2.4 nathanw u_int16_t track;
896 1.9.2.4 nathanw u_int16_t cyl;
897 1.9.2.4 nathanw u_int8_t head;
898 1.9.2.4 nathanw u_int8_t sector;
899 1.9.2.4 nathanw
900 1.9.2.4 nathanw mca_disk_busy();
901 1.9.2.4 nathanw
902 1.9.2.4 nathanw /* set WAIT and R/W flag appropriately for the DMA transfer */
903 1.9.2.4 nathanw fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK)
904 1.9.2.4 nathanw | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE);
905 1.9.2.4 nathanw
906 1.9.2.4 nathanw /* Load the buffer for DMA transfer. */
907 1.9.2.4 nathanw if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data,
908 1.9.2.4 nathanw bcount, NULL, BUS_DMA_STREAMING|fl))) {
909 1.9.2.4 nathanw printf("%s: ed_bio: unable to load DMA buffer - error %d\n",
910 1.9.2.4 nathanw ed->sc_dev.dv_xname, error);
911 1.9.2.4 nathanw goto out;
912 1.9.2.4 nathanw }
913 1.9.2.4 nathanw
914 1.9.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0,
915 1.9.2.4 nathanw bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
916 1.9.2.4 nathanw
917 1.9.2.4 nathanw track = rawblkno / ed->sectors;
918 1.9.2.4 nathanw head = track % ed->heads;
919 1.9.2.4 nathanw cyl = track / ed->heads;
920 1.9.2.4 nathanw sector = rawblkno % ed->sectors;
921 1.9.2.4 nathanw
922 1.9.2.4 nathanw /* Read or Write Data command */
923 1.9.2.4 nathanw cmd_args[0] = 2; /* Options 0000010 */
924 1.9.2.4 nathanw cmd_args[1] = bcount / DEV_BSIZE;
925 1.9.2.4 nathanw cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector;
926 1.9.2.4 nathanw cmd_args[3] = ((cyl & 0x3E0) >> 5);
927 1.9.2.4 nathanw error = edc_run_cmd(sc,
928 1.9.2.4 nathanw (isread) ? CMD_READ_DATA : CMD_WRITE_DATA,
929 1.9.2.4 nathanw ed->sc_devno, cmd_args, 4, poll);
930 1.9.2.4 nathanw
931 1.9.2.4 nathanw /* Sync the DMA memory */
932 1.9.2.4 nathanw if (!error) {
933 1.9.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount,
934 1.9.2.4 nathanw (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
935 1.9.2.4 nathanw }
936 1.9.2.4 nathanw
937 1.9.2.4 nathanw /* We are done, unload buffer from DMA map */
938 1.9.2.4 nathanw bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer);
939 1.9.2.4 nathanw
940 1.9.2.4 nathanw out:
941 1.9.2.4 nathanw mca_disk_unbusy();
942 1.9.2.4 nathanw
943 1.9.2.4 nathanw return (error);
944 1.9.2.4 nathanw }
945