edc_mca.c revision 1.45.6.1
1 /* $NetBSD: edc_mca.c,v 1.45.6.1 2012/02/18 07:34:31 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 34 * spec. 35 * 36 * The driver was written with DASD Storage Interface Specification 37 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st (at) epcc.ed.ac.uk>. 38 * 39 * TODO: 40 * - improve error recovery 41 * Issue soft reset on error or timeout? 42 * - test with > 1 disk (this is supported by some controllers) 43 * - test with > 1 ESDI controller in machine; shared interrupts 44 * necessary for this to work should be supported - edc_intr() specifically 45 * checks if the interrupt is for this controller 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.45.6.1 2012/02/18 07:34:31 mrg Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/buf.h> 54 #include <sys/bufq.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/endian.h> 59 #include <sys/disklabel.h> 60 #include <sys/disk.h> 61 #include <sys/syslog.h> 62 #include <sys/proc.h> 63 #include <sys/vnode.h> 64 #include <sys/kernel.h> 65 #include <sys/kthread.h> 66 #include <sys/rnd.h> 67 68 #include <sys/bus.h> 69 #include <sys/intr.h> 70 71 #include <dev/mca/mcareg.h> 72 #include <dev/mca/mcavar.h> 73 #include <dev/mca/mcadevs.h> 74 75 #include <dev/mca/edcreg.h> 76 #include <dev/mca/edvar.h> 77 #include <dev/mca/edcvar.h> 78 79 #include "locators.h" 80 81 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 82 #define EDC_MAX_CMD_RES_LEN 8 83 84 struct edc_mca_softc { 85 struct device sc_dev; 86 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 90 /* DMA related stuff */ 91 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 92 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 93 94 void *sc_ih; /* interrupt handle */ 95 96 int sc_flags; 97 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 98 99 #define DASD_MAXDEVS 8 100 struct ed_softc *sc_ed[DASD_MAXDEVS]; 101 int sc_maxdevs; /* max number of disks attached to this 102 * controller */ 103 104 /* I/O results variables */ 105 volatile int sc_stat; 106 #define STAT_START 0 107 #define STAT_ERROR 1 108 #define STAT_DONE 2 109 volatile int sc_resblk; /* residual block count */ 110 111 /* CMD status block - only set & used in edc_intr() */ 112 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 113 }; 114 115 int edc_mca_probe(device_t, cfdata_t, void *); 116 void edc_mca_attach(device_t, device_t, void *); 117 118 CFATTACH_DECL(edc_mca, sizeof(struct edc_mca_softc), 119 edc_mca_probe, edc_mca_attach, NULL, NULL); 120 121 static int edc_intr(void *); 122 static void edc_dump_status_block(struct edc_mca_softc *, 123 u_int16_t *, int); 124 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 125 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 126 static void edcworker(void *); 127 128 int 129 edc_mca_probe(device_t parent, cfdata_t match, 130 void *aux) 131 { 132 struct mca_attach_args *ma = aux; 133 134 switch (ma->ma_id) { 135 case MCA_PRODUCT_IBM_ESDIC: 136 case MCA_PRODUCT_IBM_ESDIC_IG: 137 return (1); 138 default: 139 return (0); 140 } 141 } 142 143 void 144 edc_mca_attach(device_t parent, device_t self, void *aux) 145 { 146 struct edc_mca_softc *sc = device_private(self); 147 struct mca_attach_args *ma = aux; 148 struct ed_attach_args eda; 149 int pos2, pos3, pos4; 150 int irq, drq, iobase; 151 const char *typestr; 152 int devno, error; 153 int locs[EDCCF_NLOCS]; 154 155 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 156 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 157 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 158 159 /* 160 * POS register 2: (adf pos0) 161 * 162 * 7 6 5 4 3 2 1 0 163 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 164 * \ \ \___ Primary/Alternate Port Addresses: 165 * \ \ 0=0x3510-3517 1=0x3518-0x351f 166 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 167 * \ 0000=0 0001=1 0011=3 0100=4 168 * \_________ Fairness On/Off: 1=On 0=Off 169 * 170 * POS register 3: (adf pos1) 171 * 172 * 7 6 5 4 3 2 1 0 173 * 0 0 \_/ 174 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 175 * 01=16ms 00=Burst Disabled 176 * 177 * POS register 4: (adf pos2) 178 * 179 * 7 6 5 4 3 2 1 0 180 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 181 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 182 * 183 * IRQ is fixed to 14 (0x0e). 184 */ 185 186 switch (ma->ma_id) { 187 case MCA_PRODUCT_IBM_ESDIC: 188 typestr = "IBM ESDI Fixed Disk Controller"; 189 break; 190 case MCA_PRODUCT_IBM_ESDIC_IG: 191 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 192 break; 193 default: 194 typestr = NULL; 195 break; 196 } 197 198 irq = ESDIC_IRQ; 199 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 200 drq = (pos2 & DRQ_MASK) >> 2; 201 202 printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 203 irq, drq, typestr); 204 205 #ifdef DIAGNOSTIC 206 /* 207 * It's not strictly necessary to check this, machine configuration 208 * utility uses only valid addresses. 209 */ 210 if (drq == 2 || drq >= 8) { 211 aprint_error_dev(&sc->sc_dev, "invalid DMA Arbitration Level %d\n", drq); 212 return; 213 } 214 #endif 215 216 printf("%s: Fairness %s, Release %s, ", 217 device_xname(&sc->sc_dev), 218 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 219 (pos4 & RELEASE_1) ? "6ms" 220 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 221 ); 222 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 223 static const char * const pacint[] = 224 { "disabled", "16ms", "24ms", "31ms"}; 225 printf("DMA burst pacing interval %s\n", 226 pacint[(pos3 & PACING_INT_MASK) >> 4]); 227 } else 228 printf("DMA pacing control disabled\n"); 229 230 sc->sc_iot = ma->ma_iot; 231 232 if (bus_space_map(sc->sc_iot, iobase, 233 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 234 aprint_error_dev(&sc->sc_dev, "couldn't map registers\n"); 235 return; 236 } 237 238 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 239 if (sc->sc_ih == NULL) { 240 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt handler\n"); 241 return; 242 } 243 244 /* Create a MCA DMA map, used for data transfer */ 245 sc->sc_dmat = ma->ma_dmat; 246 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 247 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 248 &sc->sc_dmamap_xfer, drq)) != 0){ 249 aprint_error_dev(&sc->sc_dev, "couldn't create DMA map - error %d\n", error); 250 return; 251 } 252 253 /* 254 * Integrated ESDI controller supports only one disk, other 255 * controllers support two disks. 256 */ 257 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 258 sc->sc_maxdevs = 1; 259 else 260 sc->sc_maxdevs = 2; 261 262 /* 263 * Reset controller and attach individual disks. ed attach routine 264 * uses polling so that this works with interrupts disabled. 265 */ 266 267 /* Do a reset to ensure sane state after warm boot. */ 268 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 269 /* hard reset */ 270 printf("%s: controller busy, performing hardware reset ...\n", 271 device_xname(&sc->sc_dev)); 272 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 273 BCR_INT_ENABLE|BCR_RESET); 274 } else { 275 /* "SOFT" reset */ 276 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 277 } 278 279 /* 280 * Since interrupts are disabled, it's necessary 281 * to detect the interrupt request and call edc_intr() 282 * explicitly. See also edc_run_cmd(). 283 */ 284 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 285 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 286 edc_intr(sc); 287 288 delay(100); 289 } 290 291 /* be quiet during probes */ 292 sc->sc_flags |= DASD_QUIET; 293 294 /* check for attached disks */ 295 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 296 eda.edc_drive = devno; 297 locs[EDCCF_DRIVE] = devno; 298 sc->sc_ed[devno] = 299 (void *) config_found_sm_loc(self, "edc", locs, &eda, 300 NULL, config_stdsubmatch); 301 302 /* If initialization did not succeed, NULL the pointer. */ 303 if (sc->sc_ed[devno] 304 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 305 sc->sc_ed[devno] = NULL; 306 } 307 308 /* enable full error dumps again */ 309 sc->sc_flags &= ~DASD_QUIET; 310 311 /* 312 * Check if there are any disks attached. If not, disestablish 313 * the interrupt. 314 */ 315 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 316 if (sc->sc_ed[devno]) 317 break; 318 } 319 320 if (devno == sc->sc_maxdevs) { 321 printf("%s: disabling controller (no drives attached)\n", 322 device_xname(&sc->sc_dev)); 323 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 324 return; 325 } 326 327 /* 328 * Run the worker thread. 329 */ 330 config_pending_incr(); 331 if ((error = kthread_create(PRI_NONE, 0, NULL, edcworker, sc, NULL, 332 "%s", device_xname(&sc->sc_dev)))) { 333 aprint_error_dev(&sc->sc_dev, "cannot spawn worker thread: errno=%d\n", error); 334 panic("edc_mca_attach"); 335 } 336 } 337 338 void 339 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 340 { 341 sc->sc_ed[ed->sc_devno] = ed; 342 } 343 344 static int 345 edc_intr(void *arg) 346 { 347 struct edc_mca_softc *sc = arg; 348 u_int8_t isr, intr_id; 349 u_int16_t sifr; 350 int cmd=-1, devno; 351 352 /* 353 * Check if the interrupt was for us. 354 */ 355 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 356 return (0); 357 358 /* 359 * Read ISR to find out interrupt type. This also clears the interrupt 360 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 361 * and 4 are reserved and not used. 362 */ 363 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 364 intr_id = isr & ISR_INTR_ID_MASK; 365 366 #ifdef EDC_DEBUG 367 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 368 aprint_error_dev(&sc->sc_dev, "bogus interrupt id %d\n", 369 (int) intr_id); 370 return (0); 371 } 372 #endif 373 374 /* Get number of device whose intr this was */ 375 devno = (isr & 0xe0) >> 5; 376 377 /* 378 * Get Status block. Higher byte always says how long the status 379 * block is, rest is device number and command code. 380 * Check the status block length against our supported maximum length 381 * and fetch the data. 382 */ 383 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 384 size_t len; 385 int i; 386 387 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 388 len = (sifr & 0xff00) >> 8; 389 #ifdef DEBUG 390 if (len > EDC_MAX_CMD_RES_LEN) 391 panic("%s: maximum Status Length exceeded: %d > %d", 392 device_xname(&sc->sc_dev), 393 len, EDC_MAX_CMD_RES_LEN); 394 #endif 395 396 /* Get command code */ 397 cmd = sifr & SIFR_CMD_MASK; 398 399 /* Read whole status block */ 400 sc->status_block[0] = sifr; 401 for(i=1; i < len; i++) { 402 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 403 & BSR_SIFR_FULL) == 0) 404 ; 405 406 sc->status_block[i] = le16toh( 407 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 408 } 409 /* zero out rest */ 410 if (i < EDC_MAX_CMD_RES_LEN) { 411 memset(&sc->status_block[i], 0, 412 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 413 } 414 } 415 416 switch (intr_id) { 417 case ISR_DATA_TRANSFER_RDY: 418 /* 419 * Ready to do DMA. The DMA controller has already been 420 * setup, now just kick disk controller to do the transfer. 421 */ 422 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 423 BCR_INT_ENABLE|BCR_DMA_ENABLE); 424 break; 425 426 case ISR_COMPLETED: 427 case ISR_COMPLETED_WITH_ECC: 428 case ISR_COMPLETED_RETRIES: 429 case ISR_COMPLETED_WARNING: 430 /* 431 * Copy device config data if appropriate. sc->sc_ed[] 432 * entry might be NULL during probe. 433 */ 434 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 435 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 436 sizeof(sc->sc_ed[devno]->sense_data)); 437 } 438 439 sc->sc_stat = STAT_DONE; 440 break; 441 442 case ISR_RESET_COMPLETED: 443 case ISR_ABORT_COMPLETED: 444 /* nothing to do */ 445 break; 446 447 case ISR_ATTN_ERROR: 448 /* 449 * Basically, this means driver bug or something seriously 450 * hosed. panic rather than extending the lossage. 451 * No status block available, so no further info. 452 */ 453 panic("%s: dev %d: attention error", 454 device_xname(&sc->sc_dev), 455 devno); 456 /* NOTREACHED */ 457 break; 458 459 default: 460 if ((sc->sc_flags & DASD_QUIET) == 0) 461 edc_dump_status_block(sc, sc->status_block, intr_id); 462 463 sc->sc_stat = STAT_ERROR; 464 break; 465 } 466 467 /* 468 * Unless the interrupt is for Data Transfer Ready or 469 * Attention Error, finish by assertion EOI. This makes 470 * attachment aware the interrupt is processed and system 471 * is ready to accept another one. 472 */ 473 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 474 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 475 476 /* If Read or Write Data, wakeup worker thread to finish it */ 477 if (intr_id != ISR_DATA_TRANSFER_RDY) { 478 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 479 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 480 wakeup(sc); 481 } 482 483 return (1); 484 } 485 486 /* 487 * This follows the exact order for Attention Request as 488 * written in DASD Storage Interface Specification MC (Rev 2.2). 489 */ 490 static int 491 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 492 { 493 int tries; 494 495 /* 1. Disable interrupts in BCR. */ 496 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 497 498 /* 499 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 500 * a RESET COMPLETED interrupt. 501 */ 502 if (intr_id != ISR_RESET_COMPLETED) { 503 #ifdef EDC_DEBUG 504 if (attn_type == ATN_CMD_REQ 505 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 506 & BSR_INT_PENDING)) 507 panic("%s: edc int pending", device_xname(&sc->sc_dev)); 508 #endif 509 510 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 511 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 512 & BSR_BUSY) == 0) 513 break; 514 } 515 516 if (tries == EDC_ATTN_MAXTRIES) { 517 printf("%s: edc_do_attn: timeout waiting for attachment to become available\n", 518 device_xname(&sc->sc_ed[devno]->sc_dev)); 519 return (EIO); 520 } 521 } 522 523 /* 524 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 525 */ 526 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 527 528 /* 529 * 4. Enable interrupts via BCR. 530 */ 531 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 532 533 return (0); 534 } 535 536 /* 537 * Wait until command is processed, timeout after 'secs' seconds. 538 * We use mono_time, since we don't need actual RTC, just time 539 * interval. 540 */ 541 static void 542 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 543 { 544 int val; 545 546 if (!poll) { 547 int s; 548 549 /* Not polling, can sleep. Sleep until we are awakened, 550 * but maximum secs seconds. 551 */ 552 s = splbio(); 553 if (sc->sc_stat != STAT_DONE) 554 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 555 splx(s); 556 } 557 558 /* Wait until the command is completely finished */ 559 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 560 & BSR_CMD_INPROGRESS) { 561 if (poll && (val & BSR_INTR)) 562 edc_intr(sc); 563 } 564 } 565 566 /* 567 * Command controller to execute specified command on a device. 568 */ 569 int 570 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 571 u_int16_t cmd_args[], int cmd_len, int poll) 572 { 573 int i, error, tries; 574 u_int16_t cmd0; 575 576 sc->sc_stat = STAT_START; 577 578 /* Do Attention Request for Command Request. */ 579 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 580 return (error); 581 582 /* 583 * Construct the command. The bits are like this: 584 * 585 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 586 * \_/ 0 0 1 0 \__/ \_____/ 587 * \ \__________/ \ \_ Command Code (see CMD_*) 588 * \ \ \__ Device: 0 common, 7 controller 589 * \ \__ Options: reserved, bit 10=cache bypass bit 590 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 591 * 592 * We always use device 0 or 1, so difference is made only by Command 593 * Code, Command Options and command length. 594 */ 595 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 596 | (devno << 5) 597 | (cmd_args[0] << 8) | cmd; 598 cmd_args[0] = cmd0; 599 600 /* 601 * Write word of CMD to the CIFR. This sets "Command 602 * Interface Register Full (CMD IN)" in BSR. Once the attachment 603 * detects it, it reads the word and clears CMD IN. This all should 604 * be quite fast, so don't sleep in !poll case neither. 605 */ 606 for(i=0; i < cmd_len; i++) { 607 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 608 htole16(cmd_args[i])); 609 610 /* Wait until CMD IN is cleared. */ 611 tries = 0; 612 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 613 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 614 delay(poll ? 1000 : 1); 615 ; 616 617 if (tries == 10000 618 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 619 & BSR_CIFR_FULL) { 620 aprint_error_dev(&sc->sc_dev, "device too slow to accept command %d\n", cmd); 621 return (EIO); 622 } 623 } 624 625 /* Wait for command to complete, but maximum 15 seconds. */ 626 edc_cmd_wait(sc, 15, poll); 627 628 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 629 } 630 631 #ifdef EDC_DEBUG 632 static const char * const edc_commands[] = { 633 "Invalid Command", 634 "Read Data", 635 "Write Data", 636 "Read Verify", 637 "Write with Verify", 638 "Seek", 639 "Park Head", 640 "Get Command Complete Status", 641 "Get Device Status", 642 "Get Device Configuration", 643 "Get POS Information", 644 "Translate RBA", 645 "Write Attachment Buffer", 646 "Read Attachment Buffer", 647 "Run Diagnostic Test", 648 "Get Diagnostic Status Block", 649 "Get MFG Header", 650 "Format Unit", 651 "Format Prepare", 652 "Set MAX RBA", 653 "Set Power Saving Mode", 654 "Power Conservation Command", 655 }; 656 657 static const char * const edc_cmd_status[256] = { 658 "Reserved", 659 "Command completed successfully", 660 "Reserved", 661 "Command completed successfully with ECC applied", 662 "Reserved", 663 "Command completed successfully with retries", 664 "Format Command partially completed", /* Status available */ 665 "Command completed successfully with ECC and retries", 666 "Command completed with Warning", /* Command Error is available */ 667 "Aborted", 668 "Reset completed", 669 "Data Transfer Ready", /* No Status Block available */ 670 "Command terminated with failure", /* Device Error is available */ 671 "DMA Error", /* Retry entire command as recovery */ 672 "Command Block Error", 673 "Attention Error (Illegal Attention Code)", 674 /* 0x14 - 0xff reserved */ 675 }; 676 677 static const char * const edc_cmd_error[256] = { 678 "No Error", 679 "Invalid parameter in the command block", 680 "Reserved", 681 "Command not supported", 682 "Command Aborted per request", 683 "Reserved", 684 "Command rejected", /* Attachment diagnostic failure */ 685 "Format Rejected", /* Prepare Format command is required */ 686 "Format Error (Primary Map is not readable)", 687 "Format Error (Secondary map is not readable)", 688 "Format Error (Diagnostic Failure)", 689 "Format Warning (Secondary Map Overflow)", 690 "Reserved" 691 "Format Error (Host Checksum Error)", 692 "Reserved", 693 "Format Warning (Push table overflow)", 694 "Format Warning (More pushes than allowed)", 695 "Reserved", 696 "Format Warning (Error during verifying)", 697 "Invalid device number for the command", 698 /* 0x14-0xff reserved */ 699 }; 700 701 static const char * const edc_dev_errors[] = { 702 "No Error", 703 "Seek Fault", /* Device report */ 704 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 705 "Block not found (ID not found)", 706 "Block not found (AM not found)", 707 "Data ECC Error (hard error)", 708 "ID CRC Error", 709 "RBA Out of Range", 710 "Reserved", 711 "Defective Block", 712 "Reserved", 713 "Selection Error", 714 "Reserved", 715 "Write Fault", 716 "No index or sector pulse", 717 "Device Not Ready", 718 "Seek Error", /* Attachment report */ 719 "Bad Format", 720 "Volume Overflow", 721 "No Data AM Found", 722 "Block not found (No ID AM or ID CRC error occurred)", 723 "Reserved", 724 "Reserved", 725 "No ID found on track (ID search)", 726 /* 0x19 - 0xff reserved */ 727 }; 728 #endif /* EDC_DEBUG */ 729 730 static void 731 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 732 int intr_id) 733 { 734 #ifdef EDC_DEBUG 735 printf("%s: Command: %s, Status: %s (intr %d)\n", 736 device_xname(&sc->sc_dev), 737 edc_commands[status_block[0] & 0x1f], 738 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 739 intr_id 740 ); 741 #else 742 printf("%s: Command: %d, Status: %d (intr %d)\n", 743 device_xname(&sc->sc_dev), 744 status_block[0] & 0x1f, 745 SB_GET_CMD_STATUS(status_block), 746 intr_id 747 ); 748 #endif 749 printf("%s: # left blocks: %u, last processed RBA: %u\n", 750 device_xname(&sc->sc_dev), 751 status_block[SB_RESBLKCNT_IDX], 752 (status_block[5] << 16) | status_block[4]); 753 754 if (intr_id == ISR_COMPLETED_WARNING) { 755 #ifdef EDC_DEBUG 756 aprint_error_dev(&sc->sc_dev, "Command Error Code: %s\n", 757 edc_cmd_error[status_block[1] & 0xff]); 758 #else 759 aprint_error_dev(&sc->sc_dev, "Command Error Code: %d\n", 760 status_block[1] & 0xff); 761 #endif 762 } 763 764 if (intr_id == ISR_CMD_FAILED) { 765 #ifdef EDC_DEBUG 766 char buf[100]; 767 768 printf("%s: Device Error Code: %s\n", 769 device_xname(&sc->sc_dev), 770 edc_dev_errors[status_block[2] & 0xff]); 771 snprintb(buf, sizeof(buf), 772 "\20" 773 "\01SeekOrCmdComplete" 774 "\02Track0Flag" 775 "\03WriteFault" 776 "\04Selected" 777 "\05Ready" 778 "\06Reserved0" 779 "\07STANDBY" 780 "\010Reserved0", (status_block[2] & 0xff00) >> 8); 781 782 printf("%s: Device Status: %s\n", 783 device_xname(&sc->sc_dev), buf); 784 #else 785 printf("%s: Device Error Code: %d, Device Status: %d\n", 786 device_xname(&sc->sc_dev), 787 status_block[2] & 0xff, 788 (status_block[2] & 0xff00) >> 8); 789 #endif 790 } 791 } 792 /* 793 * Main worker thread function. 794 */ 795 void 796 edcworker(void *arg) 797 { 798 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 799 struct ed_softc *ed; 800 struct buf *bp; 801 int i, error; 802 803 config_pending_decr(); 804 805 for(;;) { 806 /* Wait until awakened */ 807 (void) tsleep(sc, PRIBIO, "edcidle", 0); 808 809 for(i=0; i<sc->sc_maxdevs; ) { 810 if ((ed = sc->sc_ed[i]) == NULL) { 811 i++; 812 continue; 813 } 814 815 /* Is there a buf for us ? */ 816 simple_lock(&ed->sc_q_lock); 817 if ((bp = bufq_get(ed->sc_q)) == NULL) { 818 simple_unlock(&ed->sc_q_lock); 819 i++; 820 continue; 821 } 822 simple_unlock(&ed->sc_q_lock); 823 824 /* Instrumentation. */ 825 disk_busy(&ed->sc_dk); 826 827 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 828 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 829 830 if (error) { 831 bp->b_error = error; 832 } else { 833 /* Set resid, most commonly to zero. */ 834 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 835 } 836 837 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 838 (bp->b_flags & B_READ)); 839 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 840 biodone(bp); 841 } 842 } 843 } 844 845 int 846 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 847 size_t bcount, daddr_t rawblkno, int isread, int poll) 848 { 849 u_int16_t cmd_args[4]; 850 int error=0, fl; 851 u_int16_t track; 852 u_int16_t cyl; 853 u_int8_t head; 854 u_int8_t sector; 855 856 mca_disk_busy(); 857 858 /* set WAIT and R/W flag appropriately for the DMA transfer */ 859 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 860 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 861 862 /* Load the buffer for DMA transfer. */ 863 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 864 bcount, NULL, BUS_DMA_STREAMING|fl))) { 865 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 866 device_xname(&ed->sc_dev), error); 867 goto out; 868 } 869 870 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 871 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 872 873 track = rawblkno / ed->sectors; 874 head = track % ed->heads; 875 cyl = track / ed->heads; 876 sector = rawblkno % ed->sectors; 877 878 /* Read or Write Data command */ 879 cmd_args[0] = 2; /* Options 0000010 */ 880 cmd_args[1] = bcount / DEV_BSIZE; 881 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 882 cmd_args[3] = ((cyl & 0x3E0) >> 5); 883 error = edc_run_cmd(sc, 884 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 885 ed->sc_devno, cmd_args, 4, poll); 886 887 /* Sync the DMA memory */ 888 if (!error) { 889 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 890 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 891 } 892 893 /* We are done, unload buffer from DMA map */ 894 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 895 896 out: 897 mca_disk_unbusy(); 898 899 return (error); 900 } 901
Indexes created Sun Oct 12 05:10:08 GMT 2025