edc_mca.c revision 1.52.34.1
1 /* $NetBSD: edc_mca.c,v 1.52.34.1 2021/03/22 02:01:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for MCA ESDI controllers and disks conforming to IBM DASD 34 * spec. 35 * 36 * The driver was written with DASD Storage Interface Specification 37 * for MCA rev. 2.2 in hands, thanks to Scott Telford <st (at) epcc.ed.ac.uk>. 38 * 39 * TODO: 40 * - improve error recovery 41 * Issue soft reset on error or timeout? 42 * - test with > 1 disk (this is supported by some controllers) 43 * - test with > 1 ESDI controller in machine; shared interrupts 44 * necessary for this to work should be supported - edc_intr() specifically 45 * checks if the interrupt is for this controller 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: edc_mca.c,v 1.52.34.1 2021/03/22 02:01:01 thorpej Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/buf.h> 54 #include <sys/bufq.h> 55 #include <sys/errno.h> 56 #include <sys/device.h> 57 #include <sys/malloc.h> 58 #include <sys/endian.h> 59 #include <sys/disklabel.h> 60 #include <sys/disk.h> 61 #include <sys/syslog.h> 62 #include <sys/proc.h> 63 #include <sys/vnode.h> 64 #include <sys/kernel.h> 65 #include <sys/kthread.h> 66 #include <sys/rndsource.h> 67 68 #include <sys/bus.h> 69 #include <sys/intr.h> 70 71 #include <dev/mca/mcareg.h> 72 #include <dev/mca/mcavar.h> 73 #include <dev/mca/mcadevs.h> 74 75 #include <dev/mca/edcreg.h> 76 #include <dev/mca/edvar.h> 77 #include <dev/mca/edcvar.h> 78 79 #include "locators.h" 80 81 #define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */ 82 #define EDC_MAX_CMD_RES_LEN 8 83 84 struct edc_mca_softc { 85 device_t sc_dev; 86 87 bus_space_tag_t sc_iot; 88 bus_space_handle_t sc_ioh; 89 90 /* DMA related stuff */ 91 bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */ 92 bus_dmamap_t sc_dmamap_xfer; /* transfer dma map */ 93 94 void *sc_ih; /* interrupt handle */ 95 96 int sc_flags; 97 #define DASD_QUIET 0x01 /* don't dump cmd error info */ 98 99 #define DASD_MAXDEVS 8 100 struct ed_softc *sc_ed[DASD_MAXDEVS]; 101 int sc_maxdevs; /* max number of disks attached to this 102 * controller */ 103 104 /* I/O results variables */ 105 volatile int sc_stat; 106 #define STAT_START 0 107 #define STAT_ERROR 1 108 #define STAT_DONE 2 109 volatile int sc_resblk; /* residual block count */ 110 111 /* CMD status block - only set & used in edc_intr() */ 112 u_int16_t status_block[EDC_MAX_CMD_RES_LEN]; 113 }; 114 115 int edc_mca_probe(device_t, cfdata_t, void *); 116 void edc_mca_attach(device_t, device_t, void *); 117 118 CFATTACH_DECL_NEW(edc_mca, sizeof(struct edc_mca_softc), 119 edc_mca_probe, edc_mca_attach, NULL, NULL); 120 121 static int edc_intr(void *); 122 static void edc_dump_status_block(struct edc_mca_softc *, 123 u_int16_t *, int); 124 static int edc_do_attn(struct edc_mca_softc *, int, int, int); 125 static void edc_cmd_wait(struct edc_mca_softc *, int, int); 126 static void edcworker(void *); 127 128 int 129 edc_mca_probe(device_t parent, cfdata_t match, void *aux) 130 { 131 struct mca_attach_args *ma = aux; 132 133 switch (ma->ma_id) { 134 case MCA_PRODUCT_IBM_ESDIC: 135 case MCA_PRODUCT_IBM_ESDIC_IG: 136 return (1); 137 default: 138 return (0); 139 } 140 } 141 142 void 143 edc_mca_attach(device_t parent, device_t self, void *aux) 144 { 145 struct edc_mca_softc *sc = device_private(self); 146 struct mca_attach_args *ma = aux; 147 struct ed_attach_args eda; 148 int pos2, pos3, pos4; 149 int irq, drq, iobase; 150 const char *typestr; 151 int devno, error; 152 int locs[EDCCF_NLOCS]; 153 154 sc->sc_dev = self; 155 156 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 157 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 158 pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4); 159 160 /* 161 * POS register 2: (adf pos0) 162 * 163 * 7 6 5 4 3 2 1 0 164 * \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled 165 * \ \ \___ Primary/Alternate Port Addresses: 166 * \ \ 0=0x3510-3517 1=0x3518-0x351f 167 * \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7 168 * \ 0000=0 0001=1 0011=3 0100=4 169 * \_________ Fairness On/Off: 1=On 0=Off 170 * 171 * POS register 3: (adf pos1) 172 * 173 * 7 6 5 4 3 2 1 0 174 * 0 0 \_/ 175 * \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms 176 * 01=16ms 00=Burst Disabled 177 * 178 * POS register 4: (adf pos2) 179 * 180 * 7 6 5 4 3 2 1 0 181 * \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled 182 * \____ Time to Release: 1X=6ms 01=3ms 00=Immediate 183 * 184 * IRQ is fixed to 14 (0x0e). 185 */ 186 187 switch (ma->ma_id) { 188 case MCA_PRODUCT_IBM_ESDIC: 189 typestr = "IBM ESDI Fixed Disk Controller"; 190 break; 191 case MCA_PRODUCT_IBM_ESDIC_IG: 192 typestr = "IBM Integ. ESDI Fixed Disk & Controller"; 193 break; 194 default: 195 typestr = NULL; 196 break; 197 } 198 199 irq = ESDIC_IRQ; 200 iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM; 201 drq = (pos2 & DRQ_MASK) >> 2; 202 203 aprint_naive("\n"); 204 aprint_normal(": slot %d irq %d drq %d: %s\n", ma->ma_slot+1, 205 irq, drq, typestr); 206 207 #ifdef DIAGNOSTIC 208 /* 209 * It's not strictly necessary to check this, machine configuration 210 * utility uses only valid addresses. 211 */ 212 if (drq == 2 || drq >= 8) { 213 aprint_error_dev(sc->sc_dev, 214 "invalid DMA Arbitration Level %d\n", drq); 215 return; 216 } 217 #endif 218 219 aprint_normal_dev(self, "Fairness %s, Release %s, ", 220 (pos2 & FAIRNESS_ENABLE) ? "On" : "Off", 221 (pos4 & RELEASE_1) ? "6ms" 222 : ((pos4 & RELEASE_2) ? "3ms" : "Immediate") 223 ); 224 if ((pos4 & PACING_CTRL_DISABLE) == 0) { 225 static const char * const pacint[] = 226 { "disabled", "16ms", "24ms", "31ms"}; 227 aprint_normal("DMA burst pacing interval %s\n", 228 pacint[(pos3 & PACING_INT_MASK) >> 4]); 229 } else 230 aprint_normal("DMA pacing control disabled\n"); 231 232 sc->sc_iot = ma->ma_iot; 233 234 if (bus_space_map(sc->sc_iot, iobase, 235 ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) { 236 aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 237 return; 238 } 239 240 sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc); 241 if (sc->sc_ih == NULL) { 242 aprint_error_dev(sc->sc_dev, 243 "couldn't establish interrupt handler\n"); 244 return; 245 } 246 247 /* Create a MCA DMA map, used for data transfer */ 248 sc->sc_dmat = ma->ma_dmat; 249 if ((error = mca_dmamap_create(sc->sc_dmat, MAXPHYS, 250 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_16BIT, 251 &sc->sc_dmamap_xfer, drq)) != 0){ 252 aprint_error_dev(sc->sc_dev, 253 "couldn't create DMA map - error %d\n", error); 254 return; 255 } 256 257 /* 258 * Integrated ESDI controller supports only one disk, other 259 * controllers support two disks. 260 */ 261 if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG) 262 sc->sc_maxdevs = 1; 263 else 264 sc->sc_maxdevs = 2; 265 266 /* 267 * Reset controller and attach individual disks. ed attach routine 268 * uses polling so that this works with interrupts disabled. 269 */ 270 271 /* Do a reset to ensure sane state after warm boot. */ 272 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 273 /* hard reset */ 274 aprint_normal_dev(self, "controller busy, " 275 "performing hardware reset ...\n"); 276 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 277 BCR_INT_ENABLE|BCR_RESET); 278 } else { 279 /* "SOFT" reset */ 280 edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0); 281 } 282 283 /* 284 * Since interrupts are disabled, it's necessary 285 * to detect the interrupt request and call edc_intr() 286 * explicitly. See also edc_run_cmd(). 287 */ 288 while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) { 289 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) 290 edc_intr(sc); 291 292 delay(100); 293 } 294 295 /* be quiet during probes */ 296 sc->sc_flags |= DASD_QUIET; 297 298 /* check for attached disks */ 299 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 300 eda.edc_drive = devno; 301 locs[EDCCF_DRIVE] = devno; 302 303 sc->sc_ed[devno] = device_private( 304 config_found(self, &eda, NULL, 305 CFARG_SUBMATCH, config_stdsubmatch, 306 CFARG_IATTR, "edc", 307 CFARG_LOCATORS, locs, 308 CFARG_EOL)); 309 310 /* If initialization did not succeed, NULL the pointer. */ 311 if (sc->sc_ed[devno] 312 && (sc->sc_ed[devno]->sc_flags & EDF_INIT) == 0) 313 sc->sc_ed[devno] = NULL; 314 } 315 316 /* enable full error dumps again */ 317 sc->sc_flags &= ~DASD_QUIET; 318 319 /* 320 * Check if there are any disks attached. If not, disestablish 321 * the interrupt. 322 */ 323 for (devno = 0; devno < sc->sc_maxdevs; devno++) { 324 if (sc->sc_ed[devno]) 325 break; 326 } 327 328 if (devno == sc->sc_maxdevs) { 329 aprint_error("%s: disabling controller (no drives attached)\n", 330 device_xname(sc->sc_dev)); 331 mca_intr_disestablish(ma->ma_mc, sc->sc_ih); 332 return; 333 } 334 335 /* 336 * Run the worker thread. 337 */ 338 config_pending_incr(self); 339 if ((error = kthread_create(PRI_NONE, 0, NULL, edcworker, sc, NULL, 340 "%s", device_xname(sc->sc_dev)))) { 341 aprint_error_dev(sc->sc_dev, 342 "cannot spawn worker thread: errno=%d\n", error); 343 panic("edc_mca_attach"); 344 } 345 } 346 347 void 348 edc_add_disk(struct edc_mca_softc *sc, struct ed_softc *ed) 349 { 350 sc->sc_ed[ed->sc_devno] = ed; 351 } 352 353 static int 354 edc_intr(void *arg) 355 { 356 struct edc_mca_softc *sc = arg; 357 u_int8_t isr, intr_id; 358 u_int16_t sifr; 359 int cmd = -1, devno; 360 361 /* 362 * Check if the interrupt was for us. 363 */ 364 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0) 365 return (0); 366 367 /* 368 * Read ISR to find out interrupt type. This also clears the interrupt 369 * condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2 370 * and 4 are reserved and not used. 371 */ 372 isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR); 373 intr_id = isr & ISR_INTR_ID_MASK; 374 375 #ifdef EDC_DEBUG 376 if (intr_id == 0 || intr_id == 2 || intr_id == 4) { 377 aprint_error_dev(sc->sc_dev, "bogus interrupt id %d\n", 378 (int) intr_id); 379 return (0); 380 } 381 #endif 382 383 /* Get number of device whose intr this was */ 384 devno = (isr & 0xe0) >> 5; 385 386 /* 387 * Get Status block. Higher byte always says how long the status 388 * block is, rest is device number and command code. 389 * Check the status block length against our supported maximum length 390 * and fetch the data. 391 */ 392 if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) { 393 size_t len; 394 int i; 395 396 sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 397 len = (sifr & 0xff00) >> 8; 398 #ifdef DEBUG 399 if (len > EDC_MAX_CMD_RES_LEN) 400 panic("%s: maximum Status Length exceeded: %d > %d", 401 device_xname(sc->sc_dev), 402 len, EDC_MAX_CMD_RES_LEN); 403 #endif 404 405 /* Get command code */ 406 cmd = sifr & SIFR_CMD_MASK; 407 408 /* Read whole status block */ 409 sc->status_block[0] = sifr; 410 for(i=1; i < len; i++) { 411 while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 412 & BSR_SIFR_FULL) == 0) 413 ; 414 415 sc->status_block[i] = le16toh( 416 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR)); 417 } 418 /* zero out rest */ 419 if (i < EDC_MAX_CMD_RES_LEN) { 420 memset(&sc->status_block[i], 0, 421 (EDC_MAX_CMD_RES_LEN-i)*sizeof(u_int16_t)); 422 } 423 } 424 425 switch (intr_id) { 426 case ISR_DATA_TRANSFER_RDY: 427 /* 428 * Ready to do DMA. The DMA controller has already been 429 * setup, now just kick disk controller to do the transfer. 430 */ 431 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 432 BCR_INT_ENABLE|BCR_DMA_ENABLE); 433 break; 434 435 case ISR_COMPLETED: 436 case ISR_COMPLETED_WITH_ECC: 437 case ISR_COMPLETED_RETRIES: 438 case ISR_COMPLETED_WARNING: 439 /* 440 * Copy device config data if appropriate. sc->sc_ed[] 441 * entry might be NULL during probe. 442 */ 443 if (cmd == CMD_GET_DEV_CONF && sc->sc_ed[devno]) { 444 memcpy(sc->sc_ed[devno]->sense_data, sc->status_block, 445 sizeof(sc->sc_ed[devno]->sense_data)); 446 } 447 448 sc->sc_stat = STAT_DONE; 449 break; 450 451 case ISR_RESET_COMPLETED: 452 case ISR_ABORT_COMPLETED: 453 /* nothing to do */ 454 break; 455 456 case ISR_ATTN_ERROR: 457 /* 458 * Basically, this means driver bug or something seriously 459 * hosed. panic rather than extending the lossage. 460 * No status block available, so no further info. 461 */ 462 panic("%s: dev %d: attention error", 463 device_xname(sc->sc_dev), 464 devno); 465 /* NOTREACHED */ 466 break; 467 468 default: 469 if ((sc->sc_flags & DASD_QUIET) == 0) 470 edc_dump_status_block(sc, sc->status_block, intr_id); 471 472 sc->sc_stat = STAT_ERROR; 473 break; 474 } 475 476 /* 477 * Unless the interrupt is for Data Transfer Ready or 478 * Attention Error, finish by assertion EOI. This makes 479 * attachment aware the interrupt is processed and system 480 * is ready to accept another one. 481 */ 482 if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR) 483 edc_do_attn(sc, ATN_END_INT, devno, intr_id); 484 485 /* If Read or Write Data, wakeup worker thread to finish it */ 486 if (intr_id != ISR_DATA_TRANSFER_RDY) { 487 if (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA) 488 sc->sc_resblk = sc->status_block[SB_RESBLKCNT_IDX]; 489 wakeup(sc); 490 } 491 492 return (1); 493 } 494 495 /* 496 * This follows the exact order for Attention Request as 497 * written in DASD Storage Interface Specification MC (Rev 2.2). 498 */ 499 static int 500 edc_do_attn(struct edc_mca_softc *sc, int attn_type, int devno, int intr_id) 501 { 502 int tries; 503 504 /* 1. Disable interrupts in BCR. */ 505 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0); 506 507 /* 508 * 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging 509 * a RESET COMPLETED interrupt. 510 */ 511 if (intr_id != ISR_RESET_COMPLETED) { 512 #ifdef EDC_DEBUG 513 if (attn_type == ATN_CMD_REQ 514 && (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 515 & BSR_INT_PENDING)) 516 panic("%s: edc int pending", device_xname(sc->sc_dev)); 517 #endif 518 519 for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) { 520 if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 521 & BSR_BUSY) == 0) 522 break; 523 } 524 525 if (tries == EDC_ATTN_MAXTRIES) { 526 printf("%s: edc_do_attn: timeout waiting for " 527 "attachment to become available\n", 528 device_xname(sc->sc_ed[devno]->sc_dev)); 529 return (EIO); 530 } 531 } 532 533 /* 534 * 3. Write proper DEVICE NUMBER and Attention number to ATN. 535 */ 536 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN, attn_type | (devno<<5)); 537 538 /* 539 * 4. Enable interrupts via BCR. 540 */ 541 bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE); 542 543 return (0); 544 } 545 546 /* 547 * Wait until command is processed, timeout after 'secs' seconds. 548 * We use mono_time, since we don't need actual RTC, just time 549 * interval. 550 */ 551 static void 552 edc_cmd_wait(struct edc_mca_softc *sc, int secs, int poll) 553 { 554 int val; 555 556 if (!poll) { 557 int s; 558 559 /* Not polling, can sleep. Sleep until we are awakened, 560 * but maximum secs seconds. 561 */ 562 s = splbio(); 563 if (sc->sc_stat != STAT_DONE) 564 (void) tsleep(sc, PRIBIO, "edcwcmd", secs * hz); 565 splx(s); 566 } 567 568 /* Wait until the command is completely finished */ 569 while((val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)) 570 & BSR_CMD_INPROGRESS) { 571 if (poll && (val & BSR_INTR)) 572 edc_intr(sc); 573 } 574 } 575 576 /* 577 * Command controller to execute specified command on a device. 578 */ 579 int 580 edc_run_cmd(struct edc_mca_softc *sc, int cmd, int devno, 581 u_int16_t cmd_args[], int cmd_len, int poll) 582 { 583 int i, error, tries; 584 u_int16_t cmd0; 585 586 sc->sc_stat = STAT_START; 587 588 /* Do Attention Request for Command Request. */ 589 if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0))) 590 return (error); 591 592 /* 593 * Construct the command. The bits are like this: 594 * 595 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 596 * \_/ 0 0 1 0 \__/ \_____/ 597 * \ \__________/ \ \_ Command Code (see CMD_*) 598 * \ \ \__ Device: 0 common, 7 controller 599 * \ \__ Options: reserved, bit 10=cache bypass bit 600 * \_ Type: 00=2B, 01=4B, 10 and 11 reserved 601 * 602 * We always use device 0 or 1, so difference is made only by Command 603 * Code, Command Options and command length. 604 */ 605 cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0) 606 | (devno << 5) 607 | (cmd_args[0] << 8) | cmd; 608 cmd_args[0] = cmd0; 609 610 /* 611 * Write word of CMD to the CIFR. This sets "Command 612 * Interface Register Full (CMD IN)" in BSR. Once the attachment 613 * detects it, it reads the word and clears CMD IN. This all should 614 * be quite fast, so don't sleep in !poll case neither. 615 */ 616 for(i=0; i < cmd_len; i++) { 617 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR, 618 htole16(cmd_args[i])); 619 620 /* Wait until CMD IN is cleared. */ 621 tries = 0; 622 for(; (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 623 & BSR_CIFR_FULL) && tries < 10000 ; tries++) 624 delay(poll ? 1000 : 1); 625 ; 626 627 if (tries == 10000 628 && bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) 629 & BSR_CIFR_FULL) { 630 aprint_error_dev(sc->sc_dev, 631 "device too slow to accept command %d\n", cmd); 632 return (EIO); 633 } 634 } 635 636 /* Wait for command to complete, but maximum 15 seconds. */ 637 edc_cmd_wait(sc, 15, poll); 638 639 return ((sc->sc_stat != STAT_DONE) ? EIO : 0); 640 } 641 642 #ifdef EDC_DEBUG 643 static const char * const edc_commands[] = { 644 "Invalid Command", 645 "Read Data", 646 "Write Data", 647 "Read Verify", 648 "Write with Verify", 649 "Seek", 650 "Park Head", 651 "Get Command Complete Status", 652 "Get Device Status", 653 "Get Device Configuration", 654 "Get POS Information", 655 "Translate RBA", 656 "Write Attachment Buffer", 657 "Read Attachment Buffer", 658 "Run Diagnostic Test", 659 "Get Diagnostic Status Block", 660 "Get MFG Header", 661 "Format Unit", 662 "Format Prepare", 663 "Set MAX RBA", 664 "Set Power Saving Mode", 665 "Power Conservation Command", 666 }; 667 668 static const char * const edc_cmd_status[256] = { 669 "Reserved", 670 "Command completed successfully", 671 "Reserved", 672 "Command completed successfully with ECC applied", 673 "Reserved", 674 "Command completed successfully with retries", 675 "Format Command partially completed", /* Status available */ 676 "Command completed successfully with ECC and retries", 677 "Command completed with Warning", /* Command Error is available */ 678 "Aborted", 679 "Reset completed", 680 "Data Transfer Ready", /* No Status Block available */ 681 "Command terminated with failure", /* Device Error is available */ 682 "DMA Error", /* Retry entire command as recovery */ 683 "Command Block Error", 684 "Attention Error (Illegal Attention Code)", 685 /* 0x14 - 0xff reserved */ 686 }; 687 688 static const char * const edc_cmd_error[256] = { 689 "No Error", 690 "Invalid parameter in the command block", 691 "Reserved", 692 "Command not supported", 693 "Command Aborted per request", 694 "Reserved", 695 "Command rejected", /* Attachment diagnostic failure */ 696 "Format Rejected", /* Prepare Format command is required */ 697 "Format Error (Primary Map is not readable)", 698 "Format Error (Secondary map is not readable)", 699 "Format Error (Diagnostic Failure)", 700 "Format Warning (Secondary Map Overflow)", 701 "Reserved" 702 "Format Error (Host Checksum Error)", 703 "Reserved", 704 "Format Warning (Push table overflow)", 705 "Format Warning (More pushes than allowed)", 706 "Reserved", 707 "Format Warning (Error during verifying)", 708 "Invalid device number for the command", 709 /* 0x14-0xff reserved */ 710 }; 711 712 static const char * const edc_dev_errors[] = { 713 "No Error", 714 "Seek Fault", /* Device report */ 715 "Interface Fault (Parity, Attn, or Cmd Complete Error)", 716 "Block not found (ID not found)", 717 "Block not found (AM not found)", 718 "Data ECC Error (hard error)", 719 "ID CRC Error", 720 "RBA Out of Range", 721 "Reserved", 722 "Defective Block", 723 "Reserved", 724 "Selection Error", 725 "Reserved", 726 "Write Fault", 727 "No index or sector pulse", 728 "Device Not Ready", 729 "Seek Error", /* Attachment report */ 730 "Bad Format", 731 "Volume Overflow", 732 "No Data AM Found", 733 "Block not found (No ID AM or ID CRC error occurred)", 734 "Reserved", 735 "Reserved", 736 "No ID found on track (ID search)", 737 /* 0x19 - 0xff reserved */ 738 }; 739 #endif /* EDC_DEBUG */ 740 741 static void 742 edc_dump_status_block(struct edc_mca_softc *sc, u_int16_t *status_block, 743 int intr_id) 744 { 745 #ifdef EDC_DEBUG 746 printf("%s: Command: %s, Status: %s (intr %d)\n", 747 device_xname(sc->sc_dev), 748 edc_commands[status_block[0] & 0x1f], 749 edc_cmd_status[SB_GET_CMD_STATUS(status_block)], 750 intr_id 751 ); 752 #else 753 printf("%s: Command: %d, Status: %d (intr %d)\n", 754 device_xname(sc->sc_dev), 755 status_block[0] & 0x1f, 756 SB_GET_CMD_STATUS(status_block), 757 intr_id 758 ); 759 #endif 760 printf("%s: # left blocks: %u, last processed RBA: %u\n", 761 device_xname(sc->sc_dev), 762 status_block[SB_RESBLKCNT_IDX], 763 (status_block[5] << 16) | status_block[4]); 764 765 if (intr_id == ISR_COMPLETED_WARNING) { 766 #ifdef EDC_DEBUG 767 aprint_error_dev(sc->sc_dev, "Command Error Code: %s\n", 768 edc_cmd_error[status_block[1] & 0xff]); 769 #else 770 aprint_error_dev(sc->sc_dev, "Command Error Code: %d\n", 771 status_block[1] & 0xff); 772 #endif 773 } 774 775 if (intr_id == ISR_CMD_FAILED) { 776 #ifdef EDC_DEBUG 777 char buf[100]; 778 779 printf("%s: Device Error Code: %s\n", 780 device_xname(sc->sc_dev), 781 edc_dev_errors[status_block[2] & 0xff]); 782 snprintb(buf, sizeof(buf), 783 "\20" 784 "\01SeekOrCmdComplete" 785 "\02Track0Flag" 786 "\03WriteFault" 787 "\04Selected" 788 "\05Ready" 789 "\06Reserved0" 790 "\07STANDBY" 791 "\010Reserved0", (status_block[2] & 0xff00) >> 8); 792 793 printf("%s: Device Status: %s\n", 794 device_xname(sc->sc_dev), buf); 795 #else 796 printf("%s: Device Error Code: %d, Device Status: %d\n", 797 device_xname(sc->sc_dev), 798 status_block[2] & 0xff, 799 (status_block[2] & 0xff00) >> 8); 800 #endif 801 } 802 } 803 /* 804 * Main worker thread function. 805 */ 806 void 807 edcworker(void *arg) 808 { 809 struct edc_mca_softc *sc = (struct edc_mca_softc *) arg; 810 struct ed_softc *ed; 811 struct buf *bp; 812 int i, error; 813 814 config_pending_decr(sc->sc_dev); 815 816 for(;;) { 817 /* Wait until awakened */ 818 (void) tsleep(sc, PRIBIO, "edcidle", 0); 819 820 for(i=0; i<sc->sc_maxdevs; ) { 821 if ((ed = sc->sc_ed[i]) == NULL) { 822 i++; 823 continue; 824 } 825 826 /* Is there a buf for us ? */ 827 mutex_enter(&ed->sc_q_lock); 828 if ((bp = bufq_get(ed->sc_q)) == NULL) { 829 mutex_exit(&ed->sc_q_lock); 830 i++; 831 continue; 832 } 833 mutex_exit(&ed->sc_q_lock); 834 835 /* Instrumentation. */ 836 disk_busy(&ed->sc_dk); 837 838 error = edc_bio(sc, ed, bp->b_data, bp->b_bcount, 839 bp->b_rawblkno, (bp->b_flags & B_READ), 0); 840 841 if (error) { 842 bp->b_error = error; 843 } else { 844 /* Set resid, most commonly to zero. */ 845 bp->b_resid = sc->sc_resblk * DEV_BSIZE; 846 } 847 848 disk_unbusy(&ed->sc_dk, (bp->b_bcount - bp->b_resid), 849 (bp->b_flags & B_READ)); 850 rnd_add_uint32(&ed->rnd_source, bp->b_blkno); 851 biodone(bp); 852 } 853 } 854 } 855 856 int 857 edc_bio(struct edc_mca_softc *sc, struct ed_softc *ed, void *data, 858 size_t bcount, daddr_t rawblkno, int isread, int poll) 859 { 860 u_int16_t cmd_args[4]; 861 int error=0, fl; 862 u_int16_t track; 863 u_int16_t cyl; 864 u_int8_t head; 865 u_int8_t sector; 866 867 mca_disk_busy(); 868 869 /* set WAIT and R/W flag appropriately for the DMA transfer */ 870 fl = ((poll) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) 871 | ((isread) ? BUS_DMA_READ : BUS_DMA_WRITE); 872 873 /* Load the buffer for DMA transfer. */ 874 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_xfer, data, 875 bcount, NULL, BUS_DMA_STREAMING|fl))) { 876 printf("%s: ed_bio: unable to load DMA buffer - error %d\n", 877 device_xname(ed->sc_dev), error); 878 goto out; 879 } 880 881 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, 882 bcount, (isread) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 883 884 track = rawblkno / ed->sectors; 885 head = track % ed->heads; 886 cyl = track / ed->heads; 887 sector = rawblkno % ed->sectors; 888 889 /* Read or Write Data command */ 890 cmd_args[0] = 2; /* Options 0000010 */ 891 cmd_args[1] = bcount / DEV_BSIZE; 892 cmd_args[2] = ((cyl & 0x1f) << 11) | (head << 5) | sector; 893 cmd_args[3] = ((cyl & 0x3E0) >> 5); 894 error = edc_run_cmd(sc, 895 (isread) ? CMD_READ_DATA : CMD_WRITE_DATA, 896 ed->sc_devno, cmd_args, 4, poll); 897 898 /* Sync the DMA memory */ 899 if (!error) { 900 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_xfer, 0, bcount, 901 (isread)? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 902 } 903 904 /* We are done, unload buffer from DMA map */ 905 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_xfer); 906 907 out: 908 mca_disk_unbusy(); 909 910 return (error); 911 } 912
Indexes created Sat Oct 11 19:10:01 GMT 2025