esp_mca.c revision 1.12.10.1
1 /* $NetBSD: esp_mca.c,v 1.12.10.1 2006/10/22 06:06:12 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek <jdolecek (at) NetBSD.org>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for NCR 53c90, MCA version, with 86c01 DMA controller chip. 41 * 42 * Some of the information used to write this driver was taken 43 * from Tymm Twillman <tymm (at) computer.org>'s Linux MCA NC53c90 driver, 44 * in drivers/scsi/mca_53c9x.c 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: esp_mca.c,v 1.12.10.1 2006/10/22 06:06:12 yamt Exp $"); 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/errno.h> 55 #include <sys/ioctl.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 #include <dev/scsipi/scsi_message.h> 66 67 #include <machine/bus.h> 68 #include <machine/cpu.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/mca/espvar.h> 74 #include <dev/mca/espreg.h> 75 76 #include <dev/mca/mcavar.h> 77 #include <dev/mca/mcareg.h> 78 #include <dev/mca/mcadevs.h> 79 80 #if 0 81 #if defined(DEBUG) && !defined(NCR53C9X_DEBUG) 82 #define NCR53C9X_DEBUG 83 #endif 84 #endif 85 86 #ifdef NCR53C9X_DEBUG 87 static int esp_mca_debug = 0; 88 #define DPRINTF(x) if (esp_mca_debug) printf x; 89 #else 90 #define DPRINTF(x) 91 #endif 92 93 #define ESP_MCA_IOSIZE 0x20 94 #define ESP_REG_OFFSET 0x10 95 96 static void esp_mca_attach(struct device *, struct device *, void *); 97 static int esp_mca_match(struct device *, struct cfdata *, void *); 98 99 CFATTACH_DECL(esp_mca, sizeof(struct esp_softc), 100 esp_mca_match, esp_mca_attach, NULL, NULL); 101 102 /* 103 * Functions and the switch for the MI code. 104 */ 105 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 106 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 107 static int esp_dma_isintr(struct ncr53c9x_softc *); 108 static void esp_dma_reset(struct ncr53c9x_softc *); 109 static int esp_dma_intr(struct ncr53c9x_softc *); 110 static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 111 size_t *, int, size_t *); 112 static void esp_dma_go(struct ncr53c9x_softc *); 113 static void esp_dma_stop(struct ncr53c9x_softc *); 114 static int esp_dma_isactive(struct ncr53c9x_softc *); 115 116 static struct ncr53c9x_glue esp_glue = { 117 esp_read_reg, 118 esp_write_reg, 119 esp_dma_isintr, 120 esp_dma_reset, 121 esp_dma_intr, 122 esp_dma_setup, 123 esp_dma_go, 124 esp_dma_stop, 125 esp_dma_isactive, 126 NULL, /* gl_clear_latched_intr */ 127 }; 128 129 static int 130 esp_mca_match(parent, cf, aux) 131 struct device *parent __unused; 132 struct cfdata *cf __unused; 133 void *aux; 134 { 135 struct mca_attach_args *ma = aux; 136 137 switch (ma->ma_id) { 138 case MCA_PRODUCT_NCR53C90: 139 return 1; 140 } 141 142 return 0; 143 } 144 145 static void 146 esp_mca_attach(parent, self, aux) 147 struct device *parent __unused; 148 struct device *self; 149 void *aux; 150 { 151 struct mca_attach_args *ma = aux; 152 struct esp_softc *esc = device_private(self); 153 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 154 u_int16_t iobase; 155 int scsi_id, irq, drq, error; 156 bus_space_handle_t ioh; 157 int pos2, pos3, pos5; 158 159 static const u_int16_t ncrmca_iobase[] = { 160 0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240 161 }; 162 163 /* 164 * NCR SCSI Adapter (ADF 7f4f) 165 * 166 * POS register 2: (adf pos0) 167 * 168 * 7 6 5 4 3 2 1 0 169 * \_/ \___/ \__ enable: 0=adapter disabled, 1=adapter enabled 170 * | \____ I/O base (32B): 001=0x240 010=0x340 011=0x400 171 * | 100=0x420 101=0x3240 110=0x8240 111=0xa240 172 * \__________ IRQ: 00=3 01=5 10=7 11=9 173 * 174 * POS register 3: (adf pos1) 175 * 176 * 7 6 5 4 3 2 1 0 177 * 1 1 1 | \_____/ 178 * | \__ DMA level 179 * \_________ Fairness: 1=enabled 0=disabled 180 * 181 * POS register 5: (adf pos3) 182 * 183 * 7 6 5 4 3 2 1 0 184 * 1 | \___/ 185 * | \__ Static Ram: 0xC8000-0xC87FF + XX*0x4000 186 * \___________ Host Adapter ID: 1=7 0=6 187 */ 188 189 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 190 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 191 pos5 = mca_conf_read(ma->ma_mc, ma->ma_slot, 5); 192 193 iobase = ncrmca_iobase[(pos2 & 0x0e) >> 1]; 194 irq = 3 + 2*((pos2 & 0x30) >> 4); 195 drq = (pos3 & 0x0f); 196 scsi_id = 6 + ((pos5 & 0x20) ? 1 : 0); 197 198 printf(" slot %d irq %d drq %d: NCR SCSI Adapter\n", 199 ma->ma_slot + 1, irq, drq); 200 201 /* Map the 86C01 registers */ 202 if (bus_space_map(ma->ma_iot, iobase, ESP_MCA_IOSIZE, 0, &ioh)) { 203 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 204 return; 205 } 206 207 esc->sc_iot = ma->ma_iot; 208 esc->sc_ioh = ioh; 209 210 /* Submap the 'esp' registers */ 211 if (bus_space_subregion(ma->ma_iot, ioh, ESP_REG_OFFSET, 212 ESP_MCA_IOSIZE-ESP_REG_OFFSET, &esc->sc_esp_ioh)) { 213 printf("%s: can't subregion i/o space\n", sc->sc_dev.dv_xname); 214 return; 215 } 216 217 /* Setup DMA map */ 218 esc->sc_dmat = ma->ma_dmat; 219 if ((error = mca_dmamap_create(esc->sc_dmat, MAXPHYS, 220 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_IOPORT, 221 &esc->sc_xfer, drq)) != 0){ 222 printf("%s: couldn't create DMA map - error %d\n", 223 sc->sc_dev.dv_xname, error); 224 return; 225 } 226 227 /* MI code glue */ 228 sc->sc_id = scsi_id; 229 sc->sc_freq = 25; /* MHz */ 230 231 sc->sc_glue = &esp_glue; 232 233 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; //| NCRCFG1_SLOW; 234 /* No point setting sc_cfg[2345], they won't be used */ 235 236 sc->sc_rev = NCR_VARIANT_NCR53C90_86C01; 237 sc->sc_minsync = 0; 238 239 /* max 64KB DMA */ 240 sc->sc_maxxfer = 64 * 1024; 241 242 /* Establish interrupt */ 243 esc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, ncr53c9x_intr, 244 esc); 245 if (esc->sc_ih == NULL) { 246 printf("%s: couldn't establish interrupt\n", 247 sc->sc_dev.dv_xname); 248 return; 249 } 250 251 /* 252 * Massage the 86C01 chip - setup MCA DMA controller for DMA via 253 * the 86C01 register, and enable 86C01 interrupts. 254 */ 255 mca_dma_set_ioport(drq, iobase + N86C01_PIO); 256 257 bus_space_write_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE, 258 bus_space_read_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE) 259 | N86C01_INTR_ENABLE); 260 261 /* 262 * Now try to attach all the sub-devices 263 */ 264 sc->sc_adapter.adapt_minphys = minphys; 265 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 266 267 /* Do the common parts of attachment. */ 268 printf("%s", sc->sc_dev.dv_xname); 269 ncr53c9x_attach(sc); 270 } 271 272 /* 273 * Glue functions. 274 */ 275 276 static u_char 277 esp_read_reg(sc, reg) 278 struct ncr53c9x_softc *sc; 279 int reg; 280 { 281 struct esp_softc *esc = (struct esp_softc *)sc; 282 283 return (bus_space_read_1(esc->sc_iot, esc->sc_esp_ioh, reg)); 284 } 285 286 static void 287 esp_write_reg(sc, reg, val) 288 struct ncr53c9x_softc *sc; 289 int reg; 290 u_char val; 291 { 292 struct esp_softc *esc = (struct esp_softc *)sc; 293 294 bus_space_write_1(esc->sc_iot, esc->sc_esp_ioh, reg, val); 295 } 296 297 static int 298 esp_dma_isintr(sc) 299 struct ncr53c9x_softc *sc; 300 { 301 struct esp_softc *esc = (struct esp_softc *)sc; 302 303 DPRINTF(("[esp_dma_isintr] ")); 304 return (bus_space_read_1(esc->sc_iot, esc->sc_ioh, 305 N86C01_STATUS) & N86C01_IRQ_PEND); 306 } 307 308 static void 309 esp_dma_reset(sc) 310 struct ncr53c9x_softc *sc; 311 { 312 struct esp_softc *esc = (struct esp_softc *)sc; 313 314 DPRINTF(("[esp_dma_reset] ")); 315 316 if (esc->sc_flags & ESP_XFER_LOADED) { 317 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 318 esc->sc_flags &= ~ESP_XFER_LOADED; 319 } 320 321 if (esc->sc_flags & ESP_XFER_ACTIVE) { 322 esc->sc_flags &= ~ESP_XFER_ACTIVE; 323 mca_disk_unbusy(); 324 } 325 } 326 327 static int 328 esp_dma_intr(sc) 329 struct ncr53c9x_softc *sc; 330 { 331 struct esp_softc *esc = (struct esp_softc *) sc; 332 DPRINTF(("[esp_dma_intr] ")); 333 334 if ((esc->sc_flags & ESP_XFER_ACTIVE) == 0) { 335 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 336 return (-1); 337 } 338 339 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 340 esc->sc_flags &= ~ESP_XFER_ACTIVE; 341 mca_disk_unbusy(); 342 return (0); 343 } 344 345 sc->sc_espstat |= NCRSTAT_TC; /* XXX */ 346 347 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 348 printf("%s: DMA not complete?\n", sc->sc_dev.dv_xname); 349 return (1); 350 } 351 352 bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0, 353 *esc->sc_xfer_len, 354 (esc->sc_flags & ESP_XFER_READ) 355 ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 356 357 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 358 esc->sc_flags &= ~ESP_XFER_LOADED; 359 360 *esc->sc_xfer_addr += *esc->sc_xfer_len; 361 *esc->sc_xfer_len = 0; 362 363 esc->sc_flags &= ~ESP_XFER_ACTIVE; 364 mca_disk_unbusy(); 365 366 return (0); 367 } 368 369 /* 370 * Setup DMA transfer. 371 */ 372 static int 373 esp_dma_setup(sc, addr, len, datain, dmasize) 374 struct ncr53c9x_softc *sc; 375 caddr_t *addr; 376 size_t *len; 377 int datain; 378 size_t *dmasize __unused; 379 { 380 struct esp_softc *esc = (struct esp_softc *) sc; 381 int error; 382 int fl; 383 384 DPRINTF(("[esp_dma_setup] ")); 385 386 if (esc->sc_flags & ESP_XFER_LOADED) { 387 printf("%s: esp_dma_setup: unloading leaked xfer\n", 388 sc->sc_dev.dv_xname); 389 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 390 esc->sc_flags &= ~ESP_XFER_LOADED; 391 } 392 393 /* Load the buffer for DMA transfer. */ 394 fl = (datain) ? BUS_DMA_READ : BUS_DMA_WRITE; 395 396 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_xfer, *addr, 397 *len, NULL, BUS_DMA_STREAMING|fl))) { 398 printf("%s: esp_dma_setup: unable to load DMA buffer - error %d\n", 399 sc->sc_dev.dv_xname, error); 400 return (error); 401 } 402 403 bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0, 404 *len, (datain) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 405 406 esc->sc_flags |= ESP_XFER_LOADED | (datain ? ESP_XFER_READ : 0); 407 esc->sc_xfer_addr = addr; 408 esc->sc_xfer_len = len; 409 410 return (0); 411 } 412 413 static void 414 esp_dma_go(sc) 415 struct ncr53c9x_softc *sc; 416 { 417 struct esp_softc *esc = (struct esp_softc *) sc; 418 DPRINTF(("[esp_dma_go] ")); 419 420 esc->sc_flags |= ESP_XFER_ACTIVE; 421 mca_disk_busy(); 422 } 423 424 static void 425 esp_dma_stop(sc) 426 struct ncr53c9x_softc *sc; 427 { 428 DPRINTF(("[esp_dma_stop] ")); 429 430 panic("%s: stop not yet implemented", sc->sc_dev.dv_xname); 431 } 432 433 static int 434 esp_dma_isactive(sc) 435 struct ncr53c9x_softc *sc; 436 { 437 struct esp_softc *esc = (struct esp_softc *) sc; 438 DPRINTF(("[esp_dma_isactive] ")); 439 440 return (esc->sc_flags & ESP_XFER_ACTIVE); 441 } 442
Indexes created Sun Oct 12 09:09:55 GMT 2025