esp_mca.c revision 1.16
1 /* $NetBSD: esp_mca.c,v 1.16 2007/10/19 12:00:34 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek <jdolecek (at) NetBSD.org>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for NCR 53c90, MCA version, with 86c01 DMA controller chip. 41 * 42 * Some of the information used to write this driver was taken 43 * from Tymm Twillman <tymm (at) computer.org>'s Linux MCA NC53c90 driver, 44 * in drivers/scsi/mca_53c9x.c 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: esp_mca.c,v 1.16 2007/10/19 12:00:34 ad Exp $"); 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/errno.h> 55 #include <sys/ioctl.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 #include <dev/scsipi/scsi_message.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/mca/espvar.h> 74 #include <dev/mca/espreg.h> 75 76 #include <dev/mca/mcavar.h> 77 #include <dev/mca/mcareg.h> 78 #include <dev/mca/mcadevs.h> 79 80 #if 0 81 #if defined(DEBUG) && !defined(NCR53C9X_DEBUG) 82 #define NCR53C9X_DEBUG 83 #endif 84 #endif 85 86 #ifdef NCR53C9X_DEBUG 87 static int esp_mca_debug = 0; 88 #define DPRINTF(x) if (esp_mca_debug) printf x; 89 #else 90 #define DPRINTF(x) 91 #endif 92 93 #define ESP_MCA_IOSIZE 0x20 94 #define ESP_REG_OFFSET 0x10 95 96 static void esp_mca_attach(struct device *, struct device *, void *); 97 static int esp_mca_match(struct device *, struct cfdata *, void *); 98 99 CFATTACH_DECL(esp_mca, sizeof(struct esp_softc), 100 esp_mca_match, esp_mca_attach, NULL, NULL); 101 102 /* 103 * Functions and the switch for the MI code. 104 */ 105 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 106 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 107 static int esp_dma_isintr(struct ncr53c9x_softc *); 108 static void esp_dma_reset(struct ncr53c9x_softc *); 109 static int esp_dma_intr(struct ncr53c9x_softc *); 110 static int esp_dma_setup(struct ncr53c9x_softc *, void **, 111 size_t *, int, size_t *); 112 static void esp_dma_go(struct ncr53c9x_softc *); 113 static void esp_dma_stop(struct ncr53c9x_softc *); 114 static int esp_dma_isactive(struct ncr53c9x_softc *); 115 116 static struct ncr53c9x_glue esp_glue = { 117 esp_read_reg, 118 esp_write_reg, 119 esp_dma_isintr, 120 esp_dma_reset, 121 esp_dma_intr, 122 esp_dma_setup, 123 esp_dma_go, 124 esp_dma_stop, 125 esp_dma_isactive, 126 NULL, /* gl_clear_latched_intr */ 127 }; 128 129 static int 130 esp_mca_match( 131 struct device *parent, 132 struct cfdata *cf, 133 void *aux 134 ) 135 { 136 struct mca_attach_args *ma = aux; 137 138 switch (ma->ma_id) { 139 case MCA_PRODUCT_NCR53C90: 140 return 1; 141 } 142 143 return 0; 144 } 145 146 static void 147 esp_mca_attach( 148 struct device *parent, 149 struct device *self, 150 void *aux 151 ) 152 { 153 struct mca_attach_args *ma = aux; 154 struct esp_softc *esc = device_private(self); 155 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 156 u_int16_t iobase; 157 int scsi_id, irq, drq, error; 158 bus_space_handle_t ioh; 159 int pos2, pos3, pos5; 160 161 static const u_int16_t ncrmca_iobase[] = { 162 0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240 163 }; 164 165 /* 166 * NCR SCSI Adapter (ADF 7f4f) 167 * 168 * POS register 2: (adf pos0) 169 * 170 * 7 6 5 4 3 2 1 0 171 * \_/ \___/ \__ enable: 0=adapter disabled, 1=adapter enabled 172 * | \____ I/O base (32B): 001=0x240 010=0x340 011=0x400 173 * | 100=0x420 101=0x3240 110=0x8240 111=0xa240 174 * \__________ IRQ: 00=3 01=5 10=7 11=9 175 * 176 * POS register 3: (adf pos1) 177 * 178 * 7 6 5 4 3 2 1 0 179 * 1 1 1 | \_____/ 180 * | \__ DMA level 181 * \_________ Fairness: 1=enabled 0=disabled 182 * 183 * POS register 5: (adf pos3) 184 * 185 * 7 6 5 4 3 2 1 0 186 * 1 | \___/ 187 * | \__ Static Ram: 0xC8000-0xC87FF + XX*0x4000 188 * \___________ Host Adapter ID: 1=7 0=6 189 */ 190 191 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 192 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 193 pos5 = mca_conf_read(ma->ma_mc, ma->ma_slot, 5); 194 195 iobase = ncrmca_iobase[(pos2 & 0x0e) >> 1]; 196 irq = 3 + 2*((pos2 & 0x30) >> 4); 197 drq = (pos3 & 0x0f); 198 scsi_id = 6 + ((pos5 & 0x20) ? 1 : 0); 199 200 printf(" slot %d irq %d drq %d: NCR SCSI Adapter\n", 201 ma->ma_slot + 1, irq, drq); 202 203 /* Map the 86C01 registers */ 204 if (bus_space_map(ma->ma_iot, iobase, ESP_MCA_IOSIZE, 0, &ioh)) { 205 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 206 return; 207 } 208 209 esc->sc_iot = ma->ma_iot; 210 esc->sc_ioh = ioh; 211 212 /* Submap the 'esp' registers */ 213 if (bus_space_subregion(ma->ma_iot, ioh, ESP_REG_OFFSET, 214 ESP_MCA_IOSIZE-ESP_REG_OFFSET, &esc->sc_esp_ioh)) { 215 printf("%s: can't subregion i/o space\n", sc->sc_dev.dv_xname); 216 return; 217 } 218 219 /* Setup DMA map */ 220 esc->sc_dmat = ma->ma_dmat; 221 if ((error = mca_dmamap_create(esc->sc_dmat, MAXPHYS, 222 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_IOPORT, 223 &esc->sc_xfer, drq)) != 0){ 224 printf("%s: couldn't create DMA map - error %d\n", 225 sc->sc_dev.dv_xname, error); 226 return; 227 } 228 229 /* MI code glue */ 230 sc->sc_id = scsi_id; 231 sc->sc_freq = 25; /* MHz */ 232 233 sc->sc_glue = &esp_glue; 234 235 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; //| NCRCFG1_SLOW; 236 /* No point setting sc_cfg[2345], they won't be used */ 237 238 sc->sc_rev = NCR_VARIANT_NCR53C90_86C01; 239 sc->sc_minsync = 0; 240 241 /* max 64KB DMA */ 242 sc->sc_maxxfer = 64 * 1024; 243 244 /* Establish interrupt */ 245 esc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, ncr53c9x_intr, 246 esc); 247 if (esc->sc_ih == NULL) { 248 printf("%s: couldn't establish interrupt\n", 249 sc->sc_dev.dv_xname); 250 return; 251 } 252 253 /* 254 * Massage the 86C01 chip - setup MCA DMA controller for DMA via 255 * the 86C01 register, and enable 86C01 interrupts. 256 */ 257 mca_dma_set_ioport(drq, iobase + N86C01_PIO); 258 259 bus_space_write_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE, 260 bus_space_read_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE) 261 | N86C01_INTR_ENABLE); 262 263 /* 264 * Now try to attach all the sub-devices 265 */ 266 sc->sc_adapter.adapt_minphys = minphys; 267 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 268 269 /* Do the common parts of attachment. */ 270 printf("%s", sc->sc_dev.dv_xname); 271 ncr53c9x_attach(sc); 272 } 273 274 /* 275 * Glue functions. 276 */ 277 278 static u_char 279 esp_read_reg(sc, reg) 280 struct ncr53c9x_softc *sc; 281 int reg; 282 { 283 struct esp_softc *esc = (struct esp_softc *)sc; 284 285 return (bus_space_read_1(esc->sc_iot, esc->sc_esp_ioh, reg)); 286 } 287 288 static void 289 esp_write_reg(sc, reg, val) 290 struct ncr53c9x_softc *sc; 291 int reg; 292 u_char val; 293 { 294 struct esp_softc *esc = (struct esp_softc *)sc; 295 296 bus_space_write_1(esc->sc_iot, esc->sc_esp_ioh, reg, val); 297 } 298 299 static int 300 esp_dma_isintr(sc) 301 struct ncr53c9x_softc *sc; 302 { 303 struct esp_softc *esc = (struct esp_softc *)sc; 304 305 DPRINTF(("[esp_dma_isintr] ")); 306 return (bus_space_read_1(esc->sc_iot, esc->sc_ioh, 307 N86C01_STATUS) & N86C01_IRQ_PEND); 308 } 309 310 static void 311 esp_dma_reset(sc) 312 struct ncr53c9x_softc *sc; 313 { 314 struct esp_softc *esc = (struct esp_softc *)sc; 315 316 DPRINTF(("[esp_dma_reset] ")); 317 318 if (esc->sc_flags & ESP_XFER_LOADED) { 319 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 320 esc->sc_flags &= ~ESP_XFER_LOADED; 321 } 322 323 if (esc->sc_flags & ESP_XFER_ACTIVE) { 324 esc->sc_flags &= ~ESP_XFER_ACTIVE; 325 mca_disk_unbusy(); 326 } 327 } 328 329 static int 330 esp_dma_intr(sc) 331 struct ncr53c9x_softc *sc; 332 { 333 struct esp_softc *esc = (struct esp_softc *) sc; 334 DPRINTF(("[esp_dma_intr] ")); 335 336 if ((esc->sc_flags & ESP_XFER_ACTIVE) == 0) { 337 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 338 return (-1); 339 } 340 341 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 342 esc->sc_flags &= ~ESP_XFER_ACTIVE; 343 mca_disk_unbusy(); 344 return (0); 345 } 346 347 sc->sc_espstat |= NCRSTAT_TC; /* XXX */ 348 349 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 350 printf("%s: DMA not complete?\n", sc->sc_dev.dv_xname); 351 return (1); 352 } 353 354 bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0, 355 *esc->sc_xfer_len, 356 (esc->sc_flags & ESP_XFER_READ) 357 ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 358 359 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 360 esc->sc_flags &= ~ESP_XFER_LOADED; 361 362 *esc->sc_xfer_addr += *esc->sc_xfer_len; 363 *esc->sc_xfer_len = 0; 364 365 esc->sc_flags &= ~ESP_XFER_ACTIVE; 366 mca_disk_unbusy(); 367 368 return (0); 369 } 370 371 /* 372 * Setup DMA transfer. 373 */ 374 static int 375 esp_dma_setup( 376 struct ncr53c9x_softc *sc, 377 void **addr, 378 size_t *len, 379 int datain, 380 size_t *dmasize 381 ) 382 { 383 struct esp_softc *esc = (struct esp_softc *) sc; 384 int error; 385 int fl; 386 387 DPRINTF(("[esp_dma_setup] ")); 388 389 if (esc->sc_flags & ESP_XFER_LOADED) { 390 printf("%s: esp_dma_setup: unloading leaked xfer\n", 391 sc->sc_dev.dv_xname); 392 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 393 esc->sc_flags &= ~ESP_XFER_LOADED; 394 } 395 396 /* Load the buffer for DMA transfer. */ 397 fl = (datain) ? BUS_DMA_READ : BUS_DMA_WRITE; 398 399 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_xfer, *addr, 400 *len, NULL, BUS_DMA_STREAMING|fl))) { 401 printf("%s: esp_dma_setup: unable to load DMA buffer - error %d\n", 402 sc->sc_dev.dv_xname, error); 403 return (error); 404 } 405 406 bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0, 407 *len, (datain) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 408 409 esc->sc_flags |= ESP_XFER_LOADED | (datain ? ESP_XFER_READ : 0); 410 esc->sc_xfer_addr = addr; 411 esc->sc_xfer_len = len; 412 413 return (0); 414 } 415 416 static void 417 esp_dma_go(sc) 418 struct ncr53c9x_softc *sc; 419 { 420 struct esp_softc *esc = (struct esp_softc *) sc; 421 DPRINTF(("[esp_dma_go] ")); 422 423 esc->sc_flags |= ESP_XFER_ACTIVE; 424 mca_disk_busy(); 425 } 426 427 static void 428 esp_dma_stop(sc) 429 struct ncr53c9x_softc *sc; 430 { 431 DPRINTF(("[esp_dma_stop] ")); 432 433 panic("%s: stop not yet implemented", sc->sc_dev.dv_xname); 434 } 435 436 static int 437 esp_dma_isactive(sc) 438 struct ncr53c9x_softc *sc; 439 { 440 struct esp_softc *esc = (struct esp_softc *) sc; 441 DPRINTF(("[esp_dma_isactive] ")); 442 443 return (esc->sc_flags & ESP_XFER_ACTIVE); 444 } 445
Indexes created Tue Sep 30 11:09:46 GMT 2025