esp_mca.c revision 1.18
1 /* $NetBSD: esp_mca.c,v 1.18 2008/04/13 04:55:53 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jaromir Dolecek <jdolecek (at) NetBSD.org>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for NCR 53c90, MCA version, with 86c01 DMA controller chip. 41 * 42 * Some of the information used to write this driver was taken 43 * from Tymm Twillman <tymm (at) computer.org>'s Linux MCA NC53c90 driver, 44 * in drivers/scsi/mca_53c9x.c 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: esp_mca.c,v 1.18 2008/04/13 04:55:53 tsutsui Exp $"); 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/errno.h> 55 #include <sys/ioctl.h> 56 #include <sys/device.h> 57 #include <sys/buf.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 #include <dev/scsipi/scsi_message.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/mca/espvar.h> 74 #include <dev/mca/espreg.h> 75 76 #include <dev/mca/mcavar.h> 77 #include <dev/mca/mcareg.h> 78 #include <dev/mca/mcadevs.h> 79 80 #if 0 81 #if defined(DEBUG) && !defined(NCR53C9X_DEBUG) 82 #define NCR53C9X_DEBUG 83 #endif 84 #endif 85 86 #ifdef NCR53C9X_DEBUG 87 static int esp_mca_debug = 0; 88 #define DPRINTF(x) if (esp_mca_debug) printf x; 89 #else 90 #define DPRINTF(x) 91 #endif 92 93 #define ESP_MCA_IOSIZE 0x20 94 #define ESP_REG_OFFSET 0x10 95 96 static int esp_mca_match(device_t, cfdata_t, void *); 97 static void esp_mca_attach(device_t, device_t, void *); 98 99 CFATTACH_DECL_NWE(esp_mca, sizeof(struct esp_softc), 100 esp_mca_match, esp_mca_attach, NULL, NULL); 101 102 /* 103 * Functions and the switch for the MI code. 104 */ 105 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int); 106 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 107 static int esp_dma_isintr(struct ncr53c9x_softc *); 108 static void esp_dma_reset(struct ncr53c9x_softc *); 109 static int esp_dma_intr(struct ncr53c9x_softc *); 110 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, 111 size_t *, int, size_t *); 112 static void esp_dma_go(struct ncr53c9x_softc *); 113 static void esp_dma_stop(struct ncr53c9x_softc *); 114 static int esp_dma_isactive(struct ncr53c9x_softc *); 115 116 static struct ncr53c9x_glue esp_glue = { 117 esp_read_reg, 118 esp_write_reg, 119 esp_dma_isintr, 120 esp_dma_reset, 121 esp_dma_intr, 122 esp_dma_setup, 123 esp_dma_go, 124 esp_dma_stop, 125 esp_dma_isactive, 126 NULL, /* gl_clear_latched_intr */ 127 }; 128 129 static int 130 esp_mca_match(device_t parent, cfdata_t cf, void *aux) 131 { 132 struct mca_attach_args *ma = aux; 133 134 switch (ma->ma_id) { 135 case MCA_PRODUCT_NCR53C90: 136 return 1; 137 } 138 139 return 0; 140 } 141 142 static void 143 esp_mca_attach(device_t parent, device_t self, void *aux) 144 { 145 struct esp_softc *esc = device_private(self); 146 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 147 struct mca_attach_args *ma = aux; 148 uint16_t iobase; 149 int scsi_id, irq, drq, error; 150 bus_space_handle_t ioh; 151 int pos2, pos3, pos5; 152 153 static const uint16_t ncrmca_iobase[] = { 154 0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240 155 }; 156 157 sc->sc_dev = self; 158 159 /* 160 * NCR SCSI Adapter (ADF 7f4f) 161 * 162 * POS register 2: (adf pos0) 163 * 164 * 7 6 5 4 3 2 1 0 165 * \_/ \___/ \__ enable: 0=adapter disabled, 1=adapter enabled 166 * | \____ I/O base (32B): 001=0x240 010=0x340 011=0x400 167 * | 100=0x420 101=0x3240 110=0x8240 111=0xa240 168 * \__________ IRQ: 00=3 01=5 10=7 11=9 169 * 170 * POS register 3: (adf pos1) 171 * 172 * 7 6 5 4 3 2 1 0 173 * 1 1 1 | \_____/ 174 * | \__ DMA level 175 * \_________ Fairness: 1=enabled 0=disabled 176 * 177 * POS register 5: (adf pos3) 178 * 179 * 7 6 5 4 3 2 1 0 180 * 1 | \___/ 181 * | \__ Static Ram: 0xC8000-0xC87FF + XX*0x4000 182 * \___________ Host Adapter ID: 1=7 0=6 183 */ 184 185 pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2); 186 pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3); 187 pos5 = mca_conf_read(ma->ma_mc, ma->ma_slot, 5); 188 189 iobase = ncrmca_iobase[(pos2 & 0x0e) >> 1]; 190 irq = 3 + 2 * ((pos2 & 0x30) >> 4); 191 drq = (pos3 & 0x0f); 192 scsi_id = 6 + ((pos5 & 0x20) ? 1 : 0); 193 194 aprint_normal(" slot %d irq %d drq %d: NCR SCSI Adapter\n", 195 ma->ma_slot + 1, irq, drq); 196 197 /* Map the 86C01 registers */ 198 if (bus_space_map(ma->ma_iot, iobase, ESP_MCA_IOSIZE, 0, &ioh)) { 199 aprint_error_dev(&sc->sc_dev, "can't map i/o space\n"); 200 return; 201 } 202 203 esc->sc_iot = ma->ma_iot; 204 esc->sc_ioh = ioh; 205 206 /* Submap the 'esp' registers */ 207 if (bus_space_subregion(ma->ma_iot, ioh, ESP_REG_OFFSET, 208 ESP_MCA_IOSIZE-ESP_REG_OFFSET, &esc->sc_esp_ioh)) { 209 aprint_error_dev(&sc->sc_dev, "can't subregion i/o space\n"); 210 return; 211 } 212 213 /* Setup DMA map */ 214 esc->sc_dmat = ma->ma_dmat; 215 if ((error = mca_dmamap_create(esc->sc_dmat, MAXPHYS, 216 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_IOPORT, 217 &esc->sc_xfer, drq)) != 0){ 218 aprint_error_dev(&sc->sc_dev, 219 "couldn't create DMA map - error %d\n", error); 220 return; 221 } 222 223 /* MI code glue */ 224 sc->sc_id = scsi_id; 225 sc->sc_freq = 25; /* MHz */ 226 227 sc->sc_glue = &esp_glue; 228 229 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; //| NCRCFG1_SLOW; 230 /* No point setting sc_cfg[2345], they won't be used */ 231 232 sc->sc_rev = NCR_VARIANT_NCR53C90_86C01; 233 sc->sc_minsync = 0; 234 235 /* max 64KB DMA */ 236 sc->sc_maxxfer = 64 * 1024; 237 238 /* Establish interrupt */ 239 esc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, ncr53c9x_intr, 240 esc); 241 if (esc->sc_ih == NULL) { 242 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt\n"); 243 return; 244 } 245 246 /* 247 * Massage the 86C01 chip - setup MCA DMA controller for DMA via 248 * the 86C01 register, and enable 86C01 interrupts. 249 */ 250 mca_dma_set_ioport(drq, iobase + N86C01_PIO); 251 252 bus_space_write_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE, 253 bus_space_read_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE) | 254 N86C01_INTR_ENABLE); 255 256 /* 257 * Now try to attach all the sub-devices 258 */ 259 sc->sc_adapter.adapt_minphys = minphys; 260 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 261 262 /* Do the common parts of attachment. */ 263 printf("%s", device_xname(self)); 264 ncr53c9x_attach(sc); 265 } 266 267 /* 268 * Glue functions. 269 */ 270 271 static uint8_t 272 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 273 { 274 struct esp_softc *esc = (struct esp_softc *)sc; 275 276 return bus_space_read_1(esc->sc_iot, esc->sc_esp_ioh, reg); 277 } 278 279 static void 280 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 281 { 282 struct esp_softc *esc = (struct esp_softc *)sc; 283 284 bus_space_write_1(esc->sc_iot, esc->sc_esp_ioh, reg, val); 285 } 286 287 static int 288 esp_dma_isintr(struct ncr53c9x_softc *sc) 289 { 290 struct esp_softc *esc = (struct esp_softc *)sc; 291 292 DPRINTF(("[esp_dma_isintr] ")); 293 return bus_space_read_1(esc->sc_iot, esc->sc_ioh, N86C01_STATUS) & 294 N86C01_IRQ_PEND; 295 } 296 297 static void 298 esp_dma_reset(struct ncr53c9x_softc *sc) 299 { 300 struct esp_softc *esc = (struct esp_softc *)sc; 301 302 DPRINTF(("[esp_dma_reset] ")); 303 304 if (esc->sc_flags & ESP_XFER_LOADED) { 305 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 306 esc->sc_flags &= ~ESP_XFER_LOADED; 307 } 308 309 if (esc->sc_flags & ESP_XFER_ACTIVE) { 310 esc->sc_flags &= ~ESP_XFER_ACTIVE; 311 mca_disk_unbusy(); 312 } 313 } 314 315 static int 316 esp_dma_intr(struct ncr53c9x_softc *sc) 317 { 318 struct esp_softc *esc = (struct esp_softc *)sc; 319 320 DPRINTF(("[esp_dma_intr] ")); 321 322 if ((esc->sc_flags & ESP_XFER_ACTIVE) == 0) { 323 printf("%s: dma_intr--inactive DMA\n", 324 device_xname(sc->sc_dev)); 325 return -1; 326 } 327 328 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 329 esc->sc_flags &= ~ESP_XFER_ACTIVE; 330 mca_disk_unbusy(); 331 return 0; 332 } 333 334 sc->sc_espstat |= NCRSTAT_TC; /* XXX */ 335 336 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 337 printf("%s: DMA not complete?\n", device_xname(sc->sc_dev)); 338 return 1; 339 } 340 341 bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0, *esc->sc_xfer_len, 342 (esc->sc_flags & ESP_XFER_READ) ? 343 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 344 345 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 346 esc->sc_flags &= ~ESP_XFER_LOADED; 347 348 *esc->sc_xfer_addr += *esc->sc_xfer_len; 349 *esc->sc_xfer_len = 0; 350 351 esc->sc_flags &= ~ESP_XFER_ACTIVE; 352 mca_disk_unbusy(); 353 354 return 0; 355 } 356 357 /* 358 * Setup DMA transfer. 359 */ 360 static int 361 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 362 int datain, size_t *dmasize) 363 { 364 struct esp_softc *esc = (struct esp_softc *)sc; 365 int error; 366 int fl; 367 368 DPRINTF(("[esp_dma_setup] ")); 369 370 if (esc->sc_flags & ESP_XFER_LOADED) { 371 printf("%s: %s: unloading leaked xfer\n", 372 device_xname(sc->sc_dev), __func__); 373 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer); 374 esc->sc_flags &= ~ESP_XFER_LOADED; 375 } 376 377 /* Load the buffer for DMA transfer. */ 378 fl = (datain) ? BUS_DMA_READ : BUS_DMA_WRITE; 379 380 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_xfer, *addr, 381 *len, NULL, BUS_DMA_STREAMING|fl))) { 382 printf("%s: %s: unable to load DMA buffer - error %d\n", 383 device_xname(sc->sc_dev), __func__, error); 384 return error; 385 } 386 387 bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0, *len, 388 (datain) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 389 390 esc->sc_flags |= ESP_XFER_LOADED | (datain ? ESP_XFER_READ : 0); 391 esc->sc_xfer_addr = addr; 392 esc->sc_xfer_len = len; 393 394 return 0; 395 } 396 397 static void 398 esp_dma_go(struct ncr53c9x_softc *sc) 399 { 400 struct esp_softc *esc = (struct esp_softc *)sc; 401 DPRINTF(("[esp_dma_go] ")); 402 403 esc->sc_flags |= ESP_XFER_ACTIVE; 404 mca_disk_busy(); 405 } 406 407 static void 408 esp_dma_stop(struct ncr53c9x_softc *sc) 409 { 410 411 DPRINTF(("[esp_dma_stop] ")); 412 413 panic("%s: stop not yet implemented", device_xname(sc->sc_dev)); 414 } 415 416 static int 417 esp_dma_isactive(struct ncr53c9x_softc *sc) 418 { 419 struct esp_softc *esc = (struct esp_softc *)sc; 420 DPRINTF(("[esp_dma_isactive] ")); 421 422 return esc->sc_flags & ESP_XFER_ACTIVE; 423 } 424
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