aic79xx.reg revision 1.3
1 /* 2 * Aic79xx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.reg,v 1.10 2003/03/25 22:16:27 scottl Exp $ 41 */ 42 VERSION = "$NetBSD: aic79xx.reg,v 1.3 2003/05/14 12:57:46 wiz Exp $" 43 44 /* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic79xx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic79xx driver. 48 */ 49 50 /* Register window Modes */ 51 #define M_DFF0 0 52 #define M_DFF1 1 53 #define M_CCHAN 2 54 #define M_SCSI 3 55 #define M_CFG 4 56 #define M_DST_SHIFT 4 57 58 #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59 #define SET_MODE(src, dst) \ 60 SET_SRC_MODE src; \ 61 SET_DST_MODE dst; \ 62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63 mvi MK_MODE(src, dst) call set_mode_work_around; \ 64 } else { \ 65 mvi MODE_PTR, MK_MODE(src, dst); \ 66 } 67 68 #define TOGGLE_DFF_MODE \ 69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70 call toggle_dff_mode_work_around; \ 71 } else { \ 72 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 73 } 74 75 #define RESTORE_MODE(mode) \ 76 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 77 mov mode call set_mode_work_around; \ 78 } else { \ 79 mov MODE_PTR, mode; \ 80 } 81 82 #define SET_SEQINTCODE(code) \ 83 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 84 mvi code call set_seqint_work_around; \ 85 } else { \ 86 mvi SEQINTCODE, code; \ 87 } 88 89 /* 90 * Mode Pointer 91 * Controls which of the 5, 512byte, address spaces should be used 92 * as the source and destination of any register accesses in our 93 * register window. 94 */ 95 register MODE_PTR { 96 address 0x000 97 access_mode RW 98 field DST_MODE 0x70 99 field SRC_MODE 0x07 100 mode_pointer 101 } 102 103 const SRC_MODE_SHIFT 0 104 const DST_MODE_SHIFT 4 105 106 /* 107 * Host Interrupt Status 108 */ 109 register INTSTAT { 110 address 0x001 111 access_mode RW 112 field HWERRINT 0x80 113 field BRKADRINT 0x40 114 field SWTMINT 0x20 115 field PCIINT 0x10 116 field SCSIINT 0x08 117 field SEQINT 0x04 118 field CMDCMPLT 0x02 119 field SPLTINT 0x01 120 mask INT_PEND 0xFF 121 } 122 123 /* 124 * Sequencer Interrupt Code 125 */ 126 register SEQINTCODE { 127 address 0x002 128 access_mode RW 129 field { 130 NO_SEQINT, /* No seqint pending. */ 131 BAD_PHASE, /* unknown scsi bus phase */ 132 SEND_REJECT, /* sending a message reject */ 133 PROTO_VIOLATION, /* Protocol Violation */ 134 NO_MATCH, /* no cmd match for reconnect */ 135 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 136 PDATA_REINIT, /* 137 * Returned to data phase 138 * that requires data 139 * transfer pointers to be 140 * recalculated from the 141 * transfer residual. 142 */ 143 HOST_MSG_LOOP, /* 144 * The bus is ready for the 145 * host to perform another 146 * message transaction. This 147 * mechanism is used for things 148 * like sync/wide negotiation 149 * that require a kernel based 150 * message state engine. 151 */ 152 BAD_STATUS, /* Bad status from target */ 153 DATA_OVERRUN, /* 154 * Target attempted to write 155 * beyond the bounds of its 156 * command. 157 */ 158 MKMSG_FAILED, /* 159 * Target completed command 160 * without honoring our ATN 161 * request to issue a message. 162 */ 163 MISSED_BUSFREE, /* 164 * The sequencer never saw 165 * the bus go free after 166 * either a command complete 167 * or disconnect message. 168 */ 169 DUMP_CARD_STATE, 170 ILLEGAL_PHASE, 171 INVALID_SEQINT, 172 CFG4ISTAT_INTR, 173 STATUS_OVERRUN, 174 CFG4OVERRUN, 175 ENTERING_NONPACK, 176 TASKMGMT_FUNC_COMPLETE, /* 177 * Task management function 178 * request completed with 179 * an expected busfree. 180 */ 181 TASKMGMT_CMD_CMPLT_OKAY, /* 182 * A command with a non-zero 183 * task management function 184 * has completed via the normal 185 * command completion method 186 * for commands with a zero 187 * task management function. 188 * This happens when an attempt 189 * to abort a command loses 190 * the race for the command to 191 * complete normally. 192 */ 193 TRACEPOINT0, 194 TRACEPOINT1, 195 TRACEPOINT2, 196 TRACEPOINT3, 197 SAW_HWERR 198 } 199 } 200 201 /* 202 * Clear Host Interrupt 203 */ 204 register CLRINT { 205 address 0x003 206 access_mode WO 207 field CLRHWERRINT 0x80 /* Rev B or greater */ 208 field CLRBRKADRINT 0x40 209 field CLRSWTMINT 0x20 210 field CLRPCIINT 0x10 211 field CLRSCSIINT 0x08 212 field CLRSEQINT 0x04 213 field CLRCMDINT 0x02 214 field CLRSPLTINT 0x01 215 } 216 217 /* 218 * Error Register 219 */ 220 register ERROR { 221 address 0x004 222 access_mode RO 223 field CIOPARERR 0x80 224 field CIOACCESFAIL 0x40 /* Rev B or greater */ 225 field MPARERR 0x20 226 field DPARERR 0x10 227 field SQPARERR 0x08 228 field ILLOPCODE 0x04 229 field DSCTMOUT 0x02 230 } 231 232 /* 233 * Clear Error 234 */ 235 register CLRERR { 236 address 0x004 237 access_mode WO 238 field CLRCIOPARERR 0x80 239 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 240 field CLRMPARERR 0x20 241 field CLRDPARERR 0x10 242 field CLRSQPARERR 0x08 243 field CLRILLOPCODE 0x04 244 field CLRDSCTMOUT 0x02 245 } 246 247 /* 248 * Host Control Register 249 * Overall host control of the device. 250 */ 251 register HCNTRL { 252 address 0x005 253 access_mode RW 254 field SEQ_RESET 0x80 /* Rev B or greater */ 255 field POWRDN 0x40 256 field SWINT 0x10 257 field SWTIMER_START_B 0x08 /* Rev B or greater */ 258 field PAUSE 0x04 259 field INTEN 0x02 260 field CHIPRST 0x01 261 field CHIPRSTACK 0x01 262 } 263 264 /* 265 * Host New SCB Queue Offset 266 */ 267 register HNSCB_QOFF { 268 address 0x006 269 access_mode RW 270 size 2 271 } 272 273 /* 274 * Host Empty SCB Queue Offset 275 */ 276 register HESCB_QOFF { 277 address 0x008 278 access_mode RW 279 } 280 281 /* 282 * Host Mailbox 283 */ 284 register HS_MAILBOX { 285 address 0x00B 286 access_mode RW 287 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 288 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 289 } 290 291 /* 292 * Sequencer Interupt Status 293 */ 294 register SEQINTSTAT { 295 address 0x00C 296 access_mode RO 297 field SEQ_SWTMRTO 0x10 298 field SEQ_SEQINT 0x08 299 field SEQ_SCSIINT 0x04 300 field SEQ_PCIINT 0x02 301 field SEQ_SPLTINT 0x01 302 } 303 304 /* 305 * Clear SEQ Interrupt 306 */ 307 register CLRSEQINTSTAT { 308 address 0x00C 309 access_mode WO 310 field CLRSEQ_SWTMRTO 0x10 311 field CLRSEQ_SEQINT 0x08 312 field CLRSEQ_SCSIINT 0x04 313 field CLRSEQ_PCIINT 0x02 314 field CLRSEQ_SPLTINT 0x01 315 } 316 317 /* 318 * Software Timer 319 */ 320 register SWTIMER { 321 address 0x00E 322 access_mode RW 323 size 2 324 } 325 326 /* 327 * SEQ New SCB Queue Offset 328 */ 329 register SNSCB_QOFF { 330 address 0x010 331 access_mode RW 332 size 2 333 modes M_CCHAN 334 } 335 336 /* 337 * SEQ Empty SCB Queue Offset 338 */ 339 register SESCB_QOFF { 340 address 0x012 341 access_mode RW 342 modes M_CCHAN 343 } 344 345 /* 346 * SEQ Done SCB Queue Offset 347 */ 348 register SDSCB_QOFF { 349 address 0x014 350 access_mode RW 351 modes M_CCHAN 352 size 2 353 } 354 355 /* 356 * Queue Offset Control & Status 357 */ 358 register QOFF_CTLSTA { 359 address 0x016 360 access_mode RW 361 modes M_CCHAN 362 field EMPTY_SCB_AVAIL 0x80 363 field NEW_SCB_AVAIL 0x40 364 field SDSCB_ROLLOVR 0x20 365 field HS_MAILBOX_ACT 0x10 366 field SCB_QSIZE 0x0F { 367 SCB_QSIZE_4, 368 SCB_QSIZE_8, 369 SCB_QSIZE_16, 370 SCB_QSIZE_32, 371 SCB_QSIZE_64, 372 SCB_QSIZE_128, 373 SCB_QSIZE_256, 374 SCB_QSIZE_512, 375 SCB_QSIZE_1024, 376 SCB_QSIZE_2048, 377 SCB_QSIZE_4096, 378 SCB_QSIZE_8192, 379 SCB_QSIZE_16384 380 } 381 } 382 383 /* 384 * Interrupt Control 385 */ 386 register INTCTL { 387 address 0x018 388 access_mode RW 389 field SWTMINTMASK 0x80 390 field SWTMINTEN 0x40 391 field SWTIMER_START 0x20 392 field AUTOCLRCMDINT 0x10 393 field PCIINTEN 0x08 394 field SCSIINTEN 0x04 395 field SEQINTEN 0x02 396 field SPLTINTEN 0x01 397 } 398 399 /* 400 * Data FIFO Control 401 */ 402 register DFCNTRL { 403 address 0x019 404 access_mode RW 405 modes M_DFF0, M_DFF1 406 field PRELOADEN 0x80 407 field SCSIENWRDIS 0x40 /* Rev B only. */ 408 field SCSIEN 0x20 409 field SCSIENACK 0x20 410 field HDMAEN 0x08 411 field HDMAENACK 0x08 412 field DIRECTION 0x04 413 field DIRECTIONACK 0x04 414 field FIFOFLUSH 0x02 415 field FIFOFLUSHACK 0x02 416 field DIRECTIONEN 0x01 417 } 418 419 /* 420 * Device Space Command 0 421 */ 422 register DSCOMMAND0 { 423 address 0x019 424 access_mode RW 425 modes M_CFG 426 field CACHETHEN 0x80 /* Cache Threshold enable */ 427 field DPARCKEN 0x40 /* Data Parity Check Enable */ 428 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 429 field EXTREQLCK 0x10 /* External Request Lock */ 430 field DISABLE_TWATE 0x02 /* Rev B or greater */ 431 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 432 } 433 434 /* 435 * Data FIFO Status 436 */ 437 register DFSTATUS { 438 address 0x01A 439 access_mode RO 440 modes M_DFF0, M_DFF1 441 field PRELOAD_AVAIL 0x80 442 field PKT_PRELOAD_AVAIL 0x40 443 field MREQPEND 0x10 444 field HDONE 0x08 445 field DFTHRESH 0x04 446 field FIFOFULL 0x02 447 field FIFOEMP 0x01 448 } 449 450 /* 451 * S/G Cache Pointer 452 */ 453 register SG_CACHE_PRE { 454 address 0x01B 455 access_mode WO 456 modes M_DFF0, M_DFF1 457 field SG_ADDR_MASK 0xf8 458 field ODD_SEG 0x04 459 field LAST_SEG 0x02 460 } 461 462 register SG_CACHE_SHADOW { 463 address 0x01B 464 access_mode RO 465 modes M_DFF0, M_DFF1 466 field SG_ADDR_MASK 0xf8 467 field ODD_SEG 0x04 468 field LAST_SEG 0x02 469 field LAST_SEG_DONE 0x01 470 } 471 472 /* 473 * Arbiter Control 474 */ 475 register ARBCTL { 476 address 0x01B 477 access_mode RW 478 modes M_CFG 479 field RESET_HARB 0x80 480 field RETRY_SWEN 0x08 481 field USE_TIME 0x07 482 } 483 484 /* 485 * Data Channel Host Address 486 */ 487 register HADDR { 488 address 0x070 489 access_mode RW 490 size 8 491 modes M_DFF0, M_DFF1 492 } 493 494 /* 495 * Host Overlay DMA Address 496 */ 497 register HODMAADR { 498 address 0x070 499 access_mode RW 500 size 8 501 modes M_SCSI 502 } 503 504 /* 505 * PCI PLL Delay. 506 */ 507 register PLLDELAY { 508 address 0x070 509 access_mode RW 510 size 1 511 modes M_CFG 512 field SPLIT_DROP_REQ 0x80 513 } 514 515 /* 516 * Data Channel Host Count 517 */ 518 register HCNT { 519 address 0x078 520 access_mode RW 521 size 3 522 modes M_DFF0, M_DFF1 523 } 524 525 /* 526 * Host Overlay DMA Count 527 */ 528 register HODMACNT { 529 address 0x078 530 access_mode RW 531 size 2 532 modes M_SCSI 533 } 534 535 /* 536 * Host Overlay DMA Enable 537 */ 538 register HODMAEN { 539 address 0x07A 540 access_mode RW 541 modes M_SCSI 542 } 543 544 /* 545 * Scatter/Gather Host Address 546 */ 547 register SGHADDR { 548 address 0x07C 549 access_mode RW 550 size 8 551 modes M_DFF0, M_DFF1 552 } 553 554 /* 555 * SCB Host Address 556 */ 557 register SCBHADDR { 558 address 0x07C 559 access_mode RW 560 size 8 561 modes M_CCHAN 562 } 563 564 /* 565 * Scatter/Gather Host Count 566 */ 567 register SGHCNT { 568 address 0x084 569 access_mode RW 570 modes M_DFF0, M_DFF1 571 } 572 573 /* 574 * SCB Host Count 575 */ 576 register SCBHCNT { 577 address 0x084 578 access_mode RW 579 modes M_CCHAN 580 } 581 582 /* 583 * Data FIFO Threshold 584 */ 585 register DFF_THRSH { 586 address 0x088 587 access_mode RW 588 modes M_CFG 589 field WR_DFTHRSH 0x70 { 590 WR_DFTHRSH_MIN, 591 WR_DFTHRSH_25, 592 WR_DFTHRSH_50, 593 WR_DFTHRSH_63, 594 WR_DFTHRSH_75, 595 WR_DFTHRSH_85, 596 WR_DFTHRSH_90, 597 WR_DFTHRSH_MAX 598 } 599 field RD_DFTHRSH 0x07 { 600 RD_DFTHRSH_MIN, 601 RD_DFTHRSH_25, 602 RD_DFTHRSH_50, 603 RD_DFTHRSH_63, 604 RD_DFTHRSH_75, 605 RD_DFTHRSH_85, 606 RD_DFTHRSH_90, 607 RD_DFTHRSH_MAX 608 } 609 } 610 611 /* 612 * ROM Address 613 */ 614 register ROMADDR { 615 address 0x08A 616 access_mode RW 617 size 3 618 } 619 620 /* 621 * ROM Control 622 */ 623 register ROMCNTRL { 624 address 0x08D 625 access_mode RW 626 field ROMOP 0xE0 627 field ROMSPD 0x18 628 field REPEAT 0x02 629 field RDY 0x01 630 } 631 632 /* 633 * ROM Data 634 */ 635 register ROMDATA { 636 address 0x08E 637 access_mode RW 638 } 639 640 /* 641 * Data Channel Receive Message 0 642 */ 643 register DCHRXMSG0 { 644 address 0x090 645 access_mode RO 646 modes M_DFF0, M_DFF1 647 field CDNUM 0xF8 648 field CFNUM 0x07 649 } 650 651 /* 652 * CMC Recieve Message 0 653 */ 654 register CMCRXMSG0 { 655 address 0x090 656 access_mode RO 657 modes M_CCHAN 658 field CDNUM 0xF8 659 field CFNUM 0x07 660 } 661 662 /* 663 * Overlay Recieve Message 0 664 */ 665 register OVLYRXMSG0 { 666 address 0x090 667 access_mode RO 668 modes M_SCSI 669 field CDNUM 0xF8 670 field CFNUM 0x07 671 } 672 673 /* 674 * Relaxed Order Enable 675 */ 676 register ROENABLE { 677 address 0x090 678 access_mode RW 679 modes M_CFG 680 field MSIROEN 0x20 681 field OVLYROEN 0x10 682 field CMCROEN 0x08 683 field SGROEN 0x04 684 field DCH1ROEN 0x02 685 field DCH0ROEN 0x01 686 } 687 688 /* 689 * Data Channel Receive Message 1 690 */ 691 register DCHRXMSG1 { 692 address 0x091 693 access_mode RO 694 modes M_DFF0, M_DFF1 695 field CBNUM 0xFF 696 } 697 698 /* 699 * CMC Recieve Message 1 700 */ 701 register CMCRXMSG1 { 702 address 0x091 703 access_mode RO 704 modes M_CCHAN 705 field CBNUM 0xFF 706 } 707 708 /* 709 * Overlay Recieve Message 1 710 */ 711 register OVLYRXMSG1 { 712 address 0x091 713 access_mode RO 714 modes M_SCSI 715 field CBNUM 0xFF 716 } 717 718 /* 719 * No Snoop Enable 720 */ 721 register NSENABLE { 722 address 0x091 723 access_mode RW 724 modes M_CFG 725 field MSINSEN 0x20 726 field OVLYNSEN 0x10 727 field CMCNSEN 0x08 728 field SGNSEN 0x04 729 field DCH1NSEN 0x02 730 field DCH0NSEN 0x01 731 } 732 733 /* 734 * Data Channel Receive Message 2 735 */ 736 register DCHRXMSG2 { 737 address 0x092 738 access_mode RO 739 modes M_DFF0, M_DFF1 740 field MINDEX 0xFF 741 } 742 743 /* 744 * CMC Recieve Message 2 745 */ 746 register CMCRXMSG2 { 747 address 0x092 748 access_mode RO 749 modes M_CCHAN 750 field MINDEX 0xFF 751 } 752 753 /* 754 * Overlay Recieve Message 2 755 */ 756 register OVLYRXMSG2 { 757 address 0x092 758 access_mode RO 759 modes M_SCSI 760 field MINDEX 0xFF 761 } 762 763 /* 764 * Outstanding Split Transactions 765 */ 766 register OST { 767 address 0x092 768 access_mode RW 769 modes M_CFG 770 } 771 772 /* 773 * Data Channel Receive Message 3 774 */ 775 register DCHRXMSG3 { 776 address 0x093 777 access_mode RO 778 modes M_DFF0, M_DFF1 779 field MCLASS 0x0F 780 } 781 782 /* 783 * CMC Recieve Message 3 784 */ 785 register CMCRXMSG3 { 786 address 0x093 787 access_mode RO 788 modes M_CCHAN 789 field MCLASS 0x0F 790 } 791 792 /* 793 * Overlay Recieve Message 3 794 */ 795 register OVLYRXMSG3 { 796 address 0x093 797 access_mode RO 798 modes M_SCSI 799 field MCLASS 0x0F 800 } 801 802 /* 803 * PCI-X Control 804 */ 805 register PCIXCTL { 806 address 0x093 807 access_mode RW 808 modes M_CFG 809 field SERRPULSE 0x80 810 field UNEXPSCIEN 0x20 811 field SPLTSMADIS 0x10 812 field SPLTSTADIS 0x08 813 field SRSPDPEEN 0x04 814 field TSCSERREN 0x02 815 field CMPABCDIS 0x01 816 } 817 818 /* 819 * CMC Sequencer Byte Count 820 */ 821 register CMCSEQBCNT { 822 address 0x094 823 access_mode RO 824 modes M_CCHAN 825 } 826 827 /* 828 * Overlay Sequencer Byte Count 829 */ 830 register OVLYSEQBCNT { 831 address 0x094 832 access_mode RO 833 modes M_SCSI 834 } 835 836 /* 837 * Data Channel Sequencer Byte Count 838 */ 839 register DCHSEQBCNT { 840 address 0x094 841 access_mode RO 842 size 2 843 modes M_DFF0, M_DFF1 844 } 845 846 /* 847 * Data Channel Split Status 0 848 */ 849 register DCHSPLTSTAT0 { 850 address 0x096 851 access_mode RW 852 modes M_DFF0, M_DFF1 853 field STAETERM 0x80 854 field SCBCERR 0x40 855 field SCADERR 0x20 856 field SCDATBUCKET 0x10 857 field CNTNOTCMPLT 0x08 858 field RXOVRUN 0x04 859 field RXSCEMSG 0x02 860 field RXSPLTRSP 0x01 861 } 862 863 /* 864 * CMC Split Status 0 865 */ 866 register CMCSPLTSTAT0 { 867 address 0x096 868 access_mode RW 869 modes M_CCHAN 870 field STAETERM 0x80 871 field SCBCERR 0x40 872 field SCADERR 0x20 873 field SCDATBUCKET 0x10 874 field CNTNOTCMPLT 0x08 875 field RXOVRUN 0x04 876 field RXSCEMSG 0x02 877 field RXSPLTRSP 0x01 878 } 879 880 /* 881 * Overlay Split Status 0 882 */ 883 register OVLYSPLTSTAT0 { 884 address 0x096 885 access_mode RW 886 modes M_SCSI 887 field STAETERM 0x80 888 field SCBCERR 0x40 889 field SCADERR 0x20 890 field SCDATBUCKET 0x10 891 field CNTNOTCMPLT 0x08 892 field RXOVRUN 0x04 893 field RXSCEMSG 0x02 894 field RXSPLTRSP 0x01 895 } 896 897 /* 898 * Data Channel Split Status 1 899 */ 900 register DCHSPLTSTAT1 { 901 address 0x097 902 access_mode RW 903 modes M_DFF0, M_DFF1 904 field RXDATABUCKET 0x01 905 } 906 907 /* 908 * CMC Split Status 1 909 */ 910 register CMCSPLTSTAT1 { 911 address 0x097 912 access_mode RW 913 modes M_CCHAN 914 field RXDATABUCKET 0x01 915 } 916 917 /* 918 * Overlay Split Status 1 919 */ 920 register OVLYSPLTSTAT1 { 921 address 0x097 922 access_mode RW 923 modes M_SCSI 924 field RXDATABUCKET 0x01 925 } 926 927 /* 928 * S/G Receive Message 0 929 */ 930 register SGRXMSG0 { 931 address 0x098 932 access_mode RO 933 modes M_DFF0, M_DFF1 934 field CDNUM 0xF8 935 field CFNUM 0x07 936 } 937 938 /* 939 * S/G Receive Message 1 940 */ 941 register SGRXMSG1 { 942 address 0x099 943 access_mode RO 944 modes M_DFF0, M_DFF1 945 field CBNUM 0xFF 946 } 947 948 /* 949 * S/G Receive Message 2 950 */ 951 register SGRXMSG2 { 952 address 0x09A 953 access_mode RO 954 modes M_DFF0, M_DFF1 955 field MINDEX 0xFF 956 } 957 958 /* 959 * S/G Receive Message 3 960 */ 961 register SGRXMSG3 { 962 address 0x09B 963 access_mode RO 964 modes M_DFF0, M_DFF1 965 field MCLASS 0x0F 966 } 967 968 /* 969 * Slave Split Out Address 0 970 */ 971 register SLVSPLTOUTADR0 { 972 address 0x098 973 access_mode RO 974 modes M_SCSI 975 field LOWER_ADDR 0x7F 976 } 977 978 /* 979 * Slave Split Out Address 1 980 */ 981 register SLVSPLTOUTADR1 { 982 address 0x099 983 access_mode RO 984 modes M_SCSI 985 field REQ_DNUM 0xF8 986 field REQ_FNUM 0x07 987 } 988 989 /* 990 * Slave Split Out Address 2 991 */ 992 register SLVSPLTOUTADR2 { 993 address 0x09A 994 access_mode RO 995 modes M_SCSI 996 field REQ_BNUM 0xFF 997 } 998 999 /* 1000 * Slave Split Out Address 3 1001 */ 1002 register SLVSPLTOUTADR3 { 1003 address 0x09B 1004 access_mode RO 1005 modes M_SCSI 1006 field RLXORD 020 1007 field TAG_NUM 0x1F 1008 } 1009 1010 /* 1011 * SG Sequencer Byte Count 1012 */ 1013 register SGSEQBCNT { 1014 address 0x09C 1015 access_mode RO 1016 modes M_DFF0, M_DFF1 1017 } 1018 1019 /* 1020 * Slave Split Out Attribute 0 1021 */ 1022 register SLVSPLTOUTATTR0 { 1023 address 0x09C 1024 access_mode RO 1025 modes M_SCSI 1026 field LOWER_BCNT 0xFF 1027 } 1028 1029 /* 1030 * Slave Split Out Attribute 1 1031 */ 1032 register SLVSPLTOUTATTR1 { 1033 address 0x09D 1034 access_mode RO 1035 modes M_SCSI 1036 field CMPLT_DNUM 0xF8 1037 field CMPLT_FNUM 0x07 1038 } 1039 1040 /* 1041 * Slave Split Out Attribute 2 1042 */ 1043 register SLVSPLTOUTATTR2 { 1044 address 0x09E 1045 access_mode RO 1046 size 2 1047 modes M_SCSI 1048 field CMPLT_BNUM 0xFF 1049 } 1050 /* 1051 * S/G Split Status 0 1052 */ 1053 register SGSPLTSTAT0 { 1054 address 0x09E 1055 access_mode RW 1056 modes M_DFF0, M_DFF1 1057 field STAETERM 0x80 1058 field SCBCERR 0x40 1059 field SCADERR 0x20 1060 field SCDATBUCKET 0x10 1061 field CNTNOTCMPLT 0x08 1062 field RXOVRUN 0x04 1063 field RXSCEMSG 0x02 1064 field RXSPLTRSP 0x01 1065 } 1066 1067 /* 1068 * S/G Split Status 1 1069 */ 1070 register SGSPLTSTAT1 { 1071 address 0x09F 1072 access_mode RW 1073 modes M_DFF0, M_DFF1 1074 field RXDATABUCKET 0x01 1075 } 1076 1077 /* 1078 * Special Function 1079 */ 1080 register SFUNCT { 1081 address 0x09f 1082 access_mode RW 1083 modes M_CFG 1084 field TEST_GROUP 0xF0 1085 field TEST_NUM 0x0F 1086 } 1087 1088 /* 1089 * Data FIFO 0 PCI Status 1090 */ 1091 register DF0PCISTAT { 1092 address 0x0A0 1093 access_mode RW 1094 modes M_CFG 1095 field DPE 0x80 1096 field SSE 0x40 1097 field RMA 0x20 1098 field RTA 0x10 1099 field SCAAPERR 0x08 1100 field RDPERR 0x04 1101 field TWATERR 0x02 1102 field DPR 0x01 1103 } 1104 1105 /* 1106 * Data FIFO 1 PCI Status 1107 */ 1108 register DF1PCISTAT { 1109 address 0x0A1 1110 access_mode RW 1111 modes M_CFG 1112 field DPE 0x80 1113 field SSE 0x40 1114 field RMA 0x20 1115 field RTA 0x10 1116 field SCAAPERR 0x08 1117 field RDPERR 0x04 1118 field TWATERR 0x02 1119 field DPR 0x01 1120 } 1121 1122 /* 1123 * S/G PCI Status 1124 */ 1125 register SGPCISTAT { 1126 address 0x0A2 1127 access_mode RW 1128 modes M_CFG 1129 field DPE 0x80 1130 field SSE 0x40 1131 field RMA 0x20 1132 field RTA 0x10 1133 field SCAAPERR 0x08 1134 field RDPERR 0x04 1135 field DPR 0x01 1136 } 1137 1138 /* 1139 * CMC PCI Status 1140 */ 1141 register CMCPCISTAT { 1142 address 0x0A3 1143 access_mode RW 1144 modes M_CFG 1145 field DPE 0x80 1146 field SSE 0x40 1147 field RMA 0x20 1148 field RTA 0x10 1149 field SCAAPERR 0x08 1150 field RDPERR 0x04 1151 field TWATERR 0x02 1152 field DPR 0x01 1153 } 1154 1155 /* 1156 * Overlay PCI Status 1157 */ 1158 register OVLYPCISTAT { 1159 address 0x0A4 1160 access_mode RW 1161 modes M_CFG 1162 field DPE 0x80 1163 field SSE 0x40 1164 field RMA 0x20 1165 field RTA 0x10 1166 field SCAAPERR 0x08 1167 field RDPERR 0x04 1168 field DPR 0x01 1169 } 1170 1171 /* 1172 * PCI Status for MSI Master DMA Transfer 1173 */ 1174 register MSIPCISTAT { 1175 address 0x0A6 1176 access_mode RW 1177 modes M_CFG 1178 field SSE 0x40 1179 field RMA 0x20 1180 field RTA 0x10 1181 field CLRPENDMSI 0x08 1182 field TWATERR 0x02 1183 field DPR 0x01 1184 } 1185 1186 /* 1187 * PCI Status for Target 1188 */ 1189 register TARGPCISTAT { 1190 address 0x0A7 1191 access_mode RW 1192 modes M_CFG 1193 field DPE 0x80 1194 field SSE 0x40 1195 field STA 0x08 1196 field TWATERR 0x02 1197 } 1198 1199 /* 1200 * LQ Packet In 1201 * The last LQ Packet recieved 1202 */ 1203 register LQIN { 1204 address 0x020 1205 access_mode RW 1206 size 20 1207 modes M_DFF0, M_DFF1, M_SCSI 1208 } 1209 1210 /* 1211 * SCB Type Pointer 1212 * SCB offset for Target Mode SCB type information 1213 */ 1214 register TYPEPTR { 1215 address 0x020 1216 access_mode RW 1217 modes M_CFG 1218 } 1219 1220 /* 1221 * Queue Tag Pointer 1222 * SCB offset to the Two Byte tag identifier used for target mode. 1223 */ 1224 register TAGPTR { 1225 address 0x021 1226 access_mode RW 1227 modes M_CFG 1228 } 1229 1230 /* 1231 * Logical Unit Number Pointer 1232 * SCB offset to the LSB (little endian) of the lun field. 1233 */ 1234 register LUNPTR { 1235 address 0x022 1236 access_mode RW 1237 modes M_CFG 1238 } 1239 1240 /* 1241 * Data Length Pointer 1242 * SCB offset for the 4 byte data length field in target mode. 1243 */ 1244 register DATALENPTR { 1245 address 0x023 1246 access_mode RW 1247 modes M_CFG 1248 } 1249 1250 /* 1251 * Status Length Pointer 1252 * SCB offset to the two byte status field in target SCBs. 1253 */ 1254 register STATLENPTR { 1255 address 0x024 1256 access_mode RW 1257 modes M_CFG 1258 } 1259 1260 /* 1261 * Command Length Pointer 1262 * Scb offset for the CDB length field in initiator SCBs. 1263 */ 1264 register CMDLENPTR { 1265 address 0x025 1266 access_mode RW 1267 modes M_CFG 1268 } 1269 1270 /* 1271 * Task Attribute Pointer 1272 * Scb offset for the byte field specifying the attribute byte 1273 * to be used in command packets. 1274 */ 1275 register ATTRPTR { 1276 address 0x026 1277 access_mode RW 1278 modes M_CFG 1279 } 1280 1281 /* 1282 * Task Management Flags Pointer 1283 * Scb offset for the byte field specifying the attribute flags 1284 * byte to be used in command packets. 1285 */ 1286 register FLAGPTR { 1287 address 0x027 1288 access_mode RW 1289 modes M_CFG 1290 } 1291 1292 /* 1293 * Command Pointer 1294 * Scb offset for the first byte in the CDB for initiator SCBs. 1295 */ 1296 register CMDPTR { 1297 address 0x028 1298 access_mode RW 1299 modes M_CFG 1300 } 1301 1302 /* 1303 * Queue Next Pointer 1304 * Scb offset for the 2 byte "next scb link". 1305 */ 1306 register QNEXTPTR { 1307 address 0x029 1308 access_mode RW 1309 modes M_CFG 1310 } 1311 1312 /* 1313 * SCSI ID Pointer 1314 * Scb offset to the value to place in the SCSIID register 1315 * during target mode connections. 1316 */ 1317 register IDPTR { 1318 address 0x02A 1319 access_mode RW 1320 modes M_CFG 1321 } 1322 1323 /* 1324 * Command Aborted Byte Pointer 1325 * Offset to the SCB flags field that includes the 1326 * "SCB aborted" status bit. 1327 */ 1328 register ABRTBYTEPTR { 1329 address 0x02B 1330 access_mode RW 1331 modes M_CFG 1332 } 1333 1334 /* 1335 * Command Aborted Bit Pointer 1336 * Bit offset in the SCB flags field for "SCB aborted" status. 1337 */ 1338 register ABRTBITPTR { 1339 address 0x02C 1340 access_mode RW 1341 modes M_CFG 1342 } 1343 1344 /* 1345 * Rev B or greater. 1346 */ 1347 register MAXCMDBYTES { 1348 address 0x02D 1349 access_mode RW 1350 modes M_CFG 1351 } 1352 1353 /* 1354 * Rev B or greater. 1355 */ 1356 register MAXCMD2RCV { 1357 address 0x02E 1358 access_mode RW 1359 modes M_CFG 1360 } 1361 1362 /* 1363 * Rev B or greater. 1364 */ 1365 register SHORTTHRESH { 1366 address 0x02F 1367 access_mode RW 1368 modes M_CFG 1369 } 1370 1371 /* 1372 * Logical Unit Number Length 1373 * The length, in bytes, of the SCB lun field. 1374 */ 1375 register LUNLEN { 1376 address 0x030 1377 access_mode RW 1378 modes M_CFG 1379 } 1380 1381 /* 1382 * CDB Limit 1383 * The size, in bytes, of the embedded CDB field in initator SCBs. 1384 */ 1385 register CDBLIMIT { 1386 address 0x031 1387 access_mode RW 1388 modes M_CFG 1389 } 1390 1391 /* 1392 * Maximum Commands 1393 * The maximum number of commands to issue during a 1394 * single packetized connection. 1395 */ 1396 register MAXCMD { 1397 address 0x032 1398 access_mode RW 1399 modes M_CFG 1400 } 1401 1402 /* 1403 * Maximum Command Counter 1404 * The number of commands already sent during this connection 1405 */ 1406 register MAXCMDCNT { 1407 address 0x033 1408 access_mode RW 1409 modes M_CFG 1410 } 1411 1412 /* 1413 * LQ Packet Reserved Bytes 1414 * The bytes to be sent in the currently reserved fileds 1415 * of all LQ packets. 1416 */ 1417 register LQRSVD01 { 1418 address 0x034 1419 access_mode RW 1420 modes M_SCSI 1421 } 1422 register LQRSVD16 { 1423 address 0x035 1424 access_mode RW 1425 modes M_SCSI 1426 } 1427 register LQRSVD17 { 1428 address 0x036 1429 access_mode RW 1430 modes M_SCSI 1431 } 1432 1433 /* 1434 * Command Reserved 0 1435 * The byte to be sent for the reserved byte 0 of 1436 * outgoing command packets. 1437 */ 1438 register CMDRSVD0 { 1439 address 0x037 1440 access_mode RW 1441 modes M_CFG 1442 } 1443 1444 /* 1445 * LQ Manager Control 0 1446 */ 1447 register LQCTL0 { 1448 address 0x038 1449 access_mode RW 1450 modes M_CFG 1451 field LQITARGCLT 0xC0 1452 field LQIINITGCLT 0x30 1453 field LQ0TARGCLT 0x0C 1454 field LQ0INITGCLT 0x03 1455 } 1456 1457 /* 1458 * LQ Manager Control 1 1459 */ 1460 register LQCTL1 { 1461 address 0x038 1462 access_mode RW 1463 modes M_DFF0, M_DFF1, M_SCSI 1464 field PCI2PCI 0x04 1465 field SINGLECMD 0x02 1466 field ABORTPENDING 0x01 1467 } 1468 1469 /* 1470 * LQ Manager Control 2 1471 */ 1472 register LQCTL2 { 1473 address 0x039 1474 access_mode RW 1475 modes M_DFF0, M_DFF1, M_SCSI 1476 field LQIRETRY 0x80 1477 field LQICONTINUE 0x40 1478 field LQITOIDLE 0x20 1479 field LQIPAUSE 0x10 1480 field LQORETRY 0x08 1481 field LQOCONTINUE 0x04 1482 field LQOTOIDLE 0x02 1483 field LQOPAUSE 0x01 1484 } 1485 1486 /* 1487 * SCSI RAM BIST0 1488 */ 1489 register SCSBIST0 { 1490 address 0x039 1491 access_mode RW 1492 modes M_CFG 1493 field GSBISTERR 0x40 1494 field GSBISTDONE 0x20 1495 field GSBISTRUN 0x10 1496 field OSBISTERR 0x04 1497 field OSBISTDONE 0x02 1498 field OSBISTRUN 0x01 1499 } 1500 1501 /* 1502 * SCSI Sequence Control0 1503 */ 1504 register SCSISEQ0 { 1505 address 0x03A 1506 access_mode RW 1507 modes M_DFF0, M_DFF1, M_SCSI 1508 field TEMODEO 0x80 1509 field ENSELO 0x40 1510 field ENARBO 0x20 1511 field FORCEBUSFREE 0x10 1512 field SCSIRSTO 0x01 1513 } 1514 1515 /* 1516 * SCSI RAM BIST 1 1517 */ 1518 register SCSBIST1 { 1519 address 0x03A 1520 access_mode RW 1521 modes M_CFG 1522 field NTBISTERR 0x04 1523 field NTBISTDONE 0x02 1524 field NTBISTRUN 0x01 1525 } 1526 1527 /* 1528 * SCSI Sequence Control 1 1529 */ 1530 register SCSISEQ1 { 1531 address 0x03B 1532 access_mode RW 1533 modes M_DFF0, M_DFF1, M_SCSI 1534 field MANUALCTL 0x40 1535 field ENSELI 0x20 1536 field ENRSELI 0x10 1537 field MANUALP 0x0C 1538 field ENAUTOATNP 0x02 1539 field ALTSTIM 0x01 1540 } 1541 1542 /* 1543 * SCSI Transfer Control 0 1544 */ 1545 register SXFRCTL0 { 1546 address 0x03C 1547 access_mode RW 1548 modes M_SCSI 1549 field DFON 0x80 1550 field DFPEXP 0x40 1551 field BIOSCANCELEN 0x10 1552 field SPIOEN 0x08 1553 } 1554 1555 /* 1556 * SCSI Transfer Control 1 1557 */ 1558 register SXFRCTL1 { 1559 address 0x03D 1560 access_mode RW 1561 modes M_SCSI 1562 field BITBUCKET 0x80 1563 field ENSACHK 0x40 1564 field ENSPCHK 0x20 1565 field STIMESEL 0x18 1566 field ENSTIMER 0x04 1567 field ACTNEGEN 0x02 1568 field STPWEN 0x01 1569 } 1570 1571 /* 1572 * SCSI Transfer Control 2 1573 */ 1574 register SXFRCTL2 { 1575 address 0x03E 1576 access_mode RW 1577 modes M_SCSI 1578 field AUTORSTDIS 0x10 1579 field CMDDMAEN 0x08 1580 field ASU 0x07 1581 } 1582 1583 /* 1584 * SCSI Bus Initiator IDs 1585 * Bitmask of observed initiators on the bus. 1586 */ 1587 register BUSINITID { 1588 address 0x03C 1589 access_mode RW 1590 modes M_CFG 1591 size 2 1592 } 1593 1594 /* 1595 * Data Length Counters 1596 * Packet byte counter. 1597 */ 1598 register DLCOUNT { 1599 address 0x03C 1600 access_mode RW 1601 modes M_DFF0, M_DFF1 1602 size 3 1603 } 1604 1605 /* 1606 * Data FIFO Status 1607 */ 1608 register DFFSTAT { 1609 address 0x03F 1610 access_mode RW 1611 modes M_SCSI 1612 field FIFO1FREE 0x20 1613 field FIFO0FREE 0x10 1614 /* 1615 * On the B, this enum only works 1616 * in the read direction. For writes, 1617 * you must use the B version of the 1618 * CURRFIFO_0 definition which is defined 1619 * as a constant outside of this register 1620 * definition to avoid confusing the 1621 * register pretty printing code. 1622 */ 1623 enum CURRFIFO 0x03 { 1624 CURRFIFO_0, 1625 CURRFIFO_1, 1626 CURRFIFO_NONE 0x3 1627 } 1628 } 1629 1630 const B_CURRFIFO_0 0x2 1631 1632 /* 1633 * SCSI Bus Target IDs 1634 * Bitmask of observed targets on the bus. 1635 */ 1636 register BUSTARGID { 1637 address 0x03E 1638 access_mode RW 1639 modes M_CFG 1640 size 2 1641 } 1642 1643 /* 1644 * SCSI Control Signal Out 1645 */ 1646 register SCSISIGO { 1647 address 0x040 1648 access_mode RW 1649 modes M_DFF0, M_DFF1, M_SCSI 1650 field CDO 0x80 1651 field IOO 0x40 1652 field MSGO 0x20 1653 field ATNO 0x10 1654 field SELO 0x08 1655 field BSYO 0x04 1656 field REQO 0x02 1657 field ACKO 0x01 1658 /* 1659 * Possible phases to write into SCSISIG0 1660 */ 1661 enum PHASE_MASK CDO|IOO|MSGO { 1662 P_DATAOUT 0x0, 1663 P_DATAIN IOO, 1664 P_DATAOUT_DT P_DATAOUT|MSGO, 1665 P_DATAIN_DT P_DATAIN|MSGO, 1666 P_COMMAND CDO, 1667 P_MESGOUT CDO|MSGO, 1668 P_STATUS CDO|IOO, 1669 P_MESGIN CDO|IOO|MSGO 1670 } 1671 } 1672 1673 register SCSISIGI { 1674 address 0x041 1675 access_mode RO 1676 modes M_DFF0, M_DFF1, M_SCSI 1677 field CDI 0x80 1678 field IOI 0x40 1679 field MSGI 0x20 1680 field ATNI 0x10 1681 field SELI 0x08 1682 field BSYI 0x04 1683 field REQI 0x02 1684 field ACKI 0x01 1685 /* 1686 * Possible phases in SCSISIGI 1687 */ 1688 enum PHASE_MASK CDO|IOO|MSGO { 1689 P_DATAOUT 0x0, 1690 P_DATAIN IOO, 1691 P_DATAOUT_DT P_DATAOUT|MSGO, 1692 P_DATAIN_DT P_DATAIN|MSGO, 1693 P_COMMAND CDO, 1694 P_MESGOUT CDO|MSGO, 1695 P_STATUS CDO|IOO, 1696 P_MESGIN CDO|IOO|MSGO 1697 } 1698 } 1699 1700 /* 1701 * Multiple Target IDs 1702 * Bitmask of ids to respond as a target. 1703 */ 1704 register MULTARGID { 1705 address 0x040 1706 access_mode RW 1707 modes M_CFG 1708 size 2 1709 } 1710 1711 /* 1712 * SCSI Phase 1713 */ 1714 register SCSIPHASE { 1715 address 0x042 1716 access_mode RO 1717 modes M_DFF0, M_DFF1, M_SCSI 1718 field STATUS_PHASE 0x20 1719 field COMMAND_PHASE 0x10 1720 field MSG_IN_PHASE 0x08 1721 field MSG_OUT_PHASE 0x04 1722 field DATA_PHASE_MASK 0x03 { 1723 DATA_OUT_PHASE 0x01, 1724 DATA_IN_PHASE 0x02 1725 } 1726 } 1727 1728 /* 1729 * SCSI Data 0 Image 1730 */ 1731 register SCSIDAT0_IMG { 1732 address 0x043 1733 access_mode RW 1734 modes M_DFF0, M_DFF1, M_SCSI 1735 } 1736 1737 /* 1738 * SCSI Latched Data 1739 */ 1740 register SCSIDAT { 1741 address 0x044 1742 access_mode RW 1743 modes M_DFF0, M_DFF1, M_SCSI 1744 size 2 1745 } 1746 1747 /* 1748 * SCSI Data Bus 1749 */ 1750 register SCSIBUS { 1751 address 0x046 1752 access_mode RW 1753 modes M_DFF0, M_DFF1, M_SCSI 1754 size 2 1755 } 1756 1757 /* 1758 * Target ID In 1759 */ 1760 register TARGIDIN { 1761 address 0x048 1762 access_mode RO 1763 modes M_DFF0, M_DFF1, M_SCSI 1764 field CLKOUT 0x80 1765 field TARGID 0x0F 1766 } 1767 1768 /* 1769 * Selection/Reselection ID 1770 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1771 * device did not set its own ID. 1772 */ 1773 register SELID { 1774 address 0x049 1775 access_mode RW 1776 modes M_DFF0, M_DFF1, M_SCSI 1777 field SELID_MASK 0xf0 1778 field ONEBIT 0x08 1779 } 1780 1781 /* 1782 * SCSI Block Control 1783 * Controls Bus type and channel selection. SELWIDE allows for the 1784 * coexistence of 8bit and 16bit devices on a wide bus. 1785 */ 1786 register SBLKCTL { 1787 address 0x04A 1788 access_mode RW 1789 modes M_DFF0, M_DFF1, M_SCSI 1790 field DIAGLEDEN 0x80 1791 field DIAGLEDON 0x40 1792 field ENAB40 0x08 /* LVD transceiver active */ 1793 field ENAB20 0x04 /* SE/HVD transceiver active */ 1794 field SELWIDE 0x02 1795 } 1796 1797 /* 1798 * Option Mode 1799 */ 1800 register OPTIONMODE { 1801 address 0x04A 1802 access_mode RW 1803 modes M_CFG 1804 field BIOSCANCTL 0x80 1805 field AUTOACKEN 0x40 1806 field BIASCANCTL 0x20 1807 field BUSFREEREV 0x10 1808 field ENDGFORMCHK 0x04 1809 field AUTO_MSGOUT_DE 0x02 1810 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1811 } 1812 1813 /* 1814 * SCSI Status 0 1815 */ 1816 register SSTAT0 { 1817 address 0x04B 1818 access_mode RO 1819 modes M_DFF0, M_DFF1, M_SCSI 1820 field TARGET 0x80 /* Board acting as target */ 1821 field SELDO 0x40 /* Selection Done */ 1822 field SELDI 0x20 /* Board has been selected */ 1823 field SELINGO 0x10 /* Selection In Progress */ 1824 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1825 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1826 field SPIORDY 0x02 /* SCSI PIO Ready */ 1827 field ARBDO 0x01 /* Arbitration Done Out */ 1828 } 1829 1830 /* 1831 * Clear SCSI Interrupt 0 1832 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1833 */ 1834 register CLRSINT0 { 1835 address 0x04B 1836 access_mode WO 1837 modes M_DFF0, M_DFF1, M_SCSI 1838 field CLRSELDO 0x40 1839 field CLRSELDI 0x20 1840 field CLRSELINGO 0x10 1841 field CLRIOERR 0x08 1842 field CLROVERRUN 0x04 1843 field CLRSPIORDY 0x02 1844 field CLRARBDO 0x01 1845 } 1846 1847 /* 1848 * SCSI Interrupt Mode 0 1849 * Setting any bit will enable the corresponding function 1850 * in SIMODE0 to interrupt via the IRQ pin. 1851 */ 1852 register SIMODE0 { 1853 address 0x04B 1854 access_mode RW 1855 modes M_CFG 1856 field ENSELDO 0x40 1857 field ENSELDI 0x20 1858 field ENSELINGO 0x10 1859 field ENIOERR 0x08 1860 field ENOVERRUN 0x04 1861 field ENSPIORDY 0x02 1862 field ENARBDO 0x01 1863 } 1864 1865 /* 1866 * SCSI Status 1 1867 */ 1868 register SSTAT1 { 1869 address 0x04C 1870 access_mode RO 1871 modes M_DFF0, M_DFF1, M_SCSI 1872 field SELTO 0x80 1873 field ATNTARG 0x40 1874 field SCSIRSTI 0x20 1875 field PHASEMIS 0x10 1876 field BUSFREE 0x08 1877 field SCSIPERR 0x04 1878 field STRB2FAST 0x02 1879 field REQINIT 0x01 1880 } 1881 1882 /* 1883 * Clear SCSI Interrupt 1 1884 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1885 */ 1886 register CLRSINT1 { 1887 address 0x04C 1888 access_mode WO 1889 modes M_DFF0, M_DFF1, M_SCSI 1890 field CLRSELTIMEO 0x80 1891 field CLRATNO 0x40 1892 field CLRSCSIRSTI 0x20 1893 field CLRBUSFREE 0x08 1894 field CLRSCSIPERR 0x04 1895 field CLRSTRB2FAST 0x02 1896 field CLRREQINIT 0x01 1897 } 1898 1899 /* 1900 * SCSI Status 2 1901 */ 1902 register SSTAT2 { 1903 address 0x04d 1904 access_mode RO 1905 modes M_DFF0, M_DFF1, M_SCSI 1906 field BUSFREETIME 0xc0 { 1907 BUSFREE_LQO 0x40, 1908 BUSFREE_DFF0 0x80, 1909 BUSFREE_DFF1 0xC0 1910 } 1911 field NONPACKREQ 0x20 1912 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1913 field BSYX 0x08 /* Busy Expander */ 1914 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1915 field SDONE 0x02 /* Modes 0 and 1 only */ 1916 field DMADONE 0x01 /* Modes 0 and 1 only */ 1917 } 1918 1919 /* 1920 * Clear SCSI Interrupt 2 1921 */ 1922 register CLRSINT2 { 1923 address 0x04D 1924 access_mode WO 1925 modes M_DFF0, M_DFF1, M_SCSI 1926 field CLRNONPACKREQ 0x20 1927 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1928 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1929 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1930 } 1931 1932 /* 1933 * SCSI Interrupt Mode 2 1934 */ 1935 register SIMODE2 { 1936 address 0x04D 1937 access_mode RW 1938 modes M_CFG 1939 field ENWIDE_RES 0x04 1940 field ENSDONE 0x02 1941 field ENDMADONE 0x01 1942 } 1943 1944 /* 1945 * Physical Error Diagnosis 1946 */ 1947 register PERRDIAG { 1948 address 0x04E 1949 access_mode RO 1950 modes M_DFF0, M_DFF1, M_SCSI 1951 field HIZERO 0x80 1952 field HIPERR 0x40 1953 field PREVPHASE 0x20 1954 field PARITYERR 0x10 1955 field AIPERR 0x08 1956 field CRCERR 0x04 1957 field DGFORMERR 0x02 1958 field DTERR 0x01 1959 } 1960 1961 /* 1962 * LQI Manager Current State 1963 */ 1964 register LQISTATE { 1965 address 0x04E 1966 access_mode RO 1967 modes M_CFG 1968 } 1969 1970 /* 1971 * SCSI Offset Count 1972 */ 1973 register SOFFCNT { 1974 address 0x04F 1975 access_mode RO 1976 modes M_DFF0, M_DFF1, M_SCSI 1977 } 1978 1979 /* 1980 * LQO Manager Current State 1981 */ 1982 register LQOSTATE { 1983 address 0x04F 1984 access_mode RO 1985 modes M_CFG 1986 } 1987 1988 /* 1989 * LQI Manager Status 1990 */ 1991 register LQISTAT0 { 1992 address 0x050 1993 access_mode RO 1994 modes M_DFF0, M_DFF1, M_SCSI 1995 field LQIATNQAS 0x20 1996 field LQICRCT1 0x10 1997 field LQICRCT2 0x08 1998 field LQIBADLQT 0x04 1999 field LQIATNLQ 0x02 2000 field LQIATNCMD 0x01 2001 } 2002 2003 /* 2004 * Clear LQI Interrupts 0 2005 */ 2006 register CLRLQIINT0 { 2007 address 0x050 2008 access_mode WO 2009 modes M_DFF0, M_DFF1, M_SCSI 2010 field CLRLQIATNQAS 0x20 2011 field CLRLQICRCT1 0x10 2012 field CLRLQICRCT2 0x08 2013 field CLRLQIBADLQT 0x04 2014 field CLRLQIATNLQ 0x02 2015 field CLRLQIATNCMD 0x01 2016 } 2017 2018 /* 2019 * LQI Manager Interrupt Mode 0 2020 */ 2021 register LQIMODE0 { 2022 address 0x050 2023 access_mode RW 2024 modes M_CFG 2025 field ENLQIATNQASK 0x20 2026 field ENLQICRCT1 0x10 2027 field ENLQICRCT2 0x08 2028 field ENLQIBADLQT 0x04 2029 field ENLQIATNLQ 0x02 2030 field ENLQIATNCMD 0x01 2031 } 2032 2033 /* 2034 * LQI Manager Status 1 2035 */ 2036 register LQISTAT1 { 2037 address 0x051 2038 access_mode RO 2039 modes M_DFF0, M_DFF1, M_SCSI 2040 field LQIPHASE_LQ 0x80 2041 field LQIPHASE_NLQ 0x40 2042 field LQIABORT 0x20 2043 field LQICRCI_LQ 0x10 2044 field LQICRCI_NLQ 0x08 2045 field LQIBADLQI 0x04 2046 field LQIOVERI_LQ 0x02 2047 field LQIOVERI_NLQ 0x01 2048 } 2049 2050 /* 2051 * Clear LQI Manager Interrupts1 2052 */ 2053 register CLRLQIINT1 { 2054 address 0x051 2055 access_mode WO 2056 modes M_DFF0, M_DFF1, M_SCSI 2057 field CLRLQIPHASE_LQ 0x80 2058 field CLRLQIPHASE_NLQ 0x40 2059 field CLRLIQABORT 0x20 2060 field CLRLQICRCI_LQ 0x10 2061 field CLRLQICRCI_NLQ 0x08 2062 field CLRLQIBADLQI 0x04 2063 field CLRLQIOVERI_LQ 0x02 2064 field CLRLQIOVERI_NLQ 0x01 2065 } 2066 2067 /* 2068 * LQI Manager Interrupt Mode 1 2069 */ 2070 register LQIMODE1 { 2071 address 0x051 2072 access_mode RW 2073 modes M_CFG 2074 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2075 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2076 field ENLIQABORT 0x20 2077 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2078 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2079 field ENLQIBADLQI 0x04 2080 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2081 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 2082 } 2083 2084 /* 2085 * LQI Manager Status 2 2086 */ 2087 register LQISTAT2 { 2088 address 0x052 2089 access_mode RO 2090 modes M_DFF0, M_DFF1, M_SCSI 2091 field PACKETIZED 0x80 2092 field LQIPHASE_OUTPKT 0x40 2093 field LQIWORKONLQ 0x20 2094 field LQIWAITFIFO 0x10 2095 field LQISTOPPKT 0x08 2096 field LQISTOPLQ 0x04 2097 field LQISTOPCMD 0x02 2098 field LQIGSAVAIL 0x01 2099 } 2100 2101 /* 2102 * SCSI Status 3 2103 */ 2104 register SSTAT3 { 2105 address 0x053 2106 access_mode RO 2107 modes M_DFF0, M_DFF1, M_SCSI 2108 field NTRAMPERR 0x02 2109 field OSRAMPERR 0x01 2110 } 2111 2112 /* 2113 * Clear SCSI Status 3 2114 */ 2115 register CLRSINT3 { 2116 address 0x053 2117 access_mode WO 2118 modes M_DFF0, M_DFF1, M_SCSI 2119 field CLRNTRAMPERR 0x02 2120 field CLROSRAMPERR 0x01 2121 } 2122 2123 /* 2124 * SCSI Interrupt Mode 3 2125 */ 2126 register SIMODE3 { 2127 address 0x053 2128 access_mode RW 2129 modes M_CFG 2130 field ENNTRAMPERR 0x02 2131 field ENOSRAMPERR 0x01 2132 } 2133 2134 /* 2135 * LQO Manager Status 0 2136 */ 2137 register LQOSTAT0 { 2138 address 0x054 2139 access_mode RO 2140 modes M_DFF0, M_DFF1, M_SCSI 2141 field LQOTARGSCBPERR 0x10 2142 field LQOSTOPT2 0x08 2143 field LQOATNLQ 0x04 2144 field LQOATNPKT 0x02 2145 field LQOTCRC 0x01 2146 } 2147 2148 /* 2149 * Clear LQO Manager interrupt 0 2150 */ 2151 register CLRLQOINT0 { 2152 address 0x054 2153 access_mode WO 2154 modes M_DFF0, M_DFF1, M_SCSI 2155 field CLRLQOTARGSCBPERR 0x10 2156 field CLRLQOSTOPT2 0x08 2157 field CLRLQOATNLQ 0x04 2158 field CLRLQOATNPKT 0x02 2159 field CLRLQOTCRC 0x01 2160 } 2161 2162 /* 2163 * LQO Manager Interrupt Mode 0 2164 */ 2165 register LQOMODE0 { 2166 address 0x054 2167 access_mode RW 2168 modes M_CFG 2169 field ENLQOTARGSCBPERR 0x10 2170 field ENLQOSTOPT2 0x08 2171 field ENLQOATNLQ 0x04 2172 field ENLQOATNPKT 0x02 2173 field ENLQOTCRC 0x01 2174 } 2175 2176 /* 2177 * LQO Manager Status 1 2178 */ 2179 register LQOSTAT1 { 2180 address 0x055 2181 access_mode RO 2182 modes M_DFF0, M_DFF1, M_SCSI 2183 field LQOINITSCBPERR 0x10 2184 field LQOSTOPI2 0x08 2185 field LQOBADQAS 0x04 2186 field LQOBUSFREE 0x02 2187 field LQOPHACHGINPKT 0x01 2188 } 2189 2190 /* 2191 * Clear LOQ Interrupt 1 2192 */ 2193 register CLRLQOINT1 { 2194 address 0x055 2195 access_mode WO 2196 modes M_DFF0, M_DFF1, M_SCSI 2197 field CLRLQOINITSCBPERR 0x10 2198 field CLRLQOSTOPI2 0x08 2199 field CLRLQOBADQAS 0x04 2200 field CLRLQOBUSFREE 0x02 2201 field CLRLQOPHACHGINPKT 0x01 2202 } 2203 2204 /* 2205 * LQO Manager Interrupt Mode 1 2206 */ 2207 register LQOMODE1 { 2208 address 0x055 2209 access_mode RW 2210 modes M_CFG 2211 field ENLQOINITSCBPERR 0x10 2212 field ENLQOSTOPI2 0x08 2213 field ENLQOBADQAS 0x04 2214 field ENLQOBUSFREE 0x02 2215 field ENLQOPHACHGINPKT 0x01 2216 } 2217 2218 /* 2219 * LQO Manager Status 2 2220 */ 2221 register LQOSTAT2 { 2222 address 0x056 2223 access_mode RO 2224 modes M_DFF0, M_DFF1, M_SCSI 2225 field LQOPKT 0xE0 2226 field LQOWAITFIFO 0x10 2227 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2228 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2229 } 2230 2231 /* 2232 * Output Synchronizer Space Count 2233 */ 2234 register OS_SPACE_CNT { 2235 address 0x056 2236 access_mode RO 2237 modes M_CFG 2238 } 2239 2240 /* 2241 * SCSI Interrupt Mode 1 2242 * Setting any bit will enable the corresponding function 2243 * in SIMODE1 to interrupt via the IRQ pin. 2244 */ 2245 register SIMODE1 { 2246 address 0x057 2247 access_mode RW 2248 modes M_DFF0, M_DFF1, M_SCSI 2249 field ENSELTIMO 0x80 2250 field ENATNTARG 0x40 2251 field ENSCSIRST 0x20 2252 field ENPHASEMIS 0x10 2253 field ENBUSFREE 0x08 2254 field ENSCSIPERR 0x04 2255 field ENSTRB2FAST 0x02 2256 field ENREQINIT 0x01 2257 } 2258 2259 /* 2260 * Good Status FIFO 2261 */ 2262 register GSFIFO { 2263 address 0x058 2264 access_mode RO 2265 size 2 2266 modes M_DFF0, M_DFF1, M_SCSI 2267 } 2268 2269 /* 2270 * Data FIFO SCSI Transfer Control 2271 */ 2272 register DFFSXFRCTL { 2273 address 0x05A 2274 access_mode RW 2275 modes M_DFF0, M_DFF1 2276 field DFFBITBUCKET 0x08 2277 field CLRSHCNT 0x04 2278 field CLRCHN 0x02 2279 field RSTCHN 0x01 2280 } 2281 2282 /* 2283 * Next SCSI Control Block 2284 */ 2285 register NEXTSCB { 2286 address 0x05A 2287 access_mode RW 2288 size 2 2289 modes M_SCSI 2290 } 2291 2292 /* Rev B only. */ 2293 register LQOSCSCTL { 2294 address 0x05A 2295 access_mode RW 2296 size 1 2297 modes M_CFG 2298 field LQOH2A_VERSION 0x80 2299 field LQONOCHKOVER 0x01 2300 } 2301 2302 /* 2303 * SEQ Interrupts 2304 */ 2305 register SEQINTSRC { 2306 address 0x05B 2307 access_mode RO 2308 modes M_DFF0, M_DFF1 2309 field CTXTDONE 0x40 2310 field SAVEPTRS 0x20 2311 field CFG4DATA 0x10 2312 field CFG4ISTAT 0x08 2313 field CFG4TSTAT 0x04 2314 field CFG4ICMD 0x02 2315 field CFG4TCMD 0x01 2316 } 2317 2318 /* 2319 * Clear Arp Interrupts 2320 */ 2321 register CLRSEQINTSRC { 2322 address 0x05B 2323 access_mode WO 2324 modes M_DFF0, M_DFF1 2325 field CLRCTXTDONE 0x40 2326 field CLRSAVEPTRS 0x20 2327 field CLRCFG4DATA 0x10 2328 field CLRCFG4ISTAT 0x08 2329 field CLRCFG4TSTAT 0x04 2330 field CLRCFG4ICMD 0x02 2331 field CLRCFG4TCMD 0x01 2332 } 2333 2334 /* 2335 * SEQ Interrupt Enabled (Shared) 2336 */ 2337 register SEQIMODE { 2338 address 0x05C 2339 access_mode RW 2340 modes M_DFF0, M_DFF1 2341 field ENCTXTDONE 0x40 2342 field ENSAVEPTRS 0x20 2343 field ENCFG4DATA 0x10 2344 field ENCFG4ISTAT 0x08 2345 field ENCFG4TSTAT 0x04 2346 field ENCFG4ICMD 0x02 2347 field ENCFG4TCMD 0x01 2348 } 2349 2350 /* 2351 * Current SCSI Control Block 2352 */ 2353 register CURRSCB { 2354 address 0x05C 2355 access_mode RW 2356 size 2 2357 modes M_SCSI 2358 } 2359 2360 /* 2361 * Data FIFO Status 2362 */ 2363 register MDFFSTAT { 2364 address 0x05D 2365 access_mode RO 2366 modes M_DFF0, M_DFF1 2367 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2368 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2369 field LASTSDONE 0x10 2370 field SHVALID 0x08 2371 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2372 field DATAINFIFO 0x02 2373 field FIFOFREE 0x01 2374 } 2375 2376 /* 2377 * CRC Control 2378 */ 2379 register CRCCONTROL { 2380 address 0x05d 2381 access_mode RW 2382 modes M_CFG 2383 field CRCVALCHKEN 0x40 2384 } 2385 2386 /* 2387 * SCSI Test Control 2388 */ 2389 register SCSITEST { 2390 address 0x05E 2391 access_mode RW 2392 modes M_CFG 2393 field CNTRTEST 0x08 2394 field SEL_TXPLL_DEBUG 0x04 2395 } 2396 2397 /* 2398 * Data FIFO Queue Tag 2399 */ 2400 register DFFTAG { 2401 address 0x05E 2402 access_mode RW 2403 size 2 2404 modes M_DFF0, M_DFF1 2405 } 2406 2407 /* 2408 * Last SCSI Control Block 2409 */ 2410 register LASTSCB { 2411 address 0x05E 2412 access_mode RW 2413 size 2 2414 modes M_SCSI 2415 } 2416 2417 /* 2418 * SCSI I/O Cell Power-down Control 2419 */ 2420 register IOPDNCTL { 2421 address 0x05F 2422 access_mode RW 2423 modes M_CFG 2424 field DISABLE_OE 0x80 2425 field PDN_IDIST 0x04 2426 field PDN_DIFFSENSE 0x01 2427 } 2428 2429 /* 2430 * Shaddow Host Address. 2431 */ 2432 register SHADDR { 2433 address 0x060 2434 access_mode RO 2435 size 8 2436 modes M_DFF0, M_DFF1 2437 } 2438 2439 /* 2440 * Data Group CRC Interval. 2441 */ 2442 register DGRPCRCI { 2443 address 0x060 2444 access_mode RW 2445 size 2 2446 modes M_CFG 2447 } 2448 2449 /* 2450 * Data Transfer Negotiation Address 2451 */ 2452 register NEGOADDR { 2453 address 0x060 2454 access_mode RW 2455 modes M_SCSI 2456 } 2457 2458 /* 2459 * Data Transfer Negotiation Data - Period Byte 2460 */ 2461 register NEGPERIOD { 2462 address 0x061 2463 access_mode RW 2464 modes M_SCSI 2465 } 2466 2467 /* 2468 * Packetized CRC Interval 2469 */ 2470 register PACKCRCI { 2471 address 0x062 2472 access_mode RW 2473 size 2 2474 modes M_CFG 2475 } 2476 2477 /* 2478 * Data Transfer Negotiation Data - Offset Byte 2479 */ 2480 register NEGOFFSET { 2481 address 0x062 2482 access_mode RW 2483 modes M_SCSI 2484 } 2485 2486 /* 2487 * Data Transfer Negotiation Data - PPR Options 2488 */ 2489 register NEGPPROPTS { 2490 address 0x063 2491 access_mode RW 2492 modes M_SCSI 2493 field PPROPT_PACE 0x08 2494 field PPROPT_QAS 0x04 2495 field PPROPT_DT 0x02 2496 field PPROPT_IUT 0x01 2497 } 2498 2499 /* 2500 * Data Transfer Negotiation Data - Connection Options 2501 */ 2502 register NEGCONOPTS { 2503 address 0x064 2504 access_mode RW 2505 modes M_SCSI 2506 field ENSNAPSHOT 0x40 2507 field RTI_WRTDIS 0x20 2508 field RTI_OVRDTRN 0x10 2509 field ENSLOWCRC 0x08 2510 field ENAUTOATNI 0x04 2511 field ENAUTOATNO 0x02 2512 field WIDEXFER 0x01 2513 } 2514 2515 /* 2516 * Negotiation Table Annex Column Index. 2517 */ 2518 register ANNEXCOL { 2519 address 0x065 2520 access_mode RW 2521 modes M_SCSI 2522 } 2523 2524 register SCSCHKN { 2525 address 0x066 2526 access_mode RW 2527 modes M_CFG 2528 field STSELSKIDDIS 0x40 2529 field CURRFIFODEF 0x20 2530 field WIDERESEN 0x10 2531 field SDONEMSKDIS 0x08 2532 field DFFACTCLR 0x04 2533 field SHVALIDSTDIS 0x02 2534 field LSTSGCLRDIS 0x01 2535 } 2536 2537 const AHD_ANNEXCOL_PER_DEV0 4 2538 const AHD_NUM_PER_DEV_ANNEXCOLS 4 2539 const AHD_ANNEXCOL_PRECOMP_SLEW 4 2540 const AHD_PRECOMP_MASK 0x07 2541 const AHD_PRECOMP_SHIFT 0 2542 const AHD_PRECOMP_CUTBACK_17 0x04 2543 const AHD_PRECOMP_CUTBACK_29 0x06 2544 const AHD_PRECOMP_CUTBACK_37 0x07 2545 const AHD_SLEWRATE_MASK 0x78 2546 const AHD_SLEWRATE_SHIFT 3 2547 /* 2548 * Rev A has only a single bit (high bit of field) of slew adjustment. 2549 * Rev B has 4 bits. The current default happens to be the same for both. 2550 */ 2551 const AHD_SLEWRATE_DEF_REVA 0x08 2552 const AHD_SLEWRATE_DEF_REVB 0x08 2553 2554 /* Rev A does not have any amplitude setting. */ 2555 const AHD_ANNEXCOL_AMPLITUDE 6 2556 const AHD_AMPLITUDE_MASK 0x7 2557 const AHD_AMPLITUDE_SHIFT 0 2558 const AHD_AMPLITUDE_DEF 0x7 2559 2560 /* 2561 * Negotiation Table Annex Data Port. 2562 */ 2563 register ANNEXDAT { 2564 address 0x066 2565 access_mode RW 2566 modes M_SCSI 2567 } 2568 2569 /* 2570 * Initiator's Own Id. 2571 * The SCSI ID to use for Selection Out and seen during a reselection.. 2572 */ 2573 register IOWNID { 2574 address 0x067 2575 access_mode RW 2576 modes M_SCSI 2577 } 2578 2579 /* 2580 * 960MHz Phase-Locked Loop Control 0 2581 */ 2582 register PLL960CTL0 { 2583 address 0x068 2584 access_mode RW 2585 modes M_CFG 2586 field PLL_VCOSEL 0x80 2587 field PLL_PWDN 0x40 2588 field PLL_NS 0x30 2589 field PLL_ENLUD 0x08 2590 field PLL_ENLPF 0x04 2591 field PLL_DLPF 0x02 2592 field PLL_ENFBM 0x01 2593 } 2594 2595 /* 2596 * Target Own Id 2597 */ 2598 register TOWNID { 2599 address 0x069 2600 access_mode RW 2601 modes M_SCSI 2602 } 2603 2604 /* 2605 * 960MHz Phase-Locked Loop Control 1 2606 */ 2607 register PLL960CTL1 { 2608 address 0x069 2609 access_mode RW 2610 modes M_CFG 2611 field PLL_CNTEN 0x80 2612 field PLL_CNTCLR 0x40 2613 field PLL_RST 0x01 2614 } 2615 2616 /* 2617 * Expander Signature 2618 */ 2619 register XSIG { 2620 address 0x06A 2621 access_mode RW 2622 modes M_SCSI 2623 } 2624 2625 /* 2626 * Shadow Byte Count 2627 */ 2628 register SHCNT { 2629 address 0x068 2630 access_mode RW 2631 size 3 2632 modes M_DFF0, M_DFF1 2633 } 2634 2635 /* 2636 * Selection Out ID 2637 */ 2638 register SELOID { 2639 address 0x06B 2640 access_mode RW 2641 modes M_SCSI 2642 } 2643 2644 /* 2645 * 960-MHz Phase-Locked Loop Test Count 2646 */ 2647 register PLL960CNT0 { 2648 address 0x06A 2649 access_mode RO 2650 size 2 2651 modes M_CFG 2652 } 2653 2654 /* 2655 * 400-MHz Phase-Locked Loop Control 0 2656 */ 2657 register PLL400CTL0 { 2658 address 0x06C 2659 access_mode RW 2660 modes M_CFG 2661 field PLL_VCOSEL 0x80 2662 field PLL_PWDN 0x40 2663 field PLL_NS 0x30 2664 field PLL_ENLUD 0x08 2665 field PLL_ENLPF 0x04 2666 field PLL_DLPF 0x02 2667 field PLL_ENFBM 0x01 2668 } 2669 2670 /* 2671 * Arbitration Fairness 2672 */ 2673 register FAIRNESS { 2674 address 0x06C 2675 access_mode RW 2676 size 2 2677 modes M_SCSI 2678 } 2679 2680 /* 2681 * 400-MHz Phase-Locked Loop Control 1 2682 */ 2683 register PLL400CTL1 { 2684 address 0x06D 2685 access_mode RW 2686 modes M_CFG 2687 field PLL_CNTEN 0x80 2688 field PLL_CNTCLR 0x40 2689 field PLL_RST 0x01 2690 } 2691 2692 /* 2693 * Arbitration Unfairness 2694 */ 2695 register UNFAIRNESS { 2696 address 0x06E 2697 access_mode RW 2698 size 2 2699 modes M_SCSI 2700 } 2701 2702 /* 2703 * 400-MHz Phase-Locked Loop Test Count 2704 */ 2705 register PLL400CNT0 { 2706 address 0x06E 2707 access_mode RO 2708 size 2 2709 modes M_CFG 2710 } 2711 2712 /* 2713 * SCB Page Pointer 2714 */ 2715 register SCBPTR { 2716 address 0x0A8 2717 access_mode RW 2718 size 2 2719 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2720 } 2721 2722 /* 2723 * CMC SCB Array Count 2724 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2725 * Transfers must be 8byte aligned and sized. 2726 */ 2727 register CCSCBACNT { 2728 address 0x0AB 2729 access_mode RW 2730 modes M_CCHAN 2731 } 2732 2733 /* 2734 * SCB Autopointer 2735 * SCB-Next Address Snooping logic. When an SCB is transferred to 2736 * the card, the next SCB address to be used by the CMC array can 2737 * be autoloaded from that transfer. 2738 */ 2739 register SCBAUTOPTR { 2740 address 0x0AB 2741 access_mode RW 2742 modes M_CFG 2743 field AUSCBPTR_EN 0x80 2744 field SCBPTR_ADDR 0x38 2745 field SCBPTR_OFF 0x07 2746 } 2747 2748 /* 2749 * CMC SG Ram Address Pointer 2750 */ 2751 register CCSGADDR { 2752 address 0x0AC 2753 access_mode RW 2754 modes M_DFF0, M_DFF1 2755 } 2756 2757 /* 2758 * CMC SCB RAM Address Pointer 2759 */ 2760 register CCSCBADDR { 2761 address 0x0AC 2762 access_mode RW 2763 modes M_CCHAN 2764 } 2765 2766 /* 2767 * CMC SCB Ram Back-up Address Pointer 2768 * Indicates the true stop location of transfers halted prior 2769 * to SCBHCNT going to 0. 2770 */ 2771 register CCSCBADR_BK { 2772 address 0x0AC 2773 access_mode RO 2774 modes M_CFG 2775 } 2776 2777 /* 2778 * CMC SG Control 2779 */ 2780 register CCSGCTL { 2781 address 0x0AD 2782 access_mode RW 2783 modes M_DFF0, M_DFF1 2784 field CCSGDONE 0x80 2785 field SG_CACHE_AVAIL 0x10 2786 field CCSGENACK 0x08 2787 mask CCSGEN 0x0C 2788 field SG_FETCH_REQ 0x02 2789 field CCSGRESET 0x01 2790 } 2791 2792 /* 2793 * CMD SCB Control 2794 */ 2795 register CCSCBCTL { 2796 address 0x0AD 2797 access_mode RW 2798 modes M_CCHAN 2799 field CCSCBDONE 0x80 2800 field ARRDONE 0x40 2801 field CCARREN 0x10 2802 field CCSCBEN 0x08 2803 field CCSCBDIR 0x04 2804 field CCSCBRESET 0x01 2805 } 2806 2807 /* 2808 * CMC Ram BIST 2809 */ 2810 register CMC_RAMBIST { 2811 address 0x0AD 2812 access_mode RW 2813 modes M_CFG 2814 field SG_ELEMENT_SIZE 0x80 2815 field SCBRAMBIST_FAIL 0x40 2816 field SG_BIST_FAIL 0x20 2817 field SG_BIST_EN 0x10 2818 field CMC_BUFFER_BIST_FAIL 0x02 2819 field CMC_BUFFER_BIST_EN 0x01 2820 } 2821 2822 /* 2823 * CMC SG RAM Data Port 2824 */ 2825 register CCSGRAM { 2826 address 0x0B0 2827 access_mode RW 2828 modes M_DFF0, M_DFF1 2829 } 2830 2831 /* 2832 * CMC SCB RAM Data Port 2833 */ 2834 register CCSCBRAM { 2835 address 0x0B0 2836 access_mode RW 2837 modes M_CCHAN 2838 } 2839 2840 /* 2841 * Flex DMA Address. 2842 */ 2843 register FLEXADR { 2844 address 0x0B0 2845 access_mode RW 2846 size 3 2847 modes M_SCSI 2848 } 2849 2850 /* 2851 * Flex DMA Byte Count 2852 */ 2853 register FLEXCNT { 2854 address 0x0B3 2855 access_mode RW 2856 size 2 2857 modes M_SCSI 2858 } 2859 2860 /* 2861 * Flex DMA Status 2862 */ 2863 register FLEXDMASTAT { 2864 address 0x0B5 2865 access_mode RW 2866 modes M_SCSI 2867 field FLEXDMAERR 0x02 2868 field FLEXDMADONE 0x01 2869 } 2870 2871 /* 2872 * Flex DMA Data Port 2873 */ 2874 register FLEXDATA { 2875 address 0x0B6 2876 access_mode RW 2877 modes M_SCSI 2878 } 2879 2880 /* 2881 * Board Data 2882 */ 2883 register BRDDAT { 2884 address 0x0B8 2885 access_mode RW 2886 modes M_SCSI 2887 } 2888 2889 /* 2890 * Board Control 2891 */ 2892 register BRDCTL { 2893 address 0x0B9 2894 access_mode RW 2895 modes M_SCSI 2896 field FLXARBACK 0x80 2897 field FLXARBREQ 0x40 2898 field BRDADDR 0x38 2899 field BRDEN 0x04 2900 field BRDRW 0x02 2901 field BRDSTB 0x01 2902 } 2903 2904 /* 2905 * Serial EEPROM Address 2906 */ 2907 register SEEADR { 2908 address 0x0BA 2909 access_mode RW 2910 modes M_SCSI 2911 } 2912 2913 /* 2914 * Serial EEPROM Data 2915 */ 2916 register SEEDAT { 2917 address 0x0BC 2918 access_mode RW 2919 size 2 2920 modes M_SCSI 2921 } 2922 2923 /* 2924 * Serial EEPROM Status 2925 */ 2926 register SEESTAT { 2927 address 0x0BE 2928 access_mode RO 2929 modes M_SCSI 2930 field INIT_DONE 0x80 2931 field SEEOPCODE 0x70 2932 field LDALTID_L 0x08 2933 field SEEARBACK 0x04 2934 field SEEBUSY 0x02 2935 field SEESTART 0x01 2936 } 2937 2938 /* 2939 * Serial EEPROM Control 2940 */ 2941 register SEECTL { 2942 address 0x0BE 2943 access_mode RW 2944 modes M_SCSI 2945 field SEEOPCODE 0x70 { 2946 SEEOP_ERASE 0x70, 2947 SEEOP_READ 0x60, 2948 SEEOP_WRITE 0x50, 2949 /* 2950 * The following four commands use special 2951 * addresses for differentiation. 2952 */ 2953 SEEOP_ERAL 0x40 2954 } 2955 mask SEEOP_EWEN 0x40 2956 mask SEEOP_WALL 0x40 2957 mask SEEOP_EWDS 0x40 2958 field SEERST 0x02 2959 field SEESTART 0x01 2960 } 2961 2962 const SEEOP_ERAL_ADDR 0x80 2963 const SEEOP_EWEN_ADDR 0xC0 2964 const SEEOP_WRAL_ADDR 0x40 2965 const SEEOP_EWDS_ADDR 0x00 2966 2967 /* 2968 * SCB Counter 2969 */ 2970 register SCBCNT { 2971 address 0x0BF 2972 access_mode RW 2973 modes M_SCSI 2974 } 2975 2976 /* 2977 * Data FIFO Write Address 2978 * Pointer to the next QWD location to be written to the data FIFO. 2979 */ 2980 register DFWADDR { 2981 address 0x0C0 2982 access_mode RW 2983 size 2 2984 modes M_DFF0, M_DFF1 2985 } 2986 2987 /* 2988 * DSP Filter Control 2989 */ 2990 register DSPFLTRCTL { 2991 address 0x0C0 2992 access_mode RW 2993 modes M_CFG 2994 field FLTRDISABLE 0x20 2995 field EDGESENSE 0x10 2996 field DSPFCNTSEL 0x0F 2997 } 2998 2999 /* 3000 * DSP Data Channel Control 3001 */ 3002 register DSPDATACTL { 3003 address 0x0C1 3004 access_mode RW 3005 modes M_CFG 3006 field BYPASSENAB 0x80 3007 field DESQDIS 0x10 3008 field RCVROFFSTDIS 0x04 3009 field XMITOFFSTDIS 0x02 3010 } 3011 3012 /* 3013 * Data FIFO Read Address 3014 * Pointer to the next QWD location to be read from the data FIFO. 3015 */ 3016 register DFRADDR { 3017 address 0x0C2 3018 access_mode RW 3019 size 2 3020 modes M_DFF0, M_DFF1 3021 } 3022 3023 /* 3024 * DSP REQ Control 3025 */ 3026 register DSPREQCTL { 3027 address 0x0C2 3028 access_mode RW 3029 modes M_CFG 3030 field MANREQCTL 0xC0 3031 field MANREQDLY 0x3F 3032 } 3033 3034 /* 3035 * DSP ACK Control 3036 */ 3037 register DSPACKCTL { 3038 address 0x0C3 3039 access_mode RW 3040 modes M_CFG 3041 field MANACKCTL 0xC0 3042 field MANACKDLY 0x3F 3043 } 3044 3045 /* 3046 * Data FIFO Data 3047 * Read/Write byte port into the data FIFO. The read and write 3048 * FIFO pointers increment with each read and write respectively 3049 * to this port. 3050 */ 3051 register DFDAT { 3052 address 0x0C4 3053 access_mode RW 3054 modes M_DFF0, M_DFF1 3055 } 3056 3057 /* 3058 * DSP Channel Select 3059 */ 3060 register DSPSELECT { 3061 address 0x0C4 3062 access_mode RW 3063 modes M_CFG 3064 field AUTOINCEN 0x80 3065 field DSPSEL 0x1F 3066 } 3067 3068 const NUMDSPS 0x14 3069 3070 /* 3071 * Write Bias Control 3072 */ 3073 register WRTBIASCTL { 3074 address 0x0C5 3075 access_mode WO 3076 modes M_CFG 3077 field AUTOXBCDIS 0x80 3078 field XMITMANVAL 0x3F 3079 } 3080 3081 /* 3082 * Currently the WRTBIASCTL is the same as the default. 3083 */ 3084 const WRTBIASCTL_HP_DEFAULT 0x0 3085 3086 /* 3087 * Receiver Bias Control 3088 */ 3089 register RCVRBIOSCTL { 3090 address 0x0C6 3091 access_mode WO 3092 modes M_CFG 3093 field AUTORBCDIS 0x80 3094 field RCVRMANVAL 0x3F 3095 } 3096 3097 /* 3098 * Write Bias Calculator 3099 */ 3100 register WRTBIASCALC { 3101 address 0x0C7 3102 access_mode RO 3103 modes M_CFG 3104 } 3105 3106 /* 3107 * Data FIFO Pointers 3108 * Contains the byte offset from DFWADDR and DWRADDR to the current 3109 * FIFO write/read locations. 3110 */ 3111 register DFPTRS { 3112 address 0x0C8 3113 access_mode RW 3114 modes M_DFF0, M_DFF1 3115 } 3116 3117 /* 3118 * Receiver Bias Calculator 3119 */ 3120 register RCVRBIASCALC { 3121 address 0x0C8 3122 access_mode RO 3123 modes M_CFG 3124 } 3125 3126 /* 3127 * Data FIFO Backup Read Pointer 3128 * Contains the data FIFO address to be restored if the last 3129 * data accessed from the data FIFO was not transferred successfully. 3130 */ 3131 register DFBKPTR { 3132 address 0x0C9 3133 access_mode RW 3134 size 2 3135 modes M_DFF0, M_DFF1 3136 } 3137 3138 /* 3139 * Skew Calculator 3140 */ 3141 register SKEWCALC { 3142 address 0x0C9 3143 access_mode RO 3144 modes M_CFG 3145 } 3146 3147 /* 3148 * Data FIFO Debug Control 3149 */ 3150 register DFDBCTL { 3151 address 0x0CB 3152 access_mode RW 3153 modes M_DFF0, M_DFF1 3154 field DFF_CIO_WR_RDY 0x20 3155 field DFF_CIO_RD_RDY 0x10 3156 field DFF_DIR_ERR 0x08 3157 field DFF_RAMBIST_FAIL 0x04 3158 field DFF_RAMBIST_DONE 0x02 3159 field DFF_RAMBIST_EN 0x01 3160 } 3161 3162 /* 3163 * Data FIFO Space Count 3164 * Number of FIFO locations that are free. 3165 */ 3166 register DFSCNT { 3167 address 0x0CC 3168 access_mode RO 3169 size 2 3170 modes M_DFF0, M_DFF1 3171 } 3172 3173 /* 3174 * Data FIFO Byte Count 3175 * Number of filled FIFO locations. 3176 */ 3177 register DFBCNT { 3178 address 0x0CE 3179 access_mode RO 3180 size 2 3181 modes M_DFF0, M_DFF1 3182 } 3183 3184 /* 3185 * Sequencer Program Overlay Address. 3186 * Low address must be written prior to high address. 3187 */ 3188 register OVLYADDR { 3189 address 0x0D4 3190 modes M_SCSI 3191 size 2 3192 access_mode RW 3193 } 3194 3195 /* 3196 * Sequencer Control 0 3197 * Error detection mode, speed configuration, 3198 * single step, breakpoints and program load. 3199 */ 3200 register SEQCTL0 { 3201 address 0x0D6 3202 access_mode RW 3203 field PERRORDIS 0x80 3204 field PAUSEDIS 0x40 3205 field FAILDIS 0x20 3206 field FASTMODE 0x10 3207 field BRKADRINTEN 0x08 3208 field STEP 0x04 3209 field SEQRESET 0x02 3210 field LOADRAM 0x01 3211 } 3212 3213 /* 3214 * Sequencer Control 1 3215 * Instruction RAM Diagnostics 3216 */ 3217 register SEQCTL1 { 3218 address 0x0D7 3219 access_mode RW 3220 field OVRLAY_DATA_CHK 0x08 3221 field RAMBIST_DONE 0x04 3222 field RAMBIST_FAIL 0x02 3223 field RAMBIST_EN 0x01 3224 } 3225 3226 /* 3227 * Sequencer Flags 3228 * Zero and Carry state of the ALU. 3229 */ 3230 register FLAGS { 3231 address 0x0D8 3232 access_mode RO 3233 field ZERO 0x02 3234 field CARRY 0x01 3235 } 3236 3237 /* 3238 * Sequencer Interrupt Control 3239 */ 3240 register SEQINTCTL { 3241 address 0x0D9 3242 access_mode RW 3243 field INTVEC1DSL 0x80 3244 field INT1_CONTEXT 0x20 3245 field SCS_SEQ_INT1M1 0x10 3246 field SCS_SEQ_INT1M0 0x08 3247 field INTMASK2 0x04 3248 field INTMASK1 0x02 3249 field IRET 0x01 3250 } 3251 3252 /* 3253 * Sequencer RAM Data Port 3254 * Single byte window into the Sequencer Instruction Ram area starting 3255 * at the address specified by OVLYADDR. To write a full instruction word, 3256 * simply write four bytes in succession. OVLYADDR will increment after the 3257 * most significant instrution byte (the byte with the parity bit) is written. 3258 */ 3259 register SEQRAM { 3260 address 0x0DA 3261 access_mode RW 3262 } 3263 3264 /* 3265 * Sequencer Program Counter 3266 * Low byte must be written prior to high byte. 3267 */ 3268 register PRGMCNT { 3269 address 0x0DE 3270 access_mode RW 3271 size 2 3272 } 3273 3274 /* 3275 * Accumulator 3276 */ 3277 register ACCUM { 3278 address 0x0E0 3279 access_mode RW 3280 accumulator 3281 } 3282 3283 /* 3284 * Source Index Register 3285 * Incrementing index for reads of SINDIR and the destination (low byte only) 3286 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3287 * Example: 3288 * mvi 0xFF call some_routine; 3289 * 3290 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3291 */ 3292 register SINDEX { 3293 address 0x0E2 3294 access_mode RW 3295 size 2 3296 sindex 3297 } 3298 3299 /* 3300 * Destination Index Register 3301 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3302 */ 3303 register DINDEX { 3304 address 0x0E4 3305 access_mode RW 3306 size 2 3307 } 3308 3309 /* 3310 * Break Address 3311 * Sequencer instruction breakpoint address address. 3312 */ 3313 register BRKADDR0 { 3314 address 0x0E6 3315 access_mode RW 3316 } 3317 3318 register BRKADDR1 { 3319 address 0x0E6 3320 access_mode RW 3321 field BRKDIS 0x80 /* Disable Breakpoint */ 3322 } 3323 3324 /* 3325 * All Ones 3326 * All reads to this register return the value 0xFF. 3327 */ 3328 register ALLONES { 3329 address 0x0E8 3330 access_mode RO 3331 allones 3332 } 3333 3334 /* 3335 * All Zeros 3336 * All reads to this register return the value 0. 3337 */ 3338 register ALLZEROS { 3339 address 0x0EA 3340 access_mode RO 3341 allzeros 3342 } 3343 3344 /* 3345 * No Destination 3346 * Writes to this register have no effect. 3347 */ 3348 register NONE { 3349 address 0x0EA 3350 access_mode WO 3351 none 3352 } 3353 3354 /* 3355 * Source Index Indirect 3356 * Reading this register is equivalent to reading (register_base + SINDEX) and 3357 * incrementing SINDEX by 1. 3358 */ 3359 register SINDIR { 3360 address 0x0EC 3361 access_mode RO 3362 } 3363 3364 /* 3365 * Destination Index Indirect 3366 * Writing this register is equivalent to writing to (register_base + DINDEX) 3367 * and incrementing DINDEX by 1. 3368 */ 3369 register DINDIR { 3370 address 0x0ED 3371 access_mode WO 3372 } 3373 3374 /* 3375 * Function One 3376 * 2's complement to bit value conversion. Write the 2's complement value 3377 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3378 * on the next read of this register. 3379 * Example: 3380 * Write 0x60 3381 * Read 0x40 3382 */ 3383 register FUNCTION1 { 3384 address 0x0F0 3385 access_mode RW 3386 } 3387 3388 /* 3389 * Stack 3390 * Window into the stack. Each stack location is 10 bits wide reported 3391 * low byte followed by high byte. There are 8 stack locations. 3392 */ 3393 register STACK { 3394 address 0x0F2 3395 access_mode RW 3396 } 3397 3398 /* 3399 * Interrupt Vector 1 Address 3400 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3401 */ 3402 register INTVEC1_ADDR { 3403 address 0x0F4 3404 access_mode RW 3405 size 2 3406 modes M_CFG 3407 } 3408 3409 /* 3410 * Current Address 3411 * Address of the SEQRAM instruction currently executing instruction. 3412 */ 3413 register CURADDR { 3414 address 0x0F4 3415 access_mode RW 3416 size 2 3417 modes M_SCSI 3418 } 3419 3420 /* 3421 * Interrupt Vector 2 Address 3422 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3423 */ 3424 register INTVEC2_ADDR { 3425 address 0x0F6 3426 access_mode RW 3427 size 2 3428 modes M_CFG 3429 } 3430 3431 /* 3432 * Last Address 3433 * Address of the SEQRAM instruction executed prior to the current instruction. 3434 */ 3435 register LASTADDR { 3436 address 0x0F6 3437 access_mode RW 3438 size 2 3439 modes M_SCSI 3440 } 3441 3442 register AHD_PCI_CONFIG_BASE { 3443 address 0x100 3444 access_mode RW 3445 size 256 3446 modes M_CFG 3447 } 3448 3449 /* ---------------------- Scratch RAM Offsets ------------------------- */ 3450 scratch_ram { 3451 /* Mode Specific */ 3452 address 0x0A0 3453 size 8 3454 modes 0, 1, 2, 3 3455 REG0 { 3456 size 2 3457 } 3458 REG1 { 3459 size 2 3460 } 3461 REG_ISR { 3462 size 2 3463 } 3464 SG_STATE { 3465 size 1 3466 field SEGS_AVAIL 0x01 3467 field LOADING_NEEDED 0x02 3468 field FETCH_INPROG 0x04 3469 } 3470 /* 3471 * Track whether the transfer byte count for 3472 * the current data phase is odd. 3473 */ 3474 DATA_COUNT_ODD { 3475 size 1 3476 } 3477 } 3478 3479 scratch_ram { 3480 /* Mode Specific */ 3481 address 0x0F8 3482 size 8 3483 modes 0, 1, 2, 3 3484 LONGJMP_ADDR { 3485 size 2 3486 } 3487 LONGJMP_SCB { 3488 size 2 3489 } 3490 ACCUM_SAVE { 3491 size 1 3492 } 3493 } 3494 3495 3496 scratch_ram { 3497 address 0x100 3498 size 128 3499 modes 0, 1, 2, 3 3500 /* 3501 * Per "other-id" execution queues. We use an array of 3502 * tail pointers into lists of SCBs sorted by "other-id". 3503 * The execution head pointer threads the head SCBs for 3504 * each list. 3505 */ 3506 WAITING_SCB_TAILS { 3507 size 32 3508 } 3509 WAITING_TID_HEAD { 3510 size 2 3511 } 3512 WAITING_TID_TAIL { 3513 size 2 3514 } 3515 /* 3516 * SCBID of the next SCB in the new SCB queue. 3517 */ 3518 NEXT_QUEUED_SCB_ADDR { 3519 size 4 3520 } 3521 /* 3522 * head of list of SCBs that have 3523 * completed but have not been 3524 * put into the qoutfifo. 3525 */ 3526 COMPLETE_SCB_HEAD { 3527 size 2 3528 } 3529 /* 3530 * The list of completed SCBs in 3531 * the active DMA. 3532 */ 3533 COMPLETE_SCB_DMAINPROG_HEAD { 3534 size 2 3535 } 3536 /* 3537 * head of list of SCBs that have 3538 * completed but need to be uploaded 3539 * to the host prior to being completed. 3540 */ 3541 COMPLETE_DMA_SCB_HEAD { 3542 size 2 3543 } 3544 /* Counting semaphore to prevent new select-outs */ 3545 QFREEZE_COUNT { 3546 size 2 3547 } 3548 /* 3549 * Mode to restore on legacy idle loop exit. 3550 */ 3551 SAVED_MODE { 3552 size 1 3553 } 3554 /* 3555 * Single byte buffer used to designate the type or message 3556 * to send to a target. 3557 */ 3558 MSG_OUT { 3559 size 1 3560 } 3561 /* Parameters for DMA Logic */ 3562 DMAPARAMS { 3563 size 1 3564 field PRELOADEN 0x80 3565 field WIDEODD 0x40 3566 field SCSIEN 0x20 3567 field SDMAEN 0x10 3568 field SDMAENACK 0x10 3569 field HDMAEN 0x08 3570 field HDMAENACK 0x08 3571 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3572 field FIFOFLUSH 0x02 3573 field FIFORESET 0x01 3574 } 3575 SEQ_FLAGS { 3576 size 1 3577 field NOT_IDENTIFIED 0x80 3578 field NO_CDB_SENT 0x40 3579 field TARGET_CMD_IS_TAGGED 0x40 3580 field DPHASE 0x20 3581 /* Target flags */ 3582 field TARG_CMD_PENDING 0x10 3583 field CMDPHASE_PENDING 0x08 3584 field DPHASE_PENDING 0x04 3585 field SPHASE_PENDING 0x02 3586 field NO_DISCONNECT 0x01 3587 } 3588 /* 3589 * Temporary storage for the 3590 * target/channel/lun of a 3591 * reconnecting target 3592 */ 3593 SAVED_SCSIID { 3594 size 1 3595 } 3596 SAVED_LUN { 3597 size 1 3598 } 3599 /* 3600 * The last bus phase as seen by the sequencer. 3601 */ 3602 LASTPHASE { 3603 size 1 3604 field CDI 0x80 3605 field IOI 0x40 3606 field MSGI 0x20 3607 field P_BUSFREE 0x01 3608 enum PHASE_MASK CDO|IOO|MSGO { 3609 P_DATAOUT 0x0, 3610 P_DATAIN IOO, 3611 P_DATAOUT_DT P_DATAOUT|MSGO, 3612 P_DATAIN_DT P_DATAIN|MSGO, 3613 P_COMMAND CDO, 3614 P_MESGOUT CDO|MSGO, 3615 P_STATUS CDO|IOO, 3616 P_MESGIN CDO|IOO|MSGO 3617 } 3618 } 3619 /* 3620 * Value to "or" into the SCBPTR[1] value to 3621 * indicate that an entry in the QINFIFO is valid. 3622 */ 3623 QOUTFIFO_ENTRY_VALID_TAG { 3624 size 1 3625 } 3626 /* 3627 * Base address of our shared data with the kernel driver in host 3628 * memory. This includes the qoutfifo and target mode 3629 * incoming command queue. 3630 */ 3631 SHARED_DATA_ADDR { 3632 size 4 3633 } 3634 /* 3635 * Pointer to location in host memory for next 3636 * position in the qoutfifo. 3637 */ 3638 QOUTFIFO_NEXT_ADDR { 3639 size 4 3640 } 3641 /* 3642 * Kernel and sequencer offsets into the queue of 3643 * incoming target mode command descriptors. The 3644 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3645 */ 3646 KERNEL_TQINPOS { 3647 size 1 3648 } 3649 TQINPOS { 3650 size 1 3651 } 3652 ARG_1 { 3653 size 1 3654 mask SEND_MSG 0x80 3655 mask SEND_SENSE 0x40 3656 mask SEND_REJ 0x20 3657 mask MSGOUT_PHASEMIS 0x10 3658 mask EXIT_MSG_LOOP 0x08 3659 mask CONT_MSG_LOOP_WRITE 0x04 3660 mask CONT_MSG_LOOP_READ 0x03 3661 mask CONT_MSG_LOOP_TARG 0x02 3662 alias RETURN_1 3663 } 3664 ARG_2 { 3665 size 1 3666 alias RETURN_2 3667 } 3668 3669 /* 3670 * Snapshot of MSG_OUT taken after each message is sent. 3671 */ 3672 LAST_MSG { 3673 size 1 3674 } 3675 3676 /* 3677 * Sequences the kernel driver has okayed for us. This allows 3678 * the driver to do things like prevent initiator or target 3679 * operations. 3680 */ 3681 SCSISEQ_TEMPLATE { 3682 size 1 3683 field MANUALCTL 0x40 3684 field ENSELI 0x20 3685 field ENRSELI 0x10 3686 field MANUALP 0x0C 3687 field ENAUTOATNP 0x02 3688 field ALTSTIM 0x01 3689 } 3690 3691 /* 3692 * The initiator specified tag for this target mode transaction. 3693 */ 3694 INITIATOR_TAG { 3695 size 1 3696 } 3697 3698 SEQ_FLAGS2 { 3699 size 1 3700 field TARGET_MSG_PENDING 0x02 3701 field SELECTOUT_QFROZEN 0x04 3702 } 3703 3704 ALLOCFIFO_SCBPTR { 3705 size 2 3706 } 3707 3708 /* 3709 * The maximum amount of time to wait, when interrupt coalescing 3710 * is enabled, before issueing a CMDCMPLT interrupt for a completed 3711 * command. 3712 */ 3713 INT_COALESCING_TIMER { 3714 size 2 3715 } 3716 3717 /* 3718 * The maximum number of commands to coalesce into a single interrupt. 3719 * Actually the 2's complement of that value to simplify sequencer 3720 * code. 3721 */ 3722 INT_COALESCING_MAXCMDS { 3723 size 1 3724 } 3725 3726 /* 3727 * The minimum number of commands still outstanding required 3728 * to continue coalescing (2's complement of value). 3729 */ 3730 INT_COALESCING_MINCMDS { 3731 size 1 3732 } 3733 3734 /* 3735 * Number of commands "in-flight". 3736 */ 3737 CMDS_PENDING { 3738 size 2 3739 } 3740 3741 /* 3742 * The count of commands that have been coalesced. 3743 */ 3744 INT_COALESCING_CMDCOUNT { 3745 size 1 3746 } 3747 3748 /* 3749 * Since the HS_MAIBOX is self clearing, copy its contents to 3750 * this position in scratch ram every time it changes. 3751 */ 3752 LOCAL_HS_MAILBOX { 3753 size 1 3754 } 3755 /* 3756 * Target-mode CDB type to CDB length table used 3757 * in non-packetized operation. 3758 */ 3759 CMDSIZE_TABLE { 3760 size 8 3761 } 3762 } 3763 3764 /************************* Hardware SCB Definition ****************************/ 3765 scb { 3766 address 0x180 3767 size 64 3768 modes 0, 1, 2, 3 3769 SCB_RESIDUAL_DATACNT { 3770 size 4 3771 alias SCB_CDB_STORE 3772 alias SCB_HOST_CDB_PTR 3773 } 3774 SCB_RESIDUAL_SGPTR { 3775 size 4 3776 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3777 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3778 field SG_LIST_NULL 0x01 /* In the first byte */ 3779 } 3780 SCB_SCSI_STATUS { 3781 size 1 3782 alias SCB_HOST_CDB_LEN 3783 } 3784 SCB_TARGET_PHASES { 3785 size 1 3786 } 3787 SCB_TARGET_DATA_DIR { 3788 size 1 3789 } 3790 SCB_TARGET_ITAG { 3791 size 1 3792 } 3793 SCB_SENSE_BUSADDR { 3794 /* 3795 * Only valid if CDB length is less than 13 bytes or 3796 * we are using a CDB pointer. Otherwise contains 3797 * the last 4 bytes of embedded cdb information. 3798 */ 3799 size 4 3800 alias SCB_NEXT_COMPLETE 3801 } 3802 SCB_TAG { 3803 size 2 3804 } 3805 SCB_CDB_LEN { 3806 size 1 3807 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3808 } 3809 SCB_TASK_MANAGEMENT { 3810 size 1 3811 } 3812 SCB_NEXT { 3813 alias SCB_NEXT_SCB_BUSADDR 3814 size 2 3815 } 3816 SCB_NEXT2 { 3817 size 2 3818 } 3819 SCB_DATAPTR { 3820 size 8 3821 } 3822 SCB_DATACNT { 3823 /* 3824 * The last byte is really the high address bits for 3825 * the data address. 3826 */ 3827 size 4 3828 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3829 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3830 } 3831 SCB_SGPTR { 3832 size 4 3833 field SG_STATUS_VALID 0x04 /* In the first byte */ 3834 field SG_FULL_RESID 0x02 /* In the first byte */ 3835 field SG_LIST_NULL 0x01 /* In the first byte */ 3836 } 3837 SCB_CONTROL { 3838 size 1 3839 field TARGET_SCB 0x80 3840 field DISCENB 0x40 3841 field TAG_ENB 0x20 3842 field MK_MESSAGE 0x10 3843 field STATUS_RCVD 0x08 3844 field DISCONNECTED 0x04 3845 field SCB_TAG_TYPE 0x03 3846 } 3847 SCB_SCSIID { 3848 size 1 3849 field TID 0xF0 3850 field OID 0x0F 3851 } 3852 SCB_LUN { 3853 size 1 3854 field LID 0xff 3855 } 3856 SCB_TASK_ATTRIBUTE { 3857 size 1 3858 } 3859 SCB_BUSADDR { 3860 size 4 3861 } 3862 SCB_SPARE { 3863 size 8 3864 alias SCB_PKT_LUN 3865 } 3866 SCB_DISCONNECTED_LISTS { 3867 size 8 3868 } 3869 } 3870 3871 /*********************************** Constants ********************************/ 3872 const MK_MESSAGE_BIT_OFFSET 4 3873 const TID_SHIFT 4 3874 const TARGET_CMD_CMPLT 0xfe 3875 const INVALID_ADDR 0x80 3876 #define SCB_LIST_NULL 0xff 3877 #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3878 3879 const CCSGADDR_MAX 0x80 3880 const CCSCBADDR_MAX 0x80 3881 const CCSGRAM_MAXSEGS 16 3882 3883 /* Selection Timeout Timer Constants */ 3884 const STIMESEL_SHIFT 3 3885 const STIMESEL_MIN 0x18 3886 const STIMESEL_BUG_ADJ 0x8 3887 3888 /* WDTR Message values */ 3889 const BUS_8_BIT 0x00 3890 const BUS_16_BIT 0x01 3891 const BUS_32_BIT 0x02 3892 3893 /* Offset maximums */ 3894 const MAX_OFFSET 0xfe 3895 const MAX_OFFSET_PACED 0xfe 3896 const MAX_OFFSET_PACED_BUG 0x7f 3897 /* 3898 * Some 160 devices incorrectly accept 0xfe as a 3899 * sync offset, but will overrun this value. Limit 3900 * to 0x7f for speed lower than U320 which will 3901 * avoid the persistent sync offset overruns. 3902 */ 3903 const MAX_OFFSET_NON_PACED 0x7f 3904 const HOST_MSG 0xff 3905 3906 /* 3907 * The size of our sense buffers. 3908 * Sense buffer mapping can be handled in either of two ways. 3909 * The first is to allocate a dmamap for each transaction. 3910 * Depending on the architecture, dmamaps can be costly. The 3911 * alternative is to statically map the buffers in much the same 3912 * way we handle our scatter gather lists. The driver implements 3913 * the later. 3914 */ 3915 const AHD_SENSE_BUFSIZE 256 3916 3917 /* Target mode command processing constants */ 3918 const CMD_GROUP_CODE_SHIFT 0x05 3919 3920 const STATUS_BUSY 0x08 3921 const STATUS_QUEUE_FULL 0x28 3922 const STATUS_PKT_SENSE 0xFF 3923 const TARGET_DATA_IN 1 3924 3925 const SCB_TRANSFER_SIZE_FULL_LUN 56 3926 const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3927 /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3928 const PKT_OVERRUN_BUFSIZE 512 3929 3930 /* 3931 * Timer parameters. 3932 */ 3933 const AHD_TIMER_US_PER_TICK 25 3934 const AHD_TIMER_MAX_TICKS 0xFFFF 3935 const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 3936 3937 /* 3938 * Downloaded (kernel inserted) constants 3939 */ 3940 const SG_PREFETCH_CNT download 3941 const SG_PREFETCH_CNT_LIMIT download 3942 const SG_PREFETCH_ALIGN_MASK download 3943 const SG_PREFETCH_ADDR_MASK download 3944 const SG_SIZEOF download 3945 const PKT_OVERRUN_BUFOFFSET download 3946 const SCB_TRANSFER_SIZE download 3947 3948 /* 3949 * BIOS SCB offsets 3950 */ 3951 const NVRAM_SCB_OFFSET 0x2C 3952
Indexes created Tue Oct 28 02:10:10 GMT 2025