aic79xx.reg revision 1.5
1 /* $NetBSD: aic79xx.reg,v 1.5 2003/08/29 01:28:53 thorpej Exp $ */ 2 3 /* 4 * Aic79xx register and scratch ram definitions. 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.reg,v 1.13 2003/05/26 21:26:51 gibbs Exp $ 43 */ 44 VERSION = "Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#69 $" 45 46 /* 47 * This file is processed by the aic7xxx_asm utility for use in assembling 48 * firmware for the aic79xx family of SCSI host adapters as well as to generate 49 * a C header file for use in the kernel portion of the Aic79xx driver. 50 */ 51 52 /* Register window Modes */ 53 #define M_DFF0 0 54 #define M_DFF1 1 55 #define M_CCHAN 2 56 #define M_SCSI 3 57 #define M_CFG 4 58 #define M_DST_SHIFT 4 59 60 #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 61 #define SET_MODE(src, dst) \ 62 SET_SRC_MODE src; \ 63 SET_DST_MODE dst; \ 64 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 65 mvi MK_MODE(src, dst) call set_mode_work_around; \ 66 } else { \ 67 mvi MODE_PTR, MK_MODE(src, dst); \ 68 } 69 70 #define TOGGLE_DFF_MODE \ 71 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 72 call toggle_dff_mode_work_around; \ 73 } else { \ 74 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 75 } 76 77 #define RESTORE_MODE(mode) \ 78 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 79 mov mode call set_mode_work_around; \ 80 } else { \ 81 mov MODE_PTR, mode; \ 82 } 83 84 #define SET_SEQINTCODE(code) \ 85 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 86 mvi code call set_seqint_work_around; \ 87 } else { \ 88 mvi SEQINTCODE, code; \ 89 } 90 91 /* 92 * Mode Pointer 93 * Controls which of the 5, 512byte, address spaces should be used 94 * as the source and destination of any register accesses in our 95 * register window. 96 */ 97 register MODE_PTR { 98 address 0x000 99 access_mode RW 100 field DST_MODE 0x70 101 field SRC_MODE 0x07 102 mode_pointer 103 } 104 105 const SRC_MODE_SHIFT 0 106 const DST_MODE_SHIFT 4 107 108 /* 109 * Host Interrupt Status 110 */ 111 register INTSTAT { 112 address 0x001 113 access_mode RW 114 field HWERRINT 0x80 115 field BRKADRINT 0x40 116 field SWTMINT 0x20 117 field PCIINT 0x10 118 field SCSIINT 0x08 119 field SEQINT 0x04 120 field CMDCMPLT 0x02 121 field SPLTINT 0x01 122 mask INT_PEND 0xFF 123 } 124 125 /* 126 * Sequencer Interrupt Code 127 */ 128 register SEQINTCODE { 129 address 0x002 130 access_mode RW 131 field { 132 NO_SEQINT, /* No seqint pending. */ 133 BAD_PHASE, /* unknown scsi bus phase */ 134 SEND_REJECT, /* sending a message reject */ 135 PROTO_VIOLATION, /* Protocol Violation */ 136 NO_MATCH, /* no cmd match for reconnect */ 137 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 138 PDATA_REINIT, /* 139 * Returned to data phase 140 * that requires data 141 * transfer pointers to be 142 * recalculated from the 143 * transfer residual. 144 */ 145 HOST_MSG_LOOP, /* 146 * The bus is ready for the 147 * host to perform another 148 * message transaction. This 149 * mechanism is used for things 150 * like sync/wide negotiation 151 * that require a kernel based 152 * message state engine. 153 */ 154 BAD_STATUS, /* Bad status from target */ 155 DATA_OVERRUN, /* 156 * Target attempted to write 157 * beyond the bounds of its 158 * command. 159 */ 160 MKMSG_FAILED, /* 161 * Target completed command 162 * without honoring our ATN 163 * request to issue a message. 164 */ 165 MISSED_BUSFREE, /* 166 * The sequencer never saw 167 * the bus go free after 168 * either a command complete 169 * or disconnect message. 170 */ 171 DUMP_CARD_STATE, 172 ILLEGAL_PHASE, 173 INVALID_SEQINT, 174 CFG4ISTAT_INTR, 175 STATUS_OVERRUN, 176 CFG4OVERRUN, 177 ENTERING_NONPACK, 178 TASKMGMT_FUNC_COMPLETE, /* 179 * Task management function 180 * request completed with 181 * an expected busfree. 182 */ 183 TASKMGMT_CMD_CMPLT_OKAY, /* 184 * A command with a non-zero 185 * task management function 186 * has completed via the normal 187 * command completion method 188 * for commands with a zero 189 * task management function. 190 * This happens when an attempt 191 * to abort a command loses 192 * the race for the command to 193 * complete normally. 194 */ 195 TRACEPOINT0, 196 TRACEPOINT1, 197 TRACEPOINT2, 198 TRACEPOINT3, 199 SAW_HWERR, 200 BAD_SCB_STATUS 201 } 202 } 203 204 /* 205 * Clear Host Interrupt 206 */ 207 register CLRINT { 208 address 0x003 209 access_mode WO 210 field CLRHWERRINT 0x80 /* Rev B or greater */ 211 field CLRBRKADRINT 0x40 212 field CLRSWTMINT 0x20 213 field CLRPCIINT 0x10 214 field CLRSCSIINT 0x08 215 field CLRSEQINT 0x04 216 field CLRCMDINT 0x02 217 field CLRSPLTINT 0x01 218 } 219 220 /* 221 * Error Register 222 */ 223 register ERROR { 224 address 0x004 225 access_mode RO 226 field CIOPARERR 0x80 227 field CIOACCESFAIL 0x40 /* Rev B or greater */ 228 field MPARERR 0x20 229 field DPARERR 0x10 230 field SQPARERR 0x08 231 field ILLOPCODE 0x04 232 field DSCTMOUT 0x02 233 } 234 235 /* 236 * Clear Error 237 */ 238 register CLRERR { 239 address 0x004 240 access_mode WO 241 field CLRCIOPARERR 0x80 242 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 243 field CLRMPARERR 0x20 244 field CLRDPARERR 0x10 245 field CLRSQPARERR 0x08 246 field CLRILLOPCODE 0x04 247 field CLRDSCTMOUT 0x02 248 } 249 250 /* 251 * Host Control Register 252 * Overall host control of the device. 253 */ 254 register HCNTRL { 255 address 0x005 256 access_mode RW 257 field SEQ_RESET 0x80 /* Rev B or greater */ 258 field POWRDN 0x40 259 field SWINT 0x10 260 field SWTIMER_START_B 0x08 /* Rev B or greater */ 261 field PAUSE 0x04 262 field INTEN 0x02 263 field CHIPRST 0x01 264 field CHIPRSTACK 0x01 265 } 266 267 /* 268 * Host New SCB Queue Offset 269 */ 270 register HNSCB_QOFF { 271 address 0x006 272 access_mode RW 273 size 2 274 } 275 276 /* 277 * Host Empty SCB Queue Offset 278 */ 279 register HESCB_QOFF { 280 address 0x008 281 access_mode RW 282 } 283 284 /* 285 * Host Mailbox 286 */ 287 register HS_MAILBOX { 288 address 0x00B 289 access_mode RW 290 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 291 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 292 } 293 294 /* 295 * Sequencer Interupt Status 296 */ 297 register SEQINTSTAT { 298 address 0x00C 299 access_mode RO 300 field SEQ_SWTMRTO 0x10 301 field SEQ_SEQINT 0x08 302 field SEQ_SCSIINT 0x04 303 field SEQ_PCIINT 0x02 304 field SEQ_SPLTINT 0x01 305 } 306 307 /* 308 * Clear SEQ Interrupt 309 */ 310 register CLRSEQINTSTAT { 311 address 0x00C 312 access_mode WO 313 field CLRSEQ_SWTMRTO 0x10 314 field CLRSEQ_SEQINT 0x08 315 field CLRSEQ_SCSIINT 0x04 316 field CLRSEQ_PCIINT 0x02 317 field CLRSEQ_SPLTINT 0x01 318 } 319 320 /* 321 * Software Timer 322 */ 323 register SWTIMER { 324 address 0x00E 325 access_mode RW 326 size 2 327 } 328 329 /* 330 * SEQ New SCB Queue Offset 331 */ 332 register SNSCB_QOFF { 333 address 0x010 334 access_mode RW 335 size 2 336 modes M_CCHAN 337 } 338 339 /* 340 * SEQ Empty SCB Queue Offset 341 */ 342 register SESCB_QOFF { 343 address 0x012 344 access_mode RW 345 modes M_CCHAN 346 } 347 348 /* 349 * SEQ Done SCB Queue Offset 350 */ 351 register SDSCB_QOFF { 352 address 0x014 353 access_mode RW 354 modes M_CCHAN 355 size 2 356 } 357 358 /* 359 * Queue Offset Control & Status 360 */ 361 register QOFF_CTLSTA { 362 address 0x016 363 access_mode RW 364 modes M_CCHAN 365 field EMPTY_SCB_AVAIL 0x80 366 field NEW_SCB_AVAIL 0x40 367 field SDSCB_ROLLOVR 0x20 368 field HS_MAILBOX_ACT 0x10 369 field SCB_QSIZE 0x0F { 370 SCB_QSIZE_4, 371 SCB_QSIZE_8, 372 SCB_QSIZE_16, 373 SCB_QSIZE_32, 374 SCB_QSIZE_64, 375 SCB_QSIZE_128, 376 SCB_QSIZE_256, 377 SCB_QSIZE_512, 378 SCB_QSIZE_1024, 379 SCB_QSIZE_2048, 380 SCB_QSIZE_4096, 381 SCB_QSIZE_8192, 382 SCB_QSIZE_16384 383 } 384 } 385 386 /* 387 * Interrupt Control 388 */ 389 register INTCTL { 390 address 0x018 391 access_mode RW 392 field SWTMINTMASK 0x80 393 field SWTMINTEN 0x40 394 field SWTIMER_START 0x20 395 field AUTOCLRCMDINT 0x10 396 field PCIINTEN 0x08 397 field SCSIINTEN 0x04 398 field SEQINTEN 0x02 399 field SPLTINTEN 0x01 400 } 401 402 /* 403 * Data FIFO Control 404 */ 405 register DFCNTRL { 406 address 0x019 407 access_mode RW 408 modes M_DFF0, M_DFF1 409 field PRELOADEN 0x80 410 field SCSIENWRDIS 0x40 /* Rev B only. */ 411 field SCSIEN 0x20 412 field SCSIENACK 0x20 413 field HDMAEN 0x08 414 field HDMAENACK 0x08 415 field DIRECTION 0x04 416 field DIRECTIONACK 0x04 417 field FIFOFLUSH 0x02 418 field FIFOFLUSHACK 0x02 419 field DIRECTIONEN 0x01 420 } 421 422 /* 423 * Device Space Command 0 424 */ 425 register DSCOMMAND0 { 426 address 0x019 427 access_mode RW 428 modes M_CFG 429 field CACHETHEN 0x80 /* Cache Threshold enable */ 430 field DPARCKEN 0x40 /* Data Parity Check Enable */ 431 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 432 field EXTREQLCK 0x10 /* External Request Lock */ 433 field DISABLE_TWATE 0x02 /* Rev B or greater */ 434 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 435 } 436 437 /* 438 * Data FIFO Status 439 */ 440 register DFSTATUS { 441 address 0x01A 442 access_mode RO 443 modes M_DFF0, M_DFF1 444 field PRELOAD_AVAIL 0x80 445 field PKT_PRELOAD_AVAIL 0x40 446 field MREQPEND 0x10 447 field HDONE 0x08 448 field DFTHRESH 0x04 449 field FIFOFULL 0x02 450 field FIFOEMP 0x01 451 } 452 453 /* 454 * S/G Cache Pointer 455 */ 456 register SG_CACHE_PRE { 457 address 0x01B 458 access_mode WO 459 modes M_DFF0, M_DFF1 460 field SG_ADDR_MASK 0xf8 461 field ODD_SEG 0x04 462 field LAST_SEG 0x02 463 } 464 465 register SG_CACHE_SHADOW { 466 address 0x01B 467 access_mode RO 468 modes M_DFF0, M_DFF1 469 field SG_ADDR_MASK 0xf8 470 field ODD_SEG 0x04 471 field LAST_SEG 0x02 472 field LAST_SEG_DONE 0x01 473 } 474 475 /* 476 * Arbiter Control 477 */ 478 register ARBCTL { 479 address 0x01B 480 access_mode RW 481 modes M_CFG 482 field RESET_HARB 0x80 483 field RETRY_SWEN 0x08 484 field USE_TIME 0x07 485 } 486 487 /* 488 * Data Channel Host Address 489 */ 490 register HADDR { 491 address 0x070 492 access_mode RW 493 size 8 494 modes M_DFF0, M_DFF1 495 } 496 497 /* 498 * Host Overlay DMA Address 499 */ 500 register HODMAADR { 501 address 0x070 502 access_mode RW 503 size 8 504 modes M_SCSI 505 } 506 507 /* 508 * PCI PLL Delay. 509 */ 510 register PLLDELAY { 511 address 0x070 512 access_mode RW 513 size 1 514 modes M_CFG 515 field SPLIT_DROP_REQ 0x80 516 } 517 518 /* 519 * Data Channel Host Count 520 */ 521 register HCNT { 522 address 0x078 523 access_mode RW 524 size 3 525 modes M_DFF0, M_DFF1 526 } 527 528 /* 529 * Host Overlay DMA Count 530 */ 531 register HODMACNT { 532 address 0x078 533 access_mode RW 534 size 2 535 modes M_SCSI 536 } 537 538 /* 539 * Host Overlay DMA Enable 540 */ 541 register HODMAEN { 542 address 0x07A 543 access_mode RW 544 modes M_SCSI 545 } 546 547 /* 548 * Scatter/Gather Host Address 549 */ 550 register SGHADDR { 551 address 0x07C 552 access_mode RW 553 size 8 554 modes M_DFF0, M_DFF1 555 } 556 557 /* 558 * SCB Host Address 559 */ 560 register SCBHADDR { 561 address 0x07C 562 access_mode RW 563 size 8 564 modes M_CCHAN 565 } 566 567 /* 568 * Scatter/Gather Host Count 569 */ 570 register SGHCNT { 571 address 0x084 572 access_mode RW 573 modes M_DFF0, M_DFF1 574 } 575 576 /* 577 * SCB Host Count 578 */ 579 register SCBHCNT { 580 address 0x084 581 access_mode RW 582 modes M_CCHAN 583 } 584 585 /* 586 * Data FIFO Threshold 587 */ 588 register DFF_THRSH { 589 address 0x088 590 access_mode RW 591 modes M_CFG 592 field WR_DFTHRSH 0x70 { 593 WR_DFTHRSH_MIN, 594 WR_DFTHRSH_25, 595 WR_DFTHRSH_50, 596 WR_DFTHRSH_63, 597 WR_DFTHRSH_75, 598 WR_DFTHRSH_85, 599 WR_DFTHRSH_90, 600 WR_DFTHRSH_MAX 601 } 602 field RD_DFTHRSH 0x07 { 603 RD_DFTHRSH_MIN, 604 RD_DFTHRSH_25, 605 RD_DFTHRSH_50, 606 RD_DFTHRSH_63, 607 RD_DFTHRSH_75, 608 RD_DFTHRSH_85, 609 RD_DFTHRSH_90, 610 RD_DFTHRSH_MAX 611 } 612 } 613 614 /* 615 * ROM Address 616 */ 617 register ROMADDR { 618 address 0x08A 619 access_mode RW 620 size 3 621 } 622 623 /* 624 * ROM Control 625 */ 626 register ROMCNTRL { 627 address 0x08D 628 access_mode RW 629 field ROMOP 0xE0 630 field ROMSPD 0x18 631 field REPEAT 0x02 632 field RDY 0x01 633 } 634 635 /* 636 * ROM Data 637 */ 638 register ROMDATA { 639 address 0x08E 640 access_mode RW 641 } 642 643 /* 644 * Data Channel Receive Message 0 645 */ 646 register DCHRXMSG0 { 647 address 0x090 648 access_mode RO 649 modes M_DFF0, M_DFF1 650 field CDNUM 0xF8 651 field CFNUM 0x07 652 } 653 654 /* 655 * CMC Recieve Message 0 656 */ 657 register CMCRXMSG0 { 658 address 0x090 659 access_mode RO 660 modes M_CCHAN 661 field CDNUM 0xF8 662 field CFNUM 0x07 663 } 664 665 /* 666 * Overlay Recieve Message 0 667 */ 668 register OVLYRXMSG0 { 669 address 0x090 670 access_mode RO 671 modes M_SCSI 672 field CDNUM 0xF8 673 field CFNUM 0x07 674 } 675 676 /* 677 * Relaxed Order Enable 678 */ 679 register ROENABLE { 680 address 0x090 681 access_mode RW 682 modes M_CFG 683 field MSIROEN 0x20 684 field OVLYROEN 0x10 685 field CMCROEN 0x08 686 field SGROEN 0x04 687 field DCH1ROEN 0x02 688 field DCH0ROEN 0x01 689 } 690 691 /* 692 * Data Channel Receive Message 1 693 */ 694 register DCHRXMSG1 { 695 address 0x091 696 access_mode RO 697 modes M_DFF0, M_DFF1 698 field CBNUM 0xFF 699 } 700 701 /* 702 * CMC Recieve Message 1 703 */ 704 register CMCRXMSG1 { 705 address 0x091 706 access_mode RO 707 modes M_CCHAN 708 field CBNUM 0xFF 709 } 710 711 /* 712 * Overlay Recieve Message 1 713 */ 714 register OVLYRXMSG1 { 715 address 0x091 716 access_mode RO 717 modes M_SCSI 718 field CBNUM 0xFF 719 } 720 721 /* 722 * No Snoop Enable 723 */ 724 register NSENABLE { 725 address 0x091 726 access_mode RW 727 modes M_CFG 728 field MSINSEN 0x20 729 field OVLYNSEN 0x10 730 field CMCNSEN 0x08 731 field SGNSEN 0x04 732 field DCH1NSEN 0x02 733 field DCH0NSEN 0x01 734 } 735 736 /* 737 * Data Channel Receive Message 2 738 */ 739 register DCHRXMSG2 { 740 address 0x092 741 access_mode RO 742 modes M_DFF0, M_DFF1 743 field MINDEX 0xFF 744 } 745 746 /* 747 * CMC Recieve Message 2 748 */ 749 register CMCRXMSG2 { 750 address 0x092 751 access_mode RO 752 modes M_CCHAN 753 field MINDEX 0xFF 754 } 755 756 /* 757 * Overlay Recieve Message 2 758 */ 759 register OVLYRXMSG2 { 760 address 0x092 761 access_mode RO 762 modes M_SCSI 763 field MINDEX 0xFF 764 } 765 766 /* 767 * Outstanding Split Transactions 768 */ 769 register OST { 770 address 0x092 771 access_mode RW 772 modes M_CFG 773 } 774 775 /* 776 * Data Channel Receive Message 3 777 */ 778 register DCHRXMSG3 { 779 address 0x093 780 access_mode RO 781 modes M_DFF0, M_DFF1 782 field MCLASS 0x0F 783 } 784 785 /* 786 * CMC Recieve Message 3 787 */ 788 register CMCRXMSG3 { 789 address 0x093 790 access_mode RO 791 modes M_CCHAN 792 field MCLASS 0x0F 793 } 794 795 /* 796 * Overlay Recieve Message 3 797 */ 798 register OVLYRXMSG3 { 799 address 0x093 800 access_mode RO 801 modes M_SCSI 802 field MCLASS 0x0F 803 } 804 805 /* 806 * PCI-X Control 807 */ 808 register PCIXCTL { 809 address 0x093 810 access_mode RW 811 modes M_CFG 812 field SERRPULSE 0x80 813 field UNEXPSCIEN 0x20 814 field SPLTSMADIS 0x10 815 field SPLTSTADIS 0x08 816 field SRSPDPEEN 0x04 817 field TSCSERREN 0x02 818 field CMPABCDIS 0x01 819 } 820 821 /* 822 * CMC Sequencer Byte Count 823 */ 824 register CMCSEQBCNT { 825 address 0x094 826 access_mode RO 827 modes M_CCHAN 828 } 829 830 /* 831 * Overlay Sequencer Byte Count 832 */ 833 register OVLYSEQBCNT { 834 address 0x094 835 access_mode RO 836 modes M_SCSI 837 } 838 839 /* 840 * Data Channel Sequencer Byte Count 841 */ 842 register DCHSEQBCNT { 843 address 0x094 844 access_mode RO 845 size 2 846 modes M_DFF0, M_DFF1 847 } 848 849 /* 850 * Data Channel Split Status 0 851 */ 852 register DCHSPLTSTAT0 { 853 address 0x096 854 access_mode RW 855 modes M_DFF0, M_DFF1 856 field STAETERM 0x80 857 field SCBCERR 0x40 858 field SCADERR 0x20 859 field SCDATBUCKET 0x10 860 field CNTNOTCMPLT 0x08 861 field RXOVRUN 0x04 862 field RXSCEMSG 0x02 863 field RXSPLTRSP 0x01 864 } 865 866 /* 867 * CMC Split Status 0 868 */ 869 register CMCSPLTSTAT0 { 870 address 0x096 871 access_mode RW 872 modes M_CCHAN 873 field STAETERM 0x80 874 field SCBCERR 0x40 875 field SCADERR 0x20 876 field SCDATBUCKET 0x10 877 field CNTNOTCMPLT 0x08 878 field RXOVRUN 0x04 879 field RXSCEMSG 0x02 880 field RXSPLTRSP 0x01 881 } 882 883 /* 884 * Overlay Split Status 0 885 */ 886 register OVLYSPLTSTAT0 { 887 address 0x096 888 access_mode RW 889 modes M_SCSI 890 field STAETERM 0x80 891 field SCBCERR 0x40 892 field SCADERR 0x20 893 field SCDATBUCKET 0x10 894 field CNTNOTCMPLT 0x08 895 field RXOVRUN 0x04 896 field RXSCEMSG 0x02 897 field RXSPLTRSP 0x01 898 } 899 900 /* 901 * Data Channel Split Status 1 902 */ 903 register DCHSPLTSTAT1 { 904 address 0x097 905 access_mode RW 906 modes M_DFF0, M_DFF1 907 field RXDATABUCKET 0x01 908 } 909 910 /* 911 * CMC Split Status 1 912 */ 913 register CMCSPLTSTAT1 { 914 address 0x097 915 access_mode RW 916 modes M_CCHAN 917 field RXDATABUCKET 0x01 918 } 919 920 /* 921 * Overlay Split Status 1 922 */ 923 register OVLYSPLTSTAT1 { 924 address 0x097 925 access_mode RW 926 modes M_SCSI 927 field RXDATABUCKET 0x01 928 } 929 930 /* 931 * S/G Receive Message 0 932 */ 933 register SGRXMSG0 { 934 address 0x098 935 access_mode RO 936 modes M_DFF0, M_DFF1 937 field CDNUM 0xF8 938 field CFNUM 0x07 939 } 940 941 /* 942 * S/G Receive Message 1 943 */ 944 register SGRXMSG1 { 945 address 0x099 946 access_mode RO 947 modes M_DFF0, M_DFF1 948 field CBNUM 0xFF 949 } 950 951 /* 952 * S/G Receive Message 2 953 */ 954 register SGRXMSG2 { 955 address 0x09A 956 access_mode RO 957 modes M_DFF0, M_DFF1 958 field MINDEX 0xFF 959 } 960 961 /* 962 * S/G Receive Message 3 963 */ 964 register SGRXMSG3 { 965 address 0x09B 966 access_mode RO 967 modes M_DFF0, M_DFF1 968 field MCLASS 0x0F 969 } 970 971 /* 972 * Slave Split Out Address 0 973 */ 974 register SLVSPLTOUTADR0 { 975 address 0x098 976 access_mode RO 977 modes M_SCSI 978 field LOWER_ADDR 0x7F 979 } 980 981 /* 982 * Slave Split Out Address 1 983 */ 984 register SLVSPLTOUTADR1 { 985 address 0x099 986 access_mode RO 987 modes M_SCSI 988 field REQ_DNUM 0xF8 989 field REQ_FNUM 0x07 990 } 991 992 /* 993 * Slave Split Out Address 2 994 */ 995 register SLVSPLTOUTADR2 { 996 address 0x09A 997 access_mode RO 998 modes M_SCSI 999 field REQ_BNUM 0xFF 1000 } 1001 1002 /* 1003 * Slave Split Out Address 3 1004 */ 1005 register SLVSPLTOUTADR3 { 1006 address 0x09B 1007 access_mode RO 1008 modes M_SCSI 1009 field RLXORD 020 1010 field TAG_NUM 0x1F 1011 } 1012 1013 /* 1014 * SG Sequencer Byte Count 1015 */ 1016 register SGSEQBCNT { 1017 address 0x09C 1018 access_mode RO 1019 modes M_DFF0, M_DFF1 1020 } 1021 1022 /* 1023 * Slave Split Out Attribute 0 1024 */ 1025 register SLVSPLTOUTATTR0 { 1026 address 0x09C 1027 access_mode RO 1028 modes M_SCSI 1029 field LOWER_BCNT 0xFF 1030 } 1031 1032 /* 1033 * Slave Split Out Attribute 1 1034 */ 1035 register SLVSPLTOUTATTR1 { 1036 address 0x09D 1037 access_mode RO 1038 modes M_SCSI 1039 field CMPLT_DNUM 0xF8 1040 field CMPLT_FNUM 0x07 1041 } 1042 1043 /* 1044 * Slave Split Out Attribute 2 1045 */ 1046 register SLVSPLTOUTATTR2 { 1047 address 0x09E 1048 access_mode RO 1049 size 2 1050 modes M_SCSI 1051 field CMPLT_BNUM 0xFF 1052 } 1053 /* 1054 * S/G Split Status 0 1055 */ 1056 register SGSPLTSTAT0 { 1057 address 0x09E 1058 access_mode RW 1059 modes M_DFF0, M_DFF1 1060 field STAETERM 0x80 1061 field SCBCERR 0x40 1062 field SCADERR 0x20 1063 field SCDATBUCKET 0x10 1064 field CNTNOTCMPLT 0x08 1065 field RXOVRUN 0x04 1066 field RXSCEMSG 0x02 1067 field RXSPLTRSP 0x01 1068 } 1069 1070 /* 1071 * S/G Split Status 1 1072 */ 1073 register SGSPLTSTAT1 { 1074 address 0x09F 1075 access_mode RW 1076 modes M_DFF0, M_DFF1 1077 field RXDATABUCKET 0x01 1078 } 1079 1080 /* 1081 * Special Function 1082 */ 1083 register SFUNCT { 1084 address 0x09f 1085 access_mode RW 1086 modes M_CFG 1087 field TEST_GROUP 0xF0 1088 field TEST_NUM 0x0F 1089 } 1090 1091 /* 1092 * Data FIFO 0 PCI Status 1093 */ 1094 register DF0PCISTAT { 1095 address 0x0A0 1096 access_mode RW 1097 modes M_CFG 1098 field DPE 0x80 1099 field SSE 0x40 1100 field RMA 0x20 1101 field RTA 0x10 1102 field SCAAPERR 0x08 1103 field RDPERR 0x04 1104 field TWATERR 0x02 1105 field DPR 0x01 1106 } 1107 1108 /* 1109 * Data FIFO 1 PCI Status 1110 */ 1111 register DF1PCISTAT { 1112 address 0x0A1 1113 access_mode RW 1114 modes M_CFG 1115 field DPE 0x80 1116 field SSE 0x40 1117 field RMA 0x20 1118 field RTA 0x10 1119 field SCAAPERR 0x08 1120 field RDPERR 0x04 1121 field TWATERR 0x02 1122 field DPR 0x01 1123 } 1124 1125 /* 1126 * S/G PCI Status 1127 */ 1128 register SGPCISTAT { 1129 address 0x0A2 1130 access_mode RW 1131 modes M_CFG 1132 field DPE 0x80 1133 field SSE 0x40 1134 field RMA 0x20 1135 field RTA 0x10 1136 field SCAAPERR 0x08 1137 field RDPERR 0x04 1138 field DPR 0x01 1139 } 1140 1141 /* 1142 * CMC PCI Status 1143 */ 1144 register CMCPCISTAT { 1145 address 0x0A3 1146 access_mode RW 1147 modes M_CFG 1148 field DPE 0x80 1149 field SSE 0x40 1150 field RMA 0x20 1151 field RTA 0x10 1152 field SCAAPERR 0x08 1153 field RDPERR 0x04 1154 field TWATERR 0x02 1155 field DPR 0x01 1156 } 1157 1158 /* 1159 * Overlay PCI Status 1160 */ 1161 register OVLYPCISTAT { 1162 address 0x0A4 1163 access_mode RW 1164 modes M_CFG 1165 field DPE 0x80 1166 field SSE 0x40 1167 field RMA 0x20 1168 field RTA 0x10 1169 field SCAAPERR 0x08 1170 field RDPERR 0x04 1171 field DPR 0x01 1172 } 1173 1174 /* 1175 * PCI Status for MSI Master DMA Transfer 1176 */ 1177 register MSIPCISTAT { 1178 address 0x0A6 1179 access_mode RW 1180 modes M_CFG 1181 field SSE 0x40 1182 field RMA 0x20 1183 field RTA 0x10 1184 field CLRPENDMSI 0x08 1185 field TWATERR 0x02 1186 field DPR 0x01 1187 } 1188 1189 /* 1190 * PCI Status for Target 1191 */ 1192 register TARGPCISTAT { 1193 address 0x0A7 1194 access_mode RW 1195 modes M_CFG 1196 field DPE 0x80 1197 field SSE 0x40 1198 field STA 0x08 1199 field TWATERR 0x02 1200 } 1201 1202 /* 1203 * LQ Packet In 1204 * The last LQ Packet recieved 1205 */ 1206 register LQIN { 1207 address 0x020 1208 access_mode RW 1209 size 20 1210 modes M_DFF0, M_DFF1, M_SCSI 1211 } 1212 1213 /* 1214 * SCB Type Pointer 1215 * SCB offset for Target Mode SCB type information 1216 */ 1217 register TYPEPTR { 1218 address 0x020 1219 access_mode RW 1220 modes M_CFG 1221 } 1222 1223 /* 1224 * Queue Tag Pointer 1225 * SCB offset to the Two Byte tag identifier used for target mode. 1226 */ 1227 register TAGPTR { 1228 address 0x021 1229 access_mode RW 1230 modes M_CFG 1231 } 1232 1233 /* 1234 * Logical Unit Number Pointer 1235 * SCB offset to the LSB (little endian) of the lun field. 1236 */ 1237 register LUNPTR { 1238 address 0x022 1239 access_mode RW 1240 modes M_CFG 1241 } 1242 1243 /* 1244 * Data Length Pointer 1245 * SCB offset for the 4 byte data length field in target mode. 1246 */ 1247 register DATALENPTR { 1248 address 0x023 1249 access_mode RW 1250 modes M_CFG 1251 } 1252 1253 /* 1254 * Status Length Pointer 1255 * SCB offset to the two byte status field in target SCBs. 1256 */ 1257 register STATLENPTR { 1258 address 0x024 1259 access_mode RW 1260 modes M_CFG 1261 } 1262 1263 /* 1264 * Command Length Pointer 1265 * Scb offset for the CDB length field in initiator SCBs. 1266 */ 1267 register CMDLENPTR { 1268 address 0x025 1269 access_mode RW 1270 modes M_CFG 1271 } 1272 1273 /* 1274 * Task Attribute Pointer 1275 * Scb offset for the byte field specifying the attribute byte 1276 * to be used in command packets. 1277 */ 1278 register ATTRPTR { 1279 address 0x026 1280 access_mode RW 1281 modes M_CFG 1282 } 1283 1284 /* 1285 * Task Management Flags Pointer 1286 * Scb offset for the byte field specifying the attribute flags 1287 * byte to be used in command packets. 1288 */ 1289 register FLAGPTR { 1290 address 0x027 1291 access_mode RW 1292 modes M_CFG 1293 } 1294 1295 /* 1296 * Command Pointer 1297 * Scb offset for the first byte in the CDB for initiator SCBs. 1298 */ 1299 register CMDPTR { 1300 address 0x028 1301 access_mode RW 1302 modes M_CFG 1303 } 1304 1305 /* 1306 * Queue Next Pointer 1307 * Scb offset for the 2 byte "next scb link". 1308 */ 1309 register QNEXTPTR { 1310 address 0x029 1311 access_mode RW 1312 modes M_CFG 1313 } 1314 1315 /* 1316 * SCSI ID Pointer 1317 * Scb offset to the value to place in the SCSIID register 1318 * during target mode connections. 1319 */ 1320 register IDPTR { 1321 address 0x02A 1322 access_mode RW 1323 modes M_CFG 1324 } 1325 1326 /* 1327 * Command Aborted Byte Pointer 1328 * Offset to the SCB flags field that includes the 1329 * "SCB aborted" status bit. 1330 */ 1331 register ABRTBYTEPTR { 1332 address 0x02B 1333 access_mode RW 1334 modes M_CFG 1335 } 1336 1337 /* 1338 * Command Aborted Bit Pointer 1339 * Bit offset in the SCB flags field for "SCB aborted" status. 1340 */ 1341 register ABRTBITPTR { 1342 address 0x02C 1343 access_mode RW 1344 modes M_CFG 1345 } 1346 1347 /* 1348 * Rev B or greater. 1349 */ 1350 register MAXCMDBYTES { 1351 address 0x02D 1352 access_mode RW 1353 modes M_CFG 1354 } 1355 1356 /* 1357 * Rev B or greater. 1358 */ 1359 register MAXCMD2RCV { 1360 address 0x02E 1361 access_mode RW 1362 modes M_CFG 1363 } 1364 1365 /* 1366 * Rev B or greater. 1367 */ 1368 register SHORTTHRESH { 1369 address 0x02F 1370 access_mode RW 1371 modes M_CFG 1372 } 1373 1374 /* 1375 * Logical Unit Number Length 1376 * The length, in bytes, of the SCB lun field. 1377 */ 1378 register LUNLEN { 1379 address 0x030 1380 access_mode RW 1381 modes M_CFG 1382 } 1383 1384 /* 1385 * CDB Limit 1386 * The size, in bytes, of the embedded CDB field in initator SCBs. 1387 */ 1388 register CDBLIMIT { 1389 address 0x031 1390 access_mode RW 1391 modes M_CFG 1392 } 1393 1394 /* 1395 * Maximum Commands 1396 * The maximum number of commands to issue during a 1397 * single packetized connection. 1398 */ 1399 register MAXCMD { 1400 address 0x032 1401 access_mode RW 1402 modes M_CFG 1403 } 1404 1405 /* 1406 * Maximum Command Counter 1407 * The number of commands already sent during this connection 1408 */ 1409 register MAXCMDCNT { 1410 address 0x033 1411 access_mode RW 1412 modes M_CFG 1413 } 1414 1415 /* 1416 * LQ Packet Reserved Bytes 1417 * The bytes to be sent in the currently reserved fileds 1418 * of all LQ packets. 1419 */ 1420 register LQRSVD01 { 1421 address 0x034 1422 access_mode RW 1423 modes M_SCSI 1424 } 1425 register LQRSVD16 { 1426 address 0x035 1427 access_mode RW 1428 modes M_SCSI 1429 } 1430 register LQRSVD17 { 1431 address 0x036 1432 access_mode RW 1433 modes M_SCSI 1434 } 1435 1436 /* 1437 * Command Reserved 0 1438 * The byte to be sent for the reserved byte 0 of 1439 * outgoing command packets. 1440 */ 1441 register CMDRSVD0 { 1442 address 0x037 1443 access_mode RW 1444 modes M_CFG 1445 } 1446 1447 /* 1448 * LQ Manager Control 0 1449 */ 1450 register LQCTL0 { 1451 address 0x038 1452 access_mode RW 1453 modes M_CFG 1454 field LQITARGCLT 0xC0 1455 field LQIINITGCLT 0x30 1456 field LQ0TARGCLT 0x0C 1457 field LQ0INITGCLT 0x03 1458 } 1459 1460 /* 1461 * LQ Manager Control 1 1462 */ 1463 register LQCTL1 { 1464 address 0x038 1465 access_mode RW 1466 modes M_DFF0, M_DFF1, M_SCSI 1467 field PCI2PCI 0x04 1468 field SINGLECMD 0x02 1469 field ABORTPENDING 0x01 1470 } 1471 1472 /* 1473 * LQ Manager Control 2 1474 */ 1475 register LQCTL2 { 1476 address 0x039 1477 access_mode RW 1478 modes M_DFF0, M_DFF1, M_SCSI 1479 field LQIRETRY 0x80 1480 field LQICONTINUE 0x40 1481 field LQITOIDLE 0x20 1482 field LQIPAUSE 0x10 1483 field LQORETRY 0x08 1484 field LQOCONTINUE 0x04 1485 field LQOTOIDLE 0x02 1486 field LQOPAUSE 0x01 1487 } 1488 1489 /* 1490 * SCSI RAM BIST0 1491 */ 1492 register SCSBIST0 { 1493 address 0x039 1494 access_mode RW 1495 modes M_CFG 1496 field GSBISTERR 0x40 1497 field GSBISTDONE 0x20 1498 field GSBISTRUN 0x10 1499 field OSBISTERR 0x04 1500 field OSBISTDONE 0x02 1501 field OSBISTRUN 0x01 1502 } 1503 1504 /* 1505 * SCSI Sequence Control0 1506 */ 1507 register SCSISEQ0 { 1508 address 0x03A 1509 access_mode RW 1510 modes M_DFF0, M_DFF1, M_SCSI 1511 field TEMODEO 0x80 1512 field ENSELO 0x40 1513 field ENARBO 0x20 1514 field FORCEBUSFREE 0x10 1515 field SCSIRSTO 0x01 1516 } 1517 1518 /* 1519 * SCSI RAM BIST 1 1520 */ 1521 register SCSBIST1 { 1522 address 0x03A 1523 access_mode RW 1524 modes M_CFG 1525 field NTBISTERR 0x04 1526 field NTBISTDONE 0x02 1527 field NTBISTRUN 0x01 1528 } 1529 1530 /* 1531 * SCSI Sequence Control 1 1532 */ 1533 register SCSISEQ1 { 1534 address 0x03B 1535 access_mode RW 1536 modes M_DFF0, M_DFF1, M_SCSI 1537 field MANUALCTL 0x40 1538 field ENSELI 0x20 1539 field ENRSELI 0x10 1540 field MANUALP 0x0C 1541 field ENAUTOATNP 0x02 1542 field ALTSTIM 0x01 1543 } 1544 1545 /* 1546 * SCSI Transfer Control 0 1547 */ 1548 register SXFRCTL0 { 1549 address 0x03C 1550 access_mode RW 1551 modes M_SCSI 1552 field DFON 0x80 1553 field DFPEXP 0x40 1554 field BIOSCANCELEN 0x10 1555 field SPIOEN 0x08 1556 } 1557 1558 /* 1559 * SCSI Transfer Control 1 1560 */ 1561 register SXFRCTL1 { 1562 address 0x03D 1563 access_mode RW 1564 modes M_SCSI 1565 field BITBUCKET 0x80 1566 field ENSACHK 0x40 1567 field ENSPCHK 0x20 1568 field STIMESEL 0x18 1569 field ENSTIMER 0x04 1570 field ACTNEGEN 0x02 1571 field STPWEN 0x01 1572 } 1573 1574 /* 1575 * SCSI Transfer Control 2 1576 */ 1577 register SXFRCTL2 { 1578 address 0x03E 1579 access_mode RW 1580 modes M_SCSI 1581 field AUTORSTDIS 0x10 1582 field CMDDMAEN 0x08 1583 field ASU 0x07 1584 } 1585 1586 /* 1587 * SCSI Bus Initiator IDs 1588 * Bitmask of observed initiators on the bus. 1589 */ 1590 register BUSINITID { 1591 address 0x03C 1592 access_mode RW 1593 modes M_CFG 1594 size 2 1595 } 1596 1597 /* 1598 * Data Length Counters 1599 * Packet byte counter. 1600 */ 1601 register DLCOUNT { 1602 address 0x03C 1603 access_mode RW 1604 modes M_DFF0, M_DFF1 1605 size 3 1606 } 1607 1608 /* 1609 * Data FIFO Status 1610 */ 1611 register DFFSTAT { 1612 address 0x03F 1613 access_mode RW 1614 modes M_SCSI 1615 field FIFO1FREE 0x20 1616 field FIFO0FREE 0x10 1617 /* 1618 * On the B, this enum only works 1619 * in the read direction. For writes, 1620 * you must use the B version of the 1621 * CURRFIFO_0 definition which is defined 1622 * as a constant outside of this register 1623 * definition to avoid confusing the 1624 * register pretty printing code. 1625 */ 1626 enum CURRFIFO 0x03 { 1627 CURRFIFO_0, 1628 CURRFIFO_1, 1629 CURRFIFO_NONE 0x3 1630 } 1631 } 1632 1633 const B_CURRFIFO_0 0x2 1634 1635 /* 1636 * SCSI Bus Target IDs 1637 * Bitmask of observed targets on the bus. 1638 */ 1639 register BUSTARGID { 1640 address 0x03E 1641 access_mode RW 1642 modes M_CFG 1643 size 2 1644 } 1645 1646 /* 1647 * SCSI Control Signal Out 1648 */ 1649 register SCSISIGO { 1650 address 0x040 1651 access_mode RW 1652 modes M_DFF0, M_DFF1, M_SCSI 1653 field CDO 0x80 1654 field IOO 0x40 1655 field MSGO 0x20 1656 field ATNO 0x10 1657 field SELO 0x08 1658 field BSYO 0x04 1659 field REQO 0x02 1660 field ACKO 0x01 1661 /* 1662 * Possible phases to write into SCSISIG0 1663 */ 1664 enum PHASE_MASK CDO|IOO|MSGO { 1665 P_DATAOUT 0x0, 1666 P_DATAIN IOO, 1667 P_DATAOUT_DT P_DATAOUT|MSGO, 1668 P_DATAIN_DT P_DATAIN|MSGO, 1669 P_COMMAND CDO, 1670 P_MESGOUT CDO|MSGO, 1671 P_STATUS CDO|IOO, 1672 P_MESGIN CDO|IOO|MSGO 1673 } 1674 } 1675 1676 register SCSISIGI { 1677 address 0x041 1678 access_mode RO 1679 modes M_DFF0, M_DFF1, M_SCSI 1680 field CDI 0x80 1681 field IOI 0x40 1682 field MSGI 0x20 1683 field ATNI 0x10 1684 field SELI 0x08 1685 field BSYI 0x04 1686 field REQI 0x02 1687 field ACKI 0x01 1688 /* 1689 * Possible phases in SCSISIGI 1690 */ 1691 enum PHASE_MASK CDO|IOO|MSGO { 1692 P_DATAOUT 0x0, 1693 P_DATAIN IOO, 1694 P_DATAOUT_DT P_DATAOUT|MSGO, 1695 P_DATAIN_DT P_DATAIN|MSGO, 1696 P_COMMAND CDO, 1697 P_MESGOUT CDO|MSGO, 1698 P_STATUS CDO|IOO, 1699 P_MESGIN CDO|IOO|MSGO 1700 } 1701 } 1702 1703 /* 1704 * Multiple Target IDs 1705 * Bitmask of ids to respond as a target. 1706 */ 1707 register MULTARGID { 1708 address 0x040 1709 access_mode RW 1710 modes M_CFG 1711 size 2 1712 } 1713 1714 /* 1715 * SCSI Phase 1716 */ 1717 register SCSIPHASE { 1718 address 0x042 1719 access_mode RO 1720 modes M_DFF0, M_DFF1, M_SCSI 1721 field STATUS_PHASE 0x20 1722 field COMMAND_PHASE 0x10 1723 field MSG_IN_PHASE 0x08 1724 field MSG_OUT_PHASE 0x04 1725 field DATA_PHASE_MASK 0x03 { 1726 DATA_OUT_PHASE 0x01, 1727 DATA_IN_PHASE 0x02 1728 } 1729 } 1730 1731 /* 1732 * SCSI Data 0 Image 1733 */ 1734 register SCSIDAT0_IMG { 1735 address 0x043 1736 access_mode RW 1737 modes M_DFF0, M_DFF1, M_SCSI 1738 } 1739 1740 /* 1741 * SCSI Latched Data 1742 */ 1743 register SCSIDAT { 1744 address 0x044 1745 access_mode RW 1746 modes M_DFF0, M_DFF1, M_SCSI 1747 size 2 1748 } 1749 1750 /* 1751 * SCSI Data Bus 1752 */ 1753 register SCSIBUS { 1754 address 0x046 1755 access_mode RW 1756 modes M_DFF0, M_DFF1, M_SCSI 1757 size 2 1758 } 1759 1760 /* 1761 * Target ID In 1762 */ 1763 register TARGIDIN { 1764 address 0x048 1765 access_mode RO 1766 modes M_DFF0, M_DFF1, M_SCSI 1767 field CLKOUT 0x80 1768 field TARGID 0x0F 1769 } 1770 1771 /* 1772 * Selection/Reselection ID 1773 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1774 * device did not set its own ID. 1775 */ 1776 register SELID { 1777 address 0x049 1778 access_mode RW 1779 modes M_DFF0, M_DFF1, M_SCSI 1780 field SELID_MASK 0xf0 1781 field ONEBIT 0x08 1782 } 1783 1784 /* 1785 * SCSI Block Control 1786 * Controls Bus type and channel selection. SELWIDE allows for the 1787 * coexistence of 8bit and 16bit devices on a wide bus. 1788 */ 1789 register SBLKCTL { 1790 address 0x04A 1791 access_mode RW 1792 modes M_DFF0, M_DFF1, M_SCSI 1793 field DIAGLEDEN 0x80 1794 field DIAGLEDON 0x40 1795 field ENAB40 0x08 /* LVD transceiver active */ 1796 field ENAB20 0x04 /* SE/HVD transceiver active */ 1797 field SELWIDE 0x02 1798 } 1799 1800 /* 1801 * Option Mode 1802 */ 1803 register OPTIONMODE { 1804 address 0x04A 1805 access_mode RW 1806 modes M_CFG 1807 field BIOSCANCTL 0x80 1808 field AUTOACKEN 0x40 1809 field BIASCANCTL 0x20 1810 field BUSFREEREV 0x10 1811 field ENDGFORMCHK 0x04 1812 field AUTO_MSGOUT_DE 0x02 1813 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1814 } 1815 1816 /* 1817 * SCSI Status 0 1818 */ 1819 register SSTAT0 { 1820 address 0x04B 1821 access_mode RO 1822 modes M_DFF0, M_DFF1, M_SCSI 1823 field TARGET 0x80 /* Board acting as target */ 1824 field SELDO 0x40 /* Selection Done */ 1825 field SELDI 0x20 /* Board has been selected */ 1826 field SELINGO 0x10 /* Selection In Progress */ 1827 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1828 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1829 field SPIORDY 0x02 /* SCSI PIO Ready */ 1830 field ARBDO 0x01 /* Arbitration Done Out */ 1831 } 1832 1833 /* 1834 * Clear SCSI Interrupt 0 1835 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1836 */ 1837 register CLRSINT0 { 1838 address 0x04B 1839 access_mode WO 1840 modes M_DFF0, M_DFF1, M_SCSI 1841 field CLRSELDO 0x40 1842 field CLRSELDI 0x20 1843 field CLRSELINGO 0x10 1844 field CLRIOERR 0x08 1845 field CLROVERRUN 0x04 1846 field CLRSPIORDY 0x02 1847 field CLRARBDO 0x01 1848 } 1849 1850 /* 1851 * SCSI Interrupt Mode 0 1852 * Setting any bit will enable the corresponding function 1853 * in SIMODE0 to interrupt via the IRQ pin. 1854 */ 1855 register SIMODE0 { 1856 address 0x04B 1857 access_mode RW 1858 modes M_CFG 1859 field ENSELDO 0x40 1860 field ENSELDI 0x20 1861 field ENSELINGO 0x10 1862 field ENIOERR 0x08 1863 field ENOVERRUN 0x04 1864 field ENSPIORDY 0x02 1865 field ENARBDO 0x01 1866 } 1867 1868 /* 1869 * SCSI Status 1 1870 */ 1871 register SSTAT1 { 1872 address 0x04C 1873 access_mode RO 1874 modes M_DFF0, M_DFF1, M_SCSI 1875 field SELTO 0x80 1876 field ATNTARG 0x40 1877 field SCSIRSTI 0x20 1878 field PHASEMIS 0x10 1879 field BUSFREE 0x08 1880 field SCSIPERR 0x04 1881 field STRB2FAST 0x02 1882 field REQINIT 0x01 1883 } 1884 1885 /* 1886 * Clear SCSI Interrupt 1 1887 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1888 */ 1889 register CLRSINT1 { 1890 address 0x04C 1891 access_mode WO 1892 modes M_DFF0, M_DFF1, M_SCSI 1893 field CLRSELTIMEO 0x80 1894 field CLRATNO 0x40 1895 field CLRSCSIRSTI 0x20 1896 field CLRBUSFREE 0x08 1897 field CLRSCSIPERR 0x04 1898 field CLRSTRB2FAST 0x02 1899 field CLRREQINIT 0x01 1900 } 1901 1902 /* 1903 * SCSI Status 2 1904 */ 1905 register SSTAT2 { 1906 address 0x04d 1907 access_mode RO 1908 modes M_DFF0, M_DFF1, M_SCSI 1909 field BUSFREETIME 0xc0 { 1910 BUSFREE_LQO 0x40, 1911 BUSFREE_DFF0 0x80, 1912 BUSFREE_DFF1 0xC0 1913 } 1914 field NONPACKREQ 0x20 1915 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1916 field BSYX 0x08 /* Busy Expander */ 1917 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1918 field SDONE 0x02 /* Modes 0 and 1 only */ 1919 field DMADONE 0x01 /* Modes 0 and 1 only */ 1920 } 1921 1922 /* 1923 * Clear SCSI Interrupt 2 1924 */ 1925 register CLRSINT2 { 1926 address 0x04D 1927 access_mode WO 1928 modes M_DFF0, M_DFF1, M_SCSI 1929 field CLRNONPACKREQ 0x20 1930 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1931 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1932 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1933 } 1934 1935 /* 1936 * SCSI Interrupt Mode 2 1937 */ 1938 register SIMODE2 { 1939 address 0x04D 1940 access_mode RW 1941 modes M_CFG 1942 field ENWIDE_RES 0x04 1943 field ENSDONE 0x02 1944 field ENDMADONE 0x01 1945 } 1946 1947 /* 1948 * Physical Error Diagnosis 1949 */ 1950 register PERRDIAG { 1951 address 0x04E 1952 access_mode RO 1953 modes M_DFF0, M_DFF1, M_SCSI 1954 field HIZERO 0x80 1955 field HIPERR 0x40 1956 field PREVPHASE 0x20 1957 field PARITYERR 0x10 1958 field AIPERR 0x08 1959 field CRCERR 0x04 1960 field DGFORMERR 0x02 1961 field DTERR 0x01 1962 } 1963 1964 /* 1965 * LQI Manager Current State 1966 */ 1967 register LQISTATE { 1968 address 0x04E 1969 access_mode RO 1970 modes M_CFG 1971 } 1972 1973 /* 1974 * SCSI Offset Count 1975 */ 1976 register SOFFCNT { 1977 address 0x04F 1978 access_mode RO 1979 modes M_DFF0, M_DFF1, M_SCSI 1980 } 1981 1982 /* 1983 * LQO Manager Current State 1984 */ 1985 register LQOSTATE { 1986 address 0x04F 1987 access_mode RO 1988 modes M_CFG 1989 } 1990 1991 /* 1992 * LQI Manager Status 1993 */ 1994 register LQISTAT0 { 1995 address 0x050 1996 access_mode RO 1997 modes M_DFF0, M_DFF1, M_SCSI 1998 field LQIATNQAS 0x20 1999 field LQICRCT1 0x10 2000 field LQICRCT2 0x08 2001 field LQIBADLQT 0x04 2002 field LQIATNLQ 0x02 2003 field LQIATNCMD 0x01 2004 } 2005 2006 /* 2007 * Clear LQI Interrupts 0 2008 */ 2009 register CLRLQIINT0 { 2010 address 0x050 2011 access_mode WO 2012 modes M_DFF0, M_DFF1, M_SCSI 2013 field CLRLQIATNQAS 0x20 2014 field CLRLQICRCT1 0x10 2015 field CLRLQICRCT2 0x08 2016 field CLRLQIBADLQT 0x04 2017 field CLRLQIATNLQ 0x02 2018 field CLRLQIATNCMD 0x01 2019 } 2020 2021 /* 2022 * LQI Manager Interrupt Mode 0 2023 */ 2024 register LQIMODE0 { 2025 address 0x050 2026 access_mode RW 2027 modes M_CFG 2028 field ENLQIATNQASK 0x20 2029 field ENLQICRCT1 0x10 2030 field ENLQICRCT2 0x08 2031 field ENLQIBADLQT 0x04 2032 field ENLQIATNLQ 0x02 2033 field ENLQIATNCMD 0x01 2034 } 2035 2036 /* 2037 * LQI Manager Status 1 2038 */ 2039 register LQISTAT1 { 2040 address 0x051 2041 access_mode RO 2042 modes M_DFF0, M_DFF1, M_SCSI 2043 field LQIPHASE_LQ 0x80 2044 field LQIPHASE_NLQ 0x40 2045 field LQIABORT 0x20 2046 field LQICRCI_LQ 0x10 2047 field LQICRCI_NLQ 0x08 2048 field LQIBADLQI 0x04 2049 field LQIOVERI_LQ 0x02 2050 field LQIOVERI_NLQ 0x01 2051 } 2052 2053 /* 2054 * Clear LQI Manager Interrupts1 2055 */ 2056 register CLRLQIINT1 { 2057 address 0x051 2058 access_mode WO 2059 modes M_DFF0, M_DFF1, M_SCSI 2060 field CLRLQIPHASE_LQ 0x80 2061 field CLRLQIPHASE_NLQ 0x40 2062 field CLRLIQABORT 0x20 2063 field CLRLQICRCI_LQ 0x10 2064 field CLRLQICRCI_NLQ 0x08 2065 field CLRLQIBADLQI 0x04 2066 field CLRLQIOVERI_LQ 0x02 2067 field CLRLQIOVERI_NLQ 0x01 2068 } 2069 2070 /* 2071 * LQI Manager Interrupt Mode 1 2072 */ 2073 register LQIMODE1 { 2074 address 0x051 2075 access_mode RW 2076 modes M_CFG 2077 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2078 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2079 field ENLIQABORT 0x20 2080 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2081 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2082 field ENLQIBADLQI 0x04 2083 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2084 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 2085 } 2086 2087 /* 2088 * LQI Manager Status 2 2089 */ 2090 register LQISTAT2 { 2091 address 0x052 2092 access_mode RO 2093 modes M_DFF0, M_DFF1, M_SCSI 2094 field PACKETIZED 0x80 2095 field LQIPHASE_OUTPKT 0x40 2096 field LQIWORKONLQ 0x20 2097 field LQIWAITFIFO 0x10 2098 field LQISTOPPKT 0x08 2099 field LQISTOPLQ 0x04 2100 field LQISTOPCMD 0x02 2101 field LQIGSAVAIL 0x01 2102 } 2103 2104 /* 2105 * SCSI Status 3 2106 */ 2107 register SSTAT3 { 2108 address 0x053 2109 access_mode RO 2110 modes M_DFF0, M_DFF1, M_SCSI 2111 field NTRAMPERR 0x02 2112 field OSRAMPERR 0x01 2113 } 2114 2115 /* 2116 * Clear SCSI Status 3 2117 */ 2118 register CLRSINT3 { 2119 address 0x053 2120 access_mode WO 2121 modes M_DFF0, M_DFF1, M_SCSI 2122 field CLRNTRAMPERR 0x02 2123 field CLROSRAMPERR 0x01 2124 } 2125 2126 /* 2127 * SCSI Interrupt Mode 3 2128 */ 2129 register SIMODE3 { 2130 address 0x053 2131 access_mode RW 2132 modes M_CFG 2133 field ENNTRAMPERR 0x02 2134 field ENOSRAMPERR 0x01 2135 } 2136 2137 /* 2138 * LQO Manager Status 0 2139 */ 2140 register LQOSTAT0 { 2141 address 0x054 2142 access_mode RO 2143 modes M_DFF0, M_DFF1, M_SCSI 2144 field LQOTARGSCBPERR 0x10 2145 field LQOSTOPT2 0x08 2146 field LQOATNLQ 0x04 2147 field LQOATNPKT 0x02 2148 field LQOTCRC 0x01 2149 } 2150 2151 /* 2152 * Clear LQO Manager interrupt 0 2153 */ 2154 register CLRLQOINT0 { 2155 address 0x054 2156 access_mode WO 2157 modes M_DFF0, M_DFF1, M_SCSI 2158 field CLRLQOTARGSCBPERR 0x10 2159 field CLRLQOSTOPT2 0x08 2160 field CLRLQOATNLQ 0x04 2161 field CLRLQOATNPKT 0x02 2162 field CLRLQOTCRC 0x01 2163 } 2164 2165 /* 2166 * LQO Manager Interrupt Mode 0 2167 */ 2168 register LQOMODE0 { 2169 address 0x054 2170 access_mode RW 2171 modes M_CFG 2172 field ENLQOTARGSCBPERR 0x10 2173 field ENLQOSTOPT2 0x08 2174 field ENLQOATNLQ 0x04 2175 field ENLQOATNPKT 0x02 2176 field ENLQOTCRC 0x01 2177 } 2178 2179 /* 2180 * LQO Manager Status 1 2181 */ 2182 register LQOSTAT1 { 2183 address 0x055 2184 access_mode RO 2185 modes M_DFF0, M_DFF1, M_SCSI 2186 field LQOINITSCBPERR 0x10 2187 field LQOSTOPI2 0x08 2188 field LQOBADQAS 0x04 2189 field LQOBUSFREE 0x02 2190 field LQOPHACHGINPKT 0x01 2191 } 2192 2193 /* 2194 * Clear LOQ Interrupt 1 2195 */ 2196 register CLRLQOINT1 { 2197 address 0x055 2198 access_mode WO 2199 modes M_DFF0, M_DFF1, M_SCSI 2200 field CLRLQOINITSCBPERR 0x10 2201 field CLRLQOSTOPI2 0x08 2202 field CLRLQOBADQAS 0x04 2203 field CLRLQOBUSFREE 0x02 2204 field CLRLQOPHACHGINPKT 0x01 2205 } 2206 2207 /* 2208 * LQO Manager Interrupt Mode 1 2209 */ 2210 register LQOMODE1 { 2211 address 0x055 2212 access_mode RW 2213 modes M_CFG 2214 field ENLQOINITSCBPERR 0x10 2215 field ENLQOSTOPI2 0x08 2216 field ENLQOBADQAS 0x04 2217 field ENLQOBUSFREE 0x02 2218 field ENLQOPHACHGINPKT 0x01 2219 } 2220 2221 /* 2222 * LQO Manager Status 2 2223 */ 2224 register LQOSTAT2 { 2225 address 0x056 2226 access_mode RO 2227 modes M_DFF0, M_DFF1, M_SCSI 2228 field LQOPKT 0xE0 2229 field LQOWAITFIFO 0x10 2230 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2231 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2232 } 2233 2234 /* 2235 * Output Synchronizer Space Count 2236 */ 2237 register OS_SPACE_CNT { 2238 address 0x056 2239 access_mode RO 2240 modes M_CFG 2241 } 2242 2243 /* 2244 * SCSI Interrupt Mode 1 2245 * Setting any bit will enable the corresponding function 2246 * in SIMODE1 to interrupt via the IRQ pin. 2247 */ 2248 register SIMODE1 { 2249 address 0x057 2250 access_mode RW 2251 modes M_DFF0, M_DFF1, M_SCSI 2252 field ENSELTIMO 0x80 2253 field ENATNTARG 0x40 2254 field ENSCSIRST 0x20 2255 field ENPHASEMIS 0x10 2256 field ENBUSFREE 0x08 2257 field ENSCSIPERR 0x04 2258 field ENSTRB2FAST 0x02 2259 field ENREQINIT 0x01 2260 } 2261 2262 /* 2263 * Good Status FIFO 2264 */ 2265 register GSFIFO { 2266 address 0x058 2267 access_mode RO 2268 size 2 2269 modes M_DFF0, M_DFF1, M_SCSI 2270 } 2271 2272 /* 2273 * Data FIFO SCSI Transfer Control 2274 */ 2275 register DFFSXFRCTL { 2276 address 0x05A 2277 access_mode RW 2278 modes M_DFF0, M_DFF1 2279 field DFFBITBUCKET 0x08 2280 field CLRSHCNT 0x04 2281 field CLRCHN 0x02 2282 field RSTCHN 0x01 2283 } 2284 2285 /* 2286 * Next SCSI Control Block 2287 */ 2288 register NEXTSCB { 2289 address 0x05A 2290 access_mode RW 2291 size 2 2292 modes M_SCSI 2293 } 2294 2295 /* Rev B only. */ 2296 register LQOSCSCTL { 2297 address 0x05A 2298 access_mode RW 2299 size 1 2300 modes M_CFG 2301 field LQOH2A_VERSION 0x80 2302 field LQONOCHKOVER 0x01 2303 } 2304 2305 /* 2306 * SEQ Interrupts 2307 */ 2308 register SEQINTSRC { 2309 address 0x05B 2310 access_mode RO 2311 modes M_DFF0, M_DFF1 2312 field CTXTDONE 0x40 2313 field SAVEPTRS 0x20 2314 field CFG4DATA 0x10 2315 field CFG4ISTAT 0x08 2316 field CFG4TSTAT 0x04 2317 field CFG4ICMD 0x02 2318 field CFG4TCMD 0x01 2319 } 2320 2321 /* 2322 * Clear Arp Interrupts 2323 */ 2324 register CLRSEQINTSRC { 2325 address 0x05B 2326 access_mode WO 2327 modes M_DFF0, M_DFF1 2328 field CLRCTXTDONE 0x40 2329 field CLRSAVEPTRS 0x20 2330 field CLRCFG4DATA 0x10 2331 field CLRCFG4ISTAT 0x08 2332 field CLRCFG4TSTAT 0x04 2333 field CLRCFG4ICMD 0x02 2334 field CLRCFG4TCMD 0x01 2335 } 2336 2337 /* 2338 * SEQ Interrupt Enabled (Shared) 2339 */ 2340 register SEQIMODE { 2341 address 0x05C 2342 access_mode RW 2343 modes M_DFF0, M_DFF1 2344 field ENCTXTDONE 0x40 2345 field ENSAVEPTRS 0x20 2346 field ENCFG4DATA 0x10 2347 field ENCFG4ISTAT 0x08 2348 field ENCFG4TSTAT 0x04 2349 field ENCFG4ICMD 0x02 2350 field ENCFG4TCMD 0x01 2351 } 2352 2353 /* 2354 * Current SCSI Control Block 2355 */ 2356 register CURRSCB { 2357 address 0x05C 2358 access_mode RW 2359 size 2 2360 modes M_SCSI 2361 } 2362 2363 /* 2364 * Data FIFO Status 2365 */ 2366 register MDFFSTAT { 2367 address 0x05D 2368 access_mode RO 2369 modes M_DFF0, M_DFF1 2370 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2371 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2372 field LASTSDONE 0x10 2373 field SHVALID 0x08 2374 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2375 field DATAINFIFO 0x02 2376 field FIFOFREE 0x01 2377 } 2378 2379 /* 2380 * CRC Control 2381 */ 2382 register CRCCONTROL { 2383 address 0x05d 2384 access_mode RW 2385 modes M_CFG 2386 field CRCVALCHKEN 0x40 2387 } 2388 2389 /* 2390 * SCSI Test Control 2391 */ 2392 register SCSITEST { 2393 address 0x05E 2394 access_mode RW 2395 modes M_CFG 2396 field CNTRTEST 0x08 2397 field SEL_TXPLL_DEBUG 0x04 2398 } 2399 2400 /* 2401 * Data FIFO Queue Tag 2402 */ 2403 register DFFTAG { 2404 address 0x05E 2405 access_mode RW 2406 size 2 2407 modes M_DFF0, M_DFF1 2408 } 2409 2410 /* 2411 * Last SCSI Control Block 2412 */ 2413 register LASTSCB { 2414 address 0x05E 2415 access_mode RW 2416 size 2 2417 modes M_SCSI 2418 } 2419 2420 /* 2421 * SCSI I/O Cell Power-down Control 2422 */ 2423 register IOPDNCTL { 2424 address 0x05F 2425 access_mode RW 2426 modes M_CFG 2427 field DISABLE_OE 0x80 2428 field PDN_IDIST 0x04 2429 field PDN_DIFFSENSE 0x01 2430 } 2431 2432 /* 2433 * Shaddow Host Address. 2434 */ 2435 register SHADDR { 2436 address 0x060 2437 access_mode RO 2438 size 8 2439 modes M_DFF0, M_DFF1 2440 } 2441 2442 /* 2443 * Data Group CRC Interval. 2444 */ 2445 register DGRPCRCI { 2446 address 0x060 2447 access_mode RW 2448 size 2 2449 modes M_CFG 2450 } 2451 2452 /* 2453 * Data Transfer Negotiation Address 2454 */ 2455 register NEGOADDR { 2456 address 0x060 2457 access_mode RW 2458 modes M_SCSI 2459 } 2460 2461 /* 2462 * Data Transfer Negotiation Data - Period Byte 2463 */ 2464 register NEGPERIOD { 2465 address 0x061 2466 access_mode RW 2467 modes M_SCSI 2468 } 2469 2470 /* 2471 * Packetized CRC Interval 2472 */ 2473 register PACKCRCI { 2474 address 0x062 2475 access_mode RW 2476 size 2 2477 modes M_CFG 2478 } 2479 2480 /* 2481 * Data Transfer Negotiation Data - Offset Byte 2482 */ 2483 register NEGOFFSET { 2484 address 0x062 2485 access_mode RW 2486 modes M_SCSI 2487 } 2488 2489 /* 2490 * Data Transfer Negotiation Data - PPR Options 2491 */ 2492 register NEGPPROPTS { 2493 address 0x063 2494 access_mode RW 2495 modes M_SCSI 2496 field PPROPT_PACE 0x08 2497 field PPROPT_QAS 0x04 2498 field PPROPT_DT 0x02 2499 field PPROPT_IUT 0x01 2500 } 2501 2502 /* 2503 * Data Transfer Negotiation Data - Connection Options 2504 */ 2505 register NEGCONOPTS { 2506 address 0x064 2507 access_mode RW 2508 modes M_SCSI 2509 field ENSNAPSHOT 0x40 2510 field RTI_WRTDIS 0x20 2511 field RTI_OVRDTRN 0x10 2512 field ENSLOWCRC 0x08 2513 field ENAUTOATNI 0x04 2514 field ENAUTOATNO 0x02 2515 field WIDEXFER 0x01 2516 } 2517 2518 /* 2519 * Negotiation Table Annex Column Index. 2520 */ 2521 register ANNEXCOL { 2522 address 0x065 2523 access_mode RW 2524 modes M_SCSI 2525 } 2526 2527 register SCSCHKN { 2528 address 0x066 2529 access_mode RW 2530 modes M_CFG 2531 field STSELSKIDDIS 0x40 2532 field CURRFIFODEF 0x20 2533 field WIDERESEN 0x10 2534 field SDONEMSKDIS 0x08 2535 field DFFACTCLR 0x04 2536 field SHVALIDSTDIS 0x02 2537 field LSTSGCLRDIS 0x01 2538 } 2539 2540 const AHD_ANNEXCOL_PER_DEV0 4 2541 const AHD_NUM_PER_DEV_ANNEXCOLS 4 2542 const AHD_ANNEXCOL_PRECOMP_SLEW 4 2543 const AHD_PRECOMP_MASK 0x07 2544 const AHD_PRECOMP_SHIFT 0 2545 const AHD_PRECOMP_CUTBACK_17 0x04 2546 const AHD_PRECOMP_CUTBACK_29 0x06 2547 const AHD_PRECOMP_CUTBACK_37 0x07 2548 const AHD_SLEWRATE_MASK 0x78 2549 const AHD_SLEWRATE_SHIFT 3 2550 /* 2551 * Rev A has only a single bit (high bit of field) of slew adjustment. 2552 * Rev B has 4 bits. The current default happens to be the same for both. 2553 */ 2554 const AHD_SLEWRATE_DEF_REVA 0x08 2555 const AHD_SLEWRATE_DEF_REVB 0x08 2556 2557 /* Rev A does not have any amplitude setting. */ 2558 const AHD_ANNEXCOL_AMPLITUDE 6 2559 const AHD_AMPLITUDE_MASK 0x7 2560 const AHD_AMPLITUDE_SHIFT 0 2561 const AHD_AMPLITUDE_DEF 0x7 2562 2563 /* 2564 * Negotiation Table Annex Data Port. 2565 */ 2566 register ANNEXDAT { 2567 address 0x066 2568 access_mode RW 2569 modes M_SCSI 2570 } 2571 2572 /* 2573 * Initiator's Own Id. 2574 * The SCSI ID to use for Selection Out and seen during a reselection.. 2575 */ 2576 register IOWNID { 2577 address 0x067 2578 access_mode RW 2579 modes M_SCSI 2580 } 2581 2582 /* 2583 * 960MHz Phase-Locked Loop Control 0 2584 */ 2585 register PLL960CTL0 { 2586 address 0x068 2587 access_mode RW 2588 modes M_CFG 2589 field PLL_VCOSEL 0x80 2590 field PLL_PWDN 0x40 2591 field PLL_NS 0x30 2592 field PLL_ENLUD 0x08 2593 field PLL_ENLPF 0x04 2594 field PLL_DLPF 0x02 2595 field PLL_ENFBM 0x01 2596 } 2597 2598 /* 2599 * Target Own Id 2600 */ 2601 register TOWNID { 2602 address 0x069 2603 access_mode RW 2604 modes M_SCSI 2605 } 2606 2607 /* 2608 * 960MHz Phase-Locked Loop Control 1 2609 */ 2610 register PLL960CTL1 { 2611 address 0x069 2612 access_mode RW 2613 modes M_CFG 2614 field PLL_CNTEN 0x80 2615 field PLL_CNTCLR 0x40 2616 field PLL_RST 0x01 2617 } 2618 2619 /* 2620 * Expander Signature 2621 */ 2622 register XSIG { 2623 address 0x06A 2624 access_mode RW 2625 modes M_SCSI 2626 } 2627 2628 /* 2629 * Shadow Byte Count 2630 */ 2631 register SHCNT { 2632 address 0x068 2633 access_mode RW 2634 size 3 2635 modes M_DFF0, M_DFF1 2636 } 2637 2638 /* 2639 * Selection Out ID 2640 */ 2641 register SELOID { 2642 address 0x06B 2643 access_mode RW 2644 modes M_SCSI 2645 } 2646 2647 /* 2648 * 960-MHz Phase-Locked Loop Test Count 2649 */ 2650 register PLL960CNT0 { 2651 address 0x06A 2652 access_mode RO 2653 size 2 2654 modes M_CFG 2655 } 2656 2657 /* 2658 * 400-MHz Phase-Locked Loop Control 0 2659 */ 2660 register PLL400CTL0 { 2661 address 0x06C 2662 access_mode RW 2663 modes M_CFG 2664 field PLL_VCOSEL 0x80 2665 field PLL_PWDN 0x40 2666 field PLL_NS 0x30 2667 field PLL_ENLUD 0x08 2668 field PLL_ENLPF 0x04 2669 field PLL_DLPF 0x02 2670 field PLL_ENFBM 0x01 2671 } 2672 2673 /* 2674 * Arbitration Fairness 2675 */ 2676 register FAIRNESS { 2677 address 0x06C 2678 access_mode RW 2679 size 2 2680 modes M_SCSI 2681 } 2682 2683 /* 2684 * 400-MHz Phase-Locked Loop Control 1 2685 */ 2686 register PLL400CTL1 { 2687 address 0x06D 2688 access_mode RW 2689 modes M_CFG 2690 field PLL_CNTEN 0x80 2691 field PLL_CNTCLR 0x40 2692 field PLL_RST 0x01 2693 } 2694 2695 /* 2696 * Arbitration Unfairness 2697 */ 2698 register UNFAIRNESS { 2699 address 0x06E 2700 access_mode RW 2701 size 2 2702 modes M_SCSI 2703 } 2704 2705 /* 2706 * 400-MHz Phase-Locked Loop Test Count 2707 */ 2708 register PLL400CNT0 { 2709 address 0x06E 2710 access_mode RO 2711 size 2 2712 modes M_CFG 2713 } 2714 2715 /* 2716 * SCB Page Pointer 2717 */ 2718 register SCBPTR { 2719 address 0x0A8 2720 access_mode RW 2721 size 2 2722 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2723 } 2724 2725 /* 2726 * CMC SCB Array Count 2727 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2728 * Transfers must be 8byte aligned and sized. 2729 */ 2730 register CCSCBACNT { 2731 address 0x0AB 2732 access_mode RW 2733 modes M_CCHAN 2734 } 2735 2736 /* 2737 * SCB Autopointer 2738 * SCB-Next Address Snooping logic. When an SCB is transferred to 2739 * the card, the next SCB address to be used by the CMC array can 2740 * be autoloaded from that transfer. 2741 */ 2742 register SCBAUTOPTR { 2743 address 0x0AB 2744 access_mode RW 2745 modes M_CFG 2746 field AUSCBPTR_EN 0x80 2747 field SCBPTR_ADDR 0x38 2748 field SCBPTR_OFF 0x07 2749 } 2750 2751 /* 2752 * CMC SG Ram Address Pointer 2753 */ 2754 register CCSGADDR { 2755 address 0x0AC 2756 access_mode RW 2757 modes M_DFF0, M_DFF1 2758 } 2759 2760 /* 2761 * CMC SCB RAM Address Pointer 2762 */ 2763 register CCSCBADDR { 2764 address 0x0AC 2765 access_mode RW 2766 modes M_CCHAN 2767 } 2768 2769 /* 2770 * CMC SCB Ram Back-up Address Pointer 2771 * Indicates the true stop location of transfers halted prior 2772 * to SCBHCNT going to 0. 2773 */ 2774 register CCSCBADR_BK { 2775 address 0x0AC 2776 access_mode RO 2777 modes M_CFG 2778 } 2779 2780 /* 2781 * CMC SG Control 2782 */ 2783 register CCSGCTL { 2784 address 0x0AD 2785 access_mode RW 2786 modes M_DFF0, M_DFF1 2787 field CCSGDONE 0x80 2788 field SG_CACHE_AVAIL 0x10 2789 field CCSGENACK 0x08 2790 mask CCSGEN 0x0C 2791 field SG_FETCH_REQ 0x02 2792 field CCSGRESET 0x01 2793 } 2794 2795 /* 2796 * CMD SCB Control 2797 */ 2798 register CCSCBCTL { 2799 address 0x0AD 2800 access_mode RW 2801 modes M_CCHAN 2802 field CCSCBDONE 0x80 2803 field ARRDONE 0x40 2804 field CCARREN 0x10 2805 field CCSCBEN 0x08 2806 field CCSCBDIR 0x04 2807 field CCSCBRESET 0x01 2808 } 2809 2810 /* 2811 * CMC Ram BIST 2812 */ 2813 register CMC_RAMBIST { 2814 address 0x0AD 2815 access_mode RW 2816 modes M_CFG 2817 field SG_ELEMENT_SIZE 0x80 2818 field SCBRAMBIST_FAIL 0x40 2819 field SG_BIST_FAIL 0x20 2820 field SG_BIST_EN 0x10 2821 field CMC_BUFFER_BIST_FAIL 0x02 2822 field CMC_BUFFER_BIST_EN 0x01 2823 } 2824 2825 /* 2826 * CMC SG RAM Data Port 2827 */ 2828 register CCSGRAM { 2829 address 0x0B0 2830 access_mode RW 2831 modes M_DFF0, M_DFF1 2832 } 2833 2834 /* 2835 * CMC SCB RAM Data Port 2836 */ 2837 register CCSCBRAM { 2838 address 0x0B0 2839 access_mode RW 2840 modes M_CCHAN 2841 } 2842 2843 /* 2844 * Flex DMA Address. 2845 */ 2846 register FLEXADR { 2847 address 0x0B0 2848 access_mode RW 2849 size 3 2850 modes M_SCSI 2851 } 2852 2853 /* 2854 * Flex DMA Byte Count 2855 */ 2856 register FLEXCNT { 2857 address 0x0B3 2858 access_mode RW 2859 size 2 2860 modes M_SCSI 2861 } 2862 2863 /* 2864 * Flex DMA Status 2865 */ 2866 register FLEXDMASTAT { 2867 address 0x0B5 2868 access_mode RW 2869 modes M_SCSI 2870 field FLEXDMAERR 0x02 2871 field FLEXDMADONE 0x01 2872 } 2873 2874 /* 2875 * Flex DMA Data Port 2876 */ 2877 register FLEXDATA { 2878 address 0x0B6 2879 access_mode RW 2880 modes M_SCSI 2881 } 2882 2883 /* 2884 * Board Data 2885 */ 2886 register BRDDAT { 2887 address 0x0B8 2888 access_mode RW 2889 modes M_SCSI 2890 } 2891 2892 /* 2893 * Board Control 2894 */ 2895 register BRDCTL { 2896 address 0x0B9 2897 access_mode RW 2898 modes M_SCSI 2899 field FLXARBACK 0x80 2900 field FLXARBREQ 0x40 2901 field BRDADDR 0x38 2902 field BRDEN 0x04 2903 field BRDRW 0x02 2904 field BRDSTB 0x01 2905 } 2906 2907 /* 2908 * Serial EEPROM Address 2909 */ 2910 register SEEADR { 2911 address 0x0BA 2912 access_mode RW 2913 modes M_SCSI 2914 } 2915 2916 /* 2917 * Serial EEPROM Data 2918 */ 2919 register SEEDAT { 2920 address 0x0BC 2921 access_mode RW 2922 size 2 2923 modes M_SCSI 2924 } 2925 2926 /* 2927 * Serial EEPROM Status 2928 */ 2929 register SEESTAT { 2930 address 0x0BE 2931 access_mode RO 2932 modes M_SCSI 2933 field INIT_DONE 0x80 2934 field SEEOPCODE 0x70 2935 field LDALTID_L 0x08 2936 field SEEARBACK 0x04 2937 field SEEBUSY 0x02 2938 field SEESTART 0x01 2939 } 2940 2941 /* 2942 * Serial EEPROM Control 2943 */ 2944 register SEECTL { 2945 address 0x0BE 2946 access_mode RW 2947 modes M_SCSI 2948 field SEEOPCODE 0x70 { 2949 SEEOP_ERASE 0x70, 2950 SEEOP_READ 0x60, 2951 SEEOP_WRITE 0x50, 2952 /* 2953 * The following four commands use special 2954 * addresses for differentiation. 2955 */ 2956 SEEOP_ERAL 0x40 2957 } 2958 mask SEEOP_EWEN 0x40 2959 mask SEEOP_WALL 0x40 2960 mask SEEOP_EWDS 0x40 2961 field SEERST 0x02 2962 field SEESTART 0x01 2963 } 2964 2965 const SEEOP_ERAL_ADDR 0x80 2966 const SEEOP_EWEN_ADDR 0xC0 2967 const SEEOP_WRAL_ADDR 0x40 2968 const SEEOP_EWDS_ADDR 0x00 2969 2970 /* 2971 * SCB Counter 2972 */ 2973 register SCBCNT { 2974 address 0x0BF 2975 access_mode RW 2976 modes M_SCSI 2977 } 2978 2979 /* 2980 * Data FIFO Write Address 2981 * Pointer to the next QWD location to be written to the data FIFO. 2982 */ 2983 register DFWADDR { 2984 address 0x0C0 2985 access_mode RW 2986 size 2 2987 modes M_DFF0, M_DFF1 2988 } 2989 2990 /* 2991 * DSP Filter Control 2992 */ 2993 register DSPFLTRCTL { 2994 address 0x0C0 2995 access_mode RW 2996 modes M_CFG 2997 field FLTRDISABLE 0x20 2998 field EDGESENSE 0x10 2999 field DSPFCNTSEL 0x0F 3000 } 3001 3002 /* 3003 * DSP Data Channel Control 3004 */ 3005 register DSPDATACTL { 3006 address 0x0C1 3007 access_mode RW 3008 modes M_CFG 3009 field BYPASSENAB 0x80 3010 field DESQDIS 0x10 3011 field RCVROFFSTDIS 0x04 3012 field XMITOFFSTDIS 0x02 3013 } 3014 3015 /* 3016 * Data FIFO Read Address 3017 * Pointer to the next QWD location to be read from the data FIFO. 3018 */ 3019 register DFRADDR { 3020 address 0x0C2 3021 access_mode RW 3022 size 2 3023 modes M_DFF0, M_DFF1 3024 } 3025 3026 /* 3027 * DSP REQ Control 3028 */ 3029 register DSPREQCTL { 3030 address 0x0C2 3031 access_mode RW 3032 modes M_CFG 3033 field MANREQCTL 0xC0 3034 field MANREQDLY 0x3F 3035 } 3036 3037 /* 3038 * DSP ACK Control 3039 */ 3040 register DSPACKCTL { 3041 address 0x0C3 3042 access_mode RW 3043 modes M_CFG 3044 field MANACKCTL 0xC0 3045 field MANACKDLY 0x3F 3046 } 3047 3048 /* 3049 * Data FIFO Data 3050 * Read/Write byte port into the data FIFO. The read and write 3051 * FIFO pointers increment with each read and write respectively 3052 * to this port. 3053 */ 3054 register DFDAT { 3055 address 0x0C4 3056 access_mode RW 3057 modes M_DFF0, M_DFF1 3058 } 3059 3060 /* 3061 * DSP Channel Select 3062 */ 3063 register DSPSELECT { 3064 address 0x0C4 3065 access_mode RW 3066 modes M_CFG 3067 field AUTOINCEN 0x80 3068 field DSPSEL 0x1F 3069 } 3070 3071 const NUMDSPS 0x14 3072 3073 /* 3074 * Write Bias Control 3075 */ 3076 register WRTBIASCTL { 3077 address 0x0C5 3078 access_mode WO 3079 modes M_CFG 3080 field AUTOXBCDIS 0x80 3081 field XMITMANVAL 0x3F 3082 } 3083 3084 /* 3085 * Currently the WRTBIASCTL is the same as the default. 3086 */ 3087 const WRTBIASCTL_HP_DEFAULT 0x0 3088 3089 /* 3090 * Receiver Bias Control 3091 */ 3092 register RCVRBIOSCTL { 3093 address 0x0C6 3094 access_mode WO 3095 modes M_CFG 3096 field AUTORBCDIS 0x80 3097 field RCVRMANVAL 0x3F 3098 } 3099 3100 /* 3101 * Write Bias Calculator 3102 */ 3103 register WRTBIASCALC { 3104 address 0x0C7 3105 access_mode RO 3106 modes M_CFG 3107 } 3108 3109 /* 3110 * Data FIFO Pointers 3111 * Contains the byte offset from DFWADDR and DWRADDR to the current 3112 * FIFO write/read locations. 3113 */ 3114 register DFPTRS { 3115 address 0x0C8 3116 access_mode RW 3117 modes M_DFF0, M_DFF1 3118 } 3119 3120 /* 3121 * Receiver Bias Calculator 3122 */ 3123 register RCVRBIASCALC { 3124 address 0x0C8 3125 access_mode RO 3126 modes M_CFG 3127 } 3128 3129 /* 3130 * Data FIFO Backup Read Pointer 3131 * Contains the data FIFO address to be restored if the last 3132 * data accessed from the data FIFO was not transferred successfully. 3133 */ 3134 register DFBKPTR { 3135 address 0x0C9 3136 access_mode RW 3137 size 2 3138 modes M_DFF0, M_DFF1 3139 } 3140 3141 /* 3142 * Skew Calculator 3143 */ 3144 register SKEWCALC { 3145 address 0x0C9 3146 access_mode RO 3147 modes M_CFG 3148 } 3149 3150 /* 3151 * Data FIFO Debug Control 3152 */ 3153 register DFDBCTL { 3154 address 0x0CB 3155 access_mode RW 3156 modes M_DFF0, M_DFF1 3157 field DFF_CIO_WR_RDY 0x20 3158 field DFF_CIO_RD_RDY 0x10 3159 field DFF_DIR_ERR 0x08 3160 field DFF_RAMBIST_FAIL 0x04 3161 field DFF_RAMBIST_DONE 0x02 3162 field DFF_RAMBIST_EN 0x01 3163 } 3164 3165 /* 3166 * Data FIFO Space Count 3167 * Number of FIFO locations that are free. 3168 */ 3169 register DFSCNT { 3170 address 0x0CC 3171 access_mode RO 3172 size 2 3173 modes M_DFF0, M_DFF1 3174 } 3175 3176 /* 3177 * Data FIFO Byte Count 3178 * Number of filled FIFO locations. 3179 */ 3180 register DFBCNT { 3181 address 0x0CE 3182 access_mode RO 3183 size 2 3184 modes M_DFF0, M_DFF1 3185 } 3186 3187 /* 3188 * Sequencer Program Overlay Address. 3189 * Low address must be written prior to high address. 3190 */ 3191 register OVLYADDR { 3192 address 0x0D4 3193 modes M_SCSI 3194 size 2 3195 access_mode RW 3196 } 3197 3198 /* 3199 * Sequencer Control 0 3200 * Error detection mode, speed configuration, 3201 * single step, breakpoints and program load. 3202 */ 3203 register SEQCTL0 { 3204 address 0x0D6 3205 access_mode RW 3206 field PERRORDIS 0x80 3207 field PAUSEDIS 0x40 3208 field FAILDIS 0x20 3209 field FASTMODE 0x10 3210 field BRKADRINTEN 0x08 3211 field STEP 0x04 3212 field SEQRESET 0x02 3213 field LOADRAM 0x01 3214 } 3215 3216 /* 3217 * Sequencer Control 1 3218 * Instruction RAM Diagnostics 3219 */ 3220 register SEQCTL1 { 3221 address 0x0D7 3222 access_mode RW 3223 field OVRLAY_DATA_CHK 0x08 3224 field RAMBIST_DONE 0x04 3225 field RAMBIST_FAIL 0x02 3226 field RAMBIST_EN 0x01 3227 } 3228 3229 /* 3230 * Sequencer Flags 3231 * Zero and Carry state of the ALU. 3232 */ 3233 register FLAGS { 3234 address 0x0D8 3235 access_mode RO 3236 field ZERO 0x02 3237 field CARRY 0x01 3238 } 3239 3240 /* 3241 * Sequencer Interrupt Control 3242 */ 3243 register SEQINTCTL { 3244 address 0x0D9 3245 access_mode RW 3246 field INTVEC1DSL 0x80 3247 field INT1_CONTEXT 0x20 3248 field SCS_SEQ_INT1M1 0x10 3249 field SCS_SEQ_INT1M0 0x08 3250 field INTMASK2 0x04 3251 field INTMASK1 0x02 3252 field IRET 0x01 3253 } 3254 3255 /* 3256 * Sequencer RAM Data Port 3257 * Single byte window into the Sequencer Instruction Ram area starting 3258 * at the address specified by OVLYADDR. To write a full instruction word, 3259 * simply write four bytes in succession. OVLYADDR will increment after the 3260 * most significant instrution byte (the byte with the parity bit) is written. 3261 */ 3262 register SEQRAM { 3263 address 0x0DA 3264 access_mode RW 3265 } 3266 3267 /* 3268 * Sequencer Program Counter 3269 * Low byte must be written prior to high byte. 3270 */ 3271 register PRGMCNT { 3272 address 0x0DE 3273 access_mode RW 3274 size 2 3275 } 3276 3277 /* 3278 * Accumulator 3279 */ 3280 register ACCUM { 3281 address 0x0E0 3282 access_mode RW 3283 accumulator 3284 } 3285 3286 /* 3287 * Source Index Register 3288 * Incrementing index for reads of SINDIR and the destination (low byte only) 3289 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3290 * Example: 3291 * mvi 0xFF call some_routine; 3292 * 3293 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3294 */ 3295 register SINDEX { 3296 address 0x0E2 3297 access_mode RW 3298 size 2 3299 sindex 3300 } 3301 3302 /* 3303 * Destination Index Register 3304 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3305 */ 3306 register DINDEX { 3307 address 0x0E4 3308 access_mode RW 3309 size 2 3310 } 3311 3312 /* 3313 * Break Address 3314 * Sequencer instruction breakpoint address address. 3315 */ 3316 register BRKADDR0 { 3317 address 0x0E6 3318 access_mode RW 3319 } 3320 3321 register BRKADDR1 { 3322 address 0x0E6 3323 access_mode RW 3324 field BRKDIS 0x80 /* Disable Breakpoint */ 3325 } 3326 3327 /* 3328 * All Ones 3329 * All reads to this register return the value 0xFF. 3330 */ 3331 register ALLONES { 3332 address 0x0E8 3333 access_mode RO 3334 allones 3335 } 3336 3337 /* 3338 * All Zeros 3339 * All reads to this register return the value 0. 3340 */ 3341 register ALLZEROS { 3342 address 0x0EA 3343 access_mode RO 3344 allzeros 3345 } 3346 3347 /* 3348 * No Destination 3349 * Writes to this register have no effect. 3350 */ 3351 register NONE { 3352 address 0x0EA 3353 access_mode WO 3354 none 3355 } 3356 3357 /* 3358 * Source Index Indirect 3359 * Reading this register is equivalent to reading (register_base + SINDEX) and 3360 * incrementing SINDEX by 1. 3361 */ 3362 register SINDIR { 3363 address 0x0EC 3364 access_mode RO 3365 } 3366 3367 /* 3368 * Destination Index Indirect 3369 * Writing this register is equivalent to writing to (register_base + DINDEX) 3370 * and incrementing DINDEX by 1. 3371 */ 3372 register DINDIR { 3373 address 0x0ED 3374 access_mode WO 3375 } 3376 3377 /* 3378 * Function One 3379 * 2's complement to bit value conversion. Write the 2's complement value 3380 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3381 * on the next read of this register. 3382 * Example: 3383 * Write 0x60 3384 * Read 0x40 3385 */ 3386 register FUNCTION1 { 3387 address 0x0F0 3388 access_mode RW 3389 } 3390 3391 /* 3392 * Stack 3393 * Window into the stack. Each stack location is 10 bits wide reported 3394 * low byte followed by high byte. There are 8 stack locations. 3395 */ 3396 register STACK { 3397 address 0x0F2 3398 access_mode RW 3399 } 3400 3401 /* 3402 * Interrupt Vector 1 Address 3403 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3404 */ 3405 register INTVEC1_ADDR { 3406 address 0x0F4 3407 access_mode RW 3408 size 2 3409 modes M_CFG 3410 } 3411 3412 /* 3413 * Current Address 3414 * Address of the SEQRAM instruction currently executing instruction. 3415 */ 3416 register CURADDR { 3417 address 0x0F4 3418 access_mode RW 3419 size 2 3420 modes M_SCSI 3421 } 3422 3423 /* 3424 * Interrupt Vector 2 Address 3425 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3426 */ 3427 register INTVEC2_ADDR { 3428 address 0x0F6 3429 access_mode RW 3430 size 2 3431 modes M_CFG 3432 } 3433 3434 /* 3435 * Last Address 3436 * Address of the SEQRAM instruction executed prior to the current instruction. 3437 */ 3438 register LASTADDR { 3439 address 0x0F6 3440 access_mode RW 3441 size 2 3442 modes M_SCSI 3443 } 3444 3445 register AHD_PCI_CONFIG_BASE { 3446 address 0x100 3447 access_mode RW 3448 size 256 3449 modes M_CFG 3450 } 3451 3452 /* ---------------------- Scratch RAM Offsets ------------------------- */ 3453 scratch_ram { 3454 /* Mode Specific */ 3455 address 0x0A0 3456 size 8 3457 modes 0, 1, 2, 3 3458 REG0 { 3459 size 2 3460 } 3461 REG1 { 3462 size 2 3463 } 3464 REG_ISR { 3465 size 2 3466 } 3467 SG_STATE { 3468 size 1 3469 field SEGS_AVAIL 0x01 3470 field LOADING_NEEDED 0x02 3471 field FETCH_INPROG 0x04 3472 } 3473 /* 3474 * Track whether the transfer byte count for 3475 * the current data phase is odd. 3476 */ 3477 DATA_COUNT_ODD { 3478 size 1 3479 } 3480 } 3481 3482 scratch_ram { 3483 /* Mode Specific */ 3484 address 0x0F8 3485 size 8 3486 modes 0, 1, 2, 3 3487 LONGJMP_ADDR { 3488 size 2 3489 } 3490 ACCUM_SAVE { 3491 size 1 3492 } 3493 } 3494 3495 3496 scratch_ram { 3497 address 0x100 3498 size 128 3499 modes 0, 1, 2, 3 3500 /* 3501 * Per "other-id" execution queues. We use an array of 3502 * tail pointers into lists of SCBs sorted by "other-id". 3503 * The execution head pointer threads the head SCBs for 3504 * each list. 3505 */ 3506 WAITING_SCB_TAILS { 3507 size 32 3508 } 3509 WAITING_TID_HEAD { 3510 size 2 3511 } 3512 WAITING_TID_TAIL { 3513 size 2 3514 } 3515 /* 3516 * SCBID of the next SCB in the new SCB queue. 3517 */ 3518 NEXT_QUEUED_SCB_ADDR { 3519 size 4 3520 } 3521 /* 3522 * head of list of SCBs that have 3523 * completed but have not been 3524 * put into the qoutfifo. 3525 */ 3526 COMPLETE_SCB_HEAD { 3527 size 2 3528 } 3529 /* 3530 * The list of completed SCBs in 3531 * the active DMA. 3532 */ 3533 COMPLETE_SCB_DMAINPROG_HEAD { 3534 size 2 3535 } 3536 /* 3537 * head of list of SCBs that have 3538 * completed but need to be uploaded 3539 * to the host prior to being completed. 3540 */ 3541 COMPLETE_DMA_SCB_HEAD { 3542 size 2 3543 } 3544 /* Counting semaphore to prevent new select-outs */ 3545 QFREEZE_COUNT { 3546 size 2 3547 } 3548 /* 3549 * Mode to restore on legacy idle loop exit. 3550 */ 3551 SAVED_MODE { 3552 size 1 3553 } 3554 /* 3555 * Single byte buffer used to designate the type or message 3556 * to send to a target. 3557 */ 3558 MSG_OUT { 3559 size 1 3560 } 3561 /* Parameters for DMA Logic */ 3562 DMAPARAMS { 3563 size 1 3564 field PRELOADEN 0x80 3565 field WIDEODD 0x40 3566 field SCSIEN 0x20 3567 field SDMAEN 0x10 3568 field SDMAENACK 0x10 3569 field HDMAEN 0x08 3570 field HDMAENACK 0x08 3571 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3572 field FIFOFLUSH 0x02 3573 field FIFORESET 0x01 3574 } 3575 SEQ_FLAGS { 3576 size 1 3577 field NOT_IDENTIFIED 0x80 3578 field NO_CDB_SENT 0x40 3579 field TARGET_CMD_IS_TAGGED 0x40 3580 field DPHASE 0x20 3581 /* Target flags */ 3582 field TARG_CMD_PENDING 0x10 3583 field CMDPHASE_PENDING 0x08 3584 field DPHASE_PENDING 0x04 3585 field SPHASE_PENDING 0x02 3586 field NO_DISCONNECT 0x01 3587 } 3588 /* 3589 * Temporary storage for the 3590 * target/channel/lun of a 3591 * reconnecting target 3592 */ 3593 SAVED_SCSIID { 3594 size 1 3595 } 3596 SAVED_LUN { 3597 size 1 3598 } 3599 /* 3600 * The last bus phase as seen by the sequencer. 3601 */ 3602 LASTPHASE { 3603 size 1 3604 field CDI 0x80 3605 field IOI 0x40 3606 field MSGI 0x20 3607 field P_BUSFREE 0x01 3608 enum PHASE_MASK CDO|IOO|MSGO { 3609 P_DATAOUT 0x0, 3610 P_DATAIN IOO, 3611 P_DATAOUT_DT P_DATAOUT|MSGO, 3612 P_DATAIN_DT P_DATAIN|MSGO, 3613 P_COMMAND CDO, 3614 P_MESGOUT CDO|MSGO, 3615 P_STATUS CDO|IOO, 3616 P_MESGIN CDO|IOO|MSGO 3617 } 3618 } 3619 /* 3620 * Value to "or" into the SCBPTR[1] value to 3621 * indicate that an entry in the QINFIFO is valid. 3622 */ 3623 QOUTFIFO_ENTRY_VALID_TAG { 3624 size 1 3625 } 3626 /* 3627 * Base address of our shared data with the kernel driver in host 3628 * memory. This includes the qoutfifo and target mode 3629 * incoming command queue. 3630 */ 3631 SHARED_DATA_ADDR { 3632 size 4 3633 } 3634 /* 3635 * Pointer to location in host memory for next 3636 * position in the qoutfifo. 3637 */ 3638 QOUTFIFO_NEXT_ADDR { 3639 size 4 3640 } 3641 /* 3642 * Kernel and sequencer offsets into the queue of 3643 * incoming target mode command descriptors. The 3644 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3645 */ 3646 KERNEL_TQINPOS { 3647 size 1 3648 } 3649 TQINPOS { 3650 size 1 3651 } 3652 ARG_1 { 3653 size 1 3654 mask SEND_MSG 0x80 3655 mask SEND_SENSE 0x40 3656 mask SEND_REJ 0x20 3657 mask MSGOUT_PHASEMIS 0x10 3658 mask EXIT_MSG_LOOP 0x08 3659 mask CONT_MSG_LOOP_WRITE 0x04 3660 mask CONT_MSG_LOOP_READ 0x03 3661 mask CONT_MSG_LOOP_TARG 0x02 3662 alias RETURN_1 3663 } 3664 ARG_2 { 3665 size 1 3666 alias RETURN_2 3667 } 3668 3669 /* 3670 * Snapshot of MSG_OUT taken after each message is sent. 3671 */ 3672 LAST_MSG { 3673 size 1 3674 } 3675 3676 /* 3677 * Sequences the kernel driver has okayed for us. This allows 3678 * the driver to do things like prevent initiator or target 3679 * operations. 3680 */ 3681 SCSISEQ_TEMPLATE { 3682 size 1 3683 field MANUALCTL 0x40 3684 field ENSELI 0x20 3685 field ENRSELI 0x10 3686 field MANUALP 0x0C 3687 field ENAUTOATNP 0x02 3688 field ALTSTIM 0x01 3689 } 3690 3691 /* 3692 * The initiator specified tag for this target mode transaction. 3693 */ 3694 INITIATOR_TAG { 3695 size 1 3696 } 3697 3698 SEQ_FLAGS2 { 3699 size 1 3700 field TARGET_MSG_PENDING 0x02 3701 field SELECTOUT_QFROZEN 0x04 3702 } 3703 3704 ALLOCFIFO_SCBPTR { 3705 size 2 3706 } 3707 3708 /* 3709 * The maximum amount of time to wait, when interrupt coalescing 3710 * is enabled, before issueing a CMDCMPLT interrupt for a completed 3711 * command. 3712 */ 3713 INT_COALESCING_TIMER { 3714 size 2 3715 } 3716 3717 /* 3718 * The maximum number of commands to coalesce into a single interrupt. 3719 * Actually the 2's complement of that value to simplify sequencer 3720 * code. 3721 */ 3722 INT_COALESCING_MAXCMDS { 3723 size 1 3724 } 3725 3726 /* 3727 * The minimum number of commands still outstanding required 3728 * to continue coalescing (2's complement of value). 3729 */ 3730 INT_COALESCING_MINCMDS { 3731 size 1 3732 } 3733 3734 /* 3735 * Number of commands "in-flight". 3736 */ 3737 CMDS_PENDING { 3738 size 2 3739 } 3740 3741 /* 3742 * The count of commands that have been coalesced. 3743 */ 3744 INT_COALESCING_CMDCOUNT { 3745 size 1 3746 } 3747 3748 /* 3749 * Since the HS_MAIBOX is self clearing, copy its contents to 3750 * this position in scratch ram every time it changes. 3751 */ 3752 LOCAL_HS_MAILBOX { 3753 size 1 3754 } 3755 /* 3756 * Target-mode CDB type to CDB length table used 3757 * in non-packetized operation. 3758 */ 3759 CMDSIZE_TABLE { 3760 size 8 3761 } 3762 } 3763 3764 /************************* Hardware SCB Definition ****************************/ 3765 scb { 3766 address 0x180 3767 size 64 3768 modes 0, 1, 2, 3 3769 SCB_RESIDUAL_DATACNT { 3770 size 4 3771 alias SCB_CDB_STORE 3772 alias SCB_HOST_CDB_PTR 3773 } 3774 SCB_RESIDUAL_SGPTR { 3775 size 4 3776 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3777 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3778 field SG_LIST_NULL 0x01 /* In the first byte */ 3779 } 3780 SCB_SCSI_STATUS { 3781 size 1 3782 alias SCB_HOST_CDB_LEN 3783 } 3784 SCB_TARGET_PHASES { 3785 size 1 3786 } 3787 SCB_TARGET_DATA_DIR { 3788 size 1 3789 } 3790 SCB_TARGET_ITAG { 3791 size 1 3792 } 3793 SCB_SENSE_BUSADDR { 3794 /* 3795 * Only valid if CDB length is less than 13 bytes or 3796 * we are using a CDB pointer. Otherwise contains 3797 * the last 4 bytes of embedded cdb information. 3798 */ 3799 size 4 3800 alias SCB_NEXT_COMPLETE 3801 } 3802 SCB_DATAPTR { 3803 size 8 3804 } 3805 SCB_DATACNT { 3806 /* 3807 * The last byte is really the high address bits for 3808 * the data address. 3809 */ 3810 size 4 3811 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3812 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3813 } 3814 SCB_SGPTR { 3815 size 4 3816 field SG_STATUS_VALID 0x04 /* In the first byte */ 3817 field SG_FULL_RESID 0x02 /* In the first byte */ 3818 field SG_LIST_NULL 0x01 /* In the first byte */ 3819 } 3820 SCB_BUSADDR { 3821 size 4 3822 } 3823 SCB_NEXT { 3824 alias SCB_NEXT_SCB_BUSADDR 3825 size 2 3826 } 3827 SCB_NEXT2 { 3828 size 2 3829 } 3830 SCB_CONTROL { 3831 size 1 3832 field TARGET_SCB 0x80 3833 field DISCENB 0x40 3834 field TAG_ENB 0x20 3835 field MK_MESSAGE 0x10 3836 field STATUS_RCVD 0x08 3837 field DISCONNECTED 0x04 3838 field SCB_TAG_TYPE 0x03 3839 } 3840 SCB_SCSIID { 3841 size 1 3842 field TID 0xF0 3843 field OID 0x0F 3844 } 3845 SCB_LUN { 3846 size 1 3847 field LID 0xff 3848 } 3849 SCB_TASK_ATTRIBUTE { 3850 size 1 3851 /* 3852 * Overloaded field for non-packetized 3853 * ignore wide residue message handling. 3854 */ 3855 field SCB_XFERLEN_ODD 0x01 3856 } 3857 SCB_CDB_LEN { 3858 size 1 3859 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3860 } 3861 SCB_TASK_MANAGEMENT { 3862 size 1 3863 } 3864 SCB_TAG { 3865 alias SCB_FIFO_USE_COUNT 3866 size 2 3867 } 3868 SCB_SPARE { 3869 size 8 3870 alias SCB_PKT_LUN 3871 } 3872 SCB_DISCONNECTED_LISTS { 3873 size 8 3874 } 3875 } 3876 3877 /*********************************** Constants ********************************/ 3878 const MK_MESSAGE_BIT_OFFSET 4 3879 const TID_SHIFT 4 3880 const TARGET_CMD_CMPLT 0xfe 3881 const INVALID_ADDR 0x80 3882 #define SCB_LIST_NULL 0xff 3883 #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3884 3885 const CCSGADDR_MAX 0x80 3886 const CCSCBADDR_MAX 0x80 3887 const CCSGRAM_MAXSEGS 16 3888 3889 /* Selection Timeout Timer Constants */ 3890 const STIMESEL_SHIFT 3 3891 const STIMESEL_MIN 0x18 3892 const STIMESEL_BUG_ADJ 0x8 3893 3894 /* WDTR Message values */ 3895 const BUS_8_BIT 0x00 3896 const BUS_16_BIT 0x01 3897 const BUS_32_BIT 0x02 3898 3899 /* Offset maximums */ 3900 const MAX_OFFSET 0xfe 3901 const MAX_OFFSET_PACED 0xfe 3902 const MAX_OFFSET_PACED_BUG 0x7f 3903 /* 3904 * Some 160 devices incorrectly accept 0xfe as a 3905 * sync offset, but will overrun this value. Limit 3906 * to 0x7f for speed lower than U320 which will 3907 * avoid the persistent sync offset overruns. 3908 */ 3909 const MAX_OFFSET_NON_PACED 0x7f 3910 const HOST_MSG 0xff 3911 3912 /* 3913 * The size of our sense buffers. 3914 * Sense buffer mapping can be handled in either of two ways. 3915 * The first is to allocate a dmamap for each transaction. 3916 * Depending on the architecture, dmamaps can be costly. The 3917 * alternative is to statically map the buffers in much the same 3918 * way we handle our scatter gather lists. The driver implements 3919 * the later. 3920 */ 3921 const AHD_SENSE_BUFSIZE 256 3922 3923 /* Target mode command processing constants */ 3924 const CMD_GROUP_CODE_SHIFT 0x05 3925 3926 const STATUS_BUSY 0x08 3927 const STATUS_QUEUE_FULL 0x28 3928 const STATUS_PKT_SENSE 0xFF 3929 const TARGET_DATA_IN 1 3930 3931 const SCB_TRANSFER_SIZE_FULL_LUN 56 3932 const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3933 /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3934 const PKT_OVERRUN_BUFSIZE 512 3935 3936 /* 3937 * Timer parameters. 3938 */ 3939 const AHD_TIMER_US_PER_TICK 25 3940 const AHD_TIMER_MAX_TICKS 0xFFFF 3941 const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 3942 3943 /* 3944 * Downloaded (kernel inserted) constants 3945 */ 3946 const SG_PREFETCH_CNT download 3947 const SG_PREFETCH_CNT_LIMIT download 3948 const SG_PREFETCH_ALIGN_MASK download 3949 const SG_PREFETCH_ADDR_MASK download 3950 const SG_SIZEOF download 3951 const PKT_OVERRUN_BUFOFFSET download 3952 const SCB_TRANSFER_SIZE download 3953 3954 /* 3955 * BIOS SCB offsets 3956 */ 3957 const NVRAM_SCB_OFFSET 0x2C 3958
Indexes created Tue Oct 28 09:09:52 GMT 2025