aic79xx_reg.h revision 1.3.2.1
1 1.1 fvdl /* 2 1.1 fvdl * DO NOT EDIT - This file is automatically generated 3 1.1 fvdl * from the following source files: 4 1.1 fvdl * 5 1.3.2.1 skrll * Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#96 $ 6 1.3.2.1 skrll * Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $ 7 1.1 fvdl */ 8 1.1 fvdl typedef int (ahd_reg_print_t)(u_int, u_int *, u_int); 9 1.1 fvdl typedef struct ahd_reg_parse_entry { 10 1.1 fvdl char *name; 11 1.1 fvdl uint8_t value; 12 1.1 fvdl uint8_t mask; 13 1.1 fvdl } ahd_reg_parse_entry_t; 14 1.1 fvdl 15 1.1 fvdl #if AIC_DEBUG_REGISTERS 16 1.1 fvdl ahd_reg_print_t ahd_mode_ptr_print; 17 1.1 fvdl #else 18 1.1 fvdl #define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ 19 1.1 fvdl ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap) 20 1.1 fvdl #endif 21 1.1 fvdl 22 1.1 fvdl #if AIC_DEBUG_REGISTERS 23 1.1 fvdl ahd_reg_print_t ahd_intstat_print; 24 1.1 fvdl #else 25 1.1 fvdl #define ahd_intstat_print(regvalue, cur_col, wrap) \ 26 1.1 fvdl ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap) 27 1.1 fvdl #endif 28 1.1 fvdl 29 1.1 fvdl #if AIC_DEBUG_REGISTERS 30 1.1 fvdl ahd_reg_print_t ahd_seqintcode_print; 31 1.1 fvdl #else 32 1.1 fvdl #define ahd_seqintcode_print(regvalue, cur_col, wrap) \ 33 1.1 fvdl ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap) 34 1.1 fvdl #endif 35 1.1 fvdl 36 1.1 fvdl #if AIC_DEBUG_REGISTERS 37 1.1 fvdl ahd_reg_print_t ahd_clrint_print; 38 1.1 fvdl #else 39 1.1 fvdl #define ahd_clrint_print(regvalue, cur_col, wrap) \ 40 1.1 fvdl ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap) 41 1.1 fvdl #endif 42 1.1 fvdl 43 1.1 fvdl #if AIC_DEBUG_REGISTERS 44 1.1 fvdl ahd_reg_print_t ahd_error_print; 45 1.1 fvdl #else 46 1.1 fvdl #define ahd_error_print(regvalue, cur_col, wrap) \ 47 1.1 fvdl ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap) 48 1.1 fvdl #endif 49 1.1 fvdl 50 1.1 fvdl #if AIC_DEBUG_REGISTERS 51 1.1 fvdl ahd_reg_print_t ahd_clrerr_print; 52 1.1 fvdl #else 53 1.1 fvdl #define ahd_clrerr_print(regvalue, cur_col, wrap) \ 54 1.1 fvdl ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap) 55 1.1 fvdl #endif 56 1.1 fvdl 57 1.1 fvdl #if AIC_DEBUG_REGISTERS 58 1.1 fvdl ahd_reg_print_t ahd_hcntrl_print; 59 1.1 fvdl #else 60 1.1 fvdl #define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 61 1.1 fvdl ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap) 62 1.1 fvdl #endif 63 1.1 fvdl 64 1.1 fvdl #if AIC_DEBUG_REGISTERS 65 1.1 fvdl ahd_reg_print_t ahd_hnscb_qoff_print; 66 1.1 fvdl #else 67 1.1 fvdl #define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \ 68 1.1 fvdl ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap) 69 1.1 fvdl #endif 70 1.1 fvdl 71 1.1 fvdl #if AIC_DEBUG_REGISTERS 72 1.1 fvdl ahd_reg_print_t ahd_hescb_qoff_print; 73 1.1 fvdl #else 74 1.1 fvdl #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 75 1.1 fvdl ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap) 76 1.1 fvdl #endif 77 1.1 fvdl 78 1.1 fvdl #if AIC_DEBUG_REGISTERS 79 1.1 fvdl ahd_reg_print_t ahd_hs_mailbox_print; 80 1.1 fvdl #else 81 1.1 fvdl #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \ 82 1.1 fvdl ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap) 83 1.1 fvdl #endif 84 1.1 fvdl 85 1.1 fvdl #if AIC_DEBUG_REGISTERS 86 1.1 fvdl ahd_reg_print_t ahd_seqintstat_print; 87 1.1 fvdl #else 88 1.1 fvdl #define ahd_seqintstat_print(regvalue, cur_col, wrap) \ 89 1.1 fvdl ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 90 1.1 fvdl #endif 91 1.1 fvdl 92 1.1 fvdl #if AIC_DEBUG_REGISTERS 93 1.1 fvdl ahd_reg_print_t ahd_clrseqintstat_print; 94 1.1 fvdl #else 95 1.1 fvdl #define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \ 96 1.1 fvdl ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 97 1.1 fvdl #endif 98 1.1 fvdl 99 1.1 fvdl #if AIC_DEBUG_REGISTERS 100 1.1 fvdl ahd_reg_print_t ahd_swtimer_print; 101 1.1 fvdl #else 102 1.1 fvdl #define ahd_swtimer_print(regvalue, cur_col, wrap) \ 103 1.1 fvdl ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap) 104 1.1 fvdl #endif 105 1.1 fvdl 106 1.1 fvdl #if AIC_DEBUG_REGISTERS 107 1.1 fvdl ahd_reg_print_t ahd_snscb_qoff_print; 108 1.1 fvdl #else 109 1.1 fvdl #define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \ 110 1.1 fvdl ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap) 111 1.1 fvdl #endif 112 1.1 fvdl 113 1.1 fvdl #if AIC_DEBUG_REGISTERS 114 1.1 fvdl ahd_reg_print_t ahd_sescb_qoff_print; 115 1.1 fvdl #else 116 1.1 fvdl #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 117 1.1 fvdl ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap) 118 1.1 fvdl #endif 119 1.1 fvdl 120 1.1 fvdl #if AIC_DEBUG_REGISTERS 121 1.1 fvdl ahd_reg_print_t ahd_sdscb_qoff_print; 122 1.1 fvdl #else 123 1.1 fvdl #define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \ 124 1.1 fvdl ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap) 125 1.1 fvdl #endif 126 1.1 fvdl 127 1.1 fvdl #if AIC_DEBUG_REGISTERS 128 1.1 fvdl ahd_reg_print_t ahd_qoff_ctlsta_print; 129 1.1 fvdl #else 130 1.1 fvdl #define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 131 1.1 fvdl ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap) 132 1.1 fvdl #endif 133 1.1 fvdl 134 1.1 fvdl #if AIC_DEBUG_REGISTERS 135 1.1 fvdl ahd_reg_print_t ahd_intctl_print; 136 1.1 fvdl #else 137 1.1 fvdl #define ahd_intctl_print(regvalue, cur_col, wrap) \ 138 1.1 fvdl ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap) 139 1.1 fvdl #endif 140 1.1 fvdl 141 1.1 fvdl #if AIC_DEBUG_REGISTERS 142 1.1 fvdl ahd_reg_print_t ahd_dfcntrl_print; 143 1.1 fvdl #else 144 1.1 fvdl #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \ 145 1.1 fvdl ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap) 146 1.1 fvdl #endif 147 1.1 fvdl 148 1.1 fvdl #if AIC_DEBUG_REGISTERS 149 1.1 fvdl ahd_reg_print_t ahd_dscommand0_print; 150 1.1 fvdl #else 151 1.1 fvdl #define ahd_dscommand0_print(regvalue, cur_col, wrap) \ 152 1.1 fvdl ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap) 153 1.1 fvdl #endif 154 1.1 fvdl 155 1.1 fvdl #if AIC_DEBUG_REGISTERS 156 1.1 fvdl ahd_reg_print_t ahd_dfstatus_print; 157 1.1 fvdl #else 158 1.1 fvdl #define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 159 1.1 fvdl ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap) 160 1.1 fvdl #endif 161 1.1 fvdl 162 1.1 fvdl #if AIC_DEBUG_REGISTERS 163 1.1 fvdl ahd_reg_print_t ahd_arbctl_print; 164 1.1 fvdl #else 165 1.1 fvdl #define ahd_arbctl_print(regvalue, cur_col, wrap) \ 166 1.1 fvdl ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap) 167 1.1 fvdl #endif 168 1.1 fvdl 169 1.1 fvdl #if AIC_DEBUG_REGISTERS 170 1.1 fvdl ahd_reg_print_t ahd_sg_cache_shadow_print; 171 1.1 fvdl #else 172 1.1 fvdl #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 173 1.1 fvdl ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap) 174 1.1 fvdl #endif 175 1.1 fvdl 176 1.1 fvdl #if AIC_DEBUG_REGISTERS 177 1.1 fvdl ahd_reg_print_t ahd_sg_cache_pre_print; 178 1.1 fvdl #else 179 1.1 fvdl #define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 180 1.1 fvdl ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap) 181 1.1 fvdl #endif 182 1.1 fvdl 183 1.1 fvdl #if AIC_DEBUG_REGISTERS 184 1.1 fvdl ahd_reg_print_t ahd_typeptr_print; 185 1.1 fvdl #else 186 1.1 fvdl #define ahd_typeptr_print(regvalue, cur_col, wrap) \ 187 1.1 fvdl ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap) 188 1.1 fvdl #endif 189 1.1 fvdl 190 1.1 fvdl #if AIC_DEBUG_REGISTERS 191 1.1 fvdl ahd_reg_print_t ahd_lqin_print; 192 1.1 fvdl #else 193 1.1 fvdl #define ahd_lqin_print(regvalue, cur_col, wrap) \ 194 1.1 fvdl ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap) 195 1.1 fvdl #endif 196 1.1 fvdl 197 1.1 fvdl #if AIC_DEBUG_REGISTERS 198 1.1 fvdl ahd_reg_print_t ahd_tagptr_print; 199 1.1 fvdl #else 200 1.1 fvdl #define ahd_tagptr_print(regvalue, cur_col, wrap) \ 201 1.1 fvdl ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap) 202 1.1 fvdl #endif 203 1.1 fvdl 204 1.1 fvdl #if AIC_DEBUG_REGISTERS 205 1.1 fvdl ahd_reg_print_t ahd_lunptr_print; 206 1.1 fvdl #else 207 1.1 fvdl #define ahd_lunptr_print(regvalue, cur_col, wrap) \ 208 1.1 fvdl ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap) 209 1.1 fvdl #endif 210 1.1 fvdl 211 1.1 fvdl #if AIC_DEBUG_REGISTERS 212 1.1 fvdl ahd_reg_print_t ahd_datalenptr_print; 213 1.1 fvdl #else 214 1.1 fvdl #define ahd_datalenptr_print(regvalue, cur_col, wrap) \ 215 1.1 fvdl ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap) 216 1.1 fvdl #endif 217 1.1 fvdl 218 1.1 fvdl #if AIC_DEBUG_REGISTERS 219 1.1 fvdl ahd_reg_print_t ahd_statlenptr_print; 220 1.1 fvdl #else 221 1.1 fvdl #define ahd_statlenptr_print(regvalue, cur_col, wrap) \ 222 1.1 fvdl ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap) 223 1.1 fvdl #endif 224 1.1 fvdl 225 1.1 fvdl #if AIC_DEBUG_REGISTERS 226 1.1 fvdl ahd_reg_print_t ahd_cmdlenptr_print; 227 1.1 fvdl #else 228 1.1 fvdl #define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 229 1.1 fvdl ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap) 230 1.1 fvdl #endif 231 1.1 fvdl 232 1.1 fvdl #if AIC_DEBUG_REGISTERS 233 1.1 fvdl ahd_reg_print_t ahd_attrptr_print; 234 1.1 fvdl #else 235 1.1 fvdl #define ahd_attrptr_print(regvalue, cur_col, wrap) \ 236 1.1 fvdl ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap) 237 1.1 fvdl #endif 238 1.1 fvdl 239 1.1 fvdl #if AIC_DEBUG_REGISTERS 240 1.1 fvdl ahd_reg_print_t ahd_flagptr_print; 241 1.1 fvdl #else 242 1.1 fvdl #define ahd_flagptr_print(regvalue, cur_col, wrap) \ 243 1.1 fvdl ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap) 244 1.1 fvdl #endif 245 1.1 fvdl 246 1.1 fvdl #if AIC_DEBUG_REGISTERS 247 1.1 fvdl ahd_reg_print_t ahd_cmdptr_print; 248 1.1 fvdl #else 249 1.1 fvdl #define ahd_cmdptr_print(regvalue, cur_col, wrap) \ 250 1.1 fvdl ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap) 251 1.1 fvdl #endif 252 1.1 fvdl 253 1.1 fvdl #if AIC_DEBUG_REGISTERS 254 1.1 fvdl ahd_reg_print_t ahd_qnextptr_print; 255 1.1 fvdl #else 256 1.1 fvdl #define ahd_qnextptr_print(regvalue, cur_col, wrap) \ 257 1.1 fvdl ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap) 258 1.1 fvdl #endif 259 1.1 fvdl 260 1.1 fvdl #if AIC_DEBUG_REGISTERS 261 1.1 fvdl ahd_reg_print_t ahd_idptr_print; 262 1.1 fvdl #else 263 1.1 fvdl #define ahd_idptr_print(regvalue, cur_col, wrap) \ 264 1.1 fvdl ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap) 265 1.1 fvdl #endif 266 1.1 fvdl 267 1.1 fvdl #if AIC_DEBUG_REGISTERS 268 1.1 fvdl ahd_reg_print_t ahd_abrtbyteptr_print; 269 1.1 fvdl #else 270 1.1 fvdl #define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 271 1.1 fvdl ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap) 272 1.1 fvdl #endif 273 1.1 fvdl 274 1.1 fvdl #if AIC_DEBUG_REGISTERS 275 1.1 fvdl ahd_reg_print_t ahd_abrtbitptr_print; 276 1.1 fvdl #else 277 1.1 fvdl #define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \ 278 1.1 fvdl ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap) 279 1.1 fvdl #endif 280 1.1 fvdl 281 1.1 fvdl #if AIC_DEBUG_REGISTERS 282 1.1 fvdl ahd_reg_print_t ahd_maxcmdbytes_print; 283 1.1 fvdl #else 284 1.1 fvdl #define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \ 285 1.1 fvdl ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap) 286 1.1 fvdl #endif 287 1.1 fvdl 288 1.1 fvdl #if AIC_DEBUG_REGISTERS 289 1.1 fvdl ahd_reg_print_t ahd_maxcmd2rcv_print; 290 1.1 fvdl #else 291 1.1 fvdl #define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \ 292 1.1 fvdl ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap) 293 1.1 fvdl #endif 294 1.1 fvdl 295 1.1 fvdl #if AIC_DEBUG_REGISTERS 296 1.1 fvdl ahd_reg_print_t ahd_shortthresh_print; 297 1.1 fvdl #else 298 1.1 fvdl #define ahd_shortthresh_print(regvalue, cur_col, wrap) \ 299 1.1 fvdl ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap) 300 1.1 fvdl #endif 301 1.1 fvdl 302 1.1 fvdl #if AIC_DEBUG_REGISTERS 303 1.1 fvdl ahd_reg_print_t ahd_lunlen_print; 304 1.1 fvdl #else 305 1.1 fvdl #define ahd_lunlen_print(regvalue, cur_col, wrap) \ 306 1.1 fvdl ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap) 307 1.1 fvdl #endif 308 1.1 fvdl 309 1.1 fvdl #if AIC_DEBUG_REGISTERS 310 1.1 fvdl ahd_reg_print_t ahd_cdblimit_print; 311 1.1 fvdl #else 312 1.1 fvdl #define ahd_cdblimit_print(regvalue, cur_col, wrap) \ 313 1.1 fvdl ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap) 314 1.1 fvdl #endif 315 1.1 fvdl 316 1.1 fvdl #if AIC_DEBUG_REGISTERS 317 1.1 fvdl ahd_reg_print_t ahd_maxcmd_print; 318 1.1 fvdl #else 319 1.1 fvdl #define ahd_maxcmd_print(regvalue, cur_col, wrap) \ 320 1.1 fvdl ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap) 321 1.1 fvdl #endif 322 1.1 fvdl 323 1.1 fvdl #if AIC_DEBUG_REGISTERS 324 1.1 fvdl ahd_reg_print_t ahd_maxcmdcnt_print; 325 1.1 fvdl #else 326 1.1 fvdl #define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \ 327 1.1 fvdl ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap) 328 1.1 fvdl #endif 329 1.1 fvdl 330 1.1 fvdl #if AIC_DEBUG_REGISTERS 331 1.1 fvdl ahd_reg_print_t ahd_lqrsvd01_print; 332 1.1 fvdl #else 333 1.1 fvdl #define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \ 334 1.1 fvdl ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap) 335 1.1 fvdl #endif 336 1.1 fvdl 337 1.1 fvdl #if AIC_DEBUG_REGISTERS 338 1.1 fvdl ahd_reg_print_t ahd_lqrsvd16_print; 339 1.1 fvdl #else 340 1.1 fvdl #define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \ 341 1.1 fvdl ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap) 342 1.1 fvdl #endif 343 1.1 fvdl 344 1.1 fvdl #if AIC_DEBUG_REGISTERS 345 1.1 fvdl ahd_reg_print_t ahd_lqrsvd17_print; 346 1.1 fvdl #else 347 1.1 fvdl #define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \ 348 1.1 fvdl ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap) 349 1.1 fvdl #endif 350 1.1 fvdl 351 1.1 fvdl #if AIC_DEBUG_REGISTERS 352 1.1 fvdl ahd_reg_print_t ahd_cmdrsvd0_print; 353 1.1 fvdl #else 354 1.1 fvdl #define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \ 355 1.1 fvdl ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap) 356 1.1 fvdl #endif 357 1.1 fvdl 358 1.1 fvdl #if AIC_DEBUG_REGISTERS 359 1.1 fvdl ahd_reg_print_t ahd_lqctl0_print; 360 1.1 fvdl #else 361 1.1 fvdl #define ahd_lqctl0_print(regvalue, cur_col, wrap) \ 362 1.1 fvdl ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap) 363 1.1 fvdl #endif 364 1.1 fvdl 365 1.1 fvdl #if AIC_DEBUG_REGISTERS 366 1.1 fvdl ahd_reg_print_t ahd_lqctl1_print; 367 1.1 fvdl #else 368 1.1 fvdl #define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 369 1.1 fvdl ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap) 370 1.1 fvdl #endif 371 1.1 fvdl 372 1.1 fvdl #if AIC_DEBUG_REGISTERS 373 1.1 fvdl ahd_reg_print_t ahd_lqctl2_print; 374 1.1 fvdl #else 375 1.1 fvdl #define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 376 1.1 fvdl ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap) 377 1.1 fvdl #endif 378 1.1 fvdl 379 1.1 fvdl #if AIC_DEBUG_REGISTERS 380 1.1 fvdl ahd_reg_print_t ahd_scsbist0_print; 381 1.1 fvdl #else 382 1.1 fvdl #define ahd_scsbist0_print(regvalue, cur_col, wrap) \ 383 1.1 fvdl ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap) 384 1.1 fvdl #endif 385 1.1 fvdl 386 1.1 fvdl #if AIC_DEBUG_REGISTERS 387 1.1 fvdl ahd_reg_print_t ahd_scsiseq0_print; 388 1.1 fvdl #else 389 1.1 fvdl #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 390 1.1 fvdl ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap) 391 1.1 fvdl #endif 392 1.1 fvdl 393 1.1 fvdl #if AIC_DEBUG_REGISTERS 394 1.1 fvdl ahd_reg_print_t ahd_scsbist1_print; 395 1.1 fvdl #else 396 1.1 fvdl #define ahd_scsbist1_print(regvalue, cur_col, wrap) \ 397 1.1 fvdl ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap) 398 1.1 fvdl #endif 399 1.1 fvdl 400 1.1 fvdl #if AIC_DEBUG_REGISTERS 401 1.1 fvdl ahd_reg_print_t ahd_scsiseq1_print; 402 1.1 fvdl #else 403 1.1 fvdl #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \ 404 1.1 fvdl ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap) 405 1.1 fvdl #endif 406 1.1 fvdl 407 1.1 fvdl #if AIC_DEBUG_REGISTERS 408 1.1 fvdl ahd_reg_print_t ahd_dlcount_print; 409 1.1 fvdl #else 410 1.1 fvdl #define ahd_dlcount_print(regvalue, cur_col, wrap) \ 411 1.1 fvdl ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap) 412 1.1 fvdl #endif 413 1.1 fvdl 414 1.1 fvdl #if AIC_DEBUG_REGISTERS 415 1.1 fvdl ahd_reg_print_t ahd_businitid_print; 416 1.1 fvdl #else 417 1.1 fvdl #define ahd_businitid_print(regvalue, cur_col, wrap) \ 418 1.1 fvdl ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap) 419 1.1 fvdl #endif 420 1.1 fvdl 421 1.1 fvdl #if AIC_DEBUG_REGISTERS 422 1.1 fvdl ahd_reg_print_t ahd_sxfrctl0_print; 423 1.1 fvdl #else 424 1.1 fvdl #define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \ 425 1.1 fvdl ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap) 426 1.1 fvdl #endif 427 1.1 fvdl 428 1.1 fvdl #if AIC_DEBUG_REGISTERS 429 1.1 fvdl ahd_reg_print_t ahd_sxfrctl1_print; 430 1.1 fvdl #else 431 1.1 fvdl #define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 432 1.1 fvdl ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap) 433 1.1 fvdl #endif 434 1.1 fvdl 435 1.1 fvdl #if AIC_DEBUG_REGISTERS 436 1.1 fvdl ahd_reg_print_t ahd_sxfrctl2_print; 437 1.1 fvdl #else 438 1.1 fvdl #define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \ 439 1.1 fvdl ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap) 440 1.1 fvdl #endif 441 1.1 fvdl 442 1.1 fvdl #if AIC_DEBUG_REGISTERS 443 1.1 fvdl ahd_reg_print_t ahd_bustargid_print; 444 1.1 fvdl #else 445 1.1 fvdl #define ahd_bustargid_print(regvalue, cur_col, wrap) \ 446 1.1 fvdl ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap) 447 1.1 fvdl #endif 448 1.1 fvdl 449 1.1 fvdl #if AIC_DEBUG_REGISTERS 450 1.1 fvdl ahd_reg_print_t ahd_dffstat_print; 451 1.1 fvdl #else 452 1.1 fvdl #define ahd_dffstat_print(regvalue, cur_col, wrap) \ 453 1.1 fvdl ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap) 454 1.1 fvdl #endif 455 1.1 fvdl 456 1.1 fvdl #if AIC_DEBUG_REGISTERS 457 1.1 fvdl ahd_reg_print_t ahd_multargid_print; 458 1.1 fvdl #else 459 1.1 fvdl #define ahd_multargid_print(regvalue, cur_col, wrap) \ 460 1.1 fvdl ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 461 1.1 fvdl #endif 462 1.1 fvdl 463 1.1 fvdl #if AIC_DEBUG_REGISTERS 464 1.1 fvdl ahd_reg_print_t ahd_scsisigo_print; 465 1.1 fvdl #else 466 1.1 fvdl #define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 467 1.1 fvdl ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 468 1.1 fvdl #endif 469 1.1 fvdl 470 1.1 fvdl #if AIC_DEBUG_REGISTERS 471 1.1 fvdl ahd_reg_print_t ahd_scsisigi_print; 472 1.1 fvdl #else 473 1.1 fvdl #define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 474 1.1 fvdl ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap) 475 1.1 fvdl #endif 476 1.1 fvdl 477 1.1 fvdl #if AIC_DEBUG_REGISTERS 478 1.1 fvdl ahd_reg_print_t ahd_scsiphase_print; 479 1.1 fvdl #else 480 1.1 fvdl #define ahd_scsiphase_print(regvalue, cur_col, wrap) \ 481 1.1 fvdl ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap) 482 1.1 fvdl #endif 483 1.1 fvdl 484 1.1 fvdl #if AIC_DEBUG_REGISTERS 485 1.1 fvdl ahd_reg_print_t ahd_scsidat0_img_print; 486 1.1 fvdl #else 487 1.1 fvdl #define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \ 488 1.1 fvdl ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap) 489 1.1 fvdl #endif 490 1.1 fvdl 491 1.1 fvdl #if AIC_DEBUG_REGISTERS 492 1.1 fvdl ahd_reg_print_t ahd_scsidat_print; 493 1.1 fvdl #else 494 1.1 fvdl #define ahd_scsidat_print(regvalue, cur_col, wrap) \ 495 1.1 fvdl ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap) 496 1.1 fvdl #endif 497 1.1 fvdl 498 1.1 fvdl #if AIC_DEBUG_REGISTERS 499 1.1 fvdl ahd_reg_print_t ahd_scsibus_print; 500 1.1 fvdl #else 501 1.1 fvdl #define ahd_scsibus_print(regvalue, cur_col, wrap) \ 502 1.1 fvdl ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap) 503 1.1 fvdl #endif 504 1.1 fvdl 505 1.1 fvdl #if AIC_DEBUG_REGISTERS 506 1.1 fvdl ahd_reg_print_t ahd_targidin_print; 507 1.1 fvdl #else 508 1.1 fvdl #define ahd_targidin_print(regvalue, cur_col, wrap) \ 509 1.1 fvdl ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap) 510 1.1 fvdl #endif 511 1.1 fvdl 512 1.1 fvdl #if AIC_DEBUG_REGISTERS 513 1.1 fvdl ahd_reg_print_t ahd_selid_print; 514 1.1 fvdl #else 515 1.1 fvdl #define ahd_selid_print(regvalue, cur_col, wrap) \ 516 1.1 fvdl ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap) 517 1.1 fvdl #endif 518 1.1 fvdl 519 1.1 fvdl #if AIC_DEBUG_REGISTERS 520 1.1 fvdl ahd_reg_print_t ahd_sblkctl_print; 521 1.1 fvdl #else 522 1.1 fvdl #define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 523 1.1 fvdl ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap) 524 1.1 fvdl #endif 525 1.1 fvdl 526 1.1 fvdl #if AIC_DEBUG_REGISTERS 527 1.1 fvdl ahd_reg_print_t ahd_optionmode_print; 528 1.1 fvdl #else 529 1.1 fvdl #define ahd_optionmode_print(regvalue, cur_col, wrap) \ 530 1.1 fvdl ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap) 531 1.1 fvdl #endif 532 1.1 fvdl 533 1.1 fvdl #if AIC_DEBUG_REGISTERS 534 1.1 fvdl ahd_reg_print_t ahd_simode0_print; 535 1.1 fvdl #else 536 1.1 fvdl #define ahd_simode0_print(regvalue, cur_col, wrap) \ 537 1.1 fvdl ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap) 538 1.1 fvdl #endif 539 1.1 fvdl 540 1.1 fvdl #if AIC_DEBUG_REGISTERS 541 1.1 fvdl ahd_reg_print_t ahd_sstat0_print; 542 1.1 fvdl #else 543 1.1 fvdl #define ahd_sstat0_print(regvalue, cur_col, wrap) \ 544 1.1 fvdl ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap) 545 1.1 fvdl #endif 546 1.1 fvdl 547 1.1 fvdl #if AIC_DEBUG_REGISTERS 548 1.1 fvdl ahd_reg_print_t ahd_clrsint0_print; 549 1.1 fvdl #else 550 1.1 fvdl #define ahd_clrsint0_print(regvalue, cur_col, wrap) \ 551 1.1 fvdl ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap) 552 1.1 fvdl #endif 553 1.1 fvdl 554 1.1 fvdl #if AIC_DEBUG_REGISTERS 555 1.1 fvdl ahd_reg_print_t ahd_sstat1_print; 556 1.1 fvdl #else 557 1.1 fvdl #define ahd_sstat1_print(regvalue, cur_col, wrap) \ 558 1.1 fvdl ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap) 559 1.1 fvdl #endif 560 1.1 fvdl 561 1.1 fvdl #if AIC_DEBUG_REGISTERS 562 1.1 fvdl ahd_reg_print_t ahd_clrsint1_print; 563 1.1 fvdl #else 564 1.1 fvdl #define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 565 1.1 fvdl ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 566 1.1 fvdl #endif 567 1.1 fvdl 568 1.1 fvdl #if AIC_DEBUG_REGISTERS 569 1.1 fvdl ahd_reg_print_t ahd_sstat2_print; 570 1.1 fvdl #else 571 1.1 fvdl #define ahd_sstat2_print(regvalue, cur_col, wrap) \ 572 1.1 fvdl ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 573 1.1 fvdl #endif 574 1.1 fvdl 575 1.1 fvdl #if AIC_DEBUG_REGISTERS 576 1.1 fvdl ahd_reg_print_t ahd_clrsint2_print; 577 1.1 fvdl #else 578 1.1 fvdl #define ahd_clrsint2_print(regvalue, cur_col, wrap) \ 579 1.1 fvdl ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap) 580 1.1 fvdl #endif 581 1.1 fvdl 582 1.1 fvdl #if AIC_DEBUG_REGISTERS 583 1.1 fvdl ahd_reg_print_t ahd_simode2_print; 584 1.1 fvdl #else 585 1.1 fvdl #define ahd_simode2_print(regvalue, cur_col, wrap) \ 586 1.1 fvdl ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 587 1.1 fvdl #endif 588 1.1 fvdl 589 1.1 fvdl #if AIC_DEBUG_REGISTERS 590 1.1 fvdl ahd_reg_print_t ahd_lqistate_print; 591 1.1 fvdl #else 592 1.1 fvdl #define ahd_lqistate_print(regvalue, cur_col, wrap) \ 593 1.1 fvdl ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap) 594 1.1 fvdl #endif 595 1.1 fvdl 596 1.1 fvdl #if AIC_DEBUG_REGISTERS 597 1.1 fvdl ahd_reg_print_t ahd_perrdiag_print; 598 1.1 fvdl #else 599 1.1 fvdl #define ahd_perrdiag_print(regvalue, cur_col, wrap) \ 600 1.1 fvdl ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap) 601 1.1 fvdl #endif 602 1.1 fvdl 603 1.1 fvdl #if AIC_DEBUG_REGISTERS 604 1.1 fvdl ahd_reg_print_t ahd_soffcnt_print; 605 1.1 fvdl #else 606 1.1 fvdl #define ahd_soffcnt_print(regvalue, cur_col, wrap) \ 607 1.1 fvdl ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap) 608 1.1 fvdl #endif 609 1.1 fvdl 610 1.1 fvdl #if AIC_DEBUG_REGISTERS 611 1.1 fvdl ahd_reg_print_t ahd_lqostate_print; 612 1.1 fvdl #else 613 1.1 fvdl #define ahd_lqostate_print(regvalue, cur_col, wrap) \ 614 1.1 fvdl ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap) 615 1.1 fvdl #endif 616 1.1 fvdl 617 1.1 fvdl #if AIC_DEBUG_REGISTERS 618 1.1 fvdl ahd_reg_print_t ahd_lqistat0_print; 619 1.1 fvdl #else 620 1.1 fvdl #define ahd_lqistat0_print(regvalue, cur_col, wrap) \ 621 1.1 fvdl ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap) 622 1.1 fvdl #endif 623 1.1 fvdl 624 1.1 fvdl #if AIC_DEBUG_REGISTERS 625 1.1 fvdl ahd_reg_print_t ahd_clrlqiint0_print; 626 1.1 fvdl #else 627 1.1 fvdl #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 628 1.1 fvdl ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 629 1.1 fvdl #endif 630 1.1 fvdl 631 1.1 fvdl #if AIC_DEBUG_REGISTERS 632 1.1 fvdl ahd_reg_print_t ahd_lqimode0_print; 633 1.1 fvdl #else 634 1.1 fvdl #define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 635 1.1 fvdl ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 636 1.1 fvdl #endif 637 1.1 fvdl 638 1.1 fvdl #if AIC_DEBUG_REGISTERS 639 1.1 fvdl ahd_reg_print_t ahd_lqistat1_print; 640 1.1 fvdl #else 641 1.1 fvdl #define ahd_lqistat1_print(regvalue, cur_col, wrap) \ 642 1.1 fvdl ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap) 643 1.1 fvdl #endif 644 1.1 fvdl 645 1.1 fvdl #if AIC_DEBUG_REGISTERS 646 1.1 fvdl ahd_reg_print_t ahd_clrlqiint1_print; 647 1.1 fvdl #else 648 1.1 fvdl #define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \ 649 1.1 fvdl ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap) 650 1.1 fvdl #endif 651 1.1 fvdl 652 1.1 fvdl #if AIC_DEBUG_REGISTERS 653 1.1 fvdl ahd_reg_print_t ahd_lqimode1_print; 654 1.1 fvdl #else 655 1.1 fvdl #define ahd_lqimode1_print(regvalue, cur_col, wrap) \ 656 1.1 fvdl ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap) 657 1.1 fvdl #endif 658 1.1 fvdl 659 1.1 fvdl #if AIC_DEBUG_REGISTERS 660 1.1 fvdl ahd_reg_print_t ahd_lqistat2_print; 661 1.1 fvdl #else 662 1.1 fvdl #define ahd_lqistat2_print(regvalue, cur_col, wrap) \ 663 1.1 fvdl ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap) 664 1.1 fvdl #endif 665 1.1 fvdl 666 1.1 fvdl #if AIC_DEBUG_REGISTERS 667 1.1 fvdl ahd_reg_print_t ahd_sstat3_print; 668 1.1 fvdl #else 669 1.1 fvdl #define ahd_sstat3_print(regvalue, cur_col, wrap) \ 670 1.1 fvdl ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap) 671 1.1 fvdl #endif 672 1.1 fvdl 673 1.1 fvdl #if AIC_DEBUG_REGISTERS 674 1.1 fvdl ahd_reg_print_t ahd_clrsint3_print; 675 1.1 fvdl #else 676 1.1 fvdl #define ahd_clrsint3_print(regvalue, cur_col, wrap) \ 677 1.1 fvdl ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap) 678 1.1 fvdl #endif 679 1.1 fvdl 680 1.1 fvdl #if AIC_DEBUG_REGISTERS 681 1.1 fvdl ahd_reg_print_t ahd_simode3_print; 682 1.1 fvdl #else 683 1.1 fvdl #define ahd_simode3_print(regvalue, cur_col, wrap) \ 684 1.1 fvdl ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap) 685 1.1 fvdl #endif 686 1.1 fvdl 687 1.1 fvdl #if AIC_DEBUG_REGISTERS 688 1.1 fvdl ahd_reg_print_t ahd_lqostat0_print; 689 1.1 fvdl #else 690 1.1 fvdl #define ahd_lqostat0_print(regvalue, cur_col, wrap) \ 691 1.1 fvdl ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap) 692 1.1 fvdl #endif 693 1.1 fvdl 694 1.1 fvdl #if AIC_DEBUG_REGISTERS 695 1.1 fvdl ahd_reg_print_t ahd_clrlqoint0_print; 696 1.1 fvdl #else 697 1.1 fvdl #define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \ 698 1.1 fvdl ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap) 699 1.1 fvdl #endif 700 1.1 fvdl 701 1.1 fvdl #if AIC_DEBUG_REGISTERS 702 1.1 fvdl ahd_reg_print_t ahd_lqomode0_print; 703 1.1 fvdl #else 704 1.1 fvdl #define ahd_lqomode0_print(regvalue, cur_col, wrap) \ 705 1.1 fvdl ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap) 706 1.1 fvdl #endif 707 1.1 fvdl 708 1.1 fvdl #if AIC_DEBUG_REGISTERS 709 1.1 fvdl ahd_reg_print_t ahd_lqostat1_print; 710 1.1 fvdl #else 711 1.1 fvdl #define ahd_lqostat1_print(regvalue, cur_col, wrap) \ 712 1.1 fvdl ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap) 713 1.1 fvdl #endif 714 1.1 fvdl 715 1.1 fvdl #if AIC_DEBUG_REGISTERS 716 1.1 fvdl ahd_reg_print_t ahd_clrlqoint1_print; 717 1.1 fvdl #else 718 1.1 fvdl #define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \ 719 1.1 fvdl ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap) 720 1.1 fvdl #endif 721 1.1 fvdl 722 1.1 fvdl #if AIC_DEBUG_REGISTERS 723 1.1 fvdl ahd_reg_print_t ahd_lqomode1_print; 724 1.1 fvdl #else 725 1.1 fvdl #define ahd_lqomode1_print(regvalue, cur_col, wrap) \ 726 1.1 fvdl ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap) 727 1.1 fvdl #endif 728 1.1 fvdl 729 1.1 fvdl #if AIC_DEBUG_REGISTERS 730 1.1 fvdl ahd_reg_print_t ahd_os_space_cnt_print; 731 1.1 fvdl #else 732 1.1 fvdl #define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \ 733 1.1 fvdl ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap) 734 1.1 fvdl #endif 735 1.1 fvdl 736 1.1 fvdl #if AIC_DEBUG_REGISTERS 737 1.1 fvdl ahd_reg_print_t ahd_lqostat2_print; 738 1.1 fvdl #else 739 1.1 fvdl #define ahd_lqostat2_print(regvalue, cur_col, wrap) \ 740 1.1 fvdl ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap) 741 1.1 fvdl #endif 742 1.1 fvdl 743 1.1 fvdl #if AIC_DEBUG_REGISTERS 744 1.1 fvdl ahd_reg_print_t ahd_simode1_print; 745 1.1 fvdl #else 746 1.1 fvdl #define ahd_simode1_print(regvalue, cur_col, wrap) \ 747 1.1 fvdl ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap) 748 1.1 fvdl #endif 749 1.1 fvdl 750 1.1 fvdl #if AIC_DEBUG_REGISTERS 751 1.1 fvdl ahd_reg_print_t ahd_gsfifo_print; 752 1.1 fvdl #else 753 1.1 fvdl #define ahd_gsfifo_print(regvalue, cur_col, wrap) \ 754 1.1 fvdl ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap) 755 1.1 fvdl #endif 756 1.1 fvdl 757 1.1 fvdl #if AIC_DEBUG_REGISTERS 758 1.1 fvdl ahd_reg_print_t ahd_lqoscsctl_print; 759 1.1 fvdl #else 760 1.1 fvdl #define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \ 761 1.1 fvdl ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap) 762 1.1 fvdl #endif 763 1.1 fvdl 764 1.1 fvdl #if AIC_DEBUG_REGISTERS 765 1.1 fvdl ahd_reg_print_t ahd_nextscb_print; 766 1.1 fvdl #else 767 1.1 fvdl #define ahd_nextscb_print(regvalue, cur_col, wrap) \ 768 1.1 fvdl ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap) 769 1.1 fvdl #endif 770 1.1 fvdl 771 1.1 fvdl #if AIC_DEBUG_REGISTERS 772 1.1 fvdl ahd_reg_print_t ahd_dffsxfrctl_print; 773 1.1 fvdl #else 774 1.1 fvdl #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \ 775 1.1 fvdl ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap) 776 1.1 fvdl #endif 777 1.1 fvdl 778 1.1 fvdl #if AIC_DEBUG_REGISTERS 779 1.1 fvdl ahd_reg_print_t ahd_seqintsrc_print; 780 1.1 fvdl #else 781 1.1 fvdl #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \ 782 1.1 fvdl ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap) 783 1.1 fvdl #endif 784 1.1 fvdl 785 1.1 fvdl #if AIC_DEBUG_REGISTERS 786 1.1 fvdl ahd_reg_print_t ahd_clrseqintsrc_print; 787 1.1 fvdl #else 788 1.1 fvdl #define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \ 789 1.1 fvdl ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap) 790 1.1 fvdl #endif 791 1.1 fvdl 792 1.1 fvdl #if AIC_DEBUG_REGISTERS 793 1.1 fvdl ahd_reg_print_t ahd_seqimode_print; 794 1.1 fvdl #else 795 1.1 fvdl #define ahd_seqimode_print(regvalue, cur_col, wrap) \ 796 1.1 fvdl ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 797 1.1 fvdl #endif 798 1.1 fvdl 799 1.1 fvdl #if AIC_DEBUG_REGISTERS 800 1.1 fvdl ahd_reg_print_t ahd_currscb_print; 801 1.1 fvdl #else 802 1.1 fvdl #define ahd_currscb_print(regvalue, cur_col, wrap) \ 803 1.1 fvdl ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 804 1.1 fvdl #endif 805 1.1 fvdl 806 1.1 fvdl #if AIC_DEBUG_REGISTERS 807 1.1 fvdl ahd_reg_print_t ahd_mdffstat_print; 808 1.1 fvdl #else 809 1.1 fvdl #define ahd_mdffstat_print(regvalue, cur_col, wrap) \ 810 1.1 fvdl ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap) 811 1.1 fvdl #endif 812 1.1 fvdl 813 1.1 fvdl #if AIC_DEBUG_REGISTERS 814 1.1 fvdl ahd_reg_print_t ahd_crccontrol_print; 815 1.1 fvdl #else 816 1.1 fvdl #define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 817 1.1 fvdl ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 818 1.1 fvdl #endif 819 1.1 fvdl 820 1.1 fvdl #if AIC_DEBUG_REGISTERS 821 1.1 fvdl ahd_reg_print_t ahd_scsitest_print; 822 1.1 fvdl #else 823 1.1 fvdl #define ahd_scsitest_print(regvalue, cur_col, wrap) \ 824 1.1 fvdl ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap) 825 1.1 fvdl #endif 826 1.1 fvdl 827 1.1 fvdl #if AIC_DEBUG_REGISTERS 828 1.1 fvdl ahd_reg_print_t ahd_dfftag_print; 829 1.1 fvdl #else 830 1.1 fvdl #define ahd_dfftag_print(regvalue, cur_col, wrap) \ 831 1.1 fvdl ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 832 1.1 fvdl #endif 833 1.1 fvdl 834 1.1 fvdl #if AIC_DEBUG_REGISTERS 835 1.1 fvdl ahd_reg_print_t ahd_lastscb_print; 836 1.1 fvdl #else 837 1.1 fvdl #define ahd_lastscb_print(regvalue, cur_col, wrap) \ 838 1.1 fvdl ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap) 839 1.1 fvdl #endif 840 1.1 fvdl 841 1.1 fvdl #if AIC_DEBUG_REGISTERS 842 1.1 fvdl ahd_reg_print_t ahd_iopdnctl_print; 843 1.1 fvdl #else 844 1.1 fvdl #define ahd_iopdnctl_print(regvalue, cur_col, wrap) \ 845 1.1 fvdl ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap) 846 1.1 fvdl #endif 847 1.1 fvdl 848 1.1 fvdl #if AIC_DEBUG_REGISTERS 849 1.1 fvdl ahd_reg_print_t ahd_negoaddr_print; 850 1.1 fvdl #else 851 1.1 fvdl #define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 852 1.1 fvdl ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap) 853 1.1 fvdl #endif 854 1.1 fvdl 855 1.1 fvdl #if AIC_DEBUG_REGISTERS 856 1.1 fvdl ahd_reg_print_t ahd_shaddr_print; 857 1.1 fvdl #else 858 1.1 fvdl #define ahd_shaddr_print(regvalue, cur_col, wrap) \ 859 1.1 fvdl ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap) 860 1.1 fvdl #endif 861 1.1 fvdl 862 1.1 fvdl #if AIC_DEBUG_REGISTERS 863 1.1 fvdl ahd_reg_print_t ahd_dgrpcrci_print; 864 1.1 fvdl #else 865 1.1 fvdl #define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \ 866 1.1 fvdl ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap) 867 1.1 fvdl #endif 868 1.1 fvdl 869 1.1 fvdl #if AIC_DEBUG_REGISTERS 870 1.1 fvdl ahd_reg_print_t ahd_negperiod_print; 871 1.1 fvdl #else 872 1.1 fvdl #define ahd_negperiod_print(regvalue, cur_col, wrap) \ 873 1.1 fvdl ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap) 874 1.1 fvdl #endif 875 1.1 fvdl 876 1.1 fvdl #if AIC_DEBUG_REGISTERS 877 1.1 fvdl ahd_reg_print_t ahd_packcrci_print; 878 1.1 fvdl #else 879 1.1 fvdl #define ahd_packcrci_print(regvalue, cur_col, wrap) \ 880 1.1 fvdl ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap) 881 1.1 fvdl #endif 882 1.1 fvdl 883 1.1 fvdl #if AIC_DEBUG_REGISTERS 884 1.1 fvdl ahd_reg_print_t ahd_negoffset_print; 885 1.1 fvdl #else 886 1.1 fvdl #define ahd_negoffset_print(regvalue, cur_col, wrap) \ 887 1.1 fvdl ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap) 888 1.1 fvdl #endif 889 1.1 fvdl 890 1.1 fvdl #if AIC_DEBUG_REGISTERS 891 1.1 fvdl ahd_reg_print_t ahd_negppropts_print; 892 1.1 fvdl #else 893 1.1 fvdl #define ahd_negppropts_print(regvalue, cur_col, wrap) \ 894 1.1 fvdl ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap) 895 1.1 fvdl #endif 896 1.1 fvdl 897 1.1 fvdl #if AIC_DEBUG_REGISTERS 898 1.1 fvdl ahd_reg_print_t ahd_negconopts_print; 899 1.1 fvdl #else 900 1.1 fvdl #define ahd_negconopts_print(regvalue, cur_col, wrap) \ 901 1.1 fvdl ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap) 902 1.1 fvdl #endif 903 1.1 fvdl 904 1.1 fvdl #if AIC_DEBUG_REGISTERS 905 1.1 fvdl ahd_reg_print_t ahd_annexcol_print; 906 1.1 fvdl #else 907 1.1 fvdl #define ahd_annexcol_print(regvalue, cur_col, wrap) \ 908 1.1 fvdl ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap) 909 1.1 fvdl #endif 910 1.1 fvdl 911 1.1 fvdl #if AIC_DEBUG_REGISTERS 912 1.1 fvdl ahd_reg_print_t ahd_annexdat_print; 913 1.1 fvdl #else 914 1.1 fvdl #define ahd_annexdat_print(regvalue, cur_col, wrap) \ 915 1.1 fvdl ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap) 916 1.1 fvdl #endif 917 1.1 fvdl 918 1.1 fvdl #if AIC_DEBUG_REGISTERS 919 1.1 fvdl ahd_reg_print_t ahd_scschkn_print; 920 1.1 fvdl #else 921 1.1 fvdl #define ahd_scschkn_print(regvalue, cur_col, wrap) \ 922 1.1 fvdl ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap) 923 1.1 fvdl #endif 924 1.1 fvdl 925 1.1 fvdl #if AIC_DEBUG_REGISTERS 926 1.1 fvdl ahd_reg_print_t ahd_iownid_print; 927 1.1 fvdl #else 928 1.1 fvdl #define ahd_iownid_print(regvalue, cur_col, wrap) \ 929 1.1 fvdl ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap) 930 1.1 fvdl #endif 931 1.1 fvdl 932 1.1 fvdl #if AIC_DEBUG_REGISTERS 933 1.1 fvdl ahd_reg_print_t ahd_shcnt_print; 934 1.1 fvdl #else 935 1.1 fvdl #define ahd_shcnt_print(regvalue, cur_col, wrap) \ 936 1.1 fvdl ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap) 937 1.1 fvdl #endif 938 1.1 fvdl 939 1.1 fvdl #if AIC_DEBUG_REGISTERS 940 1.1 fvdl ahd_reg_print_t ahd_pll960ctl0_print; 941 1.1 fvdl #else 942 1.1 fvdl #define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \ 943 1.1 fvdl ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap) 944 1.1 fvdl #endif 945 1.1 fvdl 946 1.1 fvdl #if AIC_DEBUG_REGISTERS 947 1.1 fvdl ahd_reg_print_t ahd_pll960ctl1_print; 948 1.1 fvdl #else 949 1.1 fvdl #define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \ 950 1.1 fvdl ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap) 951 1.1 fvdl #endif 952 1.1 fvdl 953 1.1 fvdl #if AIC_DEBUG_REGISTERS 954 1.1 fvdl ahd_reg_print_t ahd_townid_print; 955 1.1 fvdl #else 956 1.1 fvdl #define ahd_townid_print(regvalue, cur_col, wrap) \ 957 1.1 fvdl ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap) 958 1.1 fvdl #endif 959 1.1 fvdl 960 1.1 fvdl #if AIC_DEBUG_REGISTERS 961 1.1 fvdl ahd_reg_print_t ahd_xsig_print; 962 1.1 fvdl #else 963 1.1 fvdl #define ahd_xsig_print(regvalue, cur_col, wrap) \ 964 1.1 fvdl ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap) 965 1.1 fvdl #endif 966 1.1 fvdl 967 1.1 fvdl #if AIC_DEBUG_REGISTERS 968 1.1 fvdl ahd_reg_print_t ahd_pll960cnt0_print; 969 1.1 fvdl #else 970 1.1 fvdl #define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \ 971 1.1 fvdl ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap) 972 1.1 fvdl #endif 973 1.1 fvdl 974 1.1 fvdl #if AIC_DEBUG_REGISTERS 975 1.1 fvdl ahd_reg_print_t ahd_seloid_print; 976 1.1 fvdl #else 977 1.1 fvdl #define ahd_seloid_print(regvalue, cur_col, wrap) \ 978 1.1 fvdl ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap) 979 1.1 fvdl #endif 980 1.1 fvdl 981 1.1 fvdl #if AIC_DEBUG_REGISTERS 982 1.1 fvdl ahd_reg_print_t ahd_pll400ctl0_print; 983 1.1 fvdl #else 984 1.1 fvdl #define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \ 985 1.1 fvdl ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap) 986 1.1 fvdl #endif 987 1.1 fvdl 988 1.1 fvdl #if AIC_DEBUG_REGISTERS 989 1.1 fvdl ahd_reg_print_t ahd_fairness_print; 990 1.1 fvdl #else 991 1.1 fvdl #define ahd_fairness_print(regvalue, cur_col, wrap) \ 992 1.1 fvdl ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap) 993 1.1 fvdl #endif 994 1.1 fvdl 995 1.1 fvdl #if AIC_DEBUG_REGISTERS 996 1.1 fvdl ahd_reg_print_t ahd_pll400ctl1_print; 997 1.1 fvdl #else 998 1.1 fvdl #define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \ 999 1.1 fvdl ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap) 1000 1.1 fvdl #endif 1001 1.1 fvdl 1002 1.1 fvdl #if AIC_DEBUG_REGISTERS 1003 1.1 fvdl ahd_reg_print_t ahd_pll400cnt0_print; 1004 1.1 fvdl #else 1005 1.1 fvdl #define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \ 1006 1.1 fvdl ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap) 1007 1.1 fvdl #endif 1008 1.1 fvdl 1009 1.1 fvdl #if AIC_DEBUG_REGISTERS 1010 1.1 fvdl ahd_reg_print_t ahd_unfairness_print; 1011 1.1 fvdl #else 1012 1.1 fvdl #define ahd_unfairness_print(regvalue, cur_col, wrap) \ 1013 1.1 fvdl ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap) 1014 1.1 fvdl #endif 1015 1.1 fvdl 1016 1.1 fvdl #if AIC_DEBUG_REGISTERS 1017 1.1 fvdl ahd_reg_print_t ahd_hodmaadr_print; 1018 1.1 fvdl #else 1019 1.1 fvdl #define ahd_hodmaadr_print(regvalue, cur_col, wrap) \ 1020 1.1 fvdl ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap) 1021 1.1 fvdl #endif 1022 1.1 fvdl 1023 1.1 fvdl #if AIC_DEBUG_REGISTERS 1024 1.1 fvdl ahd_reg_print_t ahd_haddr_print; 1025 1.1 fvdl #else 1026 1.1 fvdl #define ahd_haddr_print(regvalue, cur_col, wrap) \ 1027 1.1 fvdl ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap) 1028 1.1 fvdl #endif 1029 1.1 fvdl 1030 1.1 fvdl #if AIC_DEBUG_REGISTERS 1031 1.1 fvdl ahd_reg_print_t ahd_plldelay_print; 1032 1.1 fvdl #else 1033 1.1 fvdl #define ahd_plldelay_print(regvalue, cur_col, wrap) \ 1034 1.1 fvdl ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap) 1035 1.1 fvdl #endif 1036 1.1 fvdl 1037 1.1 fvdl #if AIC_DEBUG_REGISTERS 1038 1.1 fvdl ahd_reg_print_t ahd_hcnt_print; 1039 1.1 fvdl #else 1040 1.1 fvdl #define ahd_hcnt_print(regvalue, cur_col, wrap) \ 1041 1.1 fvdl ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap) 1042 1.1 fvdl #endif 1043 1.1 fvdl 1044 1.1 fvdl #if AIC_DEBUG_REGISTERS 1045 1.1 fvdl ahd_reg_print_t ahd_hodmacnt_print; 1046 1.1 fvdl #else 1047 1.1 fvdl #define ahd_hodmacnt_print(regvalue, cur_col, wrap) \ 1048 1.1 fvdl ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap) 1049 1.1 fvdl #endif 1050 1.1 fvdl 1051 1.1 fvdl #if AIC_DEBUG_REGISTERS 1052 1.1 fvdl ahd_reg_print_t ahd_hodmaen_print; 1053 1.1 fvdl #else 1054 1.1 fvdl #define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 1055 1.1 fvdl ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 1056 1.1 fvdl #endif 1057 1.1 fvdl 1058 1.1 fvdl #if AIC_DEBUG_REGISTERS 1059 1.1 fvdl ahd_reg_print_t ahd_scbhaddr_print; 1060 1.1 fvdl #else 1061 1.1 fvdl #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 1062 1.1 fvdl ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap) 1063 1.1 fvdl #endif 1064 1.1 fvdl 1065 1.1 fvdl #if AIC_DEBUG_REGISTERS 1066 1.1 fvdl ahd_reg_print_t ahd_sghaddr_print; 1067 1.1 fvdl #else 1068 1.1 fvdl #define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 1069 1.1 fvdl ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 1070 1.1 fvdl #endif 1071 1.1 fvdl 1072 1.1 fvdl #if AIC_DEBUG_REGISTERS 1073 1.1 fvdl ahd_reg_print_t ahd_sghcnt_print; 1074 1.1 fvdl #else 1075 1.1 fvdl #define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 1076 1.1 fvdl ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 1077 1.1 fvdl #endif 1078 1.1 fvdl 1079 1.1 fvdl #if AIC_DEBUG_REGISTERS 1080 1.1 fvdl ahd_reg_print_t ahd_scbhcnt_print; 1081 1.1 fvdl #else 1082 1.1 fvdl #define ahd_scbhcnt_print(regvalue, cur_col, wrap) \ 1083 1.1 fvdl ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap) 1084 1.1 fvdl #endif 1085 1.1 fvdl 1086 1.1 fvdl #if AIC_DEBUG_REGISTERS 1087 1.1 fvdl ahd_reg_print_t ahd_dff_thrsh_print; 1088 1.1 fvdl #else 1089 1.1 fvdl #define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 1090 1.1 fvdl ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 1091 1.1 fvdl #endif 1092 1.1 fvdl 1093 1.1 fvdl #if AIC_DEBUG_REGISTERS 1094 1.1 fvdl ahd_reg_print_t ahd_romaddr_print; 1095 1.1 fvdl #else 1096 1.1 fvdl #define ahd_romaddr_print(regvalue, cur_col, wrap) \ 1097 1.1 fvdl ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap) 1098 1.1 fvdl #endif 1099 1.1 fvdl 1100 1.1 fvdl #if AIC_DEBUG_REGISTERS 1101 1.1 fvdl ahd_reg_print_t ahd_romcntrl_print; 1102 1.1 fvdl #else 1103 1.1 fvdl #define ahd_romcntrl_print(regvalue, cur_col, wrap) \ 1104 1.1 fvdl ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap) 1105 1.1 fvdl #endif 1106 1.1 fvdl 1107 1.1 fvdl #if AIC_DEBUG_REGISTERS 1108 1.1 fvdl ahd_reg_print_t ahd_romdata_print; 1109 1.1 fvdl #else 1110 1.1 fvdl #define ahd_romdata_print(regvalue, cur_col, wrap) \ 1111 1.1 fvdl ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap) 1112 1.1 fvdl #endif 1113 1.1 fvdl 1114 1.1 fvdl #if AIC_DEBUG_REGISTERS 1115 1.1 fvdl ahd_reg_print_t ahd_dchrxmsg0_print; 1116 1.1 fvdl #else 1117 1.1 fvdl #define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \ 1118 1.1 fvdl ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap) 1119 1.1 fvdl #endif 1120 1.1 fvdl 1121 1.1 fvdl #if AIC_DEBUG_REGISTERS 1122 1.1 fvdl ahd_reg_print_t ahd_roenable_print; 1123 1.1 fvdl #else 1124 1.1 fvdl #define ahd_roenable_print(regvalue, cur_col, wrap) \ 1125 1.1 fvdl ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap) 1126 1.1 fvdl #endif 1127 1.1 fvdl 1128 1.1 fvdl #if AIC_DEBUG_REGISTERS 1129 1.1 fvdl ahd_reg_print_t ahd_ovlyrxmsg0_print; 1130 1.1 fvdl #else 1131 1.1 fvdl #define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \ 1132 1.1 fvdl ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap) 1133 1.1 fvdl #endif 1134 1.1 fvdl 1135 1.1 fvdl #if AIC_DEBUG_REGISTERS 1136 1.1 fvdl ahd_reg_print_t ahd_cmcrxmsg0_print; 1137 1.1 fvdl #else 1138 1.1 fvdl #define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \ 1139 1.1 fvdl ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap) 1140 1.1 fvdl #endif 1141 1.1 fvdl 1142 1.1 fvdl #if AIC_DEBUG_REGISTERS 1143 1.1 fvdl ahd_reg_print_t ahd_nsenable_print; 1144 1.1 fvdl #else 1145 1.1 fvdl #define ahd_nsenable_print(regvalue, cur_col, wrap) \ 1146 1.1 fvdl ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap) 1147 1.1 fvdl #endif 1148 1.1 fvdl 1149 1.1 fvdl #if AIC_DEBUG_REGISTERS 1150 1.1 fvdl ahd_reg_print_t ahd_dchrxmsg1_print; 1151 1.1 fvdl #else 1152 1.1 fvdl #define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \ 1153 1.1 fvdl ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap) 1154 1.1 fvdl #endif 1155 1.1 fvdl 1156 1.1 fvdl #if AIC_DEBUG_REGISTERS 1157 1.1 fvdl ahd_reg_print_t ahd_ovlyrxmsg1_print; 1158 1.1 fvdl #else 1159 1.1 fvdl #define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \ 1160 1.1 fvdl ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap) 1161 1.1 fvdl #endif 1162 1.1 fvdl 1163 1.1 fvdl #if AIC_DEBUG_REGISTERS 1164 1.1 fvdl ahd_reg_print_t ahd_cmcrxmsg1_print; 1165 1.1 fvdl #else 1166 1.1 fvdl #define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \ 1167 1.1 fvdl ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap) 1168 1.1 fvdl #endif 1169 1.1 fvdl 1170 1.1 fvdl #if AIC_DEBUG_REGISTERS 1171 1.1 fvdl ahd_reg_print_t ahd_dchrxmsg2_print; 1172 1.1 fvdl #else 1173 1.1 fvdl #define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \ 1174 1.1 fvdl ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap) 1175 1.1 fvdl #endif 1176 1.1 fvdl 1177 1.1 fvdl #if AIC_DEBUG_REGISTERS 1178 1.1 fvdl ahd_reg_print_t ahd_ovlyrxmsg2_print; 1179 1.1 fvdl #else 1180 1.1 fvdl #define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \ 1181 1.1 fvdl ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap) 1182 1.1 fvdl #endif 1183 1.1 fvdl 1184 1.1 fvdl #if AIC_DEBUG_REGISTERS 1185 1.1 fvdl ahd_reg_print_t ahd_cmcrxmsg2_print; 1186 1.1 fvdl #else 1187 1.1 fvdl #define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \ 1188 1.1 fvdl ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap) 1189 1.1 fvdl #endif 1190 1.1 fvdl 1191 1.1 fvdl #if AIC_DEBUG_REGISTERS 1192 1.1 fvdl ahd_reg_print_t ahd_ost_print; 1193 1.1 fvdl #else 1194 1.1 fvdl #define ahd_ost_print(regvalue, cur_col, wrap) \ 1195 1.1 fvdl ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap) 1196 1.1 fvdl #endif 1197 1.1 fvdl 1198 1.1 fvdl #if AIC_DEBUG_REGISTERS 1199 1.1 fvdl ahd_reg_print_t ahd_dchrxmsg3_print; 1200 1.1 fvdl #else 1201 1.1 fvdl #define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \ 1202 1.1 fvdl ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap) 1203 1.1 fvdl #endif 1204 1.1 fvdl 1205 1.1 fvdl #if AIC_DEBUG_REGISTERS 1206 1.1 fvdl ahd_reg_print_t ahd_cmcrxmsg3_print; 1207 1.1 fvdl #else 1208 1.1 fvdl #define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \ 1209 1.1 fvdl ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap) 1210 1.1 fvdl #endif 1211 1.1 fvdl 1212 1.1 fvdl #if AIC_DEBUG_REGISTERS 1213 1.1 fvdl ahd_reg_print_t ahd_pcixctl_print; 1214 1.1 fvdl #else 1215 1.1 fvdl #define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 1216 1.1 fvdl ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap) 1217 1.1 fvdl #endif 1218 1.1 fvdl 1219 1.1 fvdl #if AIC_DEBUG_REGISTERS 1220 1.1 fvdl ahd_reg_print_t ahd_ovlyrxmsg3_print; 1221 1.1 fvdl #else 1222 1.1 fvdl #define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \ 1223 1.1 fvdl ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap) 1224 1.1 fvdl #endif 1225 1.1 fvdl 1226 1.1 fvdl #if AIC_DEBUG_REGISTERS 1227 1.1 fvdl ahd_reg_print_t ahd_ovlyseqbcnt_print; 1228 1.1 fvdl #else 1229 1.1 fvdl #define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \ 1230 1.1 fvdl ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap) 1231 1.1 fvdl #endif 1232 1.1 fvdl 1233 1.1 fvdl #if AIC_DEBUG_REGISTERS 1234 1.1 fvdl ahd_reg_print_t ahd_cmcseqbcnt_print; 1235 1.1 fvdl #else 1236 1.1 fvdl #define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \ 1237 1.1 fvdl ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap) 1238 1.1 fvdl #endif 1239 1.1 fvdl 1240 1.1 fvdl #if AIC_DEBUG_REGISTERS 1241 1.1 fvdl ahd_reg_print_t ahd_dchseqbcnt_print; 1242 1.1 fvdl #else 1243 1.1 fvdl #define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \ 1244 1.1 fvdl ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap) 1245 1.1 fvdl #endif 1246 1.1 fvdl 1247 1.1 fvdl #if AIC_DEBUG_REGISTERS 1248 1.1 fvdl ahd_reg_print_t ahd_ovlyspltstat0_print; 1249 1.1 fvdl #else 1250 1.1 fvdl #define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \ 1251 1.1 fvdl ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1252 1.1 fvdl #endif 1253 1.1 fvdl 1254 1.1 fvdl #if AIC_DEBUG_REGISTERS 1255 1.1 fvdl ahd_reg_print_t ahd_cmcspltstat0_print; 1256 1.1 fvdl #else 1257 1.1 fvdl #define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \ 1258 1.1 fvdl ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1259 1.1 fvdl #endif 1260 1.1 fvdl 1261 1.1 fvdl #if AIC_DEBUG_REGISTERS 1262 1.1 fvdl ahd_reg_print_t ahd_dchspltstat0_print; 1263 1.1 fvdl #else 1264 1.1 fvdl #define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 1265 1.1 fvdl ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1266 1.1 fvdl #endif 1267 1.1 fvdl 1268 1.1 fvdl #if AIC_DEBUG_REGISTERS 1269 1.1 fvdl ahd_reg_print_t ahd_ovlyspltstat1_print; 1270 1.1 fvdl #else 1271 1.1 fvdl #define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \ 1272 1.1 fvdl ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1273 1.1 fvdl #endif 1274 1.1 fvdl 1275 1.1 fvdl #if AIC_DEBUG_REGISTERS 1276 1.1 fvdl ahd_reg_print_t ahd_dchspltstat1_print; 1277 1.1 fvdl #else 1278 1.1 fvdl #define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 1279 1.1 fvdl ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1280 1.1 fvdl #endif 1281 1.1 fvdl 1282 1.1 fvdl #if AIC_DEBUG_REGISTERS 1283 1.1 fvdl ahd_reg_print_t ahd_cmcspltstat1_print; 1284 1.1 fvdl #else 1285 1.1 fvdl #define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \ 1286 1.1 fvdl ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1287 1.1 fvdl #endif 1288 1.1 fvdl 1289 1.1 fvdl #if AIC_DEBUG_REGISTERS 1290 1.1 fvdl ahd_reg_print_t ahd_sgrxmsg0_print; 1291 1.1 fvdl #else 1292 1.1 fvdl #define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \ 1293 1.1 fvdl ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap) 1294 1.1 fvdl #endif 1295 1.1 fvdl 1296 1.1 fvdl #if AIC_DEBUG_REGISTERS 1297 1.1 fvdl ahd_reg_print_t ahd_slvspltoutadr0_print; 1298 1.1 fvdl #else 1299 1.1 fvdl #define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \ 1300 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap) 1301 1.1 fvdl #endif 1302 1.1 fvdl 1303 1.1 fvdl #if AIC_DEBUG_REGISTERS 1304 1.1 fvdl ahd_reg_print_t ahd_slvspltoutadr1_print; 1305 1.1 fvdl #else 1306 1.1 fvdl #define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \ 1307 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap) 1308 1.1 fvdl #endif 1309 1.1 fvdl 1310 1.1 fvdl #if AIC_DEBUG_REGISTERS 1311 1.1 fvdl ahd_reg_print_t ahd_sgrxmsg1_print; 1312 1.1 fvdl #else 1313 1.1 fvdl #define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \ 1314 1.1 fvdl ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap) 1315 1.1 fvdl #endif 1316 1.1 fvdl 1317 1.1 fvdl #if AIC_DEBUG_REGISTERS 1318 1.1 fvdl ahd_reg_print_t ahd_slvspltoutadr2_print; 1319 1.1 fvdl #else 1320 1.1 fvdl #define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \ 1321 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap) 1322 1.1 fvdl #endif 1323 1.1 fvdl 1324 1.1 fvdl #if AIC_DEBUG_REGISTERS 1325 1.1 fvdl ahd_reg_print_t ahd_sgrxmsg2_print; 1326 1.1 fvdl #else 1327 1.1 fvdl #define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \ 1328 1.1 fvdl ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap) 1329 1.1 fvdl #endif 1330 1.1 fvdl 1331 1.1 fvdl #if AIC_DEBUG_REGISTERS 1332 1.1 fvdl ahd_reg_print_t ahd_slvspltoutadr3_print; 1333 1.1 fvdl #else 1334 1.1 fvdl #define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \ 1335 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap) 1336 1.1 fvdl #endif 1337 1.1 fvdl 1338 1.1 fvdl #if AIC_DEBUG_REGISTERS 1339 1.1 fvdl ahd_reg_print_t ahd_sgrxmsg3_print; 1340 1.1 fvdl #else 1341 1.1 fvdl #define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \ 1342 1.1 fvdl ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap) 1343 1.1 fvdl #endif 1344 1.1 fvdl 1345 1.1 fvdl #if AIC_DEBUG_REGISTERS 1346 1.1 fvdl ahd_reg_print_t ahd_sgseqbcnt_print; 1347 1.1 fvdl #else 1348 1.1 fvdl #define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \ 1349 1.1 fvdl ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap) 1350 1.1 fvdl #endif 1351 1.1 fvdl 1352 1.1 fvdl #if AIC_DEBUG_REGISTERS 1353 1.1 fvdl ahd_reg_print_t ahd_slvspltoutattr0_print; 1354 1.1 fvdl #else 1355 1.1 fvdl #define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \ 1356 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap) 1357 1.1 fvdl #endif 1358 1.1 fvdl 1359 1.1 fvdl #if AIC_DEBUG_REGISTERS 1360 1.1 fvdl ahd_reg_print_t ahd_slvspltoutattr1_print; 1361 1.1 fvdl #else 1362 1.1 fvdl #define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \ 1363 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap) 1364 1.1 fvdl #endif 1365 1.1 fvdl 1366 1.1 fvdl #if AIC_DEBUG_REGISTERS 1367 1.1 fvdl ahd_reg_print_t ahd_sgspltstat0_print; 1368 1.1 fvdl #else 1369 1.1 fvdl #define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 1370 1.1 fvdl ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap) 1371 1.1 fvdl #endif 1372 1.1 fvdl 1373 1.1 fvdl #if AIC_DEBUG_REGISTERS 1374 1.1 fvdl ahd_reg_print_t ahd_slvspltoutattr2_print; 1375 1.1 fvdl #else 1376 1.1 fvdl #define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \ 1377 1.1 fvdl ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap) 1378 1.1 fvdl #endif 1379 1.1 fvdl 1380 1.1 fvdl #if AIC_DEBUG_REGISTERS 1381 1.1 fvdl ahd_reg_print_t ahd_sgspltstat1_print; 1382 1.1 fvdl #else 1383 1.1 fvdl #define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \ 1384 1.1 fvdl ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap) 1385 1.1 fvdl #endif 1386 1.1 fvdl 1387 1.1 fvdl #if AIC_DEBUG_REGISTERS 1388 1.1 fvdl ahd_reg_print_t ahd_sfunct_print; 1389 1.1 fvdl #else 1390 1.1 fvdl #define ahd_sfunct_print(regvalue, cur_col, wrap) \ 1391 1.1 fvdl ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 1392 1.1 fvdl #endif 1393 1.1 fvdl 1394 1.1 fvdl #if AIC_DEBUG_REGISTERS 1395 1.1 fvdl ahd_reg_print_t ahd_df0pcistat_print; 1396 1.1 fvdl #else 1397 1.1 fvdl #define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 1398 1.1 fvdl ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap) 1399 1.1 fvdl #endif 1400 1.1 fvdl 1401 1.1 fvdl #if AIC_DEBUG_REGISTERS 1402 1.1 fvdl ahd_reg_print_t ahd_reg0_print; 1403 1.1 fvdl #else 1404 1.1 fvdl #define ahd_reg0_print(regvalue, cur_col, wrap) \ 1405 1.1 fvdl ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap) 1406 1.1 fvdl #endif 1407 1.1 fvdl 1408 1.1 fvdl #if AIC_DEBUG_REGISTERS 1409 1.1 fvdl ahd_reg_print_t ahd_df1pcistat_print; 1410 1.1 fvdl #else 1411 1.1 fvdl #define ahd_df1pcistat_print(regvalue, cur_col, wrap) \ 1412 1.1 fvdl ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap) 1413 1.1 fvdl #endif 1414 1.1 fvdl 1415 1.1 fvdl #if AIC_DEBUG_REGISTERS 1416 1.1 fvdl ahd_reg_print_t ahd_sgpcistat_print; 1417 1.1 fvdl #else 1418 1.1 fvdl #define ahd_sgpcistat_print(regvalue, cur_col, wrap) \ 1419 1.1 fvdl ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap) 1420 1.1 fvdl #endif 1421 1.1 fvdl 1422 1.1 fvdl #if AIC_DEBUG_REGISTERS 1423 1.1 fvdl ahd_reg_print_t ahd_reg1_print; 1424 1.1 fvdl #else 1425 1.1 fvdl #define ahd_reg1_print(regvalue, cur_col, wrap) \ 1426 1.1 fvdl ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap) 1427 1.1 fvdl #endif 1428 1.1 fvdl 1429 1.1 fvdl #if AIC_DEBUG_REGISTERS 1430 1.1 fvdl ahd_reg_print_t ahd_cmcpcistat_print; 1431 1.1 fvdl #else 1432 1.1 fvdl #define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \ 1433 1.1 fvdl ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap) 1434 1.1 fvdl #endif 1435 1.1 fvdl 1436 1.1 fvdl #if AIC_DEBUG_REGISTERS 1437 1.1 fvdl ahd_reg_print_t ahd_ovlypcistat_print; 1438 1.1 fvdl #else 1439 1.1 fvdl #define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \ 1440 1.1 fvdl ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap) 1441 1.1 fvdl #endif 1442 1.1 fvdl 1443 1.1 fvdl #if AIC_DEBUG_REGISTERS 1444 1.1 fvdl ahd_reg_print_t ahd_reg_isr_print; 1445 1.1 fvdl #else 1446 1.1 fvdl #define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 1447 1.1 fvdl ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap) 1448 1.1 fvdl #endif 1449 1.1 fvdl 1450 1.1 fvdl #if AIC_DEBUG_REGISTERS 1451 1.1 fvdl ahd_reg_print_t ahd_msipcistat_print; 1452 1.1 fvdl #else 1453 1.1 fvdl #define ahd_msipcistat_print(regvalue, cur_col, wrap) \ 1454 1.1 fvdl ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap) 1455 1.1 fvdl #endif 1456 1.1 fvdl 1457 1.1 fvdl #if AIC_DEBUG_REGISTERS 1458 1.1 fvdl ahd_reg_print_t ahd_sg_state_print; 1459 1.1 fvdl #else 1460 1.1 fvdl #define ahd_sg_state_print(regvalue, cur_col, wrap) \ 1461 1.1 fvdl ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap) 1462 1.1 fvdl #endif 1463 1.1 fvdl 1464 1.1 fvdl #if AIC_DEBUG_REGISTERS 1465 1.1 fvdl ahd_reg_print_t ahd_data_count_odd_print; 1466 1.1 fvdl #else 1467 1.1 fvdl #define ahd_data_count_odd_print(regvalue, cur_col, wrap) \ 1468 1.1 fvdl ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap) 1469 1.1 fvdl #endif 1470 1.1 fvdl 1471 1.1 fvdl #if AIC_DEBUG_REGISTERS 1472 1.1 fvdl ahd_reg_print_t ahd_targpcistat_print; 1473 1.1 fvdl #else 1474 1.1 fvdl #define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 1475 1.1 fvdl ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap) 1476 1.1 fvdl #endif 1477 1.1 fvdl 1478 1.1 fvdl #if AIC_DEBUG_REGISTERS 1479 1.1 fvdl ahd_reg_print_t ahd_scbptr_print; 1480 1.1 fvdl #else 1481 1.1 fvdl #define ahd_scbptr_print(regvalue, cur_col, wrap) \ 1482 1.1 fvdl ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap) 1483 1.1 fvdl #endif 1484 1.1 fvdl 1485 1.1 fvdl #if AIC_DEBUG_REGISTERS 1486 1.1 fvdl ahd_reg_print_t ahd_scbautoptr_print; 1487 1.1 fvdl #else 1488 1.1 fvdl #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 1489 1.1 fvdl ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap) 1490 1.1 fvdl #endif 1491 1.1 fvdl 1492 1.1 fvdl #if AIC_DEBUG_REGISTERS 1493 1.1 fvdl ahd_reg_print_t ahd_ccscbacnt_print; 1494 1.1 fvdl #else 1495 1.1 fvdl #define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \ 1496 1.1 fvdl ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap) 1497 1.1 fvdl #endif 1498 1.1 fvdl 1499 1.1 fvdl #if AIC_DEBUG_REGISTERS 1500 1.1 fvdl ahd_reg_print_t ahd_ccscbaddr_print; 1501 1.1 fvdl #else 1502 1.1 fvdl #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 1503 1.1 fvdl ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap) 1504 1.1 fvdl #endif 1505 1.1 fvdl 1506 1.1 fvdl #if AIC_DEBUG_REGISTERS 1507 1.1 fvdl ahd_reg_print_t ahd_ccscbadr_bk_print; 1508 1.1 fvdl #else 1509 1.1 fvdl #define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \ 1510 1.1 fvdl ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap) 1511 1.1 fvdl #endif 1512 1.1 fvdl 1513 1.1 fvdl #if AIC_DEBUG_REGISTERS 1514 1.1 fvdl ahd_reg_print_t ahd_ccsgaddr_print; 1515 1.1 fvdl #else 1516 1.1 fvdl #define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \ 1517 1.1 fvdl ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap) 1518 1.1 fvdl #endif 1519 1.1 fvdl 1520 1.1 fvdl #if AIC_DEBUG_REGISTERS 1521 1.1 fvdl ahd_reg_print_t ahd_ccscbctl_print; 1522 1.1 fvdl #else 1523 1.1 fvdl #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 1524 1.1 fvdl ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap) 1525 1.1 fvdl #endif 1526 1.1 fvdl 1527 1.1 fvdl #if AIC_DEBUG_REGISTERS 1528 1.1 fvdl ahd_reg_print_t ahd_ccsgctl_print; 1529 1.1 fvdl #else 1530 1.1 fvdl #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \ 1531 1.1 fvdl ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap) 1532 1.1 fvdl #endif 1533 1.1 fvdl 1534 1.1 fvdl #if AIC_DEBUG_REGISTERS 1535 1.1 fvdl ahd_reg_print_t ahd_cmc_rambist_print; 1536 1.1 fvdl #else 1537 1.1 fvdl #define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \ 1538 1.1 fvdl ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap) 1539 1.1 fvdl #endif 1540 1.1 fvdl 1541 1.1 fvdl #if AIC_DEBUG_REGISTERS 1542 1.1 fvdl ahd_reg_print_t ahd_ccsgram_print; 1543 1.1 fvdl #else 1544 1.1 fvdl #define ahd_ccsgram_print(regvalue, cur_col, wrap) \ 1545 1.1 fvdl ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap) 1546 1.1 fvdl #endif 1547 1.1 fvdl 1548 1.1 fvdl #if AIC_DEBUG_REGISTERS 1549 1.1 fvdl ahd_reg_print_t ahd_ccscbram_print; 1550 1.1 fvdl #else 1551 1.1 fvdl #define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 1552 1.1 fvdl ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap) 1553 1.1 fvdl #endif 1554 1.1 fvdl 1555 1.1 fvdl #if AIC_DEBUG_REGISTERS 1556 1.1 fvdl ahd_reg_print_t ahd_flexadr_print; 1557 1.1 fvdl #else 1558 1.1 fvdl #define ahd_flexadr_print(regvalue, cur_col, wrap) \ 1559 1.1 fvdl ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap) 1560 1.1 fvdl #endif 1561 1.1 fvdl 1562 1.1 fvdl #if AIC_DEBUG_REGISTERS 1563 1.1 fvdl ahd_reg_print_t ahd_flexcnt_print; 1564 1.1 fvdl #else 1565 1.1 fvdl #define ahd_flexcnt_print(regvalue, cur_col, wrap) \ 1566 1.1 fvdl ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap) 1567 1.1 fvdl #endif 1568 1.1 fvdl 1569 1.1 fvdl #if AIC_DEBUG_REGISTERS 1570 1.1 fvdl ahd_reg_print_t ahd_flexdmastat_print; 1571 1.1 fvdl #else 1572 1.1 fvdl #define ahd_flexdmastat_print(regvalue, cur_col, wrap) \ 1573 1.1 fvdl ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap) 1574 1.1 fvdl #endif 1575 1.1 fvdl 1576 1.1 fvdl #if AIC_DEBUG_REGISTERS 1577 1.1 fvdl ahd_reg_print_t ahd_flexdata_print; 1578 1.1 fvdl #else 1579 1.1 fvdl #define ahd_flexdata_print(regvalue, cur_col, wrap) \ 1580 1.1 fvdl ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap) 1581 1.1 fvdl #endif 1582 1.1 fvdl 1583 1.1 fvdl #if AIC_DEBUG_REGISTERS 1584 1.1 fvdl ahd_reg_print_t ahd_brddat_print; 1585 1.1 fvdl #else 1586 1.1 fvdl #define ahd_brddat_print(regvalue, cur_col, wrap) \ 1587 1.1 fvdl ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap) 1588 1.1 fvdl #endif 1589 1.1 fvdl 1590 1.1 fvdl #if AIC_DEBUG_REGISTERS 1591 1.1 fvdl ahd_reg_print_t ahd_brdctl_print; 1592 1.1 fvdl #else 1593 1.1 fvdl #define ahd_brdctl_print(regvalue, cur_col, wrap) \ 1594 1.1 fvdl ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap) 1595 1.1 fvdl #endif 1596 1.1 fvdl 1597 1.1 fvdl #if AIC_DEBUG_REGISTERS 1598 1.1 fvdl ahd_reg_print_t ahd_seeadr_print; 1599 1.1 fvdl #else 1600 1.1 fvdl #define ahd_seeadr_print(regvalue, cur_col, wrap) \ 1601 1.1 fvdl ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap) 1602 1.1 fvdl #endif 1603 1.1 fvdl 1604 1.1 fvdl #if AIC_DEBUG_REGISTERS 1605 1.1 fvdl ahd_reg_print_t ahd_seedat_print; 1606 1.1 fvdl #else 1607 1.1 fvdl #define ahd_seedat_print(regvalue, cur_col, wrap) \ 1608 1.1 fvdl ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap) 1609 1.1 fvdl #endif 1610 1.1 fvdl 1611 1.1 fvdl #if AIC_DEBUG_REGISTERS 1612 1.1 fvdl ahd_reg_print_t ahd_seectl_print; 1613 1.1 fvdl #else 1614 1.1 fvdl #define ahd_seectl_print(regvalue, cur_col, wrap) \ 1615 1.1 fvdl ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap) 1616 1.1 fvdl #endif 1617 1.1 fvdl 1618 1.1 fvdl #if AIC_DEBUG_REGISTERS 1619 1.1 fvdl ahd_reg_print_t ahd_seestat_print; 1620 1.1 fvdl #else 1621 1.1 fvdl #define ahd_seestat_print(regvalue, cur_col, wrap) \ 1622 1.1 fvdl ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap) 1623 1.1 fvdl #endif 1624 1.1 fvdl 1625 1.1 fvdl #if AIC_DEBUG_REGISTERS 1626 1.1 fvdl ahd_reg_print_t ahd_scbcnt_print; 1627 1.1 fvdl #else 1628 1.1 fvdl #define ahd_scbcnt_print(regvalue, cur_col, wrap) \ 1629 1.1 fvdl ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap) 1630 1.1 fvdl #endif 1631 1.1 fvdl 1632 1.1 fvdl #if AIC_DEBUG_REGISTERS 1633 1.1 fvdl ahd_reg_print_t ahd_dspfltrctl_print; 1634 1.1 fvdl #else 1635 1.1 fvdl #define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \ 1636 1.1 fvdl ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap) 1637 1.1 fvdl #endif 1638 1.1 fvdl 1639 1.1 fvdl #if AIC_DEBUG_REGISTERS 1640 1.1 fvdl ahd_reg_print_t ahd_dfwaddr_print; 1641 1.1 fvdl #else 1642 1.1 fvdl #define ahd_dfwaddr_print(regvalue, cur_col, wrap) \ 1643 1.1 fvdl ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap) 1644 1.1 fvdl #endif 1645 1.1 fvdl 1646 1.1 fvdl #if AIC_DEBUG_REGISTERS 1647 1.1 fvdl ahd_reg_print_t ahd_dspdatactl_print; 1648 1.1 fvdl #else 1649 1.1 fvdl #define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 1650 1.1 fvdl ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap) 1651 1.1 fvdl #endif 1652 1.1 fvdl 1653 1.1 fvdl #if AIC_DEBUG_REGISTERS 1654 1.1 fvdl ahd_reg_print_t ahd_dspreqctl_print; 1655 1.1 fvdl #else 1656 1.1 fvdl #define ahd_dspreqctl_print(regvalue, cur_col, wrap) \ 1657 1.1 fvdl ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap) 1658 1.1 fvdl #endif 1659 1.1 fvdl 1660 1.1 fvdl #if AIC_DEBUG_REGISTERS 1661 1.1 fvdl ahd_reg_print_t ahd_dfraddr_print; 1662 1.1 fvdl #else 1663 1.1 fvdl #define ahd_dfraddr_print(regvalue, cur_col, wrap) \ 1664 1.1 fvdl ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap) 1665 1.1 fvdl #endif 1666 1.1 fvdl 1667 1.1 fvdl #if AIC_DEBUG_REGISTERS 1668 1.1 fvdl ahd_reg_print_t ahd_dspackctl_print; 1669 1.1 fvdl #else 1670 1.1 fvdl #define ahd_dspackctl_print(regvalue, cur_col, wrap) \ 1671 1.1 fvdl ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap) 1672 1.1 fvdl #endif 1673 1.1 fvdl 1674 1.1 fvdl #if AIC_DEBUG_REGISTERS 1675 1.1 fvdl ahd_reg_print_t ahd_dfdat_print; 1676 1.1 fvdl #else 1677 1.1 fvdl #define ahd_dfdat_print(regvalue, cur_col, wrap) \ 1678 1.1 fvdl ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap) 1679 1.1 fvdl #endif 1680 1.1 fvdl 1681 1.1 fvdl #if AIC_DEBUG_REGISTERS 1682 1.1 fvdl ahd_reg_print_t ahd_dspselect_print; 1683 1.1 fvdl #else 1684 1.1 fvdl #define ahd_dspselect_print(regvalue, cur_col, wrap) \ 1685 1.1 fvdl ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap) 1686 1.1 fvdl #endif 1687 1.1 fvdl 1688 1.1 fvdl #if AIC_DEBUG_REGISTERS 1689 1.1 fvdl ahd_reg_print_t ahd_wrtbiasctl_print; 1690 1.1 fvdl #else 1691 1.1 fvdl #define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \ 1692 1.1 fvdl ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap) 1693 1.1 fvdl #endif 1694 1.1 fvdl 1695 1.1 fvdl #if AIC_DEBUG_REGISTERS 1696 1.1 fvdl ahd_reg_print_t ahd_rcvrbiosctl_print; 1697 1.1 fvdl #else 1698 1.1 fvdl #define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \ 1699 1.1 fvdl ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap) 1700 1.1 fvdl #endif 1701 1.1 fvdl 1702 1.1 fvdl #if AIC_DEBUG_REGISTERS 1703 1.1 fvdl ahd_reg_print_t ahd_wrtbiascalc_print; 1704 1.1 fvdl #else 1705 1.1 fvdl #define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \ 1706 1.1 fvdl ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap) 1707 1.1 fvdl #endif 1708 1.1 fvdl 1709 1.1 fvdl #if AIC_DEBUG_REGISTERS 1710 1.1 fvdl ahd_reg_print_t ahd_dfptrs_print; 1711 1.1 fvdl #else 1712 1.1 fvdl #define ahd_dfptrs_print(regvalue, cur_col, wrap) \ 1713 1.1 fvdl ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap) 1714 1.1 fvdl #endif 1715 1.1 fvdl 1716 1.1 fvdl #if AIC_DEBUG_REGISTERS 1717 1.1 fvdl ahd_reg_print_t ahd_rcvrbiascalc_print; 1718 1.1 fvdl #else 1719 1.1 fvdl #define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \ 1720 1.1 fvdl ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap) 1721 1.1 fvdl #endif 1722 1.1 fvdl 1723 1.1 fvdl #if AIC_DEBUG_REGISTERS 1724 1.1 fvdl ahd_reg_print_t ahd_dfbkptr_print; 1725 1.1 fvdl #else 1726 1.1 fvdl #define ahd_dfbkptr_print(regvalue, cur_col, wrap) \ 1727 1.1 fvdl ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap) 1728 1.1 fvdl #endif 1729 1.1 fvdl 1730 1.1 fvdl #if AIC_DEBUG_REGISTERS 1731 1.1 fvdl ahd_reg_print_t ahd_skewcalc_print; 1732 1.1 fvdl #else 1733 1.1 fvdl #define ahd_skewcalc_print(regvalue, cur_col, wrap) \ 1734 1.1 fvdl ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap) 1735 1.1 fvdl #endif 1736 1.1 fvdl 1737 1.1 fvdl #if AIC_DEBUG_REGISTERS 1738 1.1 fvdl ahd_reg_print_t ahd_dfdbctl_print; 1739 1.1 fvdl #else 1740 1.1 fvdl #define ahd_dfdbctl_print(regvalue, cur_col, wrap) \ 1741 1.1 fvdl ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap) 1742 1.1 fvdl #endif 1743 1.1 fvdl 1744 1.1 fvdl #if AIC_DEBUG_REGISTERS 1745 1.1 fvdl ahd_reg_print_t ahd_dfscnt_print; 1746 1.1 fvdl #else 1747 1.1 fvdl #define ahd_dfscnt_print(regvalue, cur_col, wrap) \ 1748 1.1 fvdl ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap) 1749 1.1 fvdl #endif 1750 1.1 fvdl 1751 1.1 fvdl #if AIC_DEBUG_REGISTERS 1752 1.1 fvdl ahd_reg_print_t ahd_dfbcnt_print; 1753 1.1 fvdl #else 1754 1.1 fvdl #define ahd_dfbcnt_print(regvalue, cur_col, wrap) \ 1755 1.1 fvdl ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap) 1756 1.1 fvdl #endif 1757 1.1 fvdl 1758 1.1 fvdl #if AIC_DEBUG_REGISTERS 1759 1.1 fvdl ahd_reg_print_t ahd_ovlyaddr_print; 1760 1.1 fvdl #else 1761 1.1 fvdl #define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \ 1762 1.1 fvdl ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap) 1763 1.1 fvdl #endif 1764 1.1 fvdl 1765 1.1 fvdl #if AIC_DEBUG_REGISTERS 1766 1.1 fvdl ahd_reg_print_t ahd_seqctl0_print; 1767 1.1 fvdl #else 1768 1.1 fvdl #define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 1769 1.1 fvdl ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap) 1770 1.1 fvdl #endif 1771 1.1 fvdl 1772 1.1 fvdl #if AIC_DEBUG_REGISTERS 1773 1.1 fvdl ahd_reg_print_t ahd_seqctl1_print; 1774 1.1 fvdl #else 1775 1.1 fvdl #define ahd_seqctl1_print(regvalue, cur_col, wrap) \ 1776 1.1 fvdl ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap) 1777 1.1 fvdl #endif 1778 1.1 fvdl 1779 1.1 fvdl #if AIC_DEBUG_REGISTERS 1780 1.1 fvdl ahd_reg_print_t ahd_flags_print; 1781 1.1 fvdl #else 1782 1.1 fvdl #define ahd_flags_print(regvalue, cur_col, wrap) \ 1783 1.1 fvdl ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap) 1784 1.1 fvdl #endif 1785 1.1 fvdl 1786 1.1 fvdl #if AIC_DEBUG_REGISTERS 1787 1.1 fvdl ahd_reg_print_t ahd_seqintctl_print; 1788 1.1 fvdl #else 1789 1.1 fvdl #define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 1790 1.1 fvdl ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap) 1791 1.1 fvdl #endif 1792 1.1 fvdl 1793 1.1 fvdl #if AIC_DEBUG_REGISTERS 1794 1.1 fvdl ahd_reg_print_t ahd_seqram_print; 1795 1.1 fvdl #else 1796 1.1 fvdl #define ahd_seqram_print(regvalue, cur_col, wrap) \ 1797 1.1 fvdl ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap) 1798 1.1 fvdl #endif 1799 1.1 fvdl 1800 1.1 fvdl #if AIC_DEBUG_REGISTERS 1801 1.1 fvdl ahd_reg_print_t ahd_prgmcnt_print; 1802 1.1 fvdl #else 1803 1.1 fvdl #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 1804 1.1 fvdl ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap) 1805 1.1 fvdl #endif 1806 1.1 fvdl 1807 1.1 fvdl #if AIC_DEBUG_REGISTERS 1808 1.1 fvdl ahd_reg_print_t ahd_accum_print; 1809 1.1 fvdl #else 1810 1.1 fvdl #define ahd_accum_print(regvalue, cur_col, wrap) \ 1811 1.1 fvdl ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap) 1812 1.1 fvdl #endif 1813 1.1 fvdl 1814 1.1 fvdl #if AIC_DEBUG_REGISTERS 1815 1.1 fvdl ahd_reg_print_t ahd_sindex_print; 1816 1.1 fvdl #else 1817 1.1 fvdl #define ahd_sindex_print(regvalue, cur_col, wrap) \ 1818 1.1 fvdl ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap) 1819 1.1 fvdl #endif 1820 1.1 fvdl 1821 1.1 fvdl #if AIC_DEBUG_REGISTERS 1822 1.1 fvdl ahd_reg_print_t ahd_dindex_print; 1823 1.1 fvdl #else 1824 1.1 fvdl #define ahd_dindex_print(regvalue, cur_col, wrap) \ 1825 1.1 fvdl ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap) 1826 1.1 fvdl #endif 1827 1.1 fvdl 1828 1.1 fvdl #if AIC_DEBUG_REGISTERS 1829 1.1 fvdl ahd_reg_print_t ahd_brkaddr0_print; 1830 1.1 fvdl #else 1831 1.1 fvdl #define ahd_brkaddr0_print(regvalue, cur_col, wrap) \ 1832 1.1 fvdl ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap) 1833 1.1 fvdl #endif 1834 1.1 fvdl 1835 1.1 fvdl #if AIC_DEBUG_REGISTERS 1836 1.1 fvdl ahd_reg_print_t ahd_brkaddr1_print; 1837 1.1 fvdl #else 1838 1.1 fvdl #define ahd_brkaddr1_print(regvalue, cur_col, wrap) \ 1839 1.1 fvdl ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap) 1840 1.1 fvdl #endif 1841 1.1 fvdl 1842 1.1 fvdl #if AIC_DEBUG_REGISTERS 1843 1.1 fvdl ahd_reg_print_t ahd_allones_print; 1844 1.1 fvdl #else 1845 1.1 fvdl #define ahd_allones_print(regvalue, cur_col, wrap) \ 1846 1.1 fvdl ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap) 1847 1.1 fvdl #endif 1848 1.1 fvdl 1849 1.1 fvdl #if AIC_DEBUG_REGISTERS 1850 1.1 fvdl ahd_reg_print_t ahd_none_print; 1851 1.1 fvdl #else 1852 1.1 fvdl #define ahd_none_print(regvalue, cur_col, wrap) \ 1853 1.1 fvdl ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap) 1854 1.1 fvdl #endif 1855 1.1 fvdl 1856 1.1 fvdl #if AIC_DEBUG_REGISTERS 1857 1.1 fvdl ahd_reg_print_t ahd_allzeros_print; 1858 1.1 fvdl #else 1859 1.1 fvdl #define ahd_allzeros_print(regvalue, cur_col, wrap) \ 1860 1.1 fvdl ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap) 1861 1.1 fvdl #endif 1862 1.1 fvdl 1863 1.1 fvdl #if AIC_DEBUG_REGISTERS 1864 1.1 fvdl ahd_reg_print_t ahd_sindir_print; 1865 1.1 fvdl #else 1866 1.1 fvdl #define ahd_sindir_print(regvalue, cur_col, wrap) \ 1867 1.1 fvdl ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap) 1868 1.1 fvdl #endif 1869 1.1 fvdl 1870 1.1 fvdl #if AIC_DEBUG_REGISTERS 1871 1.1 fvdl ahd_reg_print_t ahd_dindir_print; 1872 1.1 fvdl #else 1873 1.1 fvdl #define ahd_dindir_print(regvalue, cur_col, wrap) \ 1874 1.1 fvdl ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap) 1875 1.1 fvdl #endif 1876 1.1 fvdl 1877 1.1 fvdl #if AIC_DEBUG_REGISTERS 1878 1.1 fvdl ahd_reg_print_t ahd_function1_print; 1879 1.1 fvdl #else 1880 1.1 fvdl #define ahd_function1_print(regvalue, cur_col, wrap) \ 1881 1.1 fvdl ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap) 1882 1.1 fvdl #endif 1883 1.1 fvdl 1884 1.1 fvdl #if AIC_DEBUG_REGISTERS 1885 1.1 fvdl ahd_reg_print_t ahd_stack_print; 1886 1.1 fvdl #else 1887 1.1 fvdl #define ahd_stack_print(regvalue, cur_col, wrap) \ 1888 1.1 fvdl ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap) 1889 1.1 fvdl #endif 1890 1.1 fvdl 1891 1.1 fvdl #if AIC_DEBUG_REGISTERS 1892 1.1 fvdl ahd_reg_print_t ahd_intvec1_addr_print; 1893 1.1 fvdl #else 1894 1.1 fvdl #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 1895 1.1 fvdl ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap) 1896 1.1 fvdl #endif 1897 1.1 fvdl 1898 1.1 fvdl #if AIC_DEBUG_REGISTERS 1899 1.1 fvdl ahd_reg_print_t ahd_curaddr_print; 1900 1.1 fvdl #else 1901 1.1 fvdl #define ahd_curaddr_print(regvalue, cur_col, wrap) \ 1902 1.1 fvdl ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap) 1903 1.1 fvdl #endif 1904 1.1 fvdl 1905 1.1 fvdl #if AIC_DEBUG_REGISTERS 1906 1.1 fvdl ahd_reg_print_t ahd_lastaddr_print; 1907 1.1 fvdl #else 1908 1.1 fvdl #define ahd_lastaddr_print(regvalue, cur_col, wrap) \ 1909 1.1 fvdl ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap) 1910 1.1 fvdl #endif 1911 1.1 fvdl 1912 1.1 fvdl #if AIC_DEBUG_REGISTERS 1913 1.1 fvdl ahd_reg_print_t ahd_intvec2_addr_print; 1914 1.1 fvdl #else 1915 1.1 fvdl #define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1916 1.1 fvdl ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap) 1917 1.1 fvdl #endif 1918 1.1 fvdl 1919 1.1 fvdl #if AIC_DEBUG_REGISTERS 1920 1.1 fvdl ahd_reg_print_t ahd_longjmp_addr_print; 1921 1.1 fvdl #else 1922 1.1 fvdl #define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \ 1923 1.1 fvdl ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap) 1924 1.1 fvdl #endif 1925 1.1 fvdl 1926 1.1 fvdl #if AIC_DEBUG_REGISTERS 1927 1.1 fvdl ahd_reg_print_t ahd_accum_save_print; 1928 1.1 fvdl #else 1929 1.1 fvdl #define ahd_accum_save_print(regvalue, cur_col, wrap) \ 1930 1.3.2.1 skrll ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap) 1931 1.1 fvdl #endif 1932 1.1 fvdl 1933 1.1 fvdl #if AIC_DEBUG_REGISTERS 1934 1.1 fvdl ahd_reg_print_t ahd_ahd_pci_config_base_print; 1935 1.1 fvdl #else 1936 1.1 fvdl #define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1937 1.1 fvdl ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1938 1.1 fvdl #endif 1939 1.1 fvdl 1940 1.1 fvdl #if AIC_DEBUG_REGISTERS 1941 1.1 fvdl ahd_reg_print_t ahd_sram_base_print; 1942 1.1 fvdl #else 1943 1.1 fvdl #define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1944 1.1 fvdl ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1945 1.1 fvdl #endif 1946 1.1 fvdl 1947 1.1 fvdl #if AIC_DEBUG_REGISTERS 1948 1.1 fvdl ahd_reg_print_t ahd_waiting_scb_tails_print; 1949 1.1 fvdl #else 1950 1.1 fvdl #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 1951 1.1 fvdl ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 1952 1.1 fvdl #endif 1953 1.1 fvdl 1954 1.1 fvdl #if AIC_DEBUG_REGISTERS 1955 1.1 fvdl ahd_reg_print_t ahd_waiting_tid_head_print; 1956 1.1 fvdl #else 1957 1.1 fvdl #define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \ 1958 1.1 fvdl ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap) 1959 1.1 fvdl #endif 1960 1.1 fvdl 1961 1.1 fvdl #if AIC_DEBUG_REGISTERS 1962 1.1 fvdl ahd_reg_print_t ahd_waiting_tid_tail_print; 1963 1.1 fvdl #else 1964 1.1 fvdl #define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \ 1965 1.1 fvdl ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap) 1966 1.1 fvdl #endif 1967 1.1 fvdl 1968 1.1 fvdl #if AIC_DEBUG_REGISTERS 1969 1.1 fvdl ahd_reg_print_t ahd_next_queued_scb_addr_print; 1970 1.1 fvdl #else 1971 1.1 fvdl #define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \ 1972 1.1 fvdl ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap) 1973 1.1 fvdl #endif 1974 1.1 fvdl 1975 1.1 fvdl #if AIC_DEBUG_REGISTERS 1976 1.1 fvdl ahd_reg_print_t ahd_complete_scb_head_print; 1977 1.1 fvdl #else 1978 1.1 fvdl #define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \ 1979 1.1 fvdl ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap) 1980 1.1 fvdl #endif 1981 1.1 fvdl 1982 1.1 fvdl #if AIC_DEBUG_REGISTERS 1983 1.1 fvdl ahd_reg_print_t ahd_complete_scb_dmainprog_head_print; 1984 1.1 fvdl #else 1985 1.1 fvdl #define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \ 1986 1.1 fvdl ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap) 1987 1.1 fvdl #endif 1988 1.1 fvdl 1989 1.1 fvdl #if AIC_DEBUG_REGISTERS 1990 1.1 fvdl ahd_reg_print_t ahd_complete_dma_scb_head_print; 1991 1.1 fvdl #else 1992 1.1 fvdl #define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \ 1993 1.1 fvdl ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap) 1994 1.1 fvdl #endif 1995 1.1 fvdl 1996 1.1 fvdl #if AIC_DEBUG_REGISTERS 1997 1.1 fvdl ahd_reg_print_t ahd_qfreeze_count_print; 1998 1.1 fvdl #else 1999 1.1 fvdl #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \ 2000 1.1 fvdl ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x12e, regvalue, cur_col, wrap) 2001 1.1 fvdl #endif 2002 1.1 fvdl 2003 1.1 fvdl #if AIC_DEBUG_REGISTERS 2004 1.1 fvdl ahd_reg_print_t ahd_saved_mode_print; 2005 1.1 fvdl #else 2006 1.1 fvdl #define ahd_saved_mode_print(regvalue, cur_col, wrap) \ 2007 1.1 fvdl ahd_print_register(NULL, 0, "SAVED_MODE", 0x130, regvalue, cur_col, wrap) 2008 1.1 fvdl #endif 2009 1.1 fvdl 2010 1.1 fvdl #if AIC_DEBUG_REGISTERS 2011 1.1 fvdl ahd_reg_print_t ahd_msg_out_print; 2012 1.1 fvdl #else 2013 1.1 fvdl #define ahd_msg_out_print(regvalue, cur_col, wrap) \ 2014 1.1 fvdl ahd_print_register(NULL, 0, "MSG_OUT", 0x131, regvalue, cur_col, wrap) 2015 1.1 fvdl #endif 2016 1.1 fvdl 2017 1.1 fvdl #if AIC_DEBUG_REGISTERS 2018 1.1 fvdl ahd_reg_print_t ahd_dmaparams_print; 2019 1.1 fvdl #else 2020 1.1 fvdl #define ahd_dmaparams_print(regvalue, cur_col, wrap) \ 2021 1.1 fvdl ahd_print_register(NULL, 0, "DMAPARAMS", 0x132, regvalue, cur_col, wrap) 2022 1.1 fvdl #endif 2023 1.1 fvdl 2024 1.1 fvdl #if AIC_DEBUG_REGISTERS 2025 1.1 fvdl ahd_reg_print_t ahd_seq_flags_print; 2026 1.1 fvdl #else 2027 1.1 fvdl #define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 2028 1.1 fvdl ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x133, regvalue, cur_col, wrap) 2029 1.1 fvdl #endif 2030 1.1 fvdl 2031 1.1 fvdl #if AIC_DEBUG_REGISTERS 2032 1.1 fvdl ahd_reg_print_t ahd_saved_scsiid_print; 2033 1.1 fvdl #else 2034 1.1 fvdl #define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \ 2035 1.1 fvdl ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x134, regvalue, cur_col, wrap) 2036 1.1 fvdl #endif 2037 1.1 fvdl 2038 1.1 fvdl #if AIC_DEBUG_REGISTERS 2039 1.1 fvdl ahd_reg_print_t ahd_saved_lun_print; 2040 1.1 fvdl #else 2041 1.1 fvdl #define ahd_saved_lun_print(regvalue, cur_col, wrap) \ 2042 1.1 fvdl ahd_print_register(NULL, 0, "SAVED_LUN", 0x135, regvalue, cur_col, wrap) 2043 1.1 fvdl #endif 2044 1.1 fvdl 2045 1.1 fvdl #if AIC_DEBUG_REGISTERS 2046 1.1 fvdl ahd_reg_print_t ahd_lastphase_print; 2047 1.1 fvdl #else 2048 1.1 fvdl #define ahd_lastphase_print(regvalue, cur_col, wrap) \ 2049 1.1 fvdl ahd_print_register(NULL, 0, "LASTPHASE", 0x136, regvalue, cur_col, wrap) 2050 1.1 fvdl #endif 2051 1.1 fvdl 2052 1.1 fvdl #if AIC_DEBUG_REGISTERS 2053 1.1 fvdl ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print; 2054 1.1 fvdl #else 2055 1.1 fvdl #define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \ 2056 1.1 fvdl ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x137, regvalue, cur_col, wrap) 2057 1.1 fvdl #endif 2058 1.1 fvdl 2059 1.1 fvdl #if AIC_DEBUG_REGISTERS 2060 1.1 fvdl ahd_reg_print_t ahd_shared_data_addr_print; 2061 1.1 fvdl #else 2062 1.1 fvdl #define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \ 2063 1.1 fvdl ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x138, regvalue, cur_col, wrap) 2064 1.1 fvdl #endif 2065 1.1 fvdl 2066 1.1 fvdl #if AIC_DEBUG_REGISTERS 2067 1.1 fvdl ahd_reg_print_t ahd_qoutfifo_next_addr_print; 2068 1.1 fvdl #else 2069 1.1 fvdl #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 2070 1.1 fvdl ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x13c, regvalue, cur_col, wrap) 2071 1.1 fvdl #endif 2072 1.1 fvdl 2073 1.1 fvdl #if AIC_DEBUG_REGISTERS 2074 1.1 fvdl ahd_reg_print_t ahd_kernel_tqinpos_print; 2075 1.1 fvdl #else 2076 1.1 fvdl #define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 2077 1.1 fvdl ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x140, regvalue, cur_col, wrap) 2078 1.1 fvdl #endif 2079 1.1 fvdl 2080 1.1 fvdl #if AIC_DEBUG_REGISTERS 2081 1.1 fvdl ahd_reg_print_t ahd_tqinpos_print; 2082 1.1 fvdl #else 2083 1.1 fvdl #define ahd_tqinpos_print(regvalue, cur_col, wrap) \ 2084 1.1 fvdl ahd_print_register(NULL, 0, "TQINPOS", 0x141, regvalue, cur_col, wrap) 2085 1.1 fvdl #endif 2086 1.1 fvdl 2087 1.1 fvdl #if AIC_DEBUG_REGISTERS 2088 1.1 fvdl ahd_reg_print_t ahd_arg_1_print; 2089 1.1 fvdl #else 2090 1.1 fvdl #define ahd_arg_1_print(regvalue, cur_col, wrap) \ 2091 1.1 fvdl ahd_print_register(NULL, 0, "ARG_1", 0x142, regvalue, cur_col, wrap) 2092 1.1 fvdl #endif 2093 1.1 fvdl 2094 1.1 fvdl #if AIC_DEBUG_REGISTERS 2095 1.1 fvdl ahd_reg_print_t ahd_arg_2_print; 2096 1.1 fvdl #else 2097 1.1 fvdl #define ahd_arg_2_print(regvalue, cur_col, wrap) \ 2098 1.1 fvdl ahd_print_register(NULL, 0, "ARG_2", 0x143, regvalue, cur_col, wrap) 2099 1.1 fvdl #endif 2100 1.1 fvdl 2101 1.1 fvdl #if AIC_DEBUG_REGISTERS 2102 1.1 fvdl ahd_reg_print_t ahd_last_msg_print; 2103 1.1 fvdl #else 2104 1.1 fvdl #define ahd_last_msg_print(regvalue, cur_col, wrap) \ 2105 1.1 fvdl ahd_print_register(NULL, 0, "LAST_MSG", 0x144, regvalue, cur_col, wrap) 2106 1.1 fvdl #endif 2107 1.1 fvdl 2108 1.1 fvdl #if AIC_DEBUG_REGISTERS 2109 1.1 fvdl ahd_reg_print_t ahd_scsiseq_template_print; 2110 1.1 fvdl #else 2111 1.1 fvdl #define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \ 2112 1.1 fvdl ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x145, regvalue, cur_col, wrap) 2113 1.1 fvdl #endif 2114 1.1 fvdl 2115 1.1 fvdl #if AIC_DEBUG_REGISTERS 2116 1.1 fvdl ahd_reg_print_t ahd_initiator_tag_print; 2117 1.1 fvdl #else 2118 1.1 fvdl #define ahd_initiator_tag_print(regvalue, cur_col, wrap) \ 2119 1.1 fvdl ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x146, regvalue, cur_col, wrap) 2120 1.1 fvdl #endif 2121 1.1 fvdl 2122 1.1 fvdl #if AIC_DEBUG_REGISTERS 2123 1.1 fvdl ahd_reg_print_t ahd_seq_flags2_print; 2124 1.1 fvdl #else 2125 1.1 fvdl #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \ 2126 1.1 fvdl ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x147, regvalue, cur_col, wrap) 2127 1.1 fvdl #endif 2128 1.1 fvdl 2129 1.1 fvdl #if AIC_DEBUG_REGISTERS 2130 1.1 fvdl ahd_reg_print_t ahd_allocfifo_scbptr_print; 2131 1.1 fvdl #else 2132 1.1 fvdl #define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \ 2133 1.1 fvdl ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x148, regvalue, cur_col, wrap) 2134 1.1 fvdl #endif 2135 1.1 fvdl 2136 1.1 fvdl #if AIC_DEBUG_REGISTERS 2137 1.3 wiz ahd_reg_print_t ahd_int_coalescing_timer_print; 2138 1.1 fvdl #else 2139 1.3 wiz #define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \ 2140 1.3 wiz ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x14a, regvalue, cur_col, wrap) 2141 1.1 fvdl #endif 2142 1.1 fvdl 2143 1.1 fvdl #if AIC_DEBUG_REGISTERS 2144 1.3 wiz ahd_reg_print_t ahd_int_coalescing_maxcmds_print; 2145 1.1 fvdl #else 2146 1.3 wiz #define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \ 2147 1.3 wiz ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x14c, regvalue, cur_col, wrap) 2148 1.1 fvdl #endif 2149 1.1 fvdl 2150 1.1 fvdl #if AIC_DEBUG_REGISTERS 2151 1.3 wiz ahd_reg_print_t ahd_int_coalescing_mincmds_print; 2152 1.1 fvdl #else 2153 1.3 wiz #define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \ 2154 1.3 wiz ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x14d, regvalue, cur_col, wrap) 2155 1.1 fvdl #endif 2156 1.1 fvdl 2157 1.1 fvdl #if AIC_DEBUG_REGISTERS 2158 1.1 fvdl ahd_reg_print_t ahd_cmds_pending_print; 2159 1.1 fvdl #else 2160 1.1 fvdl #define ahd_cmds_pending_print(regvalue, cur_col, wrap) \ 2161 1.1 fvdl ahd_print_register(NULL, 0, "CMDS_PENDING", 0x14e, regvalue, cur_col, wrap) 2162 1.1 fvdl #endif 2163 1.1 fvdl 2164 1.1 fvdl #if AIC_DEBUG_REGISTERS 2165 1.3 wiz ahd_reg_print_t ahd_int_coalescing_cmdcount_print; 2166 1.1 fvdl #else 2167 1.3 wiz #define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \ 2168 1.3 wiz ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x150, regvalue, cur_col, wrap) 2169 1.1 fvdl #endif 2170 1.1 fvdl 2171 1.1 fvdl #if AIC_DEBUG_REGISTERS 2172 1.1 fvdl ahd_reg_print_t ahd_local_hs_mailbox_print; 2173 1.1 fvdl #else 2174 1.1 fvdl #define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \ 2175 1.1 fvdl ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x151, regvalue, cur_col, wrap) 2176 1.1 fvdl #endif 2177 1.1 fvdl 2178 1.1 fvdl #if AIC_DEBUG_REGISTERS 2179 1.1 fvdl ahd_reg_print_t ahd_cmdsize_table_print; 2180 1.1 fvdl #else 2181 1.1 fvdl #define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \ 2182 1.1 fvdl ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x152, regvalue, cur_col, wrap) 2183 1.1 fvdl #endif 2184 1.1 fvdl 2185 1.1 fvdl #if AIC_DEBUG_REGISTERS 2186 1.1 fvdl ahd_reg_print_t ahd_scb_base_print; 2187 1.1 fvdl #else 2188 1.1 fvdl #define ahd_scb_base_print(regvalue, cur_col, wrap) \ 2189 1.1 fvdl ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 2190 1.1 fvdl #endif 2191 1.1 fvdl 2192 1.1 fvdl #if AIC_DEBUG_REGISTERS 2193 1.1 fvdl ahd_reg_print_t ahd_scb_residual_datacnt_print; 2194 1.1 fvdl #else 2195 1.1 fvdl #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 2196 1.1 fvdl ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 2197 1.1 fvdl #endif 2198 1.1 fvdl 2199 1.1 fvdl #if AIC_DEBUG_REGISTERS 2200 1.1 fvdl ahd_reg_print_t ahd_scb_residual_sgptr_print; 2201 1.1 fvdl #else 2202 1.1 fvdl #define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 2203 1.1 fvdl ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap) 2204 1.1 fvdl #endif 2205 1.1 fvdl 2206 1.1 fvdl #if AIC_DEBUG_REGISTERS 2207 1.1 fvdl ahd_reg_print_t ahd_scb_scsi_status_print; 2208 1.1 fvdl #else 2209 1.1 fvdl #define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 2210 1.1 fvdl ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 2211 1.1 fvdl #endif 2212 1.1 fvdl 2213 1.1 fvdl #if AIC_DEBUG_REGISTERS 2214 1.1 fvdl ahd_reg_print_t ahd_scb_target_phases_print; 2215 1.1 fvdl #else 2216 1.1 fvdl #define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \ 2217 1.1 fvdl ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap) 2218 1.1 fvdl #endif 2219 1.1 fvdl 2220 1.1 fvdl #if AIC_DEBUG_REGISTERS 2221 1.1 fvdl ahd_reg_print_t ahd_scb_target_data_dir_print; 2222 1.1 fvdl #else 2223 1.1 fvdl #define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 2224 1.1 fvdl ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap) 2225 1.1 fvdl #endif 2226 1.1 fvdl 2227 1.1 fvdl #if AIC_DEBUG_REGISTERS 2228 1.1 fvdl ahd_reg_print_t ahd_scb_target_itag_print; 2229 1.1 fvdl #else 2230 1.1 fvdl #define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \ 2231 1.1 fvdl ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap) 2232 1.1 fvdl #endif 2233 1.1 fvdl 2234 1.1 fvdl #if AIC_DEBUG_REGISTERS 2235 1.1 fvdl ahd_reg_print_t ahd_scb_sense_busaddr_print; 2236 1.1 fvdl #else 2237 1.1 fvdl #define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 2238 1.1 fvdl ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap) 2239 1.1 fvdl #endif 2240 1.1 fvdl 2241 1.1 fvdl #if AIC_DEBUG_REGISTERS 2242 1.1 fvdl ahd_reg_print_t ahd_scb_tag_print; 2243 1.1 fvdl #else 2244 1.1 fvdl #define ahd_scb_tag_print(regvalue, cur_col, wrap) \ 2245 1.1 fvdl ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap) 2246 1.1 fvdl #endif 2247 1.1 fvdl 2248 1.1 fvdl #if AIC_DEBUG_REGISTERS 2249 1.3.2.1 skrll ahd_reg_print_t ahd_scb_control_print; 2250 1.1 fvdl #else 2251 1.3.2.1 skrll #define ahd_scb_control_print(regvalue, cur_col, wrap) \ 2252 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap) 2253 1.1 fvdl #endif 2254 1.1 fvdl 2255 1.1 fvdl #if AIC_DEBUG_REGISTERS 2256 1.3.2.1 skrll ahd_reg_print_t ahd_scb_scsiid_print; 2257 1.1 fvdl #else 2258 1.3.2.1 skrll #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \ 2259 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap) 2260 1.1 fvdl #endif 2261 1.1 fvdl 2262 1.1 fvdl #if AIC_DEBUG_REGISTERS 2263 1.3.2.1 skrll ahd_reg_print_t ahd_scb_lun_print; 2264 1.1 fvdl #else 2265 1.3.2.1 skrll #define ahd_scb_lun_print(regvalue, cur_col, wrap) \ 2266 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap) 2267 1.1 fvdl #endif 2268 1.1 fvdl 2269 1.1 fvdl #if AIC_DEBUG_REGISTERS 2270 1.3.2.1 skrll ahd_reg_print_t ahd_scb_task_attribute_print; 2271 1.1 fvdl #else 2272 1.3.2.1 skrll #define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \ 2273 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap) 2274 1.3.2.1 skrll #endif 2275 1.3.2.1 skrll 2276 1.3.2.1 skrll #if AIC_DEBUG_REGISTERS 2277 1.3.2.1 skrll ahd_reg_print_t ahd_scb_cdb_len_print; 2278 1.3.2.1 skrll #else 2279 1.3.2.1 skrll #define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \ 2280 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap) 2281 1.3.2.1 skrll #endif 2282 1.3.2.1 skrll 2283 1.3.2.1 skrll #if AIC_DEBUG_REGISTERS 2284 1.3.2.1 skrll ahd_reg_print_t ahd_scb_task_management_print; 2285 1.3.2.1 skrll #else 2286 1.3.2.1 skrll #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 2287 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap) 2288 1.1 fvdl #endif 2289 1.1 fvdl 2290 1.1 fvdl #if AIC_DEBUG_REGISTERS 2291 1.1 fvdl ahd_reg_print_t ahd_scb_dataptr_print; 2292 1.1 fvdl #else 2293 1.1 fvdl #define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \ 2294 1.1 fvdl ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap) 2295 1.1 fvdl #endif 2296 1.1 fvdl 2297 1.1 fvdl #if AIC_DEBUG_REGISTERS 2298 1.1 fvdl ahd_reg_print_t ahd_scb_datacnt_print; 2299 1.1 fvdl #else 2300 1.1 fvdl #define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \ 2301 1.1 fvdl ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap) 2302 1.1 fvdl #endif 2303 1.1 fvdl 2304 1.1 fvdl #if AIC_DEBUG_REGISTERS 2305 1.1 fvdl ahd_reg_print_t ahd_scb_sgptr_print; 2306 1.1 fvdl #else 2307 1.1 fvdl #define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \ 2308 1.1 fvdl ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap) 2309 1.1 fvdl #endif 2310 1.1 fvdl 2311 1.1 fvdl #if AIC_DEBUG_REGISTERS 2312 1.3.2.1 skrll ahd_reg_print_t ahd_scb_busaddr_print; 2313 1.1 fvdl #else 2314 1.3.2.1 skrll #define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \ 2315 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap) 2316 1.1 fvdl #endif 2317 1.1 fvdl 2318 1.1 fvdl #if AIC_DEBUG_REGISTERS 2319 1.3.2.1 skrll ahd_reg_print_t ahd_scb_next_print; 2320 1.1 fvdl #else 2321 1.3.2.1 skrll #define ahd_scb_next_print(regvalue, cur_col, wrap) \ 2322 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap) 2323 1.1 fvdl #endif 2324 1.1 fvdl 2325 1.1 fvdl #if AIC_DEBUG_REGISTERS 2326 1.3.2.1 skrll ahd_reg_print_t ahd_scb_next2_print; 2327 1.1 fvdl #else 2328 1.3.2.1 skrll #define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 2329 1.3.2.1 skrll ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap) 2330 1.1 fvdl #endif 2331 1.1 fvdl 2332 1.1 fvdl #if AIC_DEBUG_REGISTERS 2333 1.1 fvdl ahd_reg_print_t ahd_scb_spare_print; 2334 1.1 fvdl #else 2335 1.1 fvdl #define ahd_scb_spare_print(regvalue, cur_col, wrap) \ 2336 1.1 fvdl ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap) 2337 1.1 fvdl #endif 2338 1.1 fvdl 2339 1.1 fvdl #if AIC_DEBUG_REGISTERS 2340 1.1 fvdl ahd_reg_print_t ahd_scb_disconnected_lists_print; 2341 1.1 fvdl #else 2342 1.1 fvdl #define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 2343 1.1 fvdl ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap) 2344 1.1 fvdl #endif 2345 1.1 fvdl 2346 1.1 fvdl 2347 1.1 fvdl #define MODE_PTR 0x00 2348 1.1 fvdl #define DST_MODE 0x70 2349 1.1 fvdl #define SRC_MODE 0x07 2350 1.1 fvdl 2351 1.1 fvdl #define INTSTAT 0x01 2352 1.1 fvdl #define INT_PEND 0xff 2353 1.1 fvdl #define HWERRINT 0x80 2354 1.1 fvdl #define BRKADRINT 0x40 2355 1.1 fvdl #define SWTMINT 0x20 2356 1.1 fvdl #define PCIINT 0x10 2357 1.1 fvdl #define SCSIINT 0x08 2358 1.1 fvdl #define SEQINT 0x04 2359 1.1 fvdl #define CMDCMPLT 0x02 2360 1.1 fvdl #define SPLTINT 0x01 2361 1.1 fvdl 2362 1.1 fvdl #define SEQINTCODE 0x02 2363 1.3.2.1 skrll #define BAD_SCB_STATUS 0x1a 2364 1.1 fvdl #define SAW_HWERR 0x19 2365 1.1 fvdl #define TRACEPOINT3 0x18 2366 1.1 fvdl #define TRACEPOINT2 0x17 2367 1.1 fvdl #define TRACEPOINT1 0x16 2368 1.1 fvdl #define TRACEPOINT0 0x15 2369 1.1 fvdl #define TASKMGMT_CMD_CMPLT_OKAY 0x14 2370 1.1 fvdl #define TASKMGMT_FUNC_COMPLETE 0x13 2371 1.1 fvdl #define ENTERING_NONPACK 0x12 2372 1.1 fvdl #define CFG4OVERRUN 0x11 2373 1.1 fvdl #define STATUS_OVERRUN 0x10 2374 1.1 fvdl #define CFG4ISTAT_INTR 0x0f 2375 1.1 fvdl #define INVALID_SEQINT 0x0e 2376 1.1 fvdl #define ILLEGAL_PHASE 0x0d 2377 1.1 fvdl #define DUMP_CARD_STATE 0x0c 2378 1.1 fvdl #define MISSED_BUSFREE 0x0b 2379 1.1 fvdl #define MKMSG_FAILED 0x0a 2380 1.1 fvdl #define DATA_OVERRUN 0x09 2381 1.1 fvdl #define BAD_STATUS 0x08 2382 1.1 fvdl #define HOST_MSG_LOOP 0x07 2383 1.1 fvdl #define PDATA_REINIT 0x06 2384 1.1 fvdl #define IGN_WIDE_RES 0x05 2385 1.1 fvdl #define NO_MATCH 0x04 2386 1.1 fvdl #define PROTO_VIOLATION 0x03 2387 1.1 fvdl #define SEND_REJECT 0x02 2388 1.1 fvdl #define BAD_PHASE 0x01 2389 1.1 fvdl #define NO_SEQINT 0x00 2390 1.1 fvdl 2391 1.1 fvdl #define CLRINT 0x03 2392 1.1 fvdl #define CLRHWERRINT 0x80 2393 1.1 fvdl #define CLRBRKADRINT 0x40 2394 1.1 fvdl #define CLRSWTMINT 0x20 2395 1.1 fvdl #define CLRPCIINT 0x10 2396 1.1 fvdl #define CLRSCSIINT 0x08 2397 1.1 fvdl #define CLRSEQINT 0x04 2398 1.1 fvdl #define CLRCMDINT 0x02 2399 1.1 fvdl #define CLRSPLTINT 0x01 2400 1.1 fvdl 2401 1.1 fvdl #define ERROR 0x04 2402 1.1 fvdl #define CIOPARERR 0x80 2403 1.1 fvdl #define CIOACCESFAIL 0x40 2404 1.1 fvdl #define MPARERR 0x20 2405 1.1 fvdl #define DPARERR 0x10 2406 1.1 fvdl #define SQPARERR 0x08 2407 1.1 fvdl #define ILLOPCODE 0x04 2408 1.1 fvdl #define DSCTMOUT 0x02 2409 1.1 fvdl 2410 1.1 fvdl #define CLRERR 0x04 2411 1.1 fvdl #define CLRCIOPARERR 0x80 2412 1.1 fvdl #define CLRCIOACCESFAIL 0x40 2413 1.1 fvdl #define CLRMPARERR 0x20 2414 1.1 fvdl #define CLRDPARERR 0x10 2415 1.1 fvdl #define CLRSQPARERR 0x08 2416 1.1 fvdl #define CLRILLOPCODE 0x04 2417 1.1 fvdl #define CLRDSCTMOUT 0x02 2418 1.1 fvdl 2419 1.1 fvdl #define HCNTRL 0x05 2420 1.1 fvdl #define SEQ_RESET 0x80 2421 1.1 fvdl #define POWRDN 0x40 2422 1.1 fvdl #define SWINT 0x10 2423 1.1 fvdl #define SWTIMER_START_B 0x08 2424 1.1 fvdl #define PAUSE 0x04 2425 1.1 fvdl #define INTEN 0x02 2426 1.1 fvdl #define CHIPRST 0x01 2427 1.1 fvdl #define CHIPRSTACK 0x01 2428 1.1 fvdl 2429 1.1 fvdl #define HNSCB_QOFF 0x06 2430 1.1 fvdl 2431 1.1 fvdl #define HESCB_QOFF 0x08 2432 1.1 fvdl 2433 1.1 fvdl #define HS_MAILBOX 0x0b 2434 1.1 fvdl #define HOST_TQINPOS 0x80 2435 1.3.2.1 skrll #define ENINT_COALESCE 0x40 2436 1.1 fvdl 2437 1.1 fvdl #define SEQINTSTAT 0x0c 2438 1.1 fvdl #define SEQ_SWTMRTO 0x10 2439 1.1 fvdl #define SEQ_SEQINT 0x08 2440 1.1 fvdl #define SEQ_SCSIINT 0x04 2441 1.1 fvdl #define SEQ_PCIINT 0x02 2442 1.1 fvdl #define SEQ_SPLTINT 0x01 2443 1.1 fvdl 2444 1.1 fvdl #define CLRSEQINTSTAT 0x0c 2445 1.1 fvdl #define CLRSEQ_SWTMRTO 0x10 2446 1.1 fvdl #define CLRSEQ_SEQINT 0x08 2447 1.1 fvdl #define CLRSEQ_SCSIINT 0x04 2448 1.1 fvdl #define CLRSEQ_PCIINT 0x02 2449 1.1 fvdl #define CLRSEQ_SPLTINT 0x01 2450 1.1 fvdl 2451 1.1 fvdl #define SWTIMER 0x0e 2452 1.1 fvdl 2453 1.1 fvdl #define SNSCB_QOFF 0x10 2454 1.1 fvdl 2455 1.1 fvdl #define SESCB_QOFF 0x12 2456 1.1 fvdl 2457 1.1 fvdl #define SDSCB_QOFF 0x14 2458 1.1 fvdl 2459 1.1 fvdl #define QOFF_CTLSTA 0x16 2460 1.1 fvdl #define EMPTY_SCB_AVAIL 0x80 2461 1.1 fvdl #define NEW_SCB_AVAIL 0x40 2462 1.1 fvdl #define SDSCB_ROLLOVR 0x20 2463 1.1 fvdl #define HS_MAILBOX_ACT 0x10 2464 1.1 fvdl #define SCB_QSIZE 0x0f 2465 1.1 fvdl #define SCB_QSIZE_16384 0x0c 2466 1.1 fvdl #define SCB_QSIZE_8192 0x0b 2467 1.1 fvdl #define SCB_QSIZE_4096 0x0a 2468 1.1 fvdl #define SCB_QSIZE_2048 0x09 2469 1.1 fvdl #define SCB_QSIZE_1024 0x08 2470 1.1 fvdl #define SCB_QSIZE_512 0x07 2471 1.1 fvdl #define SCB_QSIZE_256 0x06 2472 1.1 fvdl #define SCB_QSIZE_128 0x05 2473 1.1 fvdl #define SCB_QSIZE_64 0x04 2474 1.1 fvdl #define SCB_QSIZE_32 0x03 2475 1.1 fvdl #define SCB_QSIZE_16 0x02 2476 1.1 fvdl #define SCB_QSIZE_8 0x01 2477 1.1 fvdl #define SCB_QSIZE_4 0x00 2478 1.1 fvdl 2479 1.1 fvdl #define INTCTL 0x18 2480 1.1 fvdl #define SWTMINTMASK 0x80 2481 1.1 fvdl #define SWTMINTEN 0x40 2482 1.1 fvdl #define SWTIMER_START 0x20 2483 1.1 fvdl #define AUTOCLRCMDINT 0x10 2484 1.1 fvdl #define PCIINTEN 0x08 2485 1.1 fvdl #define SCSIINTEN 0x04 2486 1.1 fvdl #define SEQINTEN 0x02 2487 1.1 fvdl #define SPLTINTEN 0x01 2488 1.1 fvdl 2489 1.1 fvdl #define DFCNTRL 0x19 2490 1.1 fvdl #define SCSIENWRDIS 0x40 2491 1.1 fvdl #define SCSIENACK 0x20 2492 1.1 fvdl #define DIRECTIONACK 0x04 2493 1.1 fvdl #define FIFOFLUSHACK 0x02 2494 1.1 fvdl #define DIRECTIONEN 0x01 2495 1.1 fvdl 2496 1.1 fvdl #define DSCOMMAND0 0x19 2497 1.1 fvdl #define CACHETHEN 0x80 2498 1.1 fvdl #define DPARCKEN 0x40 2499 1.1 fvdl #define MPARCKEN 0x20 2500 1.1 fvdl #define EXTREQLCK 0x10 2501 1.1 fvdl #define DISABLE_TWATE 0x02 2502 1.1 fvdl #define CIOPARCKEN 0x01 2503 1.1 fvdl 2504 1.1 fvdl #define DFSTATUS 0x1a 2505 1.1 fvdl #define PRELOAD_AVAIL 0x80 2506 1.1 fvdl #define PKT_PRELOAD_AVAIL 0x40 2507 1.1 fvdl #define MREQPEND 0x10 2508 1.1 fvdl #define HDONE 0x08 2509 1.1 fvdl #define DFTHRESH 0x04 2510 1.1 fvdl #define FIFOFULL 0x02 2511 1.1 fvdl #define FIFOEMP 0x01 2512 1.1 fvdl 2513 1.1 fvdl #define ARBCTL 0x1b 2514 1.1 fvdl #define RESET_HARB 0x80 2515 1.1 fvdl #define RETRY_SWEN 0x08 2516 1.1 fvdl #define USE_TIME 0x07 2517 1.1 fvdl 2518 1.1 fvdl #define SG_CACHE_SHADOW 0x1b 2519 1.1 fvdl #define ODD_SEG 0x04 2520 1.1 fvdl #define LAST_SEG 0x02 2521 1.1 fvdl #define LAST_SEG_DONE 0x01 2522 1.1 fvdl 2523 1.1 fvdl #define SG_CACHE_PRE 0x1b 2524 1.1 fvdl 2525 1.1 fvdl #define TYPEPTR 0x20 2526 1.1 fvdl 2527 1.1 fvdl #define LQIN 0x20 2528 1.1 fvdl 2529 1.1 fvdl #define TAGPTR 0x21 2530 1.1 fvdl 2531 1.1 fvdl #define LUNPTR 0x22 2532 1.1 fvdl 2533 1.1 fvdl #define DATALENPTR 0x23 2534 1.1 fvdl 2535 1.1 fvdl #define STATLENPTR 0x24 2536 1.1 fvdl 2537 1.1 fvdl #define CMDLENPTR 0x25 2538 1.1 fvdl 2539 1.1 fvdl #define ATTRPTR 0x26 2540 1.1 fvdl 2541 1.1 fvdl #define FLAGPTR 0x27 2542 1.1 fvdl 2543 1.1 fvdl #define CMDPTR 0x28 2544 1.1 fvdl 2545 1.1 fvdl #define QNEXTPTR 0x29 2546 1.1 fvdl 2547 1.1 fvdl #define IDPTR 0x2a 2548 1.1 fvdl 2549 1.1 fvdl #define ABRTBYTEPTR 0x2b 2550 1.1 fvdl 2551 1.1 fvdl #define ABRTBITPTR 0x2c 2552 1.1 fvdl 2553 1.1 fvdl #define MAXCMDBYTES 0x2d 2554 1.1 fvdl 2555 1.1 fvdl #define MAXCMD2RCV 0x2e 2556 1.1 fvdl 2557 1.1 fvdl #define SHORTTHRESH 0x2f 2558 1.1 fvdl 2559 1.1 fvdl #define LUNLEN 0x30 2560 1.3.2.1 skrll #define TLUNLEN 0xf0 2561 1.3.2.1 skrll #define ILUNLEN 0x0f 2562 1.1 fvdl 2563 1.1 fvdl #define CDBLIMIT 0x31 2564 1.1 fvdl 2565 1.1 fvdl #define MAXCMD 0x32 2566 1.1 fvdl 2567 1.1 fvdl #define MAXCMDCNT 0x33 2568 1.1 fvdl 2569 1.1 fvdl #define LQRSVD01 0x34 2570 1.1 fvdl 2571 1.1 fvdl #define LQRSVD16 0x35 2572 1.1 fvdl 2573 1.1 fvdl #define LQRSVD17 0x36 2574 1.1 fvdl 2575 1.1 fvdl #define CMDRSVD0 0x37 2576 1.1 fvdl 2577 1.1 fvdl #define LQCTL0 0x38 2578 1.1 fvdl #define LQITARGCLT 0xc0 2579 1.1 fvdl #define LQIINITGCLT 0x30 2580 1.1 fvdl #define LQ0TARGCLT 0x0c 2581 1.1 fvdl #define LQ0INITGCLT 0x03 2582 1.1 fvdl 2583 1.1 fvdl #define LQCTL1 0x38 2584 1.1 fvdl #define PCI2PCI 0x04 2585 1.1 fvdl #define SINGLECMD 0x02 2586 1.1 fvdl #define ABORTPENDING 0x01 2587 1.1 fvdl 2588 1.1 fvdl #define LQCTL2 0x39 2589 1.1 fvdl #define LQIRETRY 0x80 2590 1.1 fvdl #define LQICONTINUE 0x40 2591 1.1 fvdl #define LQITOIDLE 0x20 2592 1.1 fvdl #define LQIPAUSE 0x10 2593 1.1 fvdl #define LQORETRY 0x08 2594 1.1 fvdl #define LQOCONTINUE 0x04 2595 1.1 fvdl #define LQOTOIDLE 0x02 2596 1.1 fvdl #define LQOPAUSE 0x01 2597 1.1 fvdl 2598 1.1 fvdl #define SCSBIST0 0x39 2599 1.1 fvdl #define GSBISTERR 0x40 2600 1.1 fvdl #define GSBISTDONE 0x20 2601 1.1 fvdl #define GSBISTRUN 0x10 2602 1.1 fvdl #define OSBISTERR 0x04 2603 1.1 fvdl #define OSBISTDONE 0x02 2604 1.1 fvdl #define OSBISTRUN 0x01 2605 1.1 fvdl 2606 1.1 fvdl #define SCSISEQ0 0x3a 2607 1.1 fvdl #define TEMODEO 0x80 2608 1.1 fvdl #define ENSELO 0x40 2609 1.1 fvdl #define ENARBO 0x20 2610 1.1 fvdl #define FORCEBUSFREE 0x10 2611 1.1 fvdl #define SCSIRSTO 0x01 2612 1.1 fvdl 2613 1.1 fvdl #define SCSBIST1 0x3a 2614 1.1 fvdl #define NTBISTERR 0x04 2615 1.1 fvdl #define NTBISTDONE 0x02 2616 1.1 fvdl #define NTBISTRUN 0x01 2617 1.1 fvdl 2618 1.1 fvdl #define SCSISEQ1 0x3b 2619 1.1 fvdl 2620 1.1 fvdl #define DLCOUNT 0x3c 2621 1.1 fvdl 2622 1.1 fvdl #define BUSINITID 0x3c 2623 1.1 fvdl 2624 1.1 fvdl #define SXFRCTL0 0x3c 2625 1.1 fvdl #define DFON 0x80 2626 1.1 fvdl #define DFPEXP 0x40 2627 1.1 fvdl #define BIOSCANCELEN 0x10 2628 1.1 fvdl #define SPIOEN 0x08 2629 1.1 fvdl 2630 1.1 fvdl #define SXFRCTL1 0x3d 2631 1.1 fvdl #define BITBUCKET 0x80 2632 1.1 fvdl #define ENSACHK 0x40 2633 1.1 fvdl #define ENSPCHK 0x20 2634 1.1 fvdl #define STIMESEL 0x18 2635 1.1 fvdl #define ENSTIMER 0x04 2636 1.1 fvdl #define ACTNEGEN 0x02 2637 1.1 fvdl #define STPWEN 0x01 2638 1.1 fvdl 2639 1.1 fvdl #define SXFRCTL2 0x3e 2640 1.1 fvdl #define AUTORSTDIS 0x10 2641 1.1 fvdl #define CMDDMAEN 0x08 2642 1.1 fvdl #define ASU 0x07 2643 1.1 fvdl 2644 1.1 fvdl #define BUSTARGID 0x3e 2645 1.1 fvdl 2646 1.1 fvdl #define DFFSTAT 0x3f 2647 1.1 fvdl #define CURRFIFO 0x03 2648 1.1 fvdl #define FIFO1FREE 0x20 2649 1.1 fvdl #define FIFO0FREE 0x10 2650 1.1 fvdl #define CURRFIFO_NONE 0x03 2651 1.1 fvdl #define CURRFIFO_1 0x01 2652 1.1 fvdl #define CURRFIFO_0 0x00 2653 1.1 fvdl 2654 1.1 fvdl #define MULTARGID 0x40 2655 1.1 fvdl 2656 1.1 fvdl #define SCSISIGO 0x40 2657 1.1 fvdl #define CDO 0x80 2658 1.1 fvdl #define IOO 0x40 2659 1.1 fvdl #define MSGO 0x20 2660 1.1 fvdl #define ATNO 0x10 2661 1.1 fvdl #define SELO 0x08 2662 1.1 fvdl #define BSYO 0x04 2663 1.1 fvdl #define REQO 0x02 2664 1.1 fvdl #define ACKO 0x01 2665 1.1 fvdl 2666 1.1 fvdl #define SCSISIGI 0x41 2667 1.1 fvdl #define ATNI 0x10 2668 1.1 fvdl #define SELI 0x08 2669 1.1 fvdl #define BSYI 0x04 2670 1.1 fvdl #define REQI 0x02 2671 1.1 fvdl #define ACKI 0x01 2672 1.1 fvdl 2673 1.1 fvdl #define SCSIPHASE 0x42 2674 1.1 fvdl #define STATUS_PHASE 0x20 2675 1.1 fvdl #define COMMAND_PHASE 0x10 2676 1.1 fvdl #define MSG_IN_PHASE 0x08 2677 1.1 fvdl #define MSG_OUT_PHASE 0x04 2678 1.1 fvdl #define DATA_PHASE_MASK 0x03 2679 1.1 fvdl #define DATA_IN_PHASE 0x02 2680 1.1 fvdl #define DATA_OUT_PHASE 0x01 2681 1.1 fvdl 2682 1.1 fvdl #define SCSIDAT0_IMG 0x43 2683 1.1 fvdl 2684 1.1 fvdl #define SCSIDAT 0x44 2685 1.1 fvdl 2686 1.1 fvdl #define SCSIBUS 0x46 2687 1.1 fvdl 2688 1.1 fvdl #define TARGIDIN 0x48 2689 1.1 fvdl #define CLKOUT 0x80 2690 1.1 fvdl #define TARGID 0x0f 2691 1.1 fvdl 2692 1.1 fvdl #define SELID 0x49 2693 1.1 fvdl #define SELID_MASK 0xf0 2694 1.1 fvdl #define ONEBIT 0x08 2695 1.1 fvdl 2696 1.1 fvdl #define SBLKCTL 0x4a 2697 1.1 fvdl #define DIAGLEDEN 0x80 2698 1.1 fvdl #define DIAGLEDON 0x40 2699 1.1 fvdl #define ENAB40 0x08 2700 1.1 fvdl #define ENAB20 0x04 2701 1.1 fvdl #define SELWIDE 0x02 2702 1.1 fvdl 2703 1.1 fvdl #define OPTIONMODE 0x4a 2704 1.1 fvdl #define OPTIONMODE_DEFAULTS 0x02 2705 1.1 fvdl #define BIOSCANCTL 0x80 2706 1.1 fvdl #define AUTOACKEN 0x40 2707 1.1 fvdl #define BIASCANCTL 0x20 2708 1.1 fvdl #define BUSFREEREV 0x10 2709 1.1 fvdl #define ENDGFORMCHK 0x04 2710 1.1 fvdl #define AUTO_MSGOUT_DE 0x02 2711 1.1 fvdl 2712 1.1 fvdl #define SIMODE0 0x4b 2713 1.1 fvdl #define ENSELDO 0x40 2714 1.1 fvdl #define ENSELDI 0x20 2715 1.1 fvdl #define ENSELINGO 0x10 2716 1.1 fvdl #define ENIOERR 0x08 2717 1.1 fvdl #define ENOVERRUN 0x04 2718 1.1 fvdl #define ENSPIORDY 0x02 2719 1.1 fvdl #define ENARBDO 0x01 2720 1.1 fvdl 2721 1.1 fvdl #define SSTAT0 0x4b 2722 1.1 fvdl #define TARGET 0x80 2723 1.1 fvdl #define SELDO 0x40 2724 1.1 fvdl #define SELDI 0x20 2725 1.1 fvdl #define SELINGO 0x10 2726 1.1 fvdl #define IOERR 0x08 2727 1.1 fvdl #define OVERRUN 0x04 2728 1.1 fvdl #define SPIORDY 0x02 2729 1.1 fvdl #define ARBDO 0x01 2730 1.1 fvdl 2731 1.1 fvdl #define CLRSINT0 0x4b 2732 1.1 fvdl #define CLRSELDO 0x40 2733 1.1 fvdl #define CLRSELDI 0x20 2734 1.1 fvdl #define CLRSELINGO 0x10 2735 1.1 fvdl #define CLRIOERR 0x08 2736 1.1 fvdl #define CLROVERRUN 0x04 2737 1.1 fvdl #define CLRSPIORDY 0x02 2738 1.1 fvdl #define CLRARBDO 0x01 2739 1.1 fvdl 2740 1.1 fvdl #define SSTAT1 0x4c 2741 1.1 fvdl #define SELTO 0x80 2742 1.1 fvdl #define ATNTARG 0x40 2743 1.1 fvdl #define SCSIRSTI 0x20 2744 1.1 fvdl #define PHASEMIS 0x10 2745 1.1 fvdl #define BUSFREE 0x08 2746 1.1 fvdl #define SCSIPERR 0x04 2747 1.1 fvdl #define STRB2FAST 0x02 2748 1.1 fvdl #define REQINIT 0x01 2749 1.1 fvdl 2750 1.1 fvdl #define CLRSINT1 0x4c 2751 1.1 fvdl #define CLRSELTIMEO 0x80 2752 1.1 fvdl #define CLRATNO 0x40 2753 1.1 fvdl #define CLRSCSIRSTI 0x20 2754 1.1 fvdl #define CLRBUSFREE 0x08 2755 1.1 fvdl #define CLRSCSIPERR 0x04 2756 1.1 fvdl #define CLRSTRB2FAST 0x02 2757 1.1 fvdl #define CLRREQINIT 0x01 2758 1.1 fvdl 2759 1.1 fvdl #define SSTAT2 0x4d 2760 1.1 fvdl #define BUSFREETIME 0xc0 2761 1.1 fvdl #define NONPACKREQ 0x20 2762 1.1 fvdl #define EXP_ACTIVE 0x10 2763 1.1 fvdl #define BSYX 0x08 2764 1.1 fvdl #define WIDE_RES 0x04 2765 1.1 fvdl #define SDONE 0x02 2766 1.1 fvdl #define DMADONE 0x01 2767 1.1 fvdl #define BUSFREE_DFF1 0xc0 2768 1.1 fvdl #define BUSFREE_DFF0 0x80 2769 1.1 fvdl #define BUSFREE_LQO 0x40 2770 1.1 fvdl 2771 1.1 fvdl #define CLRSINT2 0x4d 2772 1.1 fvdl #define CLRNONPACKREQ 0x20 2773 1.1 fvdl #define CLRWIDE_RES 0x04 2774 1.1 fvdl #define CLRSDONE 0x02 2775 1.1 fvdl #define CLRDMADONE 0x01 2776 1.1 fvdl 2777 1.1 fvdl #define SIMODE2 0x4d 2778 1.1 fvdl #define ENWIDE_RES 0x04 2779 1.1 fvdl #define ENSDONE 0x02 2780 1.1 fvdl #define ENDMADONE 0x01 2781 1.1 fvdl 2782 1.1 fvdl #define LQISTATE 0x4e 2783 1.1 fvdl 2784 1.1 fvdl #define PERRDIAG 0x4e 2785 1.1 fvdl #define HIZERO 0x80 2786 1.1 fvdl #define HIPERR 0x40 2787 1.1 fvdl #define PREVPHASE 0x20 2788 1.1 fvdl #define PARITYERR 0x10 2789 1.1 fvdl #define AIPERR 0x08 2790 1.1 fvdl #define CRCERR 0x04 2791 1.1 fvdl #define DGFORMERR 0x02 2792 1.1 fvdl #define DTERR 0x01 2793 1.1 fvdl 2794 1.1 fvdl #define SOFFCNT 0x4f 2795 1.1 fvdl 2796 1.1 fvdl #define LQOSTATE 0x4f 2797 1.1 fvdl 2798 1.1 fvdl #define LQISTAT0 0x50 2799 1.1 fvdl #define LQIATNQAS 0x20 2800 1.1 fvdl #define LQICRCT1 0x10 2801 1.1 fvdl #define LQICRCT2 0x08 2802 1.1 fvdl #define LQIBADLQT 0x04 2803 1.1 fvdl #define LQIATNLQ 0x02 2804 1.1 fvdl #define LQIATNCMD 0x01 2805 1.1 fvdl 2806 1.1 fvdl #define CLRLQIINT0 0x50 2807 1.1 fvdl #define CLRLQIATNQAS 0x20 2808 1.1 fvdl #define CLRLQICRCT1 0x10 2809 1.1 fvdl #define CLRLQICRCT2 0x08 2810 1.1 fvdl #define CLRLQIBADLQT 0x04 2811 1.1 fvdl #define CLRLQIATNLQ 0x02 2812 1.1 fvdl #define CLRLQIATNCMD 0x01 2813 1.1 fvdl 2814 1.1 fvdl #define LQIMODE0 0x50 2815 1.1 fvdl #define ENLQIATNQASK 0x20 2816 1.1 fvdl #define ENLQICRCT1 0x10 2817 1.1 fvdl #define ENLQICRCT2 0x08 2818 1.1 fvdl #define ENLQIBADLQT 0x04 2819 1.1 fvdl #define ENLQIATNLQ 0x02 2820 1.1 fvdl #define ENLQIATNCMD 0x01 2821 1.1 fvdl 2822 1.1 fvdl #define LQISTAT1 0x51 2823 1.1 fvdl #define LQIPHASE_LQ 0x80 2824 1.1 fvdl #define LQIPHASE_NLQ 0x40 2825 1.1 fvdl #define LQIABORT 0x20 2826 1.1 fvdl #define LQICRCI_LQ 0x10 2827 1.1 fvdl #define LQICRCI_NLQ 0x08 2828 1.1 fvdl #define LQIBADLQI 0x04 2829 1.1 fvdl #define LQIOVERI_LQ 0x02 2830 1.1 fvdl #define LQIOVERI_NLQ 0x01 2831 1.1 fvdl 2832 1.1 fvdl #define CLRLQIINT1 0x51 2833 1.1 fvdl #define CLRLQIPHASE_LQ 0x80 2834 1.1 fvdl #define CLRLQIPHASE_NLQ 0x40 2835 1.1 fvdl #define CLRLIQABORT 0x20 2836 1.1 fvdl #define CLRLQICRCI_LQ 0x10 2837 1.1 fvdl #define CLRLQICRCI_NLQ 0x08 2838 1.1 fvdl #define CLRLQIBADLQI 0x04 2839 1.1 fvdl #define CLRLQIOVERI_LQ 0x02 2840 1.1 fvdl #define CLRLQIOVERI_NLQ 0x01 2841 1.1 fvdl 2842 1.1 fvdl #define LQIMODE1 0x51 2843 1.1 fvdl #define ENLQIPHASE_LQ 0x80 2844 1.1 fvdl #define ENLQIPHASE_NLQ 0x40 2845 1.1 fvdl #define ENLIQABORT 0x20 2846 1.1 fvdl #define ENLQICRCI_LQ 0x10 2847 1.1 fvdl #define ENLQICRCI_NLQ 0x08 2848 1.1 fvdl #define ENLQIBADLQI 0x04 2849 1.1 fvdl #define ENLQIOVERI_LQ 0x02 2850 1.1 fvdl #define ENLQIOVERI_NLQ 0x01 2851 1.1 fvdl 2852 1.1 fvdl #define LQISTAT2 0x52 2853 1.1 fvdl #define PACKETIZED 0x80 2854 1.1 fvdl #define LQIPHASE_OUTPKT 0x40 2855 1.1 fvdl #define LQIWORKONLQ 0x20 2856 1.1 fvdl #define LQIWAITFIFO 0x10 2857 1.1 fvdl #define LQISTOPPKT 0x08 2858 1.1 fvdl #define LQISTOPLQ 0x04 2859 1.1 fvdl #define LQISTOPCMD 0x02 2860 1.1 fvdl #define LQIGSAVAIL 0x01 2861 1.1 fvdl 2862 1.1 fvdl #define SSTAT3 0x53 2863 1.1 fvdl #define NTRAMPERR 0x02 2864 1.1 fvdl #define OSRAMPERR 0x01 2865 1.1 fvdl 2866 1.1 fvdl #define CLRSINT3 0x53 2867 1.1 fvdl #define CLRNTRAMPERR 0x02 2868 1.1 fvdl #define CLROSRAMPERR 0x01 2869 1.1 fvdl 2870 1.1 fvdl #define SIMODE3 0x53 2871 1.1 fvdl #define ENNTRAMPERR 0x02 2872 1.1 fvdl #define ENOSRAMPERR 0x01 2873 1.1 fvdl 2874 1.1 fvdl #define LQOSTAT0 0x54 2875 1.1 fvdl #define LQOTARGSCBPERR 0x10 2876 1.1 fvdl #define LQOSTOPT2 0x08 2877 1.1 fvdl #define LQOATNLQ 0x04 2878 1.1 fvdl #define LQOATNPKT 0x02 2879 1.1 fvdl #define LQOTCRC 0x01 2880 1.1 fvdl 2881 1.1 fvdl #define CLRLQOINT0 0x54 2882 1.1 fvdl #define CLRLQOTARGSCBPERR 0x10 2883 1.1 fvdl #define CLRLQOSTOPT2 0x08 2884 1.1 fvdl #define CLRLQOATNLQ 0x04 2885 1.1 fvdl #define CLRLQOATNPKT 0x02 2886 1.1 fvdl #define CLRLQOTCRC 0x01 2887 1.1 fvdl 2888 1.1 fvdl #define LQOMODE0 0x54 2889 1.1 fvdl #define ENLQOTARGSCBPERR 0x10 2890 1.1 fvdl #define ENLQOSTOPT2 0x08 2891 1.1 fvdl #define ENLQOATNLQ 0x04 2892 1.1 fvdl #define ENLQOATNPKT 0x02 2893 1.1 fvdl #define ENLQOTCRC 0x01 2894 1.1 fvdl 2895 1.1 fvdl #define LQOSTAT1 0x55 2896 1.1 fvdl #define LQOINITSCBPERR 0x10 2897 1.1 fvdl #define LQOSTOPI2 0x08 2898 1.1 fvdl #define LQOBADQAS 0x04 2899 1.1 fvdl #define LQOBUSFREE 0x02 2900 1.1 fvdl #define LQOPHACHGINPKT 0x01 2901 1.1 fvdl 2902 1.1 fvdl #define CLRLQOINT1 0x55 2903 1.1 fvdl #define CLRLQOINITSCBPERR 0x10 2904 1.1 fvdl #define CLRLQOSTOPI2 0x08 2905 1.1 fvdl #define CLRLQOBADQAS 0x04 2906 1.1 fvdl #define CLRLQOBUSFREE 0x02 2907 1.1 fvdl #define CLRLQOPHACHGINPKT 0x01 2908 1.1 fvdl 2909 1.1 fvdl #define LQOMODE1 0x55 2910 1.1 fvdl #define ENLQOINITSCBPERR 0x10 2911 1.1 fvdl #define ENLQOSTOPI2 0x08 2912 1.1 fvdl #define ENLQOBADQAS 0x04 2913 1.1 fvdl #define ENLQOBUSFREE 0x02 2914 1.1 fvdl #define ENLQOPHACHGINPKT 0x01 2915 1.1 fvdl 2916 1.1 fvdl #define OS_SPACE_CNT 0x56 2917 1.1 fvdl 2918 1.1 fvdl #define LQOSTAT2 0x56 2919 1.1 fvdl #define LQOPKT 0xe0 2920 1.1 fvdl #define LQOWAITFIFO 0x10 2921 1.1 fvdl #define LQOPHACHGOUTPKT 0x02 2922 1.1 fvdl #define LQOSTOP0 0x01 2923 1.1 fvdl 2924 1.1 fvdl #define SIMODE1 0x57 2925 1.1 fvdl #define ENSELTIMO 0x80 2926 1.1 fvdl #define ENATNTARG 0x40 2927 1.1 fvdl #define ENSCSIRST 0x20 2928 1.1 fvdl #define ENPHASEMIS 0x10 2929 1.1 fvdl #define ENBUSFREE 0x08 2930 1.1 fvdl #define ENSCSIPERR 0x04 2931 1.1 fvdl #define ENSTRB2FAST 0x02 2932 1.1 fvdl #define ENREQINIT 0x01 2933 1.1 fvdl 2934 1.1 fvdl #define GSFIFO 0x58 2935 1.1 fvdl 2936 1.1 fvdl #define LQOSCSCTL 0x5a 2937 1.1 fvdl #define LQOH2A_VERSION 0x80 2938 1.1 fvdl #define LQONOCHKOVER 0x01 2939 1.1 fvdl 2940 1.1 fvdl #define NEXTSCB 0x5a 2941 1.1 fvdl 2942 1.1 fvdl #define DFFSXFRCTL 0x5a 2943 1.1 fvdl #define DFFBITBUCKET 0x08 2944 1.1 fvdl #define CLRSHCNT 0x04 2945 1.1 fvdl #define CLRCHN 0x02 2946 1.1 fvdl #define RSTCHN 0x01 2947 1.1 fvdl 2948 1.1 fvdl #define SEQINTSRC 0x5b 2949 1.1 fvdl #define CTXTDONE 0x40 2950 1.1 fvdl #define SAVEPTRS 0x20 2951 1.1 fvdl #define CFG4DATA 0x10 2952 1.1 fvdl #define CFG4ISTAT 0x08 2953 1.1 fvdl #define CFG4TSTAT 0x04 2954 1.1 fvdl #define CFG4ICMD 0x02 2955 1.1 fvdl #define CFG4TCMD 0x01 2956 1.1 fvdl 2957 1.1 fvdl #define CLRSEQINTSRC 0x5b 2958 1.1 fvdl #define CLRCTXTDONE 0x40 2959 1.1 fvdl #define CLRSAVEPTRS 0x20 2960 1.1 fvdl #define CLRCFG4DATA 0x10 2961 1.1 fvdl #define CLRCFG4ISTAT 0x08 2962 1.1 fvdl #define CLRCFG4TSTAT 0x04 2963 1.1 fvdl #define CLRCFG4ICMD 0x02 2964 1.1 fvdl #define CLRCFG4TCMD 0x01 2965 1.1 fvdl 2966 1.1 fvdl #define SEQIMODE 0x5c 2967 1.1 fvdl #define ENCTXTDONE 0x40 2968 1.1 fvdl #define ENSAVEPTRS 0x20 2969 1.1 fvdl #define ENCFG4DATA 0x10 2970 1.1 fvdl #define ENCFG4ISTAT 0x08 2971 1.1 fvdl #define ENCFG4TSTAT 0x04 2972 1.1 fvdl #define ENCFG4ICMD 0x02 2973 1.1 fvdl #define ENCFG4TCMD 0x01 2974 1.1 fvdl 2975 1.1 fvdl #define CURRSCB 0x5c 2976 1.1 fvdl 2977 1.1 fvdl #define MDFFSTAT 0x5d 2978 1.1 fvdl #define SHCNTNEGATIVE 0x40 2979 1.1 fvdl #define SHCNTMINUS1 0x20 2980 1.1 fvdl #define LASTSDONE 0x10 2981 1.1 fvdl #define SHVALID 0x08 2982 1.1 fvdl #define DLZERO 0x04 2983 1.1 fvdl #define DATAINFIFO 0x02 2984 1.1 fvdl #define FIFOFREE 0x01 2985 1.1 fvdl 2986 1.1 fvdl #define CRCCONTROL 0x5d 2987 1.1 fvdl #define CRCVALCHKEN 0x40 2988 1.1 fvdl 2989 1.1 fvdl #define SCSITEST 0x5e 2990 1.1 fvdl #define CNTRTEST 0x08 2991 1.1 fvdl #define SEL_TXPLL_DEBUG 0x04 2992 1.1 fvdl 2993 1.1 fvdl #define DFFTAG 0x5e 2994 1.1 fvdl 2995 1.1 fvdl #define LASTSCB 0x5e 2996 1.1 fvdl 2997 1.1 fvdl #define IOPDNCTL 0x5f 2998 1.1 fvdl #define DISABLE_OE 0x80 2999 1.1 fvdl #define PDN_IDIST 0x04 3000 1.1 fvdl #define PDN_DIFFSENSE 0x01 3001 1.1 fvdl 3002 1.1 fvdl #define NEGOADDR 0x60 3003 1.1 fvdl 3004 1.1 fvdl #define SHADDR 0x60 3005 1.1 fvdl 3006 1.1 fvdl #define DGRPCRCI 0x60 3007 1.1 fvdl 3008 1.1 fvdl #define NEGPERIOD 0x61 3009 1.1 fvdl 3010 1.1 fvdl #define PACKCRCI 0x62 3011 1.1 fvdl 3012 1.1 fvdl #define NEGOFFSET 0x62 3013 1.1 fvdl 3014 1.1 fvdl #define NEGPPROPTS 0x63 3015 1.1 fvdl #define PPROPT_PACE 0x08 3016 1.1 fvdl #define PPROPT_QAS 0x04 3017 1.1 fvdl #define PPROPT_DT 0x02 3018 1.1 fvdl #define PPROPT_IUT 0x01 3019 1.1 fvdl 3020 1.1 fvdl #define NEGCONOPTS 0x64 3021 1.1 fvdl #define ENSNAPSHOT 0x40 3022 1.1 fvdl #define RTI_WRTDIS 0x20 3023 1.1 fvdl #define RTI_OVRDTRN 0x10 3024 1.1 fvdl #define ENSLOWCRC 0x08 3025 1.1 fvdl #define ENAUTOATNI 0x04 3026 1.1 fvdl #define ENAUTOATNO 0x02 3027 1.1 fvdl #define WIDEXFER 0x01 3028 1.1 fvdl 3029 1.1 fvdl #define ANNEXCOL 0x65 3030 1.1 fvdl 3031 1.1 fvdl #define ANNEXDAT 0x66 3032 1.1 fvdl 3033 1.1 fvdl #define SCSCHKN 0x66 3034 1.1 fvdl #define STSELSKIDDIS 0x40 3035 1.1 fvdl #define CURRFIFODEF 0x20 3036 1.1 fvdl #define WIDERESEN 0x10 3037 1.1 fvdl #define SDONEMSKDIS 0x08 3038 1.1 fvdl #define DFFACTCLR 0x04 3039 1.1 fvdl #define SHVALIDSTDIS 0x02 3040 1.1 fvdl #define LSTSGCLRDIS 0x01 3041 1.1 fvdl 3042 1.1 fvdl #define IOWNID 0x67 3043 1.1 fvdl 3044 1.1 fvdl #define SHCNT 0x68 3045 1.1 fvdl 3046 1.1 fvdl #define PLL960CTL0 0x68 3047 1.1 fvdl 3048 1.1 fvdl #define PLL960CTL1 0x69 3049 1.1 fvdl 3050 1.1 fvdl #define TOWNID 0x69 3051 1.1 fvdl 3052 1.1 fvdl #define XSIG 0x6a 3053 1.1 fvdl 3054 1.1 fvdl #define PLL960CNT0 0x6a 3055 1.1 fvdl 3056 1.1 fvdl #define SELOID 0x6b 3057 1.1 fvdl 3058 1.1 fvdl #define PLL400CTL0 0x6c 3059 1.1 fvdl #define PLL_VCOSEL 0x80 3060 1.1 fvdl #define PLL_PWDN 0x40 3061 1.1 fvdl #define PLL_NS 0x30 3062 1.1 fvdl #define PLL_ENLUD 0x08 3063 1.1 fvdl #define PLL_ENLPF 0x04 3064 1.1 fvdl #define PLL_DLPF 0x02 3065 1.1 fvdl #define PLL_ENFBM 0x01 3066 1.1 fvdl 3067 1.1 fvdl #define FAIRNESS 0x6c 3068 1.1 fvdl 3069 1.1 fvdl #define PLL400CTL1 0x6d 3070 1.1 fvdl #define PLL_CNTEN 0x80 3071 1.1 fvdl #define PLL_CNTCLR 0x40 3072 1.1 fvdl #define PLL_RST 0x01 3073 1.1 fvdl 3074 1.1 fvdl #define PLL400CNT0 0x6e 3075 1.1 fvdl 3076 1.1 fvdl #define UNFAIRNESS 0x6e 3077 1.1 fvdl 3078 1.1 fvdl #define HODMAADR 0x70 3079 1.1 fvdl 3080 1.1 fvdl #define HADDR 0x70 3081 1.1 fvdl 3082 1.1 fvdl #define PLLDELAY 0x70 3083 1.1 fvdl #define SPLIT_DROP_REQ 0x80 3084 1.1 fvdl 3085 1.1 fvdl #define HCNT 0x78 3086 1.1 fvdl 3087 1.1 fvdl #define HODMACNT 0x78 3088 1.1 fvdl 3089 1.1 fvdl #define HODMAEN 0x7a 3090 1.1 fvdl 3091 1.1 fvdl #define SCBHADDR 0x7c 3092 1.1 fvdl 3093 1.1 fvdl #define SGHADDR 0x7c 3094 1.1 fvdl 3095 1.1 fvdl #define SGHCNT 0x84 3096 1.1 fvdl 3097 1.1 fvdl #define SCBHCNT 0x84 3098 1.1 fvdl 3099 1.1 fvdl #define DFF_THRSH 0x88 3100 1.1 fvdl #define WR_DFTHRSH 0x70 3101 1.1 fvdl #define RD_DFTHRSH 0x07 3102 1.1 fvdl #define WR_DFTHRSH_MAX 0x70 3103 1.1 fvdl #define WR_DFTHRSH_90 0x60 3104 1.1 fvdl #define WR_DFTHRSH_85 0x50 3105 1.1 fvdl #define WR_DFTHRSH_75 0x40 3106 1.1 fvdl #define WR_DFTHRSH_63 0x30 3107 1.1 fvdl #define WR_DFTHRSH_50 0x20 3108 1.1 fvdl #define WR_DFTHRSH_25 0x10 3109 1.1 fvdl #define RD_DFTHRSH_MAX 0x07 3110 1.1 fvdl #define RD_DFTHRSH_90 0x06 3111 1.1 fvdl #define RD_DFTHRSH_85 0x05 3112 1.1 fvdl #define RD_DFTHRSH_75 0x04 3113 1.1 fvdl #define RD_DFTHRSH_63 0x03 3114 1.1 fvdl #define RD_DFTHRSH_50 0x02 3115 1.1 fvdl #define RD_DFTHRSH_25 0x01 3116 1.1 fvdl #define WR_DFTHRSH_MIN 0x00 3117 1.1 fvdl #define RD_DFTHRSH_MIN 0x00 3118 1.1 fvdl 3119 1.1 fvdl #define ROMADDR 0x8a 3120 1.1 fvdl 3121 1.1 fvdl #define ROMCNTRL 0x8d 3122 1.1 fvdl #define ROMOP 0xe0 3123 1.1 fvdl #define ROMSPD 0x18 3124 1.1 fvdl #define REPEAT 0x02 3125 1.1 fvdl #define RDY 0x01 3126 1.1 fvdl 3127 1.1 fvdl #define ROMDATA 0x8e 3128 1.1 fvdl 3129 1.1 fvdl #define DCHRXMSG0 0x90 3130 1.1 fvdl 3131 1.1 fvdl #define ROENABLE 0x90 3132 1.1 fvdl #define MSIROEN 0x20 3133 1.1 fvdl #define OVLYROEN 0x10 3134 1.1 fvdl #define CMCROEN 0x08 3135 1.1 fvdl #define SGROEN 0x04 3136 1.1 fvdl #define DCH1ROEN 0x02 3137 1.1 fvdl #define DCH0ROEN 0x01 3138 1.1 fvdl 3139 1.1 fvdl #define OVLYRXMSG0 0x90 3140 1.1 fvdl 3141 1.1 fvdl #define CMCRXMSG0 0x90 3142 1.1 fvdl 3143 1.1 fvdl #define NSENABLE 0x91 3144 1.1 fvdl #define MSINSEN 0x20 3145 1.1 fvdl #define OVLYNSEN 0x10 3146 1.1 fvdl #define CMCNSEN 0x08 3147 1.1 fvdl #define SGNSEN 0x04 3148 1.1 fvdl #define DCH1NSEN 0x02 3149 1.1 fvdl #define DCH0NSEN 0x01 3150 1.1 fvdl 3151 1.1 fvdl #define DCHRXMSG1 0x91 3152 1.1 fvdl 3153 1.1 fvdl #define OVLYRXMSG1 0x91 3154 1.1 fvdl 3155 1.1 fvdl #define CMCRXMSG1 0x91 3156 1.1 fvdl 3157 1.1 fvdl #define DCHRXMSG2 0x92 3158 1.1 fvdl 3159 1.1 fvdl #define OVLYRXMSG2 0x92 3160 1.1 fvdl 3161 1.1 fvdl #define CMCRXMSG2 0x92 3162 1.1 fvdl 3163 1.1 fvdl #define OST 0x92 3164 1.1 fvdl 3165 1.1 fvdl #define DCHRXMSG3 0x93 3166 1.1 fvdl 3167 1.1 fvdl #define CMCRXMSG3 0x93 3168 1.1 fvdl 3169 1.1 fvdl #define PCIXCTL 0x93 3170 1.1 fvdl #define SERRPULSE 0x80 3171 1.1 fvdl #define UNEXPSCIEN 0x20 3172 1.1 fvdl #define SPLTSMADIS 0x10 3173 1.1 fvdl #define SPLTSTADIS 0x08 3174 1.1 fvdl #define SRSPDPEEN 0x04 3175 1.1 fvdl #define TSCSERREN 0x02 3176 1.1 fvdl #define CMPABCDIS 0x01 3177 1.1 fvdl 3178 1.1 fvdl #define OVLYRXMSG3 0x93 3179 1.1 fvdl 3180 1.1 fvdl #define OVLYSEQBCNT 0x94 3181 1.1 fvdl 3182 1.1 fvdl #define CMCSEQBCNT 0x94 3183 1.1 fvdl 3184 1.1 fvdl #define DCHSEQBCNT 0x94 3185 1.1 fvdl 3186 1.1 fvdl #define OVLYSPLTSTAT0 0x96 3187 1.1 fvdl 3188 1.1 fvdl #define CMCSPLTSTAT0 0x96 3189 1.1 fvdl 3190 1.1 fvdl #define DCHSPLTSTAT0 0x96 3191 1.1 fvdl 3192 1.1 fvdl #define OVLYSPLTSTAT1 0x97 3193 1.1 fvdl 3194 1.1 fvdl #define DCHSPLTSTAT1 0x97 3195 1.1 fvdl 3196 1.1 fvdl #define CMCSPLTSTAT1 0x97 3197 1.1 fvdl 3198 1.1 fvdl #define SGRXMSG0 0x98 3199 1.1 fvdl #define CDNUM 0xf8 3200 1.1 fvdl #define CFNUM 0x07 3201 1.1 fvdl 3202 1.1 fvdl #define SLVSPLTOUTADR0 0x98 3203 1.1 fvdl #define LOWER_ADDR 0x7f 3204 1.1 fvdl 3205 1.1 fvdl #define SLVSPLTOUTADR1 0x99 3206 1.1 fvdl #define REQ_DNUM 0xf8 3207 1.1 fvdl #define REQ_FNUM 0x07 3208 1.1 fvdl 3209 1.1 fvdl #define SGRXMSG1 0x99 3210 1.1 fvdl #define CBNUM 0xff 3211 1.1 fvdl 3212 1.1 fvdl #define SLVSPLTOUTADR2 0x9a 3213 1.1 fvdl #define REQ_BNUM 0xff 3214 1.1 fvdl 3215 1.1 fvdl #define SGRXMSG2 0x9a 3216 1.1 fvdl #define MINDEX 0xff 3217 1.1 fvdl 3218 1.1 fvdl #define SLVSPLTOUTADR3 0x9b 3219 1.1 fvdl #define TAG_NUM 0x1f 3220 1.1 fvdl #define RLXORD 0x10 3221 1.1 fvdl 3222 1.1 fvdl #define SGRXMSG3 0x9b 3223 1.1 fvdl #define MCLASS 0x0f 3224 1.1 fvdl 3225 1.1 fvdl #define SGSEQBCNT 0x9c 3226 1.1 fvdl 3227 1.1 fvdl #define SLVSPLTOUTATTR0 0x9c 3228 1.1 fvdl #define LOWER_BCNT 0xff 3229 1.1 fvdl 3230 1.1 fvdl #define SLVSPLTOUTATTR1 0x9d 3231 1.1 fvdl #define CMPLT_DNUM 0xf8 3232 1.1 fvdl #define CMPLT_FNUM 0x07 3233 1.1 fvdl 3234 1.1 fvdl #define SGSPLTSTAT0 0x9e 3235 1.1 fvdl #define STAETERM 0x80 3236 1.1 fvdl #define SCBCERR 0x40 3237 1.1 fvdl #define SCADERR 0x20 3238 1.1 fvdl #define SCDATBUCKET 0x10 3239 1.1 fvdl #define CNTNOTCMPLT 0x08 3240 1.1 fvdl #define RXOVRUN 0x04 3241 1.1 fvdl #define RXSCEMSG 0x02 3242 1.1 fvdl #define RXSPLTRSP 0x01 3243 1.1 fvdl 3244 1.1 fvdl #define SLVSPLTOUTATTR2 0x9e 3245 1.1 fvdl #define CMPLT_BNUM 0xff 3246 1.1 fvdl 3247 1.1 fvdl #define SGSPLTSTAT1 0x9f 3248 1.1 fvdl #define RXDATABUCKET 0x01 3249 1.1 fvdl 3250 1.1 fvdl #define SFUNCT 0x9f 3251 1.1 fvdl #define TEST_GROUP 0xf0 3252 1.1 fvdl #define TEST_NUM 0x0f 3253 1.1 fvdl 3254 1.1 fvdl #define DF0PCISTAT 0xa0 3255 1.1 fvdl 3256 1.1 fvdl #define REG0 0xa0 3257 1.1 fvdl 3258 1.1 fvdl #define DF1PCISTAT 0xa1 3259 1.1 fvdl 3260 1.1 fvdl #define SGPCISTAT 0xa2 3261 1.1 fvdl 3262 1.1 fvdl #define REG1 0xa2 3263 1.1 fvdl 3264 1.1 fvdl #define CMCPCISTAT 0xa3 3265 1.1 fvdl 3266 1.1 fvdl #define OVLYPCISTAT 0xa4 3267 1.1 fvdl #define SCAAPERR 0x08 3268 1.1 fvdl #define RDPERR 0x04 3269 1.1 fvdl 3270 1.1 fvdl #define REG_ISR 0xa4 3271 1.1 fvdl 3272 1.1 fvdl #define MSIPCISTAT 0xa6 3273 1.1 fvdl #define RMA 0x20 3274 1.1 fvdl #define RTA 0x10 3275 1.1 fvdl #define CLRPENDMSI 0x08 3276 1.1 fvdl #define DPR 0x01 3277 1.1 fvdl 3278 1.1 fvdl #define SG_STATE 0xa6 3279 1.1 fvdl #define FETCH_INPROG 0x04 3280 1.1 fvdl #define LOADING_NEEDED 0x02 3281 1.1 fvdl #define SEGS_AVAIL 0x01 3282 1.1 fvdl 3283 1.1 fvdl #define DATA_COUNT_ODD 0xa7 3284 1.1 fvdl 3285 1.1 fvdl #define TARGPCISTAT 0xa7 3286 1.1 fvdl #define DPE 0x80 3287 1.1 fvdl #define SSE 0x40 3288 1.1 fvdl #define STA 0x08 3289 1.1 fvdl #define TWATERR 0x02 3290 1.1 fvdl 3291 1.1 fvdl #define SCBPTR 0xa8 3292 1.1 fvdl 3293 1.1 fvdl #define SCBAUTOPTR 0xab 3294 1.1 fvdl #define AUSCBPTR_EN 0x80 3295 1.1 fvdl #define SCBPTR_ADDR 0x38 3296 1.1 fvdl #define SCBPTR_OFF 0x07 3297 1.1 fvdl 3298 1.1 fvdl #define CCSCBACNT 0xab 3299 1.1 fvdl 3300 1.1 fvdl #define CCSCBADDR 0xac 3301 1.1 fvdl 3302 1.1 fvdl #define CCSCBADR_BK 0xac 3303 1.1 fvdl 3304 1.1 fvdl #define CCSGADDR 0xac 3305 1.1 fvdl 3306 1.1 fvdl #define CCSCBCTL 0xad 3307 1.1 fvdl #define CCSCBDONE 0x80 3308 1.1 fvdl #define ARRDONE 0x40 3309 1.1 fvdl #define CCARREN 0x10 3310 1.1 fvdl #define CCSCBEN 0x08 3311 1.1 fvdl #define CCSCBDIR 0x04 3312 1.1 fvdl #define CCSCBRESET 0x01 3313 1.1 fvdl 3314 1.1 fvdl #define CCSGCTL 0xad 3315 1.1 fvdl #define CCSGEN 0x0c 3316 1.1 fvdl #define CCSGDONE 0x80 3317 1.1 fvdl #define SG_CACHE_AVAIL 0x10 3318 1.1 fvdl #define CCSGENACK 0x08 3319 1.1 fvdl #define SG_FETCH_REQ 0x02 3320 1.1 fvdl #define CCSGRESET 0x01 3321 1.1 fvdl 3322 1.1 fvdl #define CMC_RAMBIST 0xad 3323 1.1 fvdl #define SG_ELEMENT_SIZE 0x80 3324 1.1 fvdl #define SCBRAMBIST_FAIL 0x40 3325 1.1 fvdl #define SG_BIST_FAIL 0x20 3326 1.1 fvdl #define SG_BIST_EN 0x10 3327 1.1 fvdl #define CMC_BUFFER_BIST_FAIL 0x02 3328 1.1 fvdl #define CMC_BUFFER_BIST_EN 0x01 3329 1.1 fvdl 3330 1.1 fvdl #define CCSGRAM 0xb0 3331 1.1 fvdl 3332 1.1 fvdl #define CCSCBRAM 0xb0 3333 1.1 fvdl 3334 1.1 fvdl #define FLEXADR 0xb0 3335 1.1 fvdl 3336 1.1 fvdl #define FLEXCNT 0xb3 3337 1.1 fvdl 3338 1.1 fvdl #define FLEXDMASTAT 0xb5 3339 1.1 fvdl #define FLEXDMAERR 0x02 3340 1.1 fvdl #define FLEXDMADONE 0x01 3341 1.1 fvdl 3342 1.1 fvdl #define FLEXDATA 0xb6 3343 1.1 fvdl 3344 1.1 fvdl #define BRDDAT 0xb8 3345 1.1 fvdl 3346 1.1 fvdl #define BRDCTL 0xb9 3347 1.1 fvdl #define FLXARBACK 0x80 3348 1.1 fvdl #define FLXARBREQ 0x40 3349 1.1 fvdl #define BRDADDR 0x38 3350 1.1 fvdl #define BRDEN 0x04 3351 1.1 fvdl #define BRDRW 0x02 3352 1.1 fvdl #define BRDSTB 0x01 3353 1.1 fvdl 3354 1.1 fvdl #define SEEADR 0xba 3355 1.1 fvdl 3356 1.1 fvdl #define SEEDAT 0xbc 3357 1.1 fvdl 3358 1.1 fvdl #define SEECTL 0xbe 3359 1.1 fvdl #define SEEOP_EWDS 0x40 3360 1.1 fvdl #define SEEOP_WALL 0x40 3361 1.1 fvdl #define SEEOP_EWEN 0x40 3362 1.1 fvdl #define SEEOPCODE 0x70 3363 1.1 fvdl #define SEERST 0x02 3364 1.1 fvdl #define SEESTART 0x01 3365 1.1 fvdl #define SEEOP_ERASE 0x70 3366 1.1 fvdl #define SEEOP_READ 0x60 3367 1.1 fvdl #define SEEOP_WRITE 0x50 3368 1.1 fvdl #define SEEOP_ERAL 0x40 3369 1.1 fvdl 3370 1.1 fvdl #define SEESTAT 0xbe 3371 1.1 fvdl #define INIT_DONE 0x80 3372 1.1 fvdl #define LDALTID_L 0x08 3373 1.1 fvdl #define SEEARBACK 0x04 3374 1.1 fvdl #define SEEBUSY 0x02 3375 1.1 fvdl 3376 1.1 fvdl #define SCBCNT 0xbf 3377 1.1 fvdl 3378 1.1 fvdl #define DSPFLTRCTL 0xc0 3379 1.1 fvdl #define FLTRDISABLE 0x20 3380 1.1 fvdl #define EDGESENSE 0x10 3381 1.1 fvdl #define DSPFCNTSEL 0x0f 3382 1.1 fvdl 3383 1.1 fvdl #define DFWADDR 0xc0 3384 1.1 fvdl 3385 1.1 fvdl #define DSPDATACTL 0xc1 3386 1.1 fvdl #define BYPASSENAB 0x80 3387 1.1 fvdl #define DESQDIS 0x10 3388 1.1 fvdl #define RCVROFFSTDIS 0x04 3389 1.1 fvdl #define XMITOFFSTDIS 0x02 3390 1.1 fvdl 3391 1.1 fvdl #define DSPREQCTL 0xc2 3392 1.1 fvdl #define MANREQCTL 0xc0 3393 1.1 fvdl #define MANREQDLY 0x3f 3394 1.1 fvdl 3395 1.1 fvdl #define DFRADDR 0xc2 3396 1.1 fvdl 3397 1.1 fvdl #define DSPACKCTL 0xc3 3398 1.1 fvdl #define MANACKCTL 0xc0 3399 1.1 fvdl #define MANACKDLY 0x3f 3400 1.1 fvdl 3401 1.1 fvdl #define DFDAT 0xc4 3402 1.1 fvdl 3403 1.1 fvdl #define DSPSELECT 0xc4 3404 1.1 fvdl #define AUTOINCEN 0x80 3405 1.1 fvdl #define DSPSEL 0x1f 3406 1.1 fvdl 3407 1.1 fvdl #define WRTBIASCTL 0xc5 3408 1.1 fvdl #define AUTOXBCDIS 0x80 3409 1.1 fvdl #define XMITMANVAL 0x3f 3410 1.1 fvdl 3411 1.1 fvdl #define RCVRBIOSCTL 0xc6 3412 1.1 fvdl #define AUTORBCDIS 0x80 3413 1.1 fvdl #define RCVRMANVAL 0x3f 3414 1.1 fvdl 3415 1.1 fvdl #define WRTBIASCALC 0xc7 3416 1.1 fvdl 3417 1.1 fvdl #define DFPTRS 0xc8 3418 1.1 fvdl 3419 1.1 fvdl #define RCVRBIASCALC 0xc8 3420 1.1 fvdl 3421 1.1 fvdl #define DFBKPTR 0xc9 3422 1.1 fvdl 3423 1.1 fvdl #define SKEWCALC 0xc9 3424 1.1 fvdl 3425 1.1 fvdl #define DFDBCTL 0xcb 3426 1.1 fvdl #define DFF_CIO_WR_RDY 0x20 3427 1.1 fvdl #define DFF_CIO_RD_RDY 0x10 3428 1.1 fvdl #define DFF_DIR_ERR 0x08 3429 1.1 fvdl #define DFF_RAMBIST_FAIL 0x04 3430 1.1 fvdl #define DFF_RAMBIST_DONE 0x02 3431 1.1 fvdl #define DFF_RAMBIST_EN 0x01 3432 1.1 fvdl 3433 1.1 fvdl #define DFSCNT 0xcc 3434 1.1 fvdl 3435 1.1 fvdl #define DFBCNT 0xce 3436 1.1 fvdl 3437 1.1 fvdl #define OVLYADDR 0xd4 3438 1.1 fvdl 3439 1.1 fvdl #define SEQCTL0 0xd6 3440 1.1 fvdl #define PERRORDIS 0x80 3441 1.1 fvdl #define PAUSEDIS 0x40 3442 1.1 fvdl #define FAILDIS 0x20 3443 1.1 fvdl #define FASTMODE 0x10 3444 1.1 fvdl #define BRKADRINTEN 0x08 3445 1.1 fvdl #define STEP 0x04 3446 1.1 fvdl #define SEQRESET 0x02 3447 1.1 fvdl #define LOADRAM 0x01 3448 1.1 fvdl 3449 1.1 fvdl #define SEQCTL1 0xd7 3450 1.1 fvdl #define OVRLAY_DATA_CHK 0x08 3451 1.1 fvdl #define RAMBIST_DONE 0x04 3452 1.1 fvdl #define RAMBIST_FAIL 0x02 3453 1.1 fvdl #define RAMBIST_EN 0x01 3454 1.1 fvdl 3455 1.1 fvdl #define FLAGS 0xd8 3456 1.1 fvdl #define ZERO 0x02 3457 1.1 fvdl #define CARRY 0x01 3458 1.1 fvdl 3459 1.1 fvdl #define SEQINTCTL 0xd9 3460 1.1 fvdl #define INTVEC1DSL 0x80 3461 1.1 fvdl #define INT1_CONTEXT 0x20 3462 1.1 fvdl #define SCS_SEQ_INT1M1 0x10 3463 1.1 fvdl #define SCS_SEQ_INT1M0 0x08 3464 1.1 fvdl #define INTMASK2 0x04 3465 1.1 fvdl #define INTMASK1 0x02 3466 1.1 fvdl #define IRET 0x01 3467 1.1 fvdl 3468 1.1 fvdl #define SEQRAM 0xda 3469 1.1 fvdl 3470 1.1 fvdl #define PRGMCNT 0xde 3471 1.1 fvdl 3472 1.1 fvdl #define ACCUM 0xe0 3473 1.1 fvdl 3474 1.1 fvdl #define SINDEX 0xe2 3475 1.1 fvdl 3476 1.1 fvdl #define DINDEX 0xe4 3477 1.1 fvdl 3478 1.1 fvdl #define BRKADDR0 0xe6 3479 1.1 fvdl 3480 1.1 fvdl #define BRKADDR1 0xe6 3481 1.1 fvdl #define BRKDIS 0x80 3482 1.1 fvdl 3483 1.1 fvdl #define ALLONES 0xe8 3484 1.1 fvdl 3485 1.1 fvdl #define NONE 0xea 3486 1.1 fvdl 3487 1.1 fvdl #define ALLZEROS 0xea 3488 1.1 fvdl 3489 1.1 fvdl #define SINDIR 0xec 3490 1.1 fvdl 3491 1.1 fvdl #define DINDIR 0xed 3492 1.1 fvdl 3493 1.1 fvdl #define FUNCTION1 0xf0 3494 1.1 fvdl 3495 1.1 fvdl #define STACK 0xf2 3496 1.1 fvdl 3497 1.1 fvdl #define INTVEC1_ADDR 0xf4 3498 1.1 fvdl 3499 1.1 fvdl #define CURADDR 0xf4 3500 1.1 fvdl 3501 1.1 fvdl #define LASTADDR 0xf6 3502 1.1 fvdl 3503 1.1 fvdl #define INTVEC2_ADDR 0xf6 3504 1.1 fvdl 3505 1.1 fvdl #define LONGJMP_ADDR 0xf8 3506 1.1 fvdl 3507 1.3.2.1 skrll #define ACCUM_SAVE 0xfa 3508 1.1 fvdl 3509 1.1 fvdl #define AHD_PCI_CONFIG_BASE 0x100 3510 1.1 fvdl 3511 1.1 fvdl #define SRAM_BASE 0x100 3512 1.1 fvdl 3513 1.1 fvdl #define WAITING_SCB_TAILS 0x100 3514 1.1 fvdl 3515 1.1 fvdl #define WAITING_TID_HEAD 0x120 3516 1.1 fvdl 3517 1.1 fvdl #define WAITING_TID_TAIL 0x122 3518 1.1 fvdl 3519 1.1 fvdl #define NEXT_QUEUED_SCB_ADDR 0x124 3520 1.1 fvdl 3521 1.1 fvdl #define COMPLETE_SCB_HEAD 0x128 3522 1.1 fvdl 3523 1.1 fvdl #define COMPLETE_SCB_DMAINPROG_HEAD 0x12a 3524 1.1 fvdl 3525 1.1 fvdl #define COMPLETE_DMA_SCB_HEAD 0x12c 3526 1.1 fvdl 3527 1.1 fvdl #define QFREEZE_COUNT 0x12e 3528 1.1 fvdl 3529 1.1 fvdl #define SAVED_MODE 0x130 3530 1.1 fvdl 3531 1.1 fvdl #define MSG_OUT 0x131 3532 1.1 fvdl 3533 1.1 fvdl #define DMAPARAMS 0x132 3534 1.1 fvdl #define PRELOADEN 0x80 3535 1.1 fvdl #define WIDEODD 0x40 3536 1.1 fvdl #define SCSIEN 0x20 3537 1.1 fvdl #define SDMAENACK 0x10 3538 1.1 fvdl #define SDMAEN 0x10 3539 1.1 fvdl #define HDMAEN 0x08 3540 1.1 fvdl #define HDMAENACK 0x08 3541 1.1 fvdl #define DIRECTION 0x04 3542 1.1 fvdl #define FIFOFLUSH 0x02 3543 1.1 fvdl #define FIFORESET 0x01 3544 1.1 fvdl 3545 1.1 fvdl #define SEQ_FLAGS 0x133 3546 1.1 fvdl #define NOT_IDENTIFIED 0x80 3547 1.1 fvdl #define NO_CDB_SENT 0x40 3548 1.1 fvdl #define TARGET_CMD_IS_TAGGED 0x40 3549 1.1 fvdl #define DPHASE 0x20 3550 1.1 fvdl #define TARG_CMD_PENDING 0x10 3551 1.1 fvdl #define CMDPHASE_PENDING 0x08 3552 1.1 fvdl #define DPHASE_PENDING 0x04 3553 1.1 fvdl #define SPHASE_PENDING 0x02 3554 1.1 fvdl #define NO_DISCONNECT 0x01 3555 1.1 fvdl 3556 1.1 fvdl #define SAVED_SCSIID 0x134 3557 1.1 fvdl 3558 1.1 fvdl #define SAVED_LUN 0x135 3559 1.1 fvdl 3560 1.1 fvdl #define LASTPHASE 0x136 3561 1.1 fvdl #define PHASE_MASK 0xe0 3562 1.1 fvdl #define CDI 0x80 3563 1.1 fvdl #define IOI 0x40 3564 1.1 fvdl #define MSGI 0x20 3565 1.1 fvdl #define P_BUSFREE 0x01 3566 1.1 fvdl #define P_MESGIN 0xe0 3567 1.1 fvdl #define P_STATUS 0xc0 3568 1.1 fvdl #define P_MESGOUT 0xa0 3569 1.1 fvdl #define P_COMMAND 0x80 3570 1.1 fvdl #define P_DATAIN_DT 0x60 3571 1.1 fvdl #define P_DATAIN 0x40 3572 1.1 fvdl #define P_DATAOUT_DT 0x20 3573 1.1 fvdl #define P_DATAOUT 0x00 3574 1.1 fvdl 3575 1.1 fvdl #define QOUTFIFO_ENTRY_VALID_TAG 0x137 3576 1.1 fvdl 3577 1.1 fvdl #define SHARED_DATA_ADDR 0x138 3578 1.1 fvdl 3579 1.1 fvdl #define QOUTFIFO_NEXT_ADDR 0x13c 3580 1.1 fvdl 3581 1.1 fvdl #define KERNEL_TQINPOS 0x140 3582 1.1 fvdl 3583 1.1 fvdl #define TQINPOS 0x141 3584 1.1 fvdl 3585 1.1 fvdl #define ARG_1 0x142 3586 1.1 fvdl #define RETURN_1 0x142 3587 1.1 fvdl #define SEND_MSG 0x80 3588 1.1 fvdl #define SEND_SENSE 0x40 3589 1.1 fvdl #define SEND_REJ 0x20 3590 1.1 fvdl #define MSGOUT_PHASEMIS 0x10 3591 1.1 fvdl #define EXIT_MSG_LOOP 0x08 3592 1.1 fvdl #define CONT_MSG_LOOP_WRITE 0x04 3593 1.1 fvdl #define CONT_MSG_LOOP_READ 0x03 3594 1.1 fvdl #define CONT_MSG_LOOP_TARG 0x02 3595 1.1 fvdl 3596 1.1 fvdl #define ARG_2 0x143 3597 1.1 fvdl #define RETURN_2 0x143 3598 1.1 fvdl 3599 1.1 fvdl #define LAST_MSG 0x144 3600 1.1 fvdl 3601 1.1 fvdl #define SCSISEQ_TEMPLATE 0x145 3602 1.1 fvdl #define MANUALCTL 0x40 3603 1.1 fvdl #define ENSELI 0x20 3604 1.1 fvdl #define ENRSELI 0x10 3605 1.1 fvdl #define MANUALP 0x0c 3606 1.1 fvdl #define ENAUTOATNP 0x02 3607 1.1 fvdl #define ALTSTIM 0x01 3608 1.1 fvdl 3609 1.1 fvdl #define INITIATOR_TAG 0x146 3610 1.1 fvdl 3611 1.1 fvdl #define SEQ_FLAGS2 0x147 3612 1.1 fvdl #define SELECTOUT_QFROZEN 0x04 3613 1.1 fvdl #define TARGET_MSG_PENDING 0x02 3614 1.1 fvdl 3615 1.1 fvdl #define ALLOCFIFO_SCBPTR 0x148 3616 1.1 fvdl 3617 1.3 wiz #define INT_COALESCING_TIMER 0x14a 3618 1.1 fvdl 3619 1.3 wiz #define INT_COALESCING_MAXCMDS 0x14c 3620 1.1 fvdl 3621 1.3 wiz #define INT_COALESCING_MINCMDS 0x14d 3622 1.1 fvdl 3623 1.1 fvdl #define CMDS_PENDING 0x14e 3624 1.1 fvdl 3625 1.3 wiz #define INT_COALESCING_CMDCOUNT 0x150 3626 1.1 fvdl 3627 1.1 fvdl #define LOCAL_HS_MAILBOX 0x151 3628 1.1 fvdl 3629 1.1 fvdl #define CMDSIZE_TABLE 0x152 3630 1.1 fvdl 3631 1.1 fvdl #define SCB_BASE 0x180 3632 1.1 fvdl 3633 1.1 fvdl #define SCB_RESIDUAL_DATACNT 0x180 3634 1.1 fvdl #define SCB_HOST_CDB_PTR 0x180 3635 1.1 fvdl #define SCB_CDB_STORE 0x180 3636 1.1 fvdl 3637 1.1 fvdl #define SCB_RESIDUAL_SGPTR 0x184 3638 1.1 fvdl #define SG_ADDR_MASK 0xf8 3639 1.1 fvdl #define SG_OVERRUN_RESID 0x02 3640 1.1 fvdl 3641 1.1 fvdl #define SCB_SCSI_STATUS 0x188 3642 1.1 fvdl #define SCB_HOST_CDB_LEN 0x188 3643 1.1 fvdl 3644 1.1 fvdl #define SCB_TARGET_PHASES 0x189 3645 1.1 fvdl 3646 1.1 fvdl #define SCB_TARGET_DATA_DIR 0x18a 3647 1.1 fvdl 3648 1.1 fvdl #define SCB_TARGET_ITAG 0x18b 3649 1.1 fvdl 3650 1.1 fvdl #define SCB_SENSE_BUSADDR 0x18c 3651 1.1 fvdl #define SCB_NEXT_COMPLETE 0x18c 3652 1.1 fvdl 3653 1.1 fvdl #define SCB_TAG 0x190 3654 1.3.2.1 skrll #define SCB_FIFO_USE_COUNT 0x190 3655 1.1 fvdl 3656 1.3.2.1 skrll #define SCB_CONTROL 0x192 3657 1.3.2.1 skrll #define TARGET_SCB 0x80 3658 1.3.2.1 skrll #define DISCENB 0x40 3659 1.3.2.1 skrll #define TAG_ENB 0x20 3660 1.3.2.1 skrll #define MK_MESSAGE 0x10 3661 1.3.2.1 skrll #define STATUS_RCVD 0x08 3662 1.3.2.1 skrll #define DISCONNECTED 0x04 3663 1.3.2.1 skrll #define SCB_TAG_TYPE 0x03 3664 1.3.2.1 skrll 3665 1.3.2.1 skrll #define SCB_SCSIID 0x193 3666 1.3.2.1 skrll #define TID 0xf0 3667 1.3.2.1 skrll #define OID 0x0f 3668 1.1 fvdl 3669 1.3.2.1 skrll #define SCB_LUN 0x194 3670 1.3.2.1 skrll #define LID 0xff 3671 1.3.2.1 skrll 3672 1.3.2.1 skrll #define SCB_TASK_ATTRIBUTE 0x195 3673 1.3.2.1 skrll #define SCB_XFERLEN_ODD 0x01 3674 1.1 fvdl 3675 1.3.2.1 skrll #define SCB_CDB_LEN 0x196 3676 1.3.2.1 skrll #define SCB_CDB_LEN_PTR 0x80 3677 1.1 fvdl 3678 1.3.2.1 skrll #define SCB_TASK_MANAGEMENT 0x197 3679 1.1 fvdl 3680 1.1 fvdl #define SCB_DATAPTR 0x198 3681 1.1 fvdl 3682 1.1 fvdl #define SCB_DATACNT 0x1a0 3683 1.1 fvdl #define SG_LAST_SEG 0x80 3684 1.1 fvdl #define SG_HIGH_ADDR_BITS 0x7f 3685 1.1 fvdl 3686 1.1 fvdl #define SCB_SGPTR 0x1a4 3687 1.1 fvdl #define SG_STATUS_VALID 0x04 3688 1.1 fvdl #define SG_FULL_RESID 0x02 3689 1.1 fvdl #define SG_LIST_NULL 0x01 3690 1.1 fvdl 3691 1.3.2.1 skrll #define SCB_BUSADDR 0x1a8 3692 1.1 fvdl 3693 1.3.2.1 skrll #define SCB_NEXT 0x1ac 3694 1.3.2.1 skrll #define SCB_NEXT_SCB_BUSADDR 0x1ac 3695 1.1 fvdl 3696 1.3.2.1 skrll #define SCB_NEXT2 0x1ae 3697 1.1 fvdl 3698 1.1 fvdl #define SCB_SPARE 0x1b0 3699 1.1 fvdl #define SCB_PKT_LUN 0x1b0 3700 1.1 fvdl 3701 1.1 fvdl #define SCB_DISCONNECTED_LISTS 0x1b8 3702 1.1 fvdl 3703 1.1 fvdl 3704 1.1 fvdl #define PKT_OVERRUN_BUFSIZE 0x200 3705 1.1 fvdl #define SCB_TRANSFER_SIZE_FULL_LUN 0x38 3706 1.1 fvdl #define TARGET_DATA_IN 0x01 3707 1.1 fvdl #define STATUS_BUSY 0x08 3708 1.1 fvdl #define BUS_16_BIT 0x01 3709 1.1 fvdl #define CCSCBADDR_MAX 0x80 3710 1.1 fvdl #define TID_SHIFT 0x04 3711 1.1 fvdl #define AHD_AMPLITUDE_SHIFT 0x00 3712 1.2 fvdl #define AHD_SLEWRATE_DEF_REVA 0x08 3713 1.1 fvdl #define AHD_SLEWRATE_MASK 0x78 3714 1.1 fvdl #define MAX_OFFSET_PACED_BUG 0x7f 3715 1.1 fvdl #define AHD_PRECOMP_CUTBACK_17 0x04 3716 1.1 fvdl #define AHD_PRECOMP_MASK 0x07 3717 1.1 fvdl #define AHD_TIMER_US_PER_TICK 0x19 3718 1.1 fvdl #define HOST_MSG 0xff 3719 1.1 fvdl #define MAX_OFFSET 0xfe 3720 1.1 fvdl #define BUS_32_BIT 0x02 3721 1.1 fvdl #define SEEOP_EWEN_ADDR 0xc0 3722 1.1 fvdl #define AHD_AMPLITUDE_MASK 0x07 3723 1.3.2.1 skrll #define LUNLEN_SINGLE_LEVEL_LUN 0x0f 3724 1.1 fvdl #define DST_MODE_SHIFT 0x04 3725 1.1 fvdl #define AHD_TIMER_MAX_TICKS 0xffff 3726 1.1 fvdl #define STATUS_PKT_SENSE 0xff 3727 1.1 fvdl #define CMD_GROUP_CODE_SHIFT 0x05 3728 1.1 fvdl #define BUS_8_BIT 0x00 3729 1.1 fvdl #define STIMESEL_SHIFT 0x03 3730 1.1 fvdl #define CCSGRAM_MAXSEGS 0x10 3731 1.1 fvdl #define SEEOP_WRAL_ADDR 0x40 3732 1.1 fvdl #define AHD_AMPLITUDE_DEF 0x07 3733 1.1 fvdl #define AHD_SLEWRATE_DEF_REVB 0x08 3734 1.1 fvdl #define AHD_PRECOMP_CUTBACK_37 0x07 3735 1.1 fvdl #define AHD_PRECOMP_SHIFT 0x00 3736 1.1 fvdl #define AHD_ANNEXCOL_PRECOMP_SLEW 0x04 3737 1.1 fvdl #define STATUS_QUEUE_FULL 0x28 3738 1.1 fvdl #define MAX_OFFSET_NON_PACED 0x7f 3739 1.1 fvdl #define WRTBIASCTL_HP_DEFAULT 0x00 3740 1.1 fvdl #define NUMDSPS 0x14 3741 1.1 fvdl #define AHD_NUM_PER_DEV_ANNEXCOLS 0x04 3742 1.1 fvdl #define NVRAM_SCB_OFFSET 0x2c 3743 1.1 fvdl #define AHD_TIMER_MAX_US 0x18ffe7 3744 1.1 fvdl #define AHD_SENSE_BUFSIZE 0x100 3745 1.1 fvdl #define STIMESEL_BUG_ADJ 0x08 3746 1.1 fvdl #define STIMESEL_MIN 0x18 3747 1.1 fvdl #define INVALID_ADDR 0x80 3748 1.1 fvdl #define TARGET_CMD_CMPLT 0xfe 3749 1.1 fvdl #define SEEOP_ERAL_ADDR 0x80 3750 1.1 fvdl #define SRC_MODE_SHIFT 0x00 3751 1.1 fvdl #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 3752 1.1 fvdl #define MAX_OFFSET_PACED 0xfe 3753 1.1 fvdl #define CCSGADDR_MAX 0x80 3754 1.1 fvdl #define MK_MESSAGE_BIT_OFFSET 0x04 3755 1.1 fvdl #define SEEOP_EWDS_ADDR 0x00 3756 1.1 fvdl #define AHD_ANNEXCOL_AMPLITUDE 0x06 3757 1.1 fvdl #define AHD_SLEWRATE_SHIFT 0x03 3758 1.1 fvdl #define AHD_PRECOMP_CUTBACK_29 0x06 3759 1.1 fvdl #define AHD_ANNEXCOL_PER_DEV0 0x04 3760 1.1 fvdl #define B_CURRFIFO_0 0x02 3761 1.1 fvdl 3762 1.1 fvdl 3763 1.1 fvdl /* Downloaded Constant Definitions */ 3764 1.1 fvdl #define SCB_TRANSFER_SIZE 0x06 3765 1.1 fvdl #define SG_PREFETCH_CNT 0x00 3766 1.1 fvdl #define SG_PREFETCH_CNT_LIMIT 0x01 3767 1.1 fvdl #define SG_PREFETCH_ADDR_MASK 0x03 3768 1.1 fvdl #define SG_PREFETCH_ALIGN_MASK 0x02 3769 1.1 fvdl #define PKT_OVERRUN_BUFOFFSET 0x05 3770 1.1 fvdl #define SG_SIZEOF 0x04 3771 1.1 fvdl #define DOWNLOAD_CONST_COUNT 0x07 3772 1.1 fvdl 3773 1.1 fvdl 3774 1.1 fvdl /* Exported Labels */ 3775 1.3.2.1 skrll #define LABEL_seq_isr 0x269 3776 1.3.2.1 skrll #define LABEL_timer_isr 0x265 3777
Indexes created Fri Oct 31 09:09:54 GMT 2025