aic7xxx_reg.h revision 1.2
1 1.1 fvdl /* 2 1.2 fvdl * DO NOT EDIT - This file is automatically generated 3 1.2 fvdl * from the following source files: 4 1.2 fvdl * 5 1.2 fvdl * $NetBSD: aic7xxx_reg.h,v 1.2 2003/04/19 19:27:50 fvdl Exp $ 6 1.2 fvdl * $NetBSD: aic7xxx_reg.h,v 1.2 2003/04/19 19:27:50 fvdl Exp $ 7 1.2 fvdl */ 8 1.2 fvdl typedef int (ahc_reg_print_t)(u_int, u_int *, u_int); 9 1.2 fvdl typedef struct ahc_reg_parse_entry { 10 1.2 fvdl char *name; 11 1.2 fvdl uint8_t value; 12 1.2 fvdl uint8_t mask; 13 1.2 fvdl } ahc_reg_parse_entry_t; 14 1.2 fvdl 15 1.2 fvdl #if AIC_DEBUG_REGISTERS 16 1.2 fvdl ahc_reg_print_t ahc_scsiseq_print; 17 1.2 fvdl #else 18 1.2 fvdl #define ahc_scsiseq_print(regvalue, cur_col, wrap) \ 19 1.2 fvdl ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap) 20 1.2 fvdl #endif 21 1.2 fvdl 22 1.2 fvdl #if AIC_DEBUG_REGISTERS 23 1.2 fvdl ahc_reg_print_t ahc_sxfrctl0_print; 24 1.2 fvdl #else 25 1.2 fvdl #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \ 26 1.2 fvdl ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap) 27 1.2 fvdl #endif 28 1.2 fvdl 29 1.2 fvdl #if AIC_DEBUG_REGISTERS 30 1.2 fvdl ahc_reg_print_t ahc_sxfrctl1_print; 31 1.2 fvdl #else 32 1.2 fvdl #define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \ 33 1.2 fvdl ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap) 34 1.2 fvdl #endif 35 1.2 fvdl 36 1.2 fvdl #if AIC_DEBUG_REGISTERS 37 1.2 fvdl ahc_reg_print_t ahc_scsisigo_print; 38 1.2 fvdl #else 39 1.2 fvdl #define ahc_scsisigo_print(regvalue, cur_col, wrap) \ 40 1.2 fvdl ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap) 41 1.2 fvdl #endif 42 1.2 fvdl 43 1.2 fvdl #if AIC_DEBUG_REGISTERS 44 1.2 fvdl ahc_reg_print_t ahc_scsisigi_print; 45 1.2 fvdl #else 46 1.2 fvdl #define ahc_scsisigi_print(regvalue, cur_col, wrap) \ 47 1.2 fvdl ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap) 48 1.2 fvdl #endif 49 1.2 fvdl 50 1.2 fvdl #if AIC_DEBUG_REGISTERS 51 1.2 fvdl ahc_reg_print_t ahc_scsirate_print; 52 1.2 fvdl #else 53 1.2 fvdl #define ahc_scsirate_print(regvalue, cur_col, wrap) \ 54 1.2 fvdl ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap) 55 1.2 fvdl #endif 56 1.2 fvdl 57 1.2 fvdl #if AIC_DEBUG_REGISTERS 58 1.2 fvdl ahc_reg_print_t ahc_scsiid_print; 59 1.2 fvdl #else 60 1.2 fvdl #define ahc_scsiid_print(regvalue, cur_col, wrap) \ 61 1.2 fvdl ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap) 62 1.2 fvdl #endif 63 1.2 fvdl 64 1.2 fvdl #if AIC_DEBUG_REGISTERS 65 1.2 fvdl ahc_reg_print_t ahc_scsidatl_print; 66 1.2 fvdl #else 67 1.2 fvdl #define ahc_scsidatl_print(regvalue, cur_col, wrap) \ 68 1.2 fvdl ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap) 69 1.2 fvdl #endif 70 1.2 fvdl 71 1.2 fvdl #if AIC_DEBUG_REGISTERS 72 1.2 fvdl ahc_reg_print_t ahc_scsidath_print; 73 1.2 fvdl #else 74 1.2 fvdl #define ahc_scsidath_print(regvalue, cur_col, wrap) \ 75 1.2 fvdl ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap) 76 1.2 fvdl #endif 77 1.2 fvdl 78 1.2 fvdl #if AIC_DEBUG_REGISTERS 79 1.2 fvdl ahc_reg_print_t ahc_stcnt_print; 80 1.2 fvdl #else 81 1.2 fvdl #define ahc_stcnt_print(regvalue, cur_col, wrap) \ 82 1.2 fvdl ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap) 83 1.2 fvdl #endif 84 1.2 fvdl 85 1.2 fvdl #if AIC_DEBUG_REGISTERS 86 1.2 fvdl ahc_reg_print_t ahc_optionmode_print; 87 1.2 fvdl #else 88 1.2 fvdl #define ahc_optionmode_print(regvalue, cur_col, wrap) \ 89 1.2 fvdl ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap) 90 1.2 fvdl #endif 91 1.2 fvdl 92 1.2 fvdl #if AIC_DEBUG_REGISTERS 93 1.2 fvdl ahc_reg_print_t ahc_targcrccnt_print; 94 1.2 fvdl #else 95 1.2 fvdl #define ahc_targcrccnt_print(regvalue, cur_col, wrap) \ 96 1.2 fvdl ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap) 97 1.2 fvdl #endif 98 1.2 fvdl 99 1.2 fvdl #if AIC_DEBUG_REGISTERS 100 1.2 fvdl ahc_reg_print_t ahc_clrsint0_print; 101 1.2 fvdl #else 102 1.2 fvdl #define ahc_clrsint0_print(regvalue, cur_col, wrap) \ 103 1.2 fvdl ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap) 104 1.2 fvdl #endif 105 1.2 fvdl 106 1.2 fvdl #if AIC_DEBUG_REGISTERS 107 1.2 fvdl ahc_reg_print_t ahc_sstat0_print; 108 1.2 fvdl #else 109 1.2 fvdl #define ahc_sstat0_print(regvalue, cur_col, wrap) \ 110 1.2 fvdl ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap) 111 1.2 fvdl #endif 112 1.2 fvdl 113 1.2 fvdl #if AIC_DEBUG_REGISTERS 114 1.2 fvdl ahc_reg_print_t ahc_clrsint1_print; 115 1.2 fvdl #else 116 1.2 fvdl #define ahc_clrsint1_print(regvalue, cur_col, wrap) \ 117 1.2 fvdl ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap) 118 1.2 fvdl #endif 119 1.2 fvdl 120 1.2 fvdl #if AIC_DEBUG_REGISTERS 121 1.2 fvdl ahc_reg_print_t ahc_sstat1_print; 122 1.2 fvdl #else 123 1.2 fvdl #define ahc_sstat1_print(regvalue, cur_col, wrap) \ 124 1.2 fvdl ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap) 125 1.2 fvdl #endif 126 1.2 fvdl 127 1.2 fvdl #if AIC_DEBUG_REGISTERS 128 1.2 fvdl ahc_reg_print_t ahc_sstat2_print; 129 1.2 fvdl #else 130 1.2 fvdl #define ahc_sstat2_print(regvalue, cur_col, wrap) \ 131 1.2 fvdl ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap) 132 1.2 fvdl #endif 133 1.2 fvdl 134 1.2 fvdl #if AIC_DEBUG_REGISTERS 135 1.2 fvdl ahc_reg_print_t ahc_sstat3_print; 136 1.2 fvdl #else 137 1.2 fvdl #define ahc_sstat3_print(regvalue, cur_col, wrap) \ 138 1.2 fvdl ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap) 139 1.2 fvdl #endif 140 1.2 fvdl 141 1.2 fvdl #if AIC_DEBUG_REGISTERS 142 1.2 fvdl ahc_reg_print_t ahc_scsiid_ultra2_print; 143 1.2 fvdl #else 144 1.2 fvdl #define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \ 145 1.2 fvdl ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap) 146 1.2 fvdl #endif 147 1.2 fvdl 148 1.2 fvdl #if AIC_DEBUG_REGISTERS 149 1.2 fvdl ahc_reg_print_t ahc_simode0_print; 150 1.2 fvdl #else 151 1.2 fvdl #define ahc_simode0_print(regvalue, cur_col, wrap) \ 152 1.2 fvdl ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap) 153 1.2 fvdl #endif 154 1.2 fvdl 155 1.2 fvdl #if AIC_DEBUG_REGISTERS 156 1.2 fvdl ahc_reg_print_t ahc_simode1_print; 157 1.2 fvdl #else 158 1.2 fvdl #define ahc_simode1_print(regvalue, cur_col, wrap) \ 159 1.2 fvdl ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap) 160 1.2 fvdl #endif 161 1.2 fvdl 162 1.2 fvdl #if AIC_DEBUG_REGISTERS 163 1.2 fvdl ahc_reg_print_t ahc_scsibusl_print; 164 1.2 fvdl #else 165 1.2 fvdl #define ahc_scsibusl_print(regvalue, cur_col, wrap) \ 166 1.2 fvdl ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap) 167 1.2 fvdl #endif 168 1.2 fvdl 169 1.2 fvdl #if AIC_DEBUG_REGISTERS 170 1.2 fvdl ahc_reg_print_t ahc_sxfrctl2_print; 171 1.2 fvdl #else 172 1.2 fvdl #define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \ 173 1.2 fvdl ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap) 174 1.2 fvdl #endif 175 1.2 fvdl 176 1.2 fvdl #if AIC_DEBUG_REGISTERS 177 1.2 fvdl ahc_reg_print_t ahc_scsibush_print; 178 1.2 fvdl #else 179 1.2 fvdl #define ahc_scsibush_print(regvalue, cur_col, wrap) \ 180 1.2 fvdl ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap) 181 1.2 fvdl #endif 182 1.2 fvdl 183 1.2 fvdl #if AIC_DEBUG_REGISTERS 184 1.2 fvdl ahc_reg_print_t ahc_shaddr_print; 185 1.2 fvdl #else 186 1.2 fvdl #define ahc_shaddr_print(regvalue, cur_col, wrap) \ 187 1.2 fvdl ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap) 188 1.2 fvdl #endif 189 1.2 fvdl 190 1.2 fvdl #if AIC_DEBUG_REGISTERS 191 1.2 fvdl ahc_reg_print_t ahc_seltimer_print; 192 1.2 fvdl #else 193 1.2 fvdl #define ahc_seltimer_print(regvalue, cur_col, wrap) \ 194 1.2 fvdl ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap) 195 1.2 fvdl #endif 196 1.2 fvdl 197 1.2 fvdl #if AIC_DEBUG_REGISTERS 198 1.2 fvdl ahc_reg_print_t ahc_selid_print; 199 1.2 fvdl #else 200 1.2 fvdl #define ahc_selid_print(regvalue, cur_col, wrap) \ 201 1.2 fvdl ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap) 202 1.2 fvdl #endif 203 1.2 fvdl 204 1.2 fvdl #if AIC_DEBUG_REGISTERS 205 1.2 fvdl ahc_reg_print_t ahc_scamctl_print; 206 1.2 fvdl #else 207 1.2 fvdl #define ahc_scamctl_print(regvalue, cur_col, wrap) \ 208 1.2 fvdl ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap) 209 1.2 fvdl #endif 210 1.2 fvdl 211 1.2 fvdl #if AIC_DEBUG_REGISTERS 212 1.2 fvdl ahc_reg_print_t ahc_targid_print; 213 1.2 fvdl #else 214 1.2 fvdl #define ahc_targid_print(regvalue, cur_col, wrap) \ 215 1.2 fvdl ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap) 216 1.2 fvdl #endif 217 1.2 fvdl 218 1.2 fvdl #if AIC_DEBUG_REGISTERS 219 1.2 fvdl ahc_reg_print_t ahc_spiocap_print; 220 1.2 fvdl #else 221 1.2 fvdl #define ahc_spiocap_print(regvalue, cur_col, wrap) \ 222 1.2 fvdl ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap) 223 1.2 fvdl #endif 224 1.2 fvdl 225 1.2 fvdl #if AIC_DEBUG_REGISTERS 226 1.2 fvdl ahc_reg_print_t ahc_brdctl_print; 227 1.2 fvdl #else 228 1.2 fvdl #define ahc_brdctl_print(regvalue, cur_col, wrap) \ 229 1.2 fvdl ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap) 230 1.2 fvdl #endif 231 1.2 fvdl 232 1.2 fvdl #if AIC_DEBUG_REGISTERS 233 1.2 fvdl ahc_reg_print_t ahc_seectl_print; 234 1.2 fvdl #else 235 1.2 fvdl #define ahc_seectl_print(regvalue, cur_col, wrap) \ 236 1.2 fvdl ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap) 237 1.2 fvdl #endif 238 1.2 fvdl 239 1.2 fvdl #if AIC_DEBUG_REGISTERS 240 1.2 fvdl ahc_reg_print_t ahc_sblkctl_print; 241 1.2 fvdl #else 242 1.2 fvdl #define ahc_sblkctl_print(regvalue, cur_col, wrap) \ 243 1.2 fvdl ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap) 244 1.2 fvdl #endif 245 1.2 fvdl 246 1.2 fvdl #if AIC_DEBUG_REGISTERS 247 1.2 fvdl ahc_reg_print_t ahc_busy_targets_print; 248 1.2 fvdl #else 249 1.2 fvdl #define ahc_busy_targets_print(regvalue, cur_col, wrap) \ 250 1.2 fvdl ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap) 251 1.2 fvdl #endif 252 1.2 fvdl 253 1.2 fvdl #if AIC_DEBUG_REGISTERS 254 1.2 fvdl ahc_reg_print_t ahc_ultra_enb_print; 255 1.2 fvdl #else 256 1.2 fvdl #define ahc_ultra_enb_print(regvalue, cur_col, wrap) \ 257 1.2 fvdl ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap) 258 1.2 fvdl #endif 259 1.2 fvdl 260 1.2 fvdl #if AIC_DEBUG_REGISTERS 261 1.2 fvdl ahc_reg_print_t ahc_disc_dsb_print; 262 1.2 fvdl #else 263 1.2 fvdl #define ahc_disc_dsb_print(regvalue, cur_col, wrap) \ 264 1.2 fvdl ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap) 265 1.2 fvdl #endif 266 1.2 fvdl 267 1.2 fvdl #if AIC_DEBUG_REGISTERS 268 1.2 fvdl ahc_reg_print_t ahc_cmdsize_table_tail_print; 269 1.2 fvdl #else 270 1.2 fvdl #define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \ 271 1.2 fvdl ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap) 272 1.2 fvdl #endif 273 1.2 fvdl 274 1.2 fvdl #if AIC_DEBUG_REGISTERS 275 1.2 fvdl ahc_reg_print_t ahc_mwi_residual_print; 276 1.2 fvdl #else 277 1.2 fvdl #define ahc_mwi_residual_print(regvalue, cur_col, wrap) \ 278 1.2 fvdl ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap) 279 1.2 fvdl #endif 280 1.2 fvdl 281 1.2 fvdl #if AIC_DEBUG_REGISTERS 282 1.2 fvdl ahc_reg_print_t ahc_next_queued_scb_print; 283 1.2 fvdl #else 284 1.2 fvdl #define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \ 285 1.2 fvdl ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap) 286 1.2 fvdl #endif 287 1.2 fvdl 288 1.2 fvdl #if AIC_DEBUG_REGISTERS 289 1.2 fvdl ahc_reg_print_t ahc_msg_out_print; 290 1.2 fvdl #else 291 1.2 fvdl #define ahc_msg_out_print(regvalue, cur_col, wrap) \ 292 1.2 fvdl ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap) 293 1.2 fvdl #endif 294 1.2 fvdl 295 1.2 fvdl #if AIC_DEBUG_REGISTERS 296 1.2 fvdl ahc_reg_print_t ahc_dmaparams_print; 297 1.2 fvdl #else 298 1.2 fvdl #define ahc_dmaparams_print(regvalue, cur_col, wrap) \ 299 1.2 fvdl ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap) 300 1.2 fvdl #endif 301 1.2 fvdl 302 1.2 fvdl #if AIC_DEBUG_REGISTERS 303 1.2 fvdl ahc_reg_print_t ahc_seq_flags_print; 304 1.2 fvdl #else 305 1.2 fvdl #define ahc_seq_flags_print(regvalue, cur_col, wrap) \ 306 1.2 fvdl ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap) 307 1.2 fvdl #endif 308 1.2 fvdl 309 1.2 fvdl #if AIC_DEBUG_REGISTERS 310 1.2 fvdl ahc_reg_print_t ahc_saved_scsiid_print; 311 1.2 fvdl #else 312 1.2 fvdl #define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \ 313 1.2 fvdl ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap) 314 1.2 fvdl #endif 315 1.2 fvdl 316 1.2 fvdl #if AIC_DEBUG_REGISTERS 317 1.2 fvdl ahc_reg_print_t ahc_saved_lun_print; 318 1.2 fvdl #else 319 1.2 fvdl #define ahc_saved_lun_print(regvalue, cur_col, wrap) \ 320 1.2 fvdl ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap) 321 1.2 fvdl #endif 322 1.2 fvdl 323 1.2 fvdl #if AIC_DEBUG_REGISTERS 324 1.2 fvdl ahc_reg_print_t ahc_lastphase_print; 325 1.2 fvdl #else 326 1.2 fvdl #define ahc_lastphase_print(regvalue, cur_col, wrap) \ 327 1.2 fvdl ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap) 328 1.2 fvdl #endif 329 1.2 fvdl 330 1.2 fvdl #if AIC_DEBUG_REGISTERS 331 1.2 fvdl ahc_reg_print_t ahc_waiting_scbh_print; 332 1.2 fvdl #else 333 1.2 fvdl #define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \ 334 1.2 fvdl ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap) 335 1.2 fvdl #endif 336 1.2 fvdl 337 1.2 fvdl #if AIC_DEBUG_REGISTERS 338 1.2 fvdl ahc_reg_print_t ahc_disconnected_scbh_print; 339 1.2 fvdl #else 340 1.2 fvdl #define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \ 341 1.2 fvdl ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap) 342 1.2 fvdl #endif 343 1.2 fvdl 344 1.2 fvdl #if AIC_DEBUG_REGISTERS 345 1.2 fvdl ahc_reg_print_t ahc_free_scbh_print; 346 1.2 fvdl #else 347 1.2 fvdl #define ahc_free_scbh_print(regvalue, cur_col, wrap) \ 348 1.2 fvdl ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap) 349 1.2 fvdl #endif 350 1.2 fvdl 351 1.2 fvdl #if AIC_DEBUG_REGISTERS 352 1.2 fvdl ahc_reg_print_t ahc_complete_scbh_print; 353 1.2 fvdl #else 354 1.2 fvdl #define ahc_complete_scbh_print(regvalue, cur_col, wrap) \ 355 1.2 fvdl ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap) 356 1.2 fvdl #endif 357 1.2 fvdl 358 1.2 fvdl #if AIC_DEBUG_REGISTERS 359 1.2 fvdl ahc_reg_print_t ahc_hscb_addr_print; 360 1.2 fvdl #else 361 1.2 fvdl #define ahc_hscb_addr_print(regvalue, cur_col, wrap) \ 362 1.2 fvdl ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap) 363 1.2 fvdl #endif 364 1.2 fvdl 365 1.2 fvdl #if AIC_DEBUG_REGISTERS 366 1.2 fvdl ahc_reg_print_t ahc_shared_data_addr_print; 367 1.2 fvdl #else 368 1.2 fvdl #define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \ 369 1.2 fvdl ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap) 370 1.2 fvdl #endif 371 1.2 fvdl 372 1.2 fvdl #if AIC_DEBUG_REGISTERS 373 1.2 fvdl ahc_reg_print_t ahc_kernel_qinpos_print; 374 1.2 fvdl #else 375 1.2 fvdl #define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \ 376 1.2 fvdl ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap) 377 1.2 fvdl #endif 378 1.2 fvdl 379 1.2 fvdl #if AIC_DEBUG_REGISTERS 380 1.2 fvdl ahc_reg_print_t ahc_qinpos_print; 381 1.2 fvdl #else 382 1.2 fvdl #define ahc_qinpos_print(regvalue, cur_col, wrap) \ 383 1.2 fvdl ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap) 384 1.2 fvdl #endif 385 1.2 fvdl 386 1.2 fvdl #if AIC_DEBUG_REGISTERS 387 1.2 fvdl ahc_reg_print_t ahc_qoutpos_print; 388 1.2 fvdl #else 389 1.2 fvdl #define ahc_qoutpos_print(regvalue, cur_col, wrap) \ 390 1.2 fvdl ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap) 391 1.2 fvdl #endif 392 1.2 fvdl 393 1.2 fvdl #if AIC_DEBUG_REGISTERS 394 1.2 fvdl ahc_reg_print_t ahc_kernel_tqinpos_print; 395 1.2 fvdl #else 396 1.2 fvdl #define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 397 1.2 fvdl ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap) 398 1.2 fvdl #endif 399 1.2 fvdl 400 1.2 fvdl #if AIC_DEBUG_REGISTERS 401 1.2 fvdl ahc_reg_print_t ahc_tqinpos_print; 402 1.2 fvdl #else 403 1.2 fvdl #define ahc_tqinpos_print(regvalue, cur_col, wrap) \ 404 1.2 fvdl ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap) 405 1.2 fvdl #endif 406 1.2 fvdl 407 1.2 fvdl #if AIC_DEBUG_REGISTERS 408 1.2 fvdl ahc_reg_print_t ahc_arg_1_print; 409 1.2 fvdl #else 410 1.2 fvdl #define ahc_arg_1_print(regvalue, cur_col, wrap) \ 411 1.2 fvdl ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap) 412 1.2 fvdl #endif 413 1.2 fvdl 414 1.2 fvdl #if AIC_DEBUG_REGISTERS 415 1.2 fvdl ahc_reg_print_t ahc_arg_2_print; 416 1.2 fvdl #else 417 1.2 fvdl #define ahc_arg_2_print(regvalue, cur_col, wrap) \ 418 1.2 fvdl ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap) 419 1.2 fvdl #endif 420 1.2 fvdl 421 1.2 fvdl #if AIC_DEBUG_REGISTERS 422 1.2 fvdl ahc_reg_print_t ahc_last_msg_print; 423 1.2 fvdl #else 424 1.2 fvdl #define ahc_last_msg_print(regvalue, cur_col, wrap) \ 425 1.2 fvdl ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap) 426 1.2 fvdl #endif 427 1.2 fvdl 428 1.2 fvdl #if AIC_DEBUG_REGISTERS 429 1.2 fvdl ahc_reg_print_t ahc_scsiseq_template_print; 430 1.2 fvdl #else 431 1.2 fvdl #define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \ 432 1.2 fvdl ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap) 433 1.2 fvdl #endif 434 1.2 fvdl 435 1.2 fvdl #if AIC_DEBUG_REGISTERS 436 1.2 fvdl ahc_reg_print_t ahc_data_count_odd_print; 437 1.2 fvdl #else 438 1.2 fvdl #define ahc_data_count_odd_print(regvalue, cur_col, wrap) \ 439 1.2 fvdl ahc_print_register(NULL, 0, "DATA_COUNT_ODD", 0x55, regvalue, cur_col, wrap) 440 1.2 fvdl #endif 441 1.2 fvdl 442 1.2 fvdl #if AIC_DEBUG_REGISTERS 443 1.2 fvdl ahc_reg_print_t ahc_ha_274_biosglobal_print; 444 1.2 fvdl #else 445 1.2 fvdl #define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \ 446 1.2 fvdl ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap) 447 1.2 fvdl #endif 448 1.2 fvdl 449 1.2 fvdl #if AIC_DEBUG_REGISTERS 450 1.2 fvdl ahc_reg_print_t ahc_seq_flags2_print; 451 1.2 fvdl #else 452 1.2 fvdl #define ahc_seq_flags2_print(regvalue, cur_col, wrap) \ 453 1.2 fvdl ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap) 454 1.2 fvdl #endif 455 1.2 fvdl 456 1.2 fvdl #if AIC_DEBUG_REGISTERS 457 1.2 fvdl ahc_reg_print_t ahc_scsiconf_print; 458 1.2 fvdl #else 459 1.2 fvdl #define ahc_scsiconf_print(regvalue, cur_col, wrap) \ 460 1.2 fvdl ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap) 461 1.2 fvdl #endif 462 1.2 fvdl 463 1.2 fvdl #if AIC_DEBUG_REGISTERS 464 1.2 fvdl ahc_reg_print_t ahc_intdef_print; 465 1.2 fvdl #else 466 1.2 fvdl #define ahc_intdef_print(regvalue, cur_col, wrap) \ 467 1.2 fvdl ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap) 468 1.2 fvdl #endif 469 1.2 fvdl 470 1.2 fvdl #if AIC_DEBUG_REGISTERS 471 1.2 fvdl ahc_reg_print_t ahc_hostconf_print; 472 1.2 fvdl #else 473 1.2 fvdl #define ahc_hostconf_print(regvalue, cur_col, wrap) \ 474 1.2 fvdl ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap) 475 1.2 fvdl #endif 476 1.2 fvdl 477 1.2 fvdl #if AIC_DEBUG_REGISTERS 478 1.2 fvdl ahc_reg_print_t ahc_ha_274_biosctrl_print; 479 1.2 fvdl #else 480 1.2 fvdl #define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \ 481 1.2 fvdl ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap) 482 1.2 fvdl #endif 483 1.2 fvdl 484 1.2 fvdl #if AIC_DEBUG_REGISTERS 485 1.2 fvdl ahc_reg_print_t ahc_seqctl_print; 486 1.2 fvdl #else 487 1.2 fvdl #define ahc_seqctl_print(regvalue, cur_col, wrap) \ 488 1.2 fvdl ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap) 489 1.2 fvdl #endif 490 1.2 fvdl 491 1.2 fvdl #if AIC_DEBUG_REGISTERS 492 1.2 fvdl ahc_reg_print_t ahc_seqram_print; 493 1.2 fvdl #else 494 1.2 fvdl #define ahc_seqram_print(regvalue, cur_col, wrap) \ 495 1.2 fvdl ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap) 496 1.2 fvdl #endif 497 1.2 fvdl 498 1.2 fvdl #if AIC_DEBUG_REGISTERS 499 1.2 fvdl ahc_reg_print_t ahc_seqaddr0_print; 500 1.2 fvdl #else 501 1.2 fvdl #define ahc_seqaddr0_print(regvalue, cur_col, wrap) \ 502 1.2 fvdl ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap) 503 1.2 fvdl #endif 504 1.2 fvdl 505 1.2 fvdl #if AIC_DEBUG_REGISTERS 506 1.2 fvdl ahc_reg_print_t ahc_seqaddr1_print; 507 1.2 fvdl #else 508 1.2 fvdl #define ahc_seqaddr1_print(regvalue, cur_col, wrap) \ 509 1.2 fvdl ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap) 510 1.2 fvdl #endif 511 1.2 fvdl 512 1.2 fvdl #if AIC_DEBUG_REGISTERS 513 1.2 fvdl ahc_reg_print_t ahc_accum_print; 514 1.2 fvdl #else 515 1.2 fvdl #define ahc_accum_print(regvalue, cur_col, wrap) \ 516 1.2 fvdl ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap) 517 1.2 fvdl #endif 518 1.2 fvdl 519 1.2 fvdl #if AIC_DEBUG_REGISTERS 520 1.2 fvdl ahc_reg_print_t ahc_sindex_print; 521 1.2 fvdl #else 522 1.2 fvdl #define ahc_sindex_print(regvalue, cur_col, wrap) \ 523 1.2 fvdl ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap) 524 1.2 fvdl #endif 525 1.2 fvdl 526 1.2 fvdl #if AIC_DEBUG_REGISTERS 527 1.2 fvdl ahc_reg_print_t ahc_dindex_print; 528 1.2 fvdl #else 529 1.2 fvdl #define ahc_dindex_print(regvalue, cur_col, wrap) \ 530 1.2 fvdl ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap) 531 1.2 fvdl #endif 532 1.2 fvdl 533 1.2 fvdl #if AIC_DEBUG_REGISTERS 534 1.2 fvdl ahc_reg_print_t ahc_allones_print; 535 1.2 fvdl #else 536 1.2 fvdl #define ahc_allones_print(regvalue, cur_col, wrap) \ 537 1.2 fvdl ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap) 538 1.2 fvdl #endif 539 1.2 fvdl 540 1.2 fvdl #if AIC_DEBUG_REGISTERS 541 1.2 fvdl ahc_reg_print_t ahc_none_print; 542 1.2 fvdl #else 543 1.2 fvdl #define ahc_none_print(regvalue, cur_col, wrap) \ 544 1.2 fvdl ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap) 545 1.2 fvdl #endif 546 1.2 fvdl 547 1.2 fvdl #if AIC_DEBUG_REGISTERS 548 1.2 fvdl ahc_reg_print_t ahc_allzeros_print; 549 1.2 fvdl #else 550 1.2 fvdl #define ahc_allzeros_print(regvalue, cur_col, wrap) \ 551 1.2 fvdl ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap) 552 1.2 fvdl #endif 553 1.2 fvdl 554 1.2 fvdl #if AIC_DEBUG_REGISTERS 555 1.2 fvdl ahc_reg_print_t ahc_flags_print; 556 1.2 fvdl #else 557 1.2 fvdl #define ahc_flags_print(regvalue, cur_col, wrap) \ 558 1.2 fvdl ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap) 559 1.2 fvdl #endif 560 1.2 fvdl 561 1.2 fvdl #if AIC_DEBUG_REGISTERS 562 1.2 fvdl ahc_reg_print_t ahc_sindir_print; 563 1.2 fvdl #else 564 1.2 fvdl #define ahc_sindir_print(regvalue, cur_col, wrap) \ 565 1.2 fvdl ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap) 566 1.2 fvdl #endif 567 1.2 fvdl 568 1.2 fvdl #if AIC_DEBUG_REGISTERS 569 1.2 fvdl ahc_reg_print_t ahc_dindir_print; 570 1.2 fvdl #else 571 1.2 fvdl #define ahc_dindir_print(regvalue, cur_col, wrap) \ 572 1.2 fvdl ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap) 573 1.2 fvdl #endif 574 1.2 fvdl 575 1.2 fvdl #if AIC_DEBUG_REGISTERS 576 1.2 fvdl ahc_reg_print_t ahc_function1_print; 577 1.2 fvdl #else 578 1.2 fvdl #define ahc_function1_print(regvalue, cur_col, wrap) \ 579 1.2 fvdl ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap) 580 1.2 fvdl #endif 581 1.2 fvdl 582 1.2 fvdl #if AIC_DEBUG_REGISTERS 583 1.2 fvdl ahc_reg_print_t ahc_stack_print; 584 1.2 fvdl #else 585 1.2 fvdl #define ahc_stack_print(regvalue, cur_col, wrap) \ 586 1.2 fvdl ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap) 587 1.2 fvdl #endif 588 1.2 fvdl 589 1.2 fvdl #if AIC_DEBUG_REGISTERS 590 1.2 fvdl ahc_reg_print_t ahc_targ_offset_print; 591 1.2 fvdl #else 592 1.2 fvdl #define ahc_targ_offset_print(regvalue, cur_col, wrap) \ 593 1.2 fvdl ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap) 594 1.2 fvdl #endif 595 1.2 fvdl 596 1.2 fvdl #if AIC_DEBUG_REGISTERS 597 1.2 fvdl ahc_reg_print_t ahc_sram_base_print; 598 1.2 fvdl #else 599 1.2 fvdl #define ahc_sram_base_print(regvalue, cur_col, wrap) \ 600 1.2 fvdl ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap) 601 1.2 fvdl #endif 602 1.2 fvdl 603 1.2 fvdl #if AIC_DEBUG_REGISTERS 604 1.2 fvdl ahc_reg_print_t ahc_bctl_print; 605 1.2 fvdl #else 606 1.2 fvdl #define ahc_bctl_print(regvalue, cur_col, wrap) \ 607 1.2 fvdl ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap) 608 1.2 fvdl #endif 609 1.2 fvdl 610 1.2 fvdl #if AIC_DEBUG_REGISTERS 611 1.2 fvdl ahc_reg_print_t ahc_dscommand0_print; 612 1.2 fvdl #else 613 1.2 fvdl #define ahc_dscommand0_print(regvalue, cur_col, wrap) \ 614 1.2 fvdl ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap) 615 1.2 fvdl #endif 616 1.2 fvdl 617 1.2 fvdl #if AIC_DEBUG_REGISTERS 618 1.2 fvdl ahc_reg_print_t ahc_bustime_print; 619 1.2 fvdl #else 620 1.2 fvdl #define ahc_bustime_print(regvalue, cur_col, wrap) \ 621 1.2 fvdl ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap) 622 1.2 fvdl #endif 623 1.2 fvdl 624 1.2 fvdl #if AIC_DEBUG_REGISTERS 625 1.2 fvdl ahc_reg_print_t ahc_dscommand1_print; 626 1.2 fvdl #else 627 1.2 fvdl #define ahc_dscommand1_print(regvalue, cur_col, wrap) \ 628 1.2 fvdl ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap) 629 1.2 fvdl #endif 630 1.2 fvdl 631 1.2 fvdl #if AIC_DEBUG_REGISTERS 632 1.2 fvdl ahc_reg_print_t ahc_busspd_print; 633 1.2 fvdl #else 634 1.2 fvdl #define ahc_busspd_print(regvalue, cur_col, wrap) \ 635 1.2 fvdl ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap) 636 1.2 fvdl #endif 637 1.2 fvdl 638 1.2 fvdl #if AIC_DEBUG_REGISTERS 639 1.2 fvdl ahc_reg_print_t ahc_dspcistatus_print; 640 1.2 fvdl #else 641 1.2 fvdl #define ahc_dspcistatus_print(regvalue, cur_col, wrap) \ 642 1.2 fvdl ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap) 643 1.2 fvdl #endif 644 1.2 fvdl 645 1.2 fvdl #if AIC_DEBUG_REGISTERS 646 1.2 fvdl ahc_reg_print_t ahc_hs_mailbox_print; 647 1.2 fvdl #else 648 1.2 fvdl #define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \ 649 1.2 fvdl ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap) 650 1.2 fvdl #endif 651 1.2 fvdl 652 1.2 fvdl #if AIC_DEBUG_REGISTERS 653 1.2 fvdl ahc_reg_print_t ahc_hcntrl_print; 654 1.2 fvdl #else 655 1.2 fvdl #define ahc_hcntrl_print(regvalue, cur_col, wrap) \ 656 1.2 fvdl ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap) 657 1.2 fvdl #endif 658 1.2 fvdl 659 1.2 fvdl #if AIC_DEBUG_REGISTERS 660 1.2 fvdl ahc_reg_print_t ahc_haddr_print; 661 1.2 fvdl #else 662 1.2 fvdl #define ahc_haddr_print(regvalue, cur_col, wrap) \ 663 1.2 fvdl ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap) 664 1.2 fvdl #endif 665 1.2 fvdl 666 1.2 fvdl #if AIC_DEBUG_REGISTERS 667 1.2 fvdl ahc_reg_print_t ahc_hcnt_print; 668 1.2 fvdl #else 669 1.2 fvdl #define ahc_hcnt_print(regvalue, cur_col, wrap) \ 670 1.2 fvdl ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap) 671 1.2 fvdl #endif 672 1.2 fvdl 673 1.2 fvdl #if AIC_DEBUG_REGISTERS 674 1.2 fvdl ahc_reg_print_t ahc_scbptr_print; 675 1.2 fvdl #else 676 1.2 fvdl #define ahc_scbptr_print(regvalue, cur_col, wrap) \ 677 1.2 fvdl ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap) 678 1.2 fvdl #endif 679 1.2 fvdl 680 1.2 fvdl #if AIC_DEBUG_REGISTERS 681 1.2 fvdl ahc_reg_print_t ahc_intstat_print; 682 1.2 fvdl #else 683 1.2 fvdl #define ahc_intstat_print(regvalue, cur_col, wrap) \ 684 1.2 fvdl ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap) 685 1.2 fvdl #endif 686 1.2 fvdl 687 1.2 fvdl #if AIC_DEBUG_REGISTERS 688 1.2 fvdl ahc_reg_print_t ahc_error_print; 689 1.2 fvdl #else 690 1.2 fvdl #define ahc_error_print(regvalue, cur_col, wrap) \ 691 1.2 fvdl ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap) 692 1.2 fvdl #endif 693 1.2 fvdl 694 1.2 fvdl #if AIC_DEBUG_REGISTERS 695 1.2 fvdl ahc_reg_print_t ahc_clrint_print; 696 1.2 fvdl #else 697 1.2 fvdl #define ahc_clrint_print(regvalue, cur_col, wrap) \ 698 1.2 fvdl ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap) 699 1.2 fvdl #endif 700 1.2 fvdl 701 1.2 fvdl #if AIC_DEBUG_REGISTERS 702 1.2 fvdl ahc_reg_print_t ahc_dfcntrl_print; 703 1.2 fvdl #else 704 1.2 fvdl #define ahc_dfcntrl_print(regvalue, cur_col, wrap) \ 705 1.2 fvdl ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap) 706 1.2 fvdl #endif 707 1.2 fvdl 708 1.2 fvdl #if AIC_DEBUG_REGISTERS 709 1.2 fvdl ahc_reg_print_t ahc_dfstatus_print; 710 1.2 fvdl #else 711 1.2 fvdl #define ahc_dfstatus_print(regvalue, cur_col, wrap) \ 712 1.2 fvdl ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap) 713 1.2 fvdl #endif 714 1.2 fvdl 715 1.2 fvdl #if AIC_DEBUG_REGISTERS 716 1.2 fvdl ahc_reg_print_t ahc_dfwaddr_print; 717 1.2 fvdl #else 718 1.2 fvdl #define ahc_dfwaddr_print(regvalue, cur_col, wrap) \ 719 1.2 fvdl ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap) 720 1.2 fvdl #endif 721 1.2 fvdl 722 1.2 fvdl #if AIC_DEBUG_REGISTERS 723 1.2 fvdl ahc_reg_print_t ahc_dfraddr_print; 724 1.2 fvdl #else 725 1.2 fvdl #define ahc_dfraddr_print(regvalue, cur_col, wrap) \ 726 1.2 fvdl ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap) 727 1.2 fvdl #endif 728 1.2 fvdl 729 1.2 fvdl #if AIC_DEBUG_REGISTERS 730 1.2 fvdl ahc_reg_print_t ahc_dfdat_print; 731 1.2 fvdl #else 732 1.2 fvdl #define ahc_dfdat_print(regvalue, cur_col, wrap) \ 733 1.2 fvdl ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap) 734 1.2 fvdl #endif 735 1.2 fvdl 736 1.2 fvdl #if AIC_DEBUG_REGISTERS 737 1.2 fvdl ahc_reg_print_t ahc_scbcnt_print; 738 1.2 fvdl #else 739 1.2 fvdl #define ahc_scbcnt_print(regvalue, cur_col, wrap) \ 740 1.2 fvdl ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap) 741 1.2 fvdl #endif 742 1.2 fvdl 743 1.2 fvdl #if AIC_DEBUG_REGISTERS 744 1.2 fvdl ahc_reg_print_t ahc_qinfifo_print; 745 1.2 fvdl #else 746 1.2 fvdl #define ahc_qinfifo_print(regvalue, cur_col, wrap) \ 747 1.2 fvdl ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap) 748 1.2 fvdl #endif 749 1.2 fvdl 750 1.2 fvdl #if AIC_DEBUG_REGISTERS 751 1.2 fvdl ahc_reg_print_t ahc_qincnt_print; 752 1.2 fvdl #else 753 1.2 fvdl #define ahc_qincnt_print(regvalue, cur_col, wrap) \ 754 1.2 fvdl ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap) 755 1.2 fvdl #endif 756 1.2 fvdl 757 1.2 fvdl #if AIC_DEBUG_REGISTERS 758 1.2 fvdl ahc_reg_print_t ahc_crccontrol1_print; 759 1.2 fvdl #else 760 1.2 fvdl #define ahc_crccontrol1_print(regvalue, cur_col, wrap) \ 761 1.2 fvdl ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap) 762 1.2 fvdl #endif 763 1.2 fvdl 764 1.2 fvdl #if AIC_DEBUG_REGISTERS 765 1.2 fvdl ahc_reg_print_t ahc_qoutfifo_print; 766 1.2 fvdl #else 767 1.2 fvdl #define ahc_qoutfifo_print(regvalue, cur_col, wrap) \ 768 1.2 fvdl ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap) 769 1.2 fvdl #endif 770 1.2 fvdl 771 1.2 fvdl #if AIC_DEBUG_REGISTERS 772 1.2 fvdl ahc_reg_print_t ahc_scsiphase_print; 773 1.2 fvdl #else 774 1.2 fvdl #define ahc_scsiphase_print(regvalue, cur_col, wrap) \ 775 1.2 fvdl ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap) 776 1.2 fvdl #endif 777 1.2 fvdl 778 1.2 fvdl #if AIC_DEBUG_REGISTERS 779 1.2 fvdl ahc_reg_print_t ahc_qoutcnt_print; 780 1.2 fvdl #else 781 1.2 fvdl #define ahc_qoutcnt_print(regvalue, cur_col, wrap) \ 782 1.2 fvdl ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap) 783 1.2 fvdl #endif 784 1.2 fvdl 785 1.2 fvdl #if AIC_DEBUG_REGISTERS 786 1.2 fvdl ahc_reg_print_t ahc_sfunct_print; 787 1.2 fvdl #else 788 1.2 fvdl #define ahc_sfunct_print(regvalue, cur_col, wrap) \ 789 1.2 fvdl ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 790 1.2 fvdl #endif 791 1.2 fvdl 792 1.2 fvdl #if AIC_DEBUG_REGISTERS 793 1.2 fvdl ahc_reg_print_t ahc_scb_base_print; 794 1.2 fvdl #else 795 1.2 fvdl #define ahc_scb_base_print(regvalue, cur_col, wrap) \ 796 1.2 fvdl ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap) 797 1.2 fvdl #endif 798 1.2 fvdl 799 1.2 fvdl #if AIC_DEBUG_REGISTERS 800 1.2 fvdl ahc_reg_print_t ahc_scb_cdb_ptr_print; 801 1.2 fvdl #else 802 1.2 fvdl #define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \ 803 1.2 fvdl ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap) 804 1.2 fvdl #endif 805 1.2 fvdl 806 1.2 fvdl #if AIC_DEBUG_REGISTERS 807 1.2 fvdl ahc_reg_print_t ahc_scb_residual_sgptr_print; 808 1.2 fvdl #else 809 1.2 fvdl #define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 810 1.2 fvdl ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap) 811 1.2 fvdl #endif 812 1.2 fvdl 813 1.2 fvdl #if AIC_DEBUG_REGISTERS 814 1.2 fvdl ahc_reg_print_t ahc_scb_scsi_status_print; 815 1.2 fvdl #else 816 1.2 fvdl #define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \ 817 1.2 fvdl ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap) 818 1.2 fvdl #endif 819 1.2 fvdl 820 1.2 fvdl #if AIC_DEBUG_REGISTERS 821 1.2 fvdl ahc_reg_print_t ahc_scb_target_phases_print; 822 1.2 fvdl #else 823 1.2 fvdl #define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \ 824 1.2 fvdl ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap) 825 1.2 fvdl #endif 826 1.2 fvdl 827 1.2 fvdl #if AIC_DEBUG_REGISTERS 828 1.2 fvdl ahc_reg_print_t ahc_scb_target_data_dir_print; 829 1.2 fvdl #else 830 1.2 fvdl #define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 831 1.2 fvdl ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap) 832 1.2 fvdl #endif 833 1.2 fvdl 834 1.2 fvdl #if AIC_DEBUG_REGISTERS 835 1.2 fvdl ahc_reg_print_t ahc_scb_target_itag_print; 836 1.2 fvdl #else 837 1.2 fvdl #define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \ 838 1.2 fvdl ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap) 839 1.2 fvdl #endif 840 1.2 fvdl 841 1.2 fvdl #if AIC_DEBUG_REGISTERS 842 1.2 fvdl ahc_reg_print_t ahc_scb_dataptr_print; 843 1.2 fvdl #else 844 1.2 fvdl #define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \ 845 1.2 fvdl ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap) 846 1.2 fvdl #endif 847 1.2 fvdl 848 1.2 fvdl #if AIC_DEBUG_REGISTERS 849 1.2 fvdl ahc_reg_print_t ahc_scb_datacnt_print; 850 1.2 fvdl #else 851 1.2 fvdl #define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \ 852 1.2 fvdl ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap) 853 1.2 fvdl #endif 854 1.2 fvdl 855 1.2 fvdl #if AIC_DEBUG_REGISTERS 856 1.2 fvdl ahc_reg_print_t ahc_scb_sgptr_print; 857 1.2 fvdl #else 858 1.2 fvdl #define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \ 859 1.2 fvdl ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap) 860 1.2 fvdl #endif 861 1.2 fvdl 862 1.2 fvdl #if AIC_DEBUG_REGISTERS 863 1.2 fvdl ahc_reg_print_t ahc_scb_control_print; 864 1.2 fvdl #else 865 1.2 fvdl #define ahc_scb_control_print(regvalue, cur_col, wrap) \ 866 1.2 fvdl ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap) 867 1.2 fvdl #endif 868 1.2 fvdl 869 1.2 fvdl #if AIC_DEBUG_REGISTERS 870 1.2 fvdl ahc_reg_print_t ahc_scb_scsiid_print; 871 1.2 fvdl #else 872 1.2 fvdl #define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \ 873 1.2 fvdl ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap) 874 1.2 fvdl #endif 875 1.2 fvdl 876 1.2 fvdl #if AIC_DEBUG_REGISTERS 877 1.2 fvdl ahc_reg_print_t ahc_scb_lun_print; 878 1.2 fvdl #else 879 1.2 fvdl #define ahc_scb_lun_print(regvalue, cur_col, wrap) \ 880 1.2 fvdl ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap) 881 1.2 fvdl #endif 882 1.2 fvdl 883 1.2 fvdl #if AIC_DEBUG_REGISTERS 884 1.2 fvdl ahc_reg_print_t ahc_scb_tag_print; 885 1.2 fvdl #else 886 1.2 fvdl #define ahc_scb_tag_print(regvalue, cur_col, wrap) \ 887 1.2 fvdl ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) 888 1.2 fvdl #endif 889 1.2 fvdl 890 1.2 fvdl #if AIC_DEBUG_REGISTERS 891 1.2 fvdl ahc_reg_print_t ahc_scb_cdb_len_print; 892 1.2 fvdl #else 893 1.2 fvdl #define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \ 894 1.2 fvdl ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap) 895 1.2 fvdl #endif 896 1.2 fvdl 897 1.2 fvdl #if AIC_DEBUG_REGISTERS 898 1.2 fvdl ahc_reg_print_t ahc_scb_scsirate_print; 899 1.2 fvdl #else 900 1.2 fvdl #define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \ 901 1.2 fvdl ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap) 902 1.2 fvdl #endif 903 1.2 fvdl 904 1.2 fvdl #if AIC_DEBUG_REGISTERS 905 1.2 fvdl ahc_reg_print_t ahc_scb_scsioffset_print; 906 1.2 fvdl #else 907 1.2 fvdl #define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \ 908 1.2 fvdl ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap) 909 1.2 fvdl #endif 910 1.2 fvdl 911 1.2 fvdl #if AIC_DEBUG_REGISTERS 912 1.2 fvdl ahc_reg_print_t ahc_scb_next_print; 913 1.2 fvdl #else 914 1.2 fvdl #define ahc_scb_next_print(regvalue, cur_col, wrap) \ 915 1.2 fvdl ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap) 916 1.2 fvdl #endif 917 1.2 fvdl 918 1.2 fvdl #if AIC_DEBUG_REGISTERS 919 1.2 fvdl ahc_reg_print_t ahc_scb_64_spare_print; 920 1.2 fvdl #else 921 1.2 fvdl #define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \ 922 1.2 fvdl ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap) 923 1.2 fvdl #endif 924 1.2 fvdl 925 1.2 fvdl #if AIC_DEBUG_REGISTERS 926 1.2 fvdl ahc_reg_print_t ahc_seectl_2840_print; 927 1.2 fvdl #else 928 1.2 fvdl #define ahc_seectl_2840_print(regvalue, cur_col, wrap) \ 929 1.2 fvdl ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap) 930 1.2 fvdl #endif 931 1.2 fvdl 932 1.2 fvdl #if AIC_DEBUG_REGISTERS 933 1.2 fvdl ahc_reg_print_t ahc_status_2840_print; 934 1.2 fvdl #else 935 1.2 fvdl #define ahc_status_2840_print(regvalue, cur_col, wrap) \ 936 1.2 fvdl ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap) 937 1.2 fvdl #endif 938 1.2 fvdl 939 1.2 fvdl #if AIC_DEBUG_REGISTERS 940 1.2 fvdl ahc_reg_print_t ahc_scb_64_btt_print; 941 1.2 fvdl #else 942 1.2 fvdl #define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \ 943 1.2 fvdl ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap) 944 1.2 fvdl #endif 945 1.2 fvdl 946 1.2 fvdl #if AIC_DEBUG_REGISTERS 947 1.2 fvdl ahc_reg_print_t ahc_cchaddr_print; 948 1.2 fvdl #else 949 1.2 fvdl #define ahc_cchaddr_print(regvalue, cur_col, wrap) \ 950 1.2 fvdl ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap) 951 1.2 fvdl #endif 952 1.2 fvdl 953 1.2 fvdl #if AIC_DEBUG_REGISTERS 954 1.2 fvdl ahc_reg_print_t ahc_cchcnt_print; 955 1.2 fvdl #else 956 1.2 fvdl #define ahc_cchcnt_print(regvalue, cur_col, wrap) \ 957 1.2 fvdl ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap) 958 1.2 fvdl #endif 959 1.2 fvdl 960 1.2 fvdl #if AIC_DEBUG_REGISTERS 961 1.2 fvdl ahc_reg_print_t ahc_ccsgram_print; 962 1.2 fvdl #else 963 1.2 fvdl #define ahc_ccsgram_print(regvalue, cur_col, wrap) \ 964 1.2 fvdl ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap) 965 1.2 fvdl #endif 966 1.2 fvdl 967 1.2 fvdl #if AIC_DEBUG_REGISTERS 968 1.2 fvdl ahc_reg_print_t ahc_ccsgaddr_print; 969 1.2 fvdl #else 970 1.2 fvdl #define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \ 971 1.2 fvdl ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap) 972 1.2 fvdl #endif 973 1.2 fvdl 974 1.2 fvdl #if AIC_DEBUG_REGISTERS 975 1.2 fvdl ahc_reg_print_t ahc_ccsgctl_print; 976 1.2 fvdl #else 977 1.2 fvdl #define ahc_ccsgctl_print(regvalue, cur_col, wrap) \ 978 1.2 fvdl ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap) 979 1.2 fvdl #endif 980 1.2 fvdl 981 1.2 fvdl #if AIC_DEBUG_REGISTERS 982 1.2 fvdl ahc_reg_print_t ahc_ccscbram_print; 983 1.2 fvdl #else 984 1.2 fvdl #define ahc_ccscbram_print(regvalue, cur_col, wrap) \ 985 1.2 fvdl ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap) 986 1.2 fvdl #endif 987 1.2 fvdl 988 1.2 fvdl #if AIC_DEBUG_REGISTERS 989 1.2 fvdl ahc_reg_print_t ahc_ccscbaddr_print; 990 1.2 fvdl #else 991 1.2 fvdl #define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \ 992 1.2 fvdl ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap) 993 1.2 fvdl #endif 994 1.2 fvdl 995 1.2 fvdl #if AIC_DEBUG_REGISTERS 996 1.2 fvdl ahc_reg_print_t ahc_ccscbctl_print; 997 1.2 fvdl #else 998 1.2 fvdl #define ahc_ccscbctl_print(regvalue, cur_col, wrap) \ 999 1.2 fvdl ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap) 1000 1.2 fvdl #endif 1001 1.2 fvdl 1002 1.2 fvdl #if AIC_DEBUG_REGISTERS 1003 1.2 fvdl ahc_reg_print_t ahc_ccscbcnt_print; 1004 1.2 fvdl #else 1005 1.2 fvdl #define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \ 1006 1.2 fvdl ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap) 1007 1.2 fvdl #endif 1008 1.2 fvdl 1009 1.2 fvdl #if AIC_DEBUG_REGISTERS 1010 1.2 fvdl ahc_reg_print_t ahc_scbbaddr_print; 1011 1.2 fvdl #else 1012 1.2 fvdl #define ahc_scbbaddr_print(regvalue, cur_col, wrap) \ 1013 1.2 fvdl ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap) 1014 1.2 fvdl #endif 1015 1.2 fvdl 1016 1.2 fvdl #if AIC_DEBUG_REGISTERS 1017 1.2 fvdl ahc_reg_print_t ahc_ccscbptr_print; 1018 1.2 fvdl #else 1019 1.2 fvdl #define ahc_ccscbptr_print(regvalue, cur_col, wrap) \ 1020 1.2 fvdl ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap) 1021 1.2 fvdl #endif 1022 1.2 fvdl 1023 1.2 fvdl #if AIC_DEBUG_REGISTERS 1024 1.2 fvdl ahc_reg_print_t ahc_hnscb_qoff_print; 1025 1.2 fvdl #else 1026 1.2 fvdl #define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \ 1027 1.2 fvdl ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap) 1028 1.2 fvdl #endif 1029 1.2 fvdl 1030 1.2 fvdl #if AIC_DEBUG_REGISTERS 1031 1.2 fvdl ahc_reg_print_t ahc_snscb_qoff_print; 1032 1.2 fvdl #else 1033 1.2 fvdl #define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \ 1034 1.2 fvdl ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap) 1035 1.2 fvdl #endif 1036 1.2 fvdl 1037 1.2 fvdl #if AIC_DEBUG_REGISTERS 1038 1.2 fvdl ahc_reg_print_t ahc_sdscb_qoff_print; 1039 1.2 fvdl #else 1040 1.2 fvdl #define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \ 1041 1.2 fvdl ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap) 1042 1.2 fvdl #endif 1043 1.2 fvdl 1044 1.2 fvdl #if AIC_DEBUG_REGISTERS 1045 1.2 fvdl ahc_reg_print_t ahc_qoff_ctlsta_print; 1046 1.2 fvdl #else 1047 1.2 fvdl #define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 1048 1.2 fvdl ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap) 1049 1.2 fvdl #endif 1050 1.2 fvdl 1051 1.2 fvdl #if AIC_DEBUG_REGISTERS 1052 1.2 fvdl ahc_reg_print_t ahc_dff_thrsh_print; 1053 1.2 fvdl #else 1054 1.2 fvdl #define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \ 1055 1.2 fvdl ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap) 1056 1.2 fvdl #endif 1057 1.2 fvdl 1058 1.2 fvdl #if AIC_DEBUG_REGISTERS 1059 1.2 fvdl ahc_reg_print_t ahc_sg_cache_shadow_print; 1060 1.2 fvdl #else 1061 1.2 fvdl #define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 1062 1.2 fvdl ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap) 1063 1.2 fvdl #endif 1064 1.2 fvdl 1065 1.2 fvdl #if AIC_DEBUG_REGISTERS 1066 1.2 fvdl ahc_reg_print_t ahc_sg_cache_pre_print; 1067 1.2 fvdl #else 1068 1.2 fvdl #define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \ 1069 1.2 fvdl ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap) 1070 1.2 fvdl #endif 1071 1.2 fvdl 1072 1.1 fvdl 1073 1.1 fvdl #define SCSISEQ 0x00 1074 1.1 fvdl #define TEMODE 0x80 1075 1.1 fvdl #define SCSIRSTO 0x01 1076 1.1 fvdl 1077 1.1 fvdl #define SXFRCTL0 0x01 1078 1.1 fvdl #define DFON 0x80 1079 1.1 fvdl #define DFPEXP 0x40 1080 1.1 fvdl #define FAST20 0x20 1081 1.1 fvdl #define CLRSTCNT 0x10 1082 1.1 fvdl #define SPIOEN 0x08 1083 1.1 fvdl #define SCAMEN 0x04 1084 1.1 fvdl #define CLRCHN 0x02 1085 1.1 fvdl 1086 1.1 fvdl #define SXFRCTL1 0x02 1087 1.2 fvdl #define STIMESEL 0x18 1088 1.1 fvdl #define BITBUCKET 0x80 1089 1.1 fvdl #define SWRAPEN 0x40 1090 1.1 fvdl #define ENSTIMER 0x04 1091 1.1 fvdl #define ACTNEGEN 0x02 1092 1.1 fvdl #define STPWEN 0x01 1093 1.1 fvdl 1094 1.1 fvdl #define SCSISIGO 0x03 1095 1.1 fvdl #define CDO 0x80 1096 1.1 fvdl #define IOO 0x40 1097 1.1 fvdl #define MSGO 0x20 1098 1.1 fvdl #define ATNO 0x10 1099 1.1 fvdl #define SELO 0x08 1100 1.1 fvdl #define BSYO 0x04 1101 1.1 fvdl #define REQO 0x02 1102 1.1 fvdl #define ACKO 0x01 1103 1.1 fvdl 1104 1.1 fvdl #define SCSISIGI 0x03 1105 1.2 fvdl #define P_DATAIN_DT 0x60 1106 1.2 fvdl #define P_DATAOUT_DT 0x20 1107 1.1 fvdl #define ATNI 0x10 1108 1.1 fvdl #define SELI 0x08 1109 1.1 fvdl #define BSYI 0x04 1110 1.1 fvdl #define REQI 0x02 1111 1.1 fvdl #define ACKI 0x01 1112 1.1 fvdl 1113 1.1 fvdl #define SCSIRATE 0x04 1114 1.2 fvdl #define SXFR 0x70 1115 1.2 fvdl #define SXFR_ULTRA2 0x0f 1116 1.2 fvdl #define SOFS 0x0f 1117 1.1 fvdl #define WIDEXFER 0x80 1118 1.1 fvdl #define ENABLE_CRC 0x40 1119 1.1 fvdl #define SINGLE_EDGE 0x10 1120 1.1 fvdl 1121 1.1 fvdl #define SCSIID 0x05 1122 1.1 fvdl #define SCSIOFFSET 0x05 1123 1.1 fvdl #define SOFS_ULTRA2 0x7f 1124 1.1 fvdl 1125 1.1 fvdl #define SCSIDATL 0x06 1126 1.1 fvdl 1127 1.1 fvdl #define SCSIDATH 0x07 1128 1.1 fvdl 1129 1.1 fvdl #define STCNT 0x08 1130 1.1 fvdl 1131 1.1 fvdl #define OPTIONMODE 0x08 1132 1.2 fvdl #define OPTIONMODE_DEFAULTS 0x03 1133 1.1 fvdl #define AUTORATEEN 0x80 1134 1.1 fvdl #define AUTOACKEN 0x40 1135 1.1 fvdl #define ATNMGMNTEN 0x20 1136 1.1 fvdl #define BUSFREEREV 0x10 1137 1.1 fvdl #define EXPPHASEDIS 0x08 1138 1.1 fvdl #define SCSIDATL_IMGEN 0x04 1139 1.1 fvdl #define AUTO_MSGOUT_DE 0x02 1140 1.1 fvdl #define DIS_MSGIN_DUALEDGE 0x01 1141 1.1 fvdl 1142 1.1 fvdl #define TARGCRCCNT 0x0a 1143 1.1 fvdl 1144 1.1 fvdl #define CLRSINT0 0x0b 1145 1.1 fvdl #define CLRSELDO 0x40 1146 1.1 fvdl #define CLRSELDI 0x20 1147 1.1 fvdl #define CLRSELINGO 0x10 1148 1.1 fvdl #define CLRSWRAP 0x08 1149 1.2 fvdl #define CLRIOERR 0x08 1150 1.1 fvdl #define CLRSPIORDY 0x02 1151 1.1 fvdl 1152 1.1 fvdl #define SSTAT0 0x0b 1153 1.1 fvdl #define TARGET 0x80 1154 1.1 fvdl #define SELDO 0x40 1155 1.1 fvdl #define SELDI 0x20 1156 1.1 fvdl #define SELINGO 0x10 1157 1.2 fvdl #define SWRAP 0x08 1158 1.1 fvdl #define IOERR 0x08 1159 1.1 fvdl #define SDONE 0x04 1160 1.1 fvdl #define SPIORDY 0x02 1161 1.1 fvdl #define DMADONE 0x01 1162 1.1 fvdl 1163 1.1 fvdl #define CLRSINT1 0x0c 1164 1.1 fvdl #define CLRSELTIMEO 0x80 1165 1.1 fvdl #define CLRATNO 0x40 1166 1.1 fvdl #define CLRSCSIRSTI 0x20 1167 1.1 fvdl #define CLRBUSFREE 0x08 1168 1.1 fvdl #define CLRSCSIPERR 0x04 1169 1.1 fvdl #define CLRPHASECHG 0x02 1170 1.1 fvdl #define CLRREQINIT 0x01 1171 1.1 fvdl 1172 1.1 fvdl #define SSTAT1 0x0c 1173 1.1 fvdl #define SELTO 0x80 1174 1.1 fvdl #define ATNTARG 0x40 1175 1.1 fvdl #define SCSIRSTI 0x20 1176 1.1 fvdl #define PHASEMIS 0x10 1177 1.1 fvdl #define BUSFREE 0x08 1178 1.1 fvdl #define SCSIPERR 0x04 1179 1.1 fvdl #define PHASECHG 0x02 1180 1.1 fvdl #define REQINIT 0x01 1181 1.1 fvdl 1182 1.1 fvdl #define SSTAT2 0x0d 1183 1.2 fvdl #define SFCNT 0x1f 1184 1.1 fvdl #define OVERRUN 0x80 1185 1.2 fvdl #define SHVALID 0x40 1186 1.1 fvdl #define EXP_ACTIVE 0x10 1187 1.2 fvdl #define CRCVALERR 0x08 1188 1.2 fvdl #define CRCENDERR 0x04 1189 1.2 fvdl #define CRCREQERR 0x02 1190 1.2 fvdl #define DUAL_EDGE_ERR 0x01 1191 1.1 fvdl 1192 1.1 fvdl #define SSTAT3 0x0e 1193 1.1 fvdl #define SCSICNT 0xf0 1194 1.2 fvdl #define U2OFFCNT 0x7f 1195 1.1 fvdl #define OFFCNT 0x0f 1196 1.1 fvdl 1197 1.1 fvdl #define SCSIID_ULTRA2 0x0f 1198 1.1 fvdl 1199 1.1 fvdl #define SIMODE0 0x10 1200 1.1 fvdl #define ENSELDO 0x40 1201 1.1 fvdl #define ENSELDI 0x20 1202 1.1 fvdl #define ENSELINGO 0x10 1203 1.1 fvdl #define ENIOERR 0x08 1204 1.1 fvdl #define ENSWRAP 0x08 1205 1.1 fvdl #define ENSDONE 0x04 1206 1.1 fvdl #define ENSPIORDY 0x02 1207 1.1 fvdl #define ENDMADONE 0x01 1208 1.1 fvdl 1209 1.1 fvdl #define SIMODE1 0x11 1210 1.1 fvdl #define ENSELTIMO 0x80 1211 1.1 fvdl #define ENATNTARG 0x40 1212 1.1 fvdl #define ENSCSIRST 0x20 1213 1.1 fvdl #define ENPHASEMIS 0x10 1214 1.1 fvdl #define ENBUSFREE 0x08 1215 1.1 fvdl #define ENSCSIPERR 0x04 1216 1.1 fvdl #define ENPHASECHG 0x02 1217 1.1 fvdl #define ENREQINIT 0x01 1218 1.1 fvdl 1219 1.1 fvdl #define SCSIBUSL 0x12 1220 1.1 fvdl 1221 1.2 fvdl #define SXFRCTL2 0x13 1222 1.2 fvdl #define ASYNC_SETUP 0x07 1223 1.2 fvdl #define AUTORSTDIS 0x10 1224 1.2 fvdl #define CMDDMAEN 0x08 1225 1.2 fvdl 1226 1.1 fvdl #define SCSIBUSH 0x13 1227 1.1 fvdl 1228 1.1 fvdl #define SHADDR 0x14 1229 1.1 fvdl 1230 1.1 fvdl #define SELTIMER 0x18 1231 1.1 fvdl #define TARGIDIN 0x18 1232 1.1 fvdl #define STAGE6 0x20 1233 1.1 fvdl #define STAGE5 0x10 1234 1.1 fvdl #define STAGE4 0x08 1235 1.1 fvdl #define STAGE3 0x04 1236 1.1 fvdl #define STAGE2 0x02 1237 1.1 fvdl #define STAGE1 0x01 1238 1.1 fvdl 1239 1.1 fvdl #define SELID 0x19 1240 1.1 fvdl #define SELID_MASK 0xf0 1241 1.1 fvdl #define ONEBIT 0x08 1242 1.1 fvdl 1243 1.1 fvdl #define SCAMCTL 0x1a 1244 1.2 fvdl #define SCAMLVL 0x03 1245 1.1 fvdl #define ENSCAMSELO 0x80 1246 1.1 fvdl #define CLRSCAMSELID 0x40 1247 1.1 fvdl #define ALTSTIM 0x20 1248 1.1 fvdl #define DFLTTID 0x10 1249 1.1 fvdl 1250 1.1 fvdl #define TARGID 0x1b 1251 1.1 fvdl 1252 1.1 fvdl #define SPIOCAP 0x1b 1253 1.1 fvdl #define SOFT1 0x80 1254 1.1 fvdl #define SOFT0 0x40 1255 1.1 fvdl #define SOFTCMDEN 0x20 1256 1.2 fvdl #define EXT_BRDCTL 0x10 1257 1.1 fvdl #define SEEPROM 0x08 1258 1.1 fvdl #define EEPROM 0x04 1259 1.1 fvdl #define ROM 0x02 1260 1.1 fvdl #define SSPIOCPS 0x01 1261 1.1 fvdl 1262 1.1 fvdl #define BRDCTL 0x1d 1263 1.1 fvdl #define BRDDAT7 0x80 1264 1.1 fvdl #define BRDDAT6 0x40 1265 1.1 fvdl #define BRDDAT5 0x20 1266 1.1 fvdl #define BRDDAT4 0x10 1267 1.1 fvdl #define BRDSTB 0x10 1268 1.1 fvdl #define BRDCS 0x08 1269 1.1 fvdl #define BRDDAT3 0x08 1270 1.1 fvdl #define BRDDAT2 0x04 1271 1.1 fvdl #define BRDRW 0x04 1272 1.2 fvdl #define BRDCTL1 0x02 1273 1.1 fvdl #define BRDRW_ULTRA2 0x02 1274 1.1 fvdl #define BRDCTL0 0x01 1275 1.1 fvdl #define BRDSTB_ULTRA2 0x01 1276 1.1 fvdl 1277 1.1 fvdl #define SEECTL 0x1e 1278 1.1 fvdl #define EXTARBACK 0x80 1279 1.1 fvdl #define EXTARBREQ 0x40 1280 1.1 fvdl #define SEEMS 0x20 1281 1.1 fvdl #define SEERDY 0x10 1282 1.1 fvdl #define SEECS 0x08 1283 1.1 fvdl #define SEECK 0x04 1284 1.1 fvdl #define SEEDO 0x02 1285 1.1 fvdl #define SEEDI 0x01 1286 1.1 fvdl 1287 1.1 fvdl #define SBLKCTL 0x1f 1288 1.1 fvdl #define DIAGLEDEN 0x80 1289 1.1 fvdl #define DIAGLEDON 0x40 1290 1.1 fvdl #define AUTOFLUSHDIS 0x20 1291 1.1 fvdl #define ENAB40 0x08 1292 1.2 fvdl #define SELBUSB 0x08 1293 1.1 fvdl #define ENAB20 0x04 1294 1.1 fvdl #define SELWIDE 0x02 1295 1.1 fvdl #define XCVR 0x01 1296 1.1 fvdl 1297 1.2 fvdl #define BUSY_TARGETS 0x20 1298 1.1 fvdl #define TARG_SCSIRATE 0x20 1299 1.1 fvdl 1300 1.1 fvdl #define ULTRA_ENB 0x30 1301 1.2 fvdl #define CMDSIZE_TABLE 0x30 1302 1.1 fvdl 1303 1.1 fvdl #define DISC_DSB 0x32 1304 1.1 fvdl 1305 1.2 fvdl #define CMDSIZE_TABLE_TAIL 0x34 1306 1.2 fvdl 1307 1.2 fvdl #define MWI_RESIDUAL 0x38 1308 1.2 fvdl #define TARG_IMMEDIATE_SCB 0x38 1309 1.2 fvdl 1310 1.2 fvdl #define NEXT_QUEUED_SCB 0x39 1311 1.1 fvdl 1312 1.2 fvdl #define MSG_OUT 0x3a 1313 1.2 fvdl 1314 1.2 fvdl #define DMAPARAMS 0x3b 1315 1.1 fvdl #define PRELOADEN 0x80 1316 1.1 fvdl #define WIDEODD 0x40 1317 1.1 fvdl #define SCSIEN 0x20 1318 1.1 fvdl #define SDMAENACK 0x10 1319 1.1 fvdl #define SDMAEN 0x10 1320 1.1 fvdl #define HDMAEN 0x08 1321 1.1 fvdl #define HDMAENACK 0x08 1322 1.1 fvdl #define DIRECTION 0x04 1323 1.1 fvdl #define FIFOFLUSH 0x02 1324 1.1 fvdl #define FIFORESET 0x01 1325 1.1 fvdl 1326 1.2 fvdl #define SEQ_FLAGS 0x3c 1327 1.2 fvdl #define NOT_IDENTIFIED 0x80 1328 1.2 fvdl #define NO_CDB_SENT 0x40 1329 1.2 fvdl #define TARGET_CMD_IS_TAGGED 0x40 1330 1.1 fvdl #define DPHASE 0x20 1331 1.1 fvdl #define TARG_CMD_PENDING 0x10 1332 1.1 fvdl #define CMDPHASE_PENDING 0x08 1333 1.1 fvdl #define DPHASE_PENDING 0x04 1334 1.1 fvdl #define SPHASE_PENDING 0x02 1335 1.1 fvdl #define NO_DISCONNECT 0x01 1336 1.1 fvdl 1337 1.2 fvdl #define SAVED_SCSIID 0x3d 1338 1.1 fvdl 1339 1.2 fvdl #define SAVED_LUN 0x3e 1340 1.1 fvdl 1341 1.2 fvdl #define LASTPHASE 0x3f 1342 1.2 fvdl #define PHASE_MASK 0xe0 1343 1.1 fvdl #define P_MESGIN 0xe0 1344 1.1 fvdl #define P_STATUS 0xc0 1345 1.1 fvdl #define P_MESGOUT 0xa0 1346 1.1 fvdl #define P_COMMAND 0x80 1347 1.2 fvdl #define P_DATAIN 0x40 1348 1.2 fvdl #define P_BUSFREE 0x01 1349 1.2 fvdl #define P_DATAOUT 0x00 1350 1.1 fvdl #define CDI 0x80 1351 1.1 fvdl #define IOI 0x40 1352 1.1 fvdl #define MSGI 0x20 1353 1.1 fvdl 1354 1.2 fvdl #define WAITING_SCBH 0x40 1355 1.1 fvdl 1356 1.2 fvdl #define DISCONNECTED_SCBH 0x41 1357 1.1 fvdl 1358 1.2 fvdl #define FREE_SCBH 0x42 1359 1.1 fvdl 1360 1.2 fvdl #define COMPLETE_SCBH 0x43 1361 1.1 fvdl 1362 1.2 fvdl #define HSCB_ADDR 0x44 1363 1.1 fvdl 1364 1.2 fvdl #define SHARED_DATA_ADDR 0x48 1365 1.1 fvdl 1366 1.2 fvdl #define KERNEL_QINPOS 0x4c 1367 1.1 fvdl 1368 1.2 fvdl #define QINPOS 0x4d 1369 1.1 fvdl 1370 1.2 fvdl #define QOUTPOS 0x4e 1371 1.1 fvdl 1372 1.2 fvdl #define KERNEL_TQINPOS 0x4f 1373 1.1 fvdl 1374 1.2 fvdl #define TQINPOS 0x50 1375 1.1 fvdl 1376 1.2 fvdl #define ARG_1 0x51 1377 1.2 fvdl #define RETURN_1 0x51 1378 1.1 fvdl #define SEND_MSG 0x80 1379 1.1 fvdl #define SEND_SENSE 0x40 1380 1.1 fvdl #define SEND_REJ 0x20 1381 1.1 fvdl #define MSGOUT_PHASEMIS 0x10 1382 1.1 fvdl #define EXIT_MSG_LOOP 0x08 1383 1.1 fvdl #define CONT_MSG_LOOP 0x04 1384 1.1 fvdl #define CONT_TARG_SESSION 0x02 1385 1.1 fvdl 1386 1.2 fvdl #define ARG_2 0x52 1387 1.2 fvdl #define RETURN_2 0x52 1388 1.1 fvdl 1389 1.2 fvdl #define LAST_MSG 0x53 1390 1.1 fvdl 1391 1.2 fvdl #define SCSISEQ_TEMPLATE 0x54 1392 1.1 fvdl #define ENSELO 0x40 1393 1.1 fvdl #define ENSELI 0x20 1394 1.1 fvdl #define ENRSELI 0x10 1395 1.1 fvdl #define ENAUTOATNO 0x08 1396 1.1 fvdl #define ENAUTOATNI 0x04 1397 1.1 fvdl #define ENAUTOATNP 0x02 1398 1.1 fvdl 1399 1.2 fvdl #define DATA_COUNT_ODD 0x55 1400 1.2 fvdl 1401 1.2 fvdl #define HA_274_BIOSGLOBAL 0x56 1402 1.2 fvdl #define INITIATOR_TAG 0x56 1403 1.2 fvdl #define HA_274_EXTENDED_TRANS 0x01 1404 1.2 fvdl 1405 1.2 fvdl #define SEQ_FLAGS2 0x57 1406 1.2 fvdl #define TARGET_MSG_PENDING 0x02 1407 1.2 fvdl #define SCB_DMA 0x01 1408 1.1 fvdl 1409 1.1 fvdl #define SCSICONF 0x5a 1410 1.2 fvdl #define HWSCSIID 0x0f 1411 1.2 fvdl #define HSCSIID 0x07 1412 1.1 fvdl #define TERM_ENB 0x80 1413 1.1 fvdl #define RESET_SCSI 0x40 1414 1.1 fvdl #define ENSPCHK 0x20 1415 1.1 fvdl 1416 1.2 fvdl #define INTDEF 0x5c 1417 1.2 fvdl #define VECTOR 0x0f 1418 1.2 fvdl #define EDGE_TRIG 0x80 1419 1.1 fvdl 1420 1.1 fvdl #define HOSTCONF 0x5d 1421 1.1 fvdl 1422 1.1 fvdl #define HA_274_BIOSCTRL 0x5f 1423 1.2 fvdl #define BIOSDISABLED 0x30 1424 1.1 fvdl #define BIOSMODE 0x30 1425 1.1 fvdl #define CHANNEL_B_PRIMARY 0x08 1426 1.1 fvdl 1427 1.1 fvdl #define SEQCTL 0x60 1428 1.1 fvdl #define PERRORDIS 0x80 1429 1.1 fvdl #define PAUSEDIS 0x40 1430 1.1 fvdl #define FAILDIS 0x20 1431 1.1 fvdl #define FASTMODE 0x10 1432 1.1 fvdl #define BRKADRINTEN 0x08 1433 1.1 fvdl #define STEP 0x04 1434 1.1 fvdl #define SEQRESET 0x02 1435 1.1 fvdl #define LOADRAM 0x01 1436 1.1 fvdl 1437 1.1 fvdl #define SEQRAM 0x61 1438 1.1 fvdl 1439 1.1 fvdl #define SEQADDR0 0x62 1440 1.1 fvdl 1441 1.1 fvdl #define SEQADDR1 0x63 1442 1.1 fvdl #define SEQADDR1_MASK 0x01 1443 1.1 fvdl 1444 1.1 fvdl #define ACCUM 0x64 1445 1.1 fvdl 1446 1.1 fvdl #define SINDEX 0x65 1447 1.1 fvdl 1448 1.1 fvdl #define DINDEX 0x66 1449 1.1 fvdl 1450 1.1 fvdl #define ALLONES 0x69 1451 1.1 fvdl 1452 1.2 fvdl #define NONE 0x6a 1453 1.2 fvdl 1454 1.1 fvdl #define ALLZEROS 0x6a 1455 1.1 fvdl 1456 1.1 fvdl #define FLAGS 0x6b 1457 1.1 fvdl #define ZERO 0x02 1458 1.1 fvdl #define CARRY 0x01 1459 1.1 fvdl 1460 1.1 fvdl #define SINDIR 0x6c 1461 1.1 fvdl 1462 1.1 fvdl #define DINDIR 0x6d 1463 1.1 fvdl 1464 1.1 fvdl #define FUNCTION1 0x6e 1465 1.1 fvdl 1466 1.1 fvdl #define STACK 0x6f 1467 1.1 fvdl 1468 1.1 fvdl #define TARG_OFFSET 0x70 1469 1.1 fvdl 1470 1.2 fvdl #define SRAM_BASE 0x70 1471 1.2 fvdl 1472 1.1 fvdl #define BCTL 0x84 1473 1.1 fvdl #define ACE 0x08 1474 1.1 fvdl #define ENABLE 0x01 1475 1.1 fvdl 1476 1.1 fvdl #define DSCOMMAND0 0x84 1477 1.1 fvdl #define CACHETHEN 0x80 1478 1.1 fvdl #define DPARCKEN 0x40 1479 1.1 fvdl #define MPARCKEN 0x20 1480 1.1 fvdl #define EXTREQLCK 0x10 1481 1.1 fvdl #define INTSCBRAMSEL 0x08 1482 1.1 fvdl #define RAMPS 0x04 1483 1.1 fvdl #define USCBSIZE32 0x02 1484 1.1 fvdl #define CIOPARCKEN 0x01 1485 1.1 fvdl 1486 1.1 fvdl #define BUSTIME 0x85 1487 1.1 fvdl #define BOFF 0xf0 1488 1.1 fvdl #define BON 0x0f 1489 1.1 fvdl 1490 1.2 fvdl #define DSCOMMAND1 0x85 1491 1.2 fvdl #define DSLATT 0xfc 1492 1.2 fvdl #define HADDLDSEL1 0x02 1493 1.2 fvdl #define HADDLDSEL0 0x01 1494 1.2 fvdl 1495 1.1 fvdl #define BUSSPD 0x86 1496 1.1 fvdl #define DFTHRSH 0xc0 1497 1.2 fvdl #define DFTHRSH_75 0x80 1498 1.1 fvdl #define STBOFF 0x38 1499 1.1 fvdl #define STBON 0x07 1500 1.1 fvdl 1501 1.2 fvdl #define DSPCISTATUS 0x86 1502 1.2 fvdl #define DFTHRSH_100 0xc0 1503 1.2 fvdl 1504 1.1 fvdl #define HS_MAILBOX 0x86 1505 1.1 fvdl #define HOST_MAILBOX 0xf0 1506 1.2 fvdl #define HOST_TQINPOS 0x80 1507 1.1 fvdl #define SEQ_MAILBOX 0x0f 1508 1.1 fvdl 1509 1.1 fvdl #define HCNTRL 0x87 1510 1.1 fvdl #define POWRDN 0x40 1511 1.1 fvdl #define SWINT 0x10 1512 1.1 fvdl #define IRQMS 0x08 1513 1.1 fvdl #define PAUSE 0x04 1514 1.1 fvdl #define INTEN 0x02 1515 1.1 fvdl #define CHIPRST 0x01 1516 1.1 fvdl #define CHIPRSTACK 0x01 1517 1.1 fvdl 1518 1.1 fvdl #define HADDR 0x88 1519 1.1 fvdl 1520 1.1 fvdl #define HCNT 0x8c 1521 1.1 fvdl 1522 1.1 fvdl #define SCBPTR 0x90 1523 1.1 fvdl 1524 1.1 fvdl #define INTSTAT 0x91 1525 1.1 fvdl #define SEQINT_MASK 0xf1 1526 1.2 fvdl #define OUT_OF_RANGE 0xe1 1527 1.2 fvdl #define NO_FREE_SCB 0xd1 1528 1.2 fvdl #define SCB_MISMATCH 0xc1 1529 1.2 fvdl #define MISSED_BUSFREE 0xb1 1530 1.2 fvdl #define MKMSG_FAILED 0xa1 1531 1.2 fvdl #define DATA_OVERRUN 0x91 1532 1.2 fvdl #define PERR_DETECTED 0x81 1533 1.1 fvdl #define BAD_STATUS 0x71 1534 1.2 fvdl #define HOST_MSG_LOOP 0x61 1535 1.2 fvdl #define PDATA_REINIT 0x51 1536 1.2 fvdl #define IGN_WIDE_RES 0x41 1537 1.1 fvdl #define NO_MATCH 0x31 1538 1.2 fvdl #define PROTO_VIOLATION 0x21 1539 1.1 fvdl #define SEND_REJECT 0x11 1540 1.1 fvdl #define INT_PEND 0x0f 1541 1.2 fvdl #define BAD_PHASE 0x01 1542 1.1 fvdl #define BRKADRINT 0x08 1543 1.1 fvdl #define SCSIINT 0x04 1544 1.1 fvdl #define CMDCMPLT 0x02 1545 1.1 fvdl #define SEQINT 0x01 1546 1.1 fvdl 1547 1.1 fvdl #define ERROR 0x92 1548 1.1 fvdl #define CIOPARERR 0x80 1549 1.1 fvdl #define PCIERRSTAT 0x40 1550 1.1 fvdl #define MPARERR 0x20 1551 1.1 fvdl #define DPARERR 0x10 1552 1.1 fvdl #define SQPARERR 0x08 1553 1.1 fvdl #define ILLOPCODE 0x04 1554 1.1 fvdl #define ILLSADDR 0x02 1555 1.1 fvdl #define ILLHADDR 0x01 1556 1.1 fvdl 1557 1.2 fvdl #define CLRINT 0x92 1558 1.2 fvdl #define CLRPARERR 0x10 1559 1.2 fvdl #define CLRBRKADRINT 0x08 1560 1.2 fvdl #define CLRSCSIINT 0x04 1561 1.2 fvdl #define CLRCMDINT 0x02 1562 1.2 fvdl #define CLRSEQINT 0x01 1563 1.2 fvdl 1564 1.1 fvdl #define DFCNTRL 0x93 1565 1.1 fvdl 1566 1.1 fvdl #define DFSTATUS 0x94 1567 1.1 fvdl #define PRELOAD_AVAIL 0x80 1568 1.2 fvdl #define DFCACHETH 0x40 1569 1.2 fvdl #define FIFOQWDEMP 0x20 1570 1.1 fvdl #define MREQPEND 0x10 1571 1.1 fvdl #define HDONE 0x08 1572 1.1 fvdl #define DFTHRESH 0x04 1573 1.1 fvdl #define FIFOFULL 0x02 1574 1.1 fvdl #define FIFOEMP 0x01 1575 1.1 fvdl 1576 1.1 fvdl #define DFWADDR 0x95 1577 1.1 fvdl 1578 1.1 fvdl #define DFRADDR 0x97 1579 1.1 fvdl 1580 1.1 fvdl #define DFDAT 0x99 1581 1.1 fvdl 1582 1.1 fvdl #define SCBCNT 0x9a 1583 1.2 fvdl #define SCBCNT_MASK 0x1f 1584 1.1 fvdl #define SCBAUTO 0x80 1585 1.1 fvdl 1586 1.1 fvdl #define QINFIFO 0x9b 1587 1.1 fvdl 1588 1.1 fvdl #define QINCNT 0x9c 1589 1.1 fvdl 1590 1.1 fvdl #define CRCCONTROL1 0x9d 1591 1.1 fvdl #define CRCONSEEN 0x80 1592 1.1 fvdl #define CRCVALCHKEN 0x40 1593 1.1 fvdl #define CRCENDCHKEN 0x20 1594 1.1 fvdl #define CRCREQCHKEN 0x10 1595 1.1 fvdl #define TARGCRCENDEN 0x08 1596 1.1 fvdl #define TARGCRCCNTEN 0x04 1597 1.1 fvdl 1598 1.2 fvdl #define QOUTFIFO 0x9d 1599 1.1 fvdl 1600 1.1 fvdl #define SCSIPHASE 0x9e 1601 1.2 fvdl #define DATA_PHASE_MASK 0x03 1602 1.1 fvdl #define STATUS_PHASE 0x20 1603 1.1 fvdl #define COMMAND_PHASE 0x10 1604 1.1 fvdl #define MSG_IN_PHASE 0x08 1605 1.1 fvdl #define MSG_OUT_PHASE 0x04 1606 1.1 fvdl #define DATA_IN_PHASE 0x02 1607 1.1 fvdl #define DATA_OUT_PHASE 0x01 1608 1.1 fvdl 1609 1.2 fvdl #define QOUTCNT 0x9e 1610 1.2 fvdl 1611 1.1 fvdl #define SFUNCT 0x9f 1612 1.1 fvdl #define ALT_MODE 0x80 1613 1.1 fvdl 1614 1.1 fvdl #define SCB_BASE 0xa0 1615 1.1 fvdl 1616 1.2 fvdl #define SCB_CDB_PTR 0xa0 1617 1.2 fvdl #define SCB_CDB_STORE 0xa0 1618 1.2 fvdl #define SCB_RESIDUAL_DATACNT 0xa0 1619 1.1 fvdl 1620 1.2 fvdl #define SCB_RESIDUAL_SGPTR 0xa4 1621 1.1 fvdl 1622 1.2 fvdl #define SCB_SCSI_STATUS 0xa8 1623 1.1 fvdl 1624 1.2 fvdl #define SCB_TARGET_PHASES 0xa9 1625 1.1 fvdl 1626 1.2 fvdl #define SCB_TARGET_DATA_DIR 0xaa 1627 1.1 fvdl 1628 1.2 fvdl #define SCB_TARGET_ITAG 0xab 1629 1.1 fvdl 1630 1.1 fvdl #define SCB_DATAPTR 0xac 1631 1.1 fvdl 1632 1.1 fvdl #define SCB_DATACNT 0xb0 1633 1.2 fvdl #define SG_HIGH_ADDR_BITS 0x7f 1634 1.2 fvdl #define SG_LAST_SEG 0x80 1635 1.1 fvdl 1636 1.2 fvdl #define SCB_SGPTR 0xb4 1637 1.2 fvdl #define SG_RESID_VALID 0x04 1638 1.2 fvdl #define SG_FULL_RESID 0x02 1639 1.2 fvdl #define SG_LIST_NULL 0x01 1640 1.1 fvdl 1641 1.2 fvdl #define SCB_CONTROL 0xb8 1642 1.2 fvdl #define SCB_TAG_TYPE 0x03 1643 1.2 fvdl #define TARGET_SCB 0x80 1644 1.2 fvdl #define STATUS_RCVD 0x80 1645 1.2 fvdl #define DISCENB 0x40 1646 1.2 fvdl #define TAG_ENB 0x20 1647 1.2 fvdl #define MK_MESSAGE 0x10 1648 1.2 fvdl #define ULTRAENB 0x08 1649 1.2 fvdl #define DISCONNECTED 0x04 1650 1.1 fvdl 1651 1.2 fvdl #define SCB_SCSIID 0xb9 1652 1.2 fvdl #define TID 0xf0 1653 1.2 fvdl #define TWIN_TID 0x70 1654 1.2 fvdl #define OID 0x0f 1655 1.2 fvdl #define TWIN_CHNLB 0x80 1656 1.1 fvdl 1657 1.2 fvdl #define SCB_LUN 0xba 1658 1.2 fvdl #define LID 0xff 1659 1.1 fvdl 1660 1.2 fvdl #define SCB_TAG 0xbb 1661 1.1 fvdl 1662 1.2 fvdl #define SCB_CDB_LEN 0xbc 1663 1.1 fvdl 1664 1.2 fvdl #define SCB_SCSIRATE 0xbd 1665 1.1 fvdl 1666 1.2 fvdl #define SCB_SCSIOFFSET 0xbe 1667 1.2 fvdl 1668 1.2 fvdl #define SCB_NEXT 0xbf 1669 1.2 fvdl 1670 1.2 fvdl #define SCB_64_SPARE 0xc0 1671 1.1 fvdl 1672 1.1 fvdl #define SEECTL_2840 0xc0 1673 1.1 fvdl #define CS_2840 0x04 1674 1.1 fvdl #define CK_2840 0x02 1675 1.1 fvdl #define DO_2840 0x01 1676 1.1 fvdl 1677 1.1 fvdl #define STATUS_2840 0xc1 1678 1.1 fvdl #define BIOS_SEL 0x60 1679 1.1 fvdl #define ADSEL 0x1e 1680 1.2 fvdl #define EEPROM_TF 0x80 1681 1.1 fvdl #define DI_2840 0x01 1682 1.1 fvdl 1683 1.2 fvdl #define SCB_64_BTT 0xd0 1684 1.1 fvdl 1685 1.1 fvdl #define CCHADDR 0xe0 1686 1.1 fvdl 1687 1.1 fvdl #define CCHCNT 0xe8 1688 1.1 fvdl 1689 1.1 fvdl #define CCSGRAM 0xe9 1690 1.1 fvdl 1691 1.1 fvdl #define CCSGADDR 0xea 1692 1.1 fvdl 1693 1.1 fvdl #define CCSGCTL 0xeb 1694 1.1 fvdl #define CCSGDONE 0x80 1695 1.1 fvdl #define CCSGEN 0x08 1696 1.2 fvdl #define SG_FETCH_NEEDED 0x02 1697 1.1 fvdl #define CCSGRESET 0x01 1698 1.1 fvdl 1699 1.1 fvdl #define CCSCBRAM 0xec 1700 1.1 fvdl 1701 1.1 fvdl #define CCSCBADDR 0xed 1702 1.1 fvdl 1703 1.1 fvdl #define CCSCBCTL 0xee 1704 1.1 fvdl #define CCSCBDONE 0x80 1705 1.1 fvdl #define ARRDONE 0x40 1706 1.1 fvdl #define CCARREN 0x10 1707 1.1 fvdl #define CCSCBEN 0x08 1708 1.1 fvdl #define CCSCBDIR 0x04 1709 1.1 fvdl #define CCSCBRESET 0x01 1710 1.1 fvdl 1711 1.1 fvdl #define CCSCBCNT 0xef 1712 1.1 fvdl 1713 1.1 fvdl #define SCBBADDR 0xf0 1714 1.1 fvdl 1715 1.1 fvdl #define CCSCBPTR 0xf1 1716 1.1 fvdl 1717 1.1 fvdl #define HNSCB_QOFF 0xf4 1718 1.1 fvdl 1719 1.1 fvdl #define SNSCB_QOFF 0xf6 1720 1.1 fvdl 1721 1.1 fvdl #define SDSCB_QOFF 0xf8 1722 1.1 fvdl 1723 1.1 fvdl #define QOFF_CTLSTA 0xfa 1724 1.2 fvdl #define SCB_QSIZE 0x07 1725 1.2 fvdl #define SCB_QSIZE_256 0x06 1726 1.1 fvdl #define SCB_AVAIL 0x40 1727 1.1 fvdl #define SNSCB_ROLLOVER 0x20 1728 1.1 fvdl #define SDSCB_ROLLOVER 0x10 1729 1.1 fvdl 1730 1.1 fvdl #define DFF_THRSH 0xfb 1731 1.1 fvdl #define WR_DFTHRSH 0x70 1732 1.1 fvdl #define WR_DFTHRSH_MAX 0x70 1733 1.1 fvdl #define WR_DFTHRSH_90 0x60 1734 1.1 fvdl #define WR_DFTHRSH_85 0x50 1735 1.1 fvdl #define WR_DFTHRSH_75 0x40 1736 1.1 fvdl #define WR_DFTHRSH_63 0x30 1737 1.1 fvdl #define WR_DFTHRSH_50 0x20 1738 1.1 fvdl #define WR_DFTHRSH_25 0x10 1739 1.1 fvdl #define RD_DFTHRSH_MAX 0x07 1740 1.1 fvdl #define RD_DFTHRSH 0x07 1741 1.1 fvdl #define RD_DFTHRSH_90 0x06 1742 1.1 fvdl #define RD_DFTHRSH_85 0x05 1743 1.1 fvdl #define RD_DFTHRSH_75 0x04 1744 1.1 fvdl #define RD_DFTHRSH_63 0x03 1745 1.1 fvdl #define RD_DFTHRSH_50 0x02 1746 1.1 fvdl #define RD_DFTHRSH_25 0x01 1747 1.2 fvdl #define WR_DFTHRSH_MIN 0x00 1748 1.1 fvdl #define RD_DFTHRSH_MIN 0x00 1749 1.1 fvdl 1750 1.2 fvdl #define SG_CACHE_SHADOW 0xfc 1751 1.2 fvdl #define SG_ADDR_MASK 0xf8 1752 1.2 fvdl #define ODD_SEG 0x04 1753 1.1 fvdl #define LAST_SEG 0x02 1754 1.1 fvdl #define LAST_SEG_DONE 0x01 1755 1.1 fvdl 1756 1.2 fvdl #define SG_CACHE_PRE 0xfc 1757 1.2 fvdl 1758 1.1 fvdl 1759 1.2 fvdl #define TARGET_DATA_IN 0x01 1760 1.2 fvdl #define STATUS_BUSY 0x08 1761 1.2 fvdl #define BUS_16_BIT 0x01 1762 1.2 fvdl #define TID_SHIFT 0x04 1763 1.2 fvdl #define SCB_UPLOAD_SIZE 0x20 1764 1.2 fvdl #define HOST_MAILBOX_SHIFT 0x04 1765 1.2 fvdl #define MAX_OFFSET_ULTRA2 0x7f 1766 1.2 fvdl #define SCB_LIST_NULL 0xff 1767 1.2 fvdl #define HOST_MSG 0xff 1768 1.2 fvdl #define MAX_OFFSET 0xff 1769 1.2 fvdl #define BUS_32_BIT 0x02 1770 1.1 fvdl #define CMD_GROUP_CODE_SHIFT 0x05 1771 1.1 fvdl #define BUS_8_BIT 0x00 1772 1.1 fvdl #define CCSGRAM_MAXSEGS 0x10 1773 1.1 fvdl #define STATUS_QUEUE_FULL 0x28 1774 1.1 fvdl #define MAX_OFFSET_8BIT 0x0f 1775 1.2 fvdl #define SCB_DOWNLOAD_SIZE_64 0x30 1776 1.1 fvdl #define MAX_OFFSET_16BIT 0x08 1777 1.1 fvdl #define TARGET_CMD_CMPLT 0xfe 1778 1.1 fvdl #define SG_SIZEOF 0x08 1779 1.2 fvdl #define SCB_DOWNLOAD_SIZE 0x20 1780 1.1 fvdl #define SEQ_MAILBOX_SHIFT 0x00 1781 1.1 fvdl #define CCSGADDR_MAX 0x80 1782 1.2 fvdl #define STACK_SIZE 0x04 1783 1.1 fvdl 1784 1.1 fvdl 1785 1.1 fvdl /* Downloaded Constant Definitions */ 1786 1.2 fvdl #define SG_PREFETCH_CNT 0x04 1787 1.2 fvdl #define SG_PREFETCH_ADDR_MASK 0x06 1788 1.2 fvdl #define SG_PREFETCH_ALIGN_MASK 0x05 1789 1.2 fvdl #define QOUTFIFO_OFFSET 0x00 1790 1.2 fvdl #define INVERTED_CACHESIZE_MASK 0x03 1791 1.2 fvdl #define CACHESIZE_MASK 0x02 1792 1.2 fvdl #define QINFIFO_OFFSET 0x01 1793 1.2 fvdl #define DOWNLOAD_CONST_COUNT 0x07 1794 1.2 fvdl 1795 1.2 fvdl 1796 1.2 fvdl /* Exported Labels */ 1797
Indexes created Mon Oct 13 05:10:05 GMT 2025