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      1  1.1  fvdl /*	$NetBSD: aicasm_insformat.h,v 1.1 2003/04/19 19:26:11 fvdl Exp $	*/
      2  1.1  fvdl 
      3  1.1  fvdl /*
      4  1.1  fvdl  * Instruction formats for the sequencer program downloaded to
      5  1.1  fvdl  * Aic7xxx SCSI host adapters
      6  1.1  fvdl  *
      7  1.1  fvdl  * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
      8  1.1  fvdl  * All rights reserved.
      9  1.1  fvdl  *
     10  1.1  fvdl  * Redistribution and use in source and binary forms, with or without
     11  1.1  fvdl  * modification, are permitted provided that the following conditions
     12  1.1  fvdl  * are met:
     13  1.1  fvdl  * 1. Redistributions of source code must retain the above copyright
     14  1.1  fvdl  *    notice, this list of conditions, and the following disclaimer,
     15  1.1  fvdl  *    without modification.
     16  1.1  fvdl  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
     17  1.1  fvdl  *    substantially similar to the "NO WARRANTY" disclaimer below
     18  1.1  fvdl  *    ("Disclaimer") and any redistribution must be conditioned upon
     19  1.1  fvdl  *    including a substantially similar Disclaimer requirement for further
     20  1.1  fvdl  *    binary redistribution.
     21  1.1  fvdl  * 3. Neither the names of the above-listed copyright holders nor the names
     22  1.1  fvdl  *    of any contributors may be used to endorse or promote products derived
     23  1.1  fvdl  *    from this software without specific prior written permission.
     24  1.1  fvdl  *
     25  1.1  fvdl  * Alternatively, this software may be distributed under the terms of the
     26  1.1  fvdl  * GNU General Public License ("GPL") version 2 as published by the Free
     27  1.1  fvdl  * Software Foundation.
     28  1.1  fvdl  *
     29  1.1  fvdl  * NO WARRANTY
     30  1.1  fvdl  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     31  1.1  fvdl  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     32  1.1  fvdl  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
     33  1.1  fvdl  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     34  1.1  fvdl  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     35  1.1  fvdl  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     36  1.1  fvdl  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     37  1.1  fvdl  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     38  1.1  fvdl  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     39  1.1  fvdl  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     40  1.1  fvdl  * POSSIBILITY OF SUCH DAMAGES.
     41  1.1  fvdl  *
     42  1.1  fvdl  * $FreeBSD: src/sys/dev/aic7xxx/aicasm/aicasm_insformat.h,v 1.8 2002/11/27 07:06:43 scottl Exp $
     43  1.1  fvdl  */
     44  1.1  fvdl 
     45  1.1  fvdl struct ins_format1 {
     46  1.1  fvdl #if BYTE_ORDER == LITTLE_ENDIAN
     47  1.1  fvdl 	uint32_t	immediate	: 8,
     48  1.1  fvdl 			source		: 9,
     49  1.1  fvdl 			destination	: 9,
     50  1.1  fvdl 			ret		: 1,
     51  1.1  fvdl 			opcode		: 4,
     52  1.1  fvdl 			parity		: 1;
     53  1.1  fvdl #else
     54  1.1  fvdl 	uint32_t	parity		: 1,
     55  1.1  fvdl 			opcode		: 4,
     56  1.1  fvdl 			ret		: 1,
     57  1.1  fvdl 			destination	: 9,
     58  1.1  fvdl 			source		: 9,
     59  1.1  fvdl 			immediate	: 8;
     60  1.1  fvdl #endif
     61  1.1  fvdl };
     62  1.1  fvdl 
     63  1.1  fvdl struct ins_format2 {
     64  1.1  fvdl #if BYTE_ORDER == LITTLE_ENDIAN
     65  1.1  fvdl 	uint32_t	shift_control	: 8,
     66  1.1  fvdl 			source		: 9,
     67  1.1  fvdl 			destination	: 9,
     68  1.1  fvdl 			ret		: 1,
     69  1.1  fvdl 			opcode		: 4,
     70  1.1  fvdl 			parity		: 1;
     71  1.1  fvdl #else
     72  1.1  fvdl 	uint32_t	parity		: 1,
     73  1.1  fvdl 			opcode		: 4,
     74  1.1  fvdl 			ret		: 1,
     75  1.1  fvdl 			destination	: 9,
     76  1.1  fvdl 			source		: 9,
     77  1.1  fvdl 			shift_control	: 8;
     78  1.1  fvdl #endif
     79  1.1  fvdl };
     80  1.1  fvdl 
     81  1.1  fvdl struct ins_format3 {
     82  1.1  fvdl #if BYTE_ORDER == LITTLE_ENDIAN
     83  1.1  fvdl 	uint32_t	immediate	: 8,
     84  1.1  fvdl 			source		: 9,
     85  1.1  fvdl 			address		: 10,
     86  1.1  fvdl 			opcode		: 4,
     87  1.1  fvdl 			parity		: 1;
     88  1.1  fvdl #else
     89  1.1  fvdl 	uint32_t	parity		: 1,
     90  1.1  fvdl 			opcode		: 4,
     91  1.1  fvdl 			address		: 10,
     92  1.1  fvdl 			source		: 9,
     93  1.1  fvdl 			immediate	: 8;
     94  1.1  fvdl #endif
     95  1.1  fvdl };
     96  1.1  fvdl 
     97  1.1  fvdl union ins_formats {
     98  1.1  fvdl 		struct ins_format1 format1;
     99  1.1  fvdl 		struct ins_format2 format2;
    100  1.1  fvdl 		struct ins_format3 format3;
    101  1.1  fvdl 		uint8_t		   bytes[4];
    102  1.1  fvdl 		uint32_t	   integer;
    103  1.1  fvdl };
    104  1.1  fvdl struct instruction {
    105  1.1  fvdl 	union	ins_formats format;
    106  1.1  fvdl 	u_int	srcline;
    107  1.1  fvdl 	struct symbol *patch_label;
    108  1.1  fvdl 	STAILQ_ENTRY(instruction) links;
    109  1.1  fvdl };
    110  1.1  fvdl 
    111  1.1  fvdl #define	AIC_OP_OR	0x0
    112  1.1  fvdl #define	AIC_OP_AND	0x1
    113  1.1  fvdl #define AIC_OP_XOR	0x2
    114  1.1  fvdl #define	AIC_OP_ADD	0x3
    115  1.1  fvdl #define	AIC_OP_ADC	0x4
    116  1.1  fvdl #define	AIC_OP_ROL	0x5
    117  1.1  fvdl #define	AIC_OP_BMOV	0x6
    118  1.1  fvdl 
    119  1.1  fvdl #define	AIC_OP_JMP	0x8
    120  1.1  fvdl #define AIC_OP_JC	0x9
    121  1.1  fvdl #define AIC_OP_JNC	0xa
    122  1.1  fvdl #define AIC_OP_CALL	0xb
    123  1.1  fvdl #define	AIC_OP_JNE	0xc
    124  1.1  fvdl #define	AIC_OP_JNZ	0xd
    125  1.1  fvdl #define	AIC_OP_JE	0xe
    126  1.1  fvdl #define	AIC_OP_JZ	0xf
    127  1.1  fvdl 
    128  1.1  fvdl /* Pseudo Ops */
    129  1.1  fvdl #define	AIC_OP_SHL	0x10
    130  1.1  fvdl #define	AIC_OP_SHR	0x20
    131  1.1  fvdl #define	AIC_OP_ROR	0x30
    132