atphy.c revision 1.5.2.2.4.1
1 1.5.2.2.4.1 matt /* $NetBSD: atphy.c,v 1.5.2.2.4.1 2011/01/07 02:20:27 matt Exp $ */ 2 1.5.2.2 snj /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 1.5.2.2 snj 4 1.5.2.2 snj /*- 5 1.5.2.2 snj * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 1.5.2.2 snj * All rights reserved. 7 1.5.2.2 snj * 8 1.5.2.2 snj * Redistribution and use in source and binary forms, with or without 9 1.5.2.2 snj * modification, are permitted provided that the following conditions 10 1.5.2.2 snj * are met: 11 1.5.2.2 snj * 1. Redistributions of source code must retain the above copyright 12 1.5.2.2 snj * notice unmodified, this list of conditions, and the following 13 1.5.2.2 snj * disclaimer. 14 1.5.2.2 snj * 2. Redistributions in binary form must reproduce the above copyright 15 1.5.2.2 snj * notice, this list of conditions and the following disclaimer in the 16 1.5.2.2 snj * documentation and/or other materials provided with the distribution. 17 1.5.2.2 snj * 18 1.5.2.2 snj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 1.5.2.2 snj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 1.5.2.2 snj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 1.5.2.2 snj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 1.5.2.2 snj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 1.5.2.2 snj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 1.5.2.2 snj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.5.2.2 snj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 1.5.2.2 snj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.5.2.2 snj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.5.2.2 snj * SUCH DAMAGE. 29 1.5.2.2 snj */ 30 1.5.2.2 snj 31 1.5.2.2 snj /* 32 1.5.2.2 snj * Driver for the Attansic F1 10/100/1000 PHY. 33 1.5.2.2 snj */ 34 1.5.2.2 snj 35 1.5.2.2 snj #include <sys/cdefs.h> 36 1.5.2.2.4.1 matt __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.5.2.2.4.1 2011/01/07 02:20:27 matt Exp $"); 37 1.5.2.2 snj 38 1.5.2.2 snj #include <sys/param.h> 39 1.5.2.2 snj #include <sys/systm.h> 40 1.5.2.2 snj #include <sys/kernel.h> 41 1.5.2.2 snj #include <sys/device.h> 42 1.5.2.2 snj #include <sys/socket.h> 43 1.5.2.2 snj 44 1.5.2.2 snj #include <net/if.h> 45 1.5.2.2 snj #include <net/if_media.h> 46 1.5.2.2 snj 47 1.5.2.2 snj #include <dev/mii/mii.h> 48 1.5.2.2 snj #include <dev/mii/miivar.h> 49 1.5.2.2 snj #include <dev/mii/miidevs.h> 50 1.5.2.2 snj 51 1.5.2.2 snj /* Special Control Register */ 52 1.5.2.2 snj #define ATPHY_SCR 0x10 53 1.5.2.2 snj #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 1.5.2.2 snj #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 1.5.2.2 snj #define ATPHY_SCR_SQE_TEST 0x0004 56 1.5.2.2 snj #define ATPHY_SCR_MAC_PDOWN 0x0008 57 1.5.2.2 snj #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 1.5.2.2 snj #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 1.5.2.2 snj #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 1.5.2.2 snj #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 1.5.2.2 snj #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 1.5.2.2 snj #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 1.5.2.2 snj #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 1.5.2.2 snj #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 1.5.2.2 snj #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 1.5.2.2 snj #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 1.5.2.2 snj 68 1.5.2.2 snj /* Special Status Register. */ 69 1.5.2.2 snj #define ATPHY_SSR 0x11 70 1.5.2.2 snj #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 1.5.2.2 snj #define ATPHY_SSR_DUPLEX 0x2000 72 1.5.2.2 snj #define ATPHY_SSR_SPEED_MASK 0xC000 73 1.5.2.2 snj #define ATPHY_SSR_10MBS 0x0000 74 1.5.2.2 snj #define ATPHY_SSR_100MBS 0x4000 75 1.5.2.2 snj #define ATPHY_SSR_1000MBS 0x8000 76 1.5.2.2 snj 77 1.5.2.2 snj static int atphy_match(device_t, cfdata_t, void *); 78 1.5.2.2 snj static void atphy_attach(device_t, device_t, void *); 79 1.5.2.2 snj 80 1.5.2.2 snj static int atphy_service(struct mii_softc *, struct mii_data *, int); 81 1.5.2.2 snj static void atphy_reset(struct mii_softc *); 82 1.5.2.2 snj static void atphy_status(struct mii_softc *); 83 1.5.2.2 snj static int atphy_mii_phy_auto(struct mii_softc *); 84 1.5.2.2 snj 85 1.5.2.2 snj CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc), 86 1.5.2.2 snj atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 87 1.5.2.2 snj 88 1.5.2.2 snj const struct mii_phy_funcs atphy_funcs = { 89 1.5.2.2 snj atphy_service, atphy_status, atphy_reset, 90 1.5.2.2 snj }; 91 1.5.2.2 snj 92 1.5.2.2 snj static const struct mii_phydesc etphys[] = { 93 1.5.2.2 snj { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, 94 1.5.2.2 snj MII_STR_ATHEROS_F1 }, 95 1.5.2.2 snj { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, 96 1.5.2.2 snj MII_STR_ATTANSIC_L1 }, 97 1.5.2.2.4.1 matt { MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, 98 1.5.2.2.4.1 matt MII_STR_ATTANSIC_AR8021 }, 99 1.5.2.2 snj { 0, 0, 100 1.5.2.2 snj NULL }, 101 1.5.2.2 snj }; 102 1.5.2.2 snj 103 1.5.2.2 snj static int 104 1.5.2.2 snj atphy_match(device_t parent, cfdata_t match, void *aux) 105 1.5.2.2 snj { 106 1.5.2.2 snj struct mii_attach_args *ma = aux; 107 1.5.2.2 snj 108 1.5.2.2 snj if (mii_phy_match(ma, etphys) != NULL) 109 1.5.2.2 snj return 10; 110 1.5.2.2 snj 111 1.5.2.2 snj return 0; 112 1.5.2.2 snj } 113 1.5.2.2 snj 114 1.5.2.2 snj void 115 1.5.2.2 snj atphy_attach(device_t parent, device_t self, void *aux) 116 1.5.2.2 snj { 117 1.5.2.2 snj struct mii_softc *sc = device_private(self); 118 1.5.2.2 snj struct mii_attach_args *ma = aux; 119 1.5.2.2 snj struct mii_data *mii = ma->mii_data; 120 1.5.2.2 snj const struct mii_phydesc *mpd; 121 1.5.2.2 snj 122 1.5.2.2 snj mpd = mii_phy_match(ma, etphys); 123 1.5.2.2 snj aprint_naive(": Media interface\n"); 124 1.5.2.2 snj aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 125 1.5.2.2 snj 126 1.5.2.2 snj sc->mii_dev = self; 127 1.5.2.2 snj sc->mii_inst = mii->mii_instance; 128 1.5.2.2 snj sc->mii_phy = ma->mii_phyno; 129 1.5.2.2 snj sc->mii_funcs = &atphy_funcs; 130 1.5.2.2 snj sc->mii_pdata = mii; 131 1.5.2.2 snj sc->mii_flags = ma->mii_flags; 132 1.5.2.2 snj sc->mii_anegticks = MII_ANEGTICKS_GIGE; 133 1.5.2.2 snj 134 1.5.2.2 snj sc->mii_flags |= MIIF_NOLOOP; 135 1.5.2.2 snj 136 1.5.2.2 snj PHY_RESET(sc); 137 1.5.2.2 snj 138 1.5.2.2 snj sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 139 1.5.2.2 snj if (sc->mii_capabilities & BMSR_EXTSTAT) 140 1.5.2.2 snj sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 141 1.5.2.2 snj 142 1.5.2.2 snj aprint_normal_dev(self, ""); 143 1.5.2.2 snj mii_phy_add_media(sc); 144 1.5.2.2 snj aprint_normal("\n"); 145 1.5.2.2 snj } 146 1.5.2.2 snj 147 1.5.2.2 snj int 148 1.5.2.2 snj atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 149 1.5.2.2 snj { 150 1.5.2.2 snj struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 151 1.5.2.2 snj uint16_t anar, bmcr, bmsr; 152 1.5.2.2 snj 153 1.5.2.2 snj switch (cmd) { 154 1.5.2.2 snj case MII_POLLSTAT: 155 1.5.2.2 snj /* 156 1.5.2.2 snj * If we're not polling our PHY instance, just return. 157 1.5.2.2 snj */ 158 1.5.2.2 snj if (IFM_INST(ife->ifm_media) != sc->mii_inst) 159 1.5.2.2 snj return 0; 160 1.5.2.2 snj break; 161 1.5.2.2 snj 162 1.5.2.2 snj case MII_MEDIACHG: 163 1.5.2.2 snj /* 164 1.5.2.2 snj * If the media indicates a different PHY instance, 165 1.5.2.2 snj * isolate ourselves. 166 1.5.2.2 snj */ 167 1.5.2.2 snj if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 168 1.5.2.2 snj bmcr = PHY_READ(sc, MII_BMCR); 169 1.5.2.2 snj PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 170 1.5.2.2 snj return 0; 171 1.5.2.2 snj } 172 1.5.2.2 snj 173 1.5.2.2 snj /* 174 1.5.2.2 snj * If the interface is not up, don't do anything. 175 1.5.2.2 snj */ 176 1.5.2.2 snj if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 177 1.5.2.2 snj break; 178 1.5.2.2 snj 179 1.5.2.2 snj bmcr = 0; 180 1.5.2.2 snj switch (IFM_SUBTYPE(ife->ifm_media)) { 181 1.5.2.2 snj case IFM_AUTO: 182 1.5.2.2 snj case IFM_1000_T: 183 1.5.2.2 snj atphy_mii_phy_auto(sc); 184 1.5.2.2 snj goto done; 185 1.5.2.2 snj case IFM_100_TX: 186 1.5.2.2 snj bmcr = BMCR_S100; 187 1.5.2.2 snj break; 188 1.5.2.2 snj case IFM_10_T: 189 1.5.2.2 snj bmcr = BMCR_S10; 190 1.5.2.2 snj break; 191 1.5.2.2 snj case IFM_NONE: 192 1.5.2.2 snj bmcr = PHY_READ(sc, MII_BMCR); 193 1.5.2.2 snj /* 194 1.5.2.2 snj * XXX 195 1.5.2.2 snj * Due to an unknown reason powering down PHY resulted 196 1.5.2.2 snj * in unexpected results such as inaccessbility of 197 1.5.2.2 snj * hardware of freshly rebooted system. Disable 198 1.5.2.2 snj * powering down PHY until I got more information for 199 1.5.2.2 snj * Attansic/Atheros PHY hardwares. 200 1.5.2.2 snj */ 201 1.5.2.2 snj PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 202 1.5.2.2 snj goto done; 203 1.5.2.2 snj default: 204 1.5.2.2 snj return EINVAL; 205 1.5.2.2 snj } 206 1.5.2.2 snj 207 1.5.2.2 snj anar = mii_anar(ife->ifm_media); 208 1.5.2.2 snj if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 209 1.5.2.2 snj bmcr |= BMCR_FDX; 210 1.5.2.2 snj /* Enable pause. */ 211 1.5.2.2 snj if (sc->mii_flags & MIIF_DOPAUSE) 212 1.5.2.2 snj anar |= (3 << 10); 213 1.5.2.2 snj } 214 1.5.2.2 snj 215 1.5.2.2 snj if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 216 1.5.2.2 snj EXTSR_1000THDX)) != 0) 217 1.5.2.2 snj PHY_WRITE(sc, MII_100T2CR, 0); 218 1.5.2.2 snj PHY_WRITE(sc, MII_ANAR, anar); 219 1.5.2.2 snj 220 1.5.2.2 snj /* 221 1.5.2.2 snj * Reset the PHY so all changes take effect. 222 1.5.2.2 snj */ 223 1.5.2.2 snj PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN | 224 1.5.2.2 snj BMCR_STARTNEG); 225 1.5.2.2 snj done: 226 1.5.2.2 snj break; 227 1.5.2.2 snj 228 1.5.2.2 snj case MII_TICK: 229 1.5.2.2 snj /* 230 1.5.2.2 snj * If we're not currently selected, just return. 231 1.5.2.2 snj */ 232 1.5.2.2 snj if (IFM_INST(ife->ifm_media) != sc->mii_inst) 233 1.5.2.2 snj return 0; 234 1.5.2.2 snj 235 1.5.2.2 snj /* 236 1.5.2.2 snj * Is the interface even up? 237 1.5.2.2 snj */ 238 1.5.2.2 snj if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 239 1.5.2.2 snj return 0; 240 1.5.2.2 snj 241 1.5.2.2 snj /* 242 1.5.2.2 snj * Only used for autonegotiation. 243 1.5.2.2 snj */ 244 1.5.2.2 snj if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 245 1.5.2.2 snj sc->mii_ticks = 0; 246 1.5.2.2 snj break; 247 1.5.2.2 snj } 248 1.5.2.2 snj 249 1.5.2.2 snj /* 250 1.5.2.2 snj * Check for link. 251 1.5.2.2 snj * Read the status register twice; BMSR_LINK is latch-low. 252 1.5.2.2 snj */ 253 1.5.2.2 snj bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 254 1.5.2.2 snj if (bmsr & BMSR_LINK) { 255 1.5.2.2 snj sc->mii_ticks = 0; 256 1.5.2.2 snj break; 257 1.5.2.2 snj } 258 1.5.2.2 snj 259 1.5.2.2 snj /* Announce link loss right after it happens. */ 260 1.5.2.2 snj if (sc->mii_ticks++ == 0) 261 1.5.2.2 snj break; 262 1.5.2.2 snj 263 1.5.2.2 snj /* 264 1.5.2.2 snj * Only retry autonegotiation every mii_anegticks seconds. 265 1.5.2.2 snj */ 266 1.5.2.2 snj if (sc->mii_ticks <= sc->mii_anegticks) 267 1.5.2.2 snj break; 268 1.5.2.2 snj 269 1.5.2.2 snj sc->mii_ticks = 0; 270 1.5.2.2 snj atphy_mii_phy_auto(sc); 271 1.5.2.2 snj break; 272 1.5.2.2 snj } 273 1.5.2.2 snj 274 1.5.2.2 snj /* Update the media status. */ 275 1.5.2.2 snj mii_phy_status(sc); 276 1.5.2.2 snj 277 1.5.2.2 snj /* Callback if something changed. */ 278 1.5.2.2 snj mii_phy_update(sc, cmd); 279 1.5.2.2 snj return 0; 280 1.5.2.2 snj } 281 1.5.2.2 snj 282 1.5.2.2 snj static void 283 1.5.2.2 snj atphy_status(struct mii_softc *sc) 284 1.5.2.2 snj { 285 1.5.2.2 snj struct mii_data *mii = sc->mii_pdata; 286 1.5.2.2 snj uint32_t bmsr, bmcr, gsr, ssr; 287 1.5.2.2 snj 288 1.5.2.2 snj mii->mii_media_status = IFM_AVALID; 289 1.5.2.2 snj mii->mii_media_active = IFM_ETHER; 290 1.5.2.2 snj 291 1.5.2.2 snj bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 292 1.5.2.2 snj if (bmsr & BMSR_LINK) 293 1.5.2.2 snj mii->mii_media_status |= IFM_ACTIVE; 294 1.5.2.2 snj 295 1.5.2.2 snj bmcr = PHY_READ(sc, MII_BMCR); 296 1.5.2.2 snj if (bmcr & BMCR_ISO) { 297 1.5.2.2 snj mii->mii_media_active |= IFM_NONE; 298 1.5.2.2 snj mii->mii_media_status = 0; 299 1.5.2.2 snj return; 300 1.5.2.2 snj } 301 1.5.2.2 snj 302 1.5.2.2 snj if (bmcr & BMCR_LOOP) 303 1.5.2.2 snj mii->mii_media_active |= IFM_LOOP; 304 1.5.2.2 snj 305 1.5.2.2 snj ssr = PHY_READ(sc, ATPHY_SSR); 306 1.5.2.2 snj if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 307 1.5.2.2 snj /* Erg, still trying, I guess... */ 308 1.5.2.2 snj mii->mii_media_active |= IFM_NONE; 309 1.5.2.2 snj return; 310 1.5.2.2 snj } 311 1.5.2.2 snj 312 1.5.2.2 snj switch (ssr & ATPHY_SSR_SPEED_MASK) { 313 1.5.2.2 snj case ATPHY_SSR_1000MBS: 314 1.5.2.2 snj mii->mii_media_active |= IFM_1000_T; 315 1.5.2.2 snj /* 316 1.5.2.2 snj * atphy(4) has a valid link so reset mii_ticks. 317 1.5.2.2 snj * Resetting mii_ticks is needed in order to 318 1.5.2.2 snj * detect link loss after auto-negotiation. 319 1.5.2.2 snj */ 320 1.5.2.2 snj sc->mii_ticks = 0; 321 1.5.2.2 snj break; 322 1.5.2.2 snj case ATPHY_SSR_100MBS: 323 1.5.2.2 snj mii->mii_media_active |= IFM_100_TX; 324 1.5.2.2 snj sc->mii_ticks = 0; 325 1.5.2.2 snj break; 326 1.5.2.2 snj case ATPHY_SSR_10MBS: 327 1.5.2.2 snj mii->mii_media_active |= IFM_10_T; 328 1.5.2.2 snj sc->mii_ticks = 0; 329 1.5.2.2 snj break; 330 1.5.2.2 snj default: 331 1.5.2.2 snj mii->mii_media_active |= IFM_NONE; 332 1.5.2.2 snj return; 333 1.5.2.2 snj } 334 1.5.2.2 snj 335 1.5.2.2 snj if (ssr & ATPHY_SSR_DUPLEX) 336 1.5.2.2 snj mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 337 1.5.2.2 snj else 338 1.5.2.2 snj mii->mii_media_active |= IFM_HDX; 339 1.5.2.2 snj 340 1.5.2.2 snj gsr = PHY_READ(sc, MII_100T2SR); 341 1.5.2.2 snj if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 342 1.5.2.2 snj gsr & GTSR_MS_RES) 343 1.5.2.2 snj mii->mii_media_active |= IFM_ETH_MASTER; 344 1.5.2.2 snj } 345 1.5.2.2 snj 346 1.5.2.2 snj static void 347 1.5.2.2 snj atphy_reset(struct mii_softc *sc) 348 1.5.2.2 snj { 349 1.5.2.2 snj uint32_t reg; 350 1.5.2.2 snj int i; 351 1.5.2.2 snj 352 1.5.2.2 snj /* Take PHY out of power down mode. */ 353 1.5.2.2 snj PHY_WRITE(sc, 29, 0x29); 354 1.5.2.2 snj PHY_WRITE(sc, 30, 0); 355 1.5.2.2 snj 356 1.5.2.2 snj reg = PHY_READ(sc, ATPHY_SCR); 357 1.5.2.2 snj /* Enable automatic crossover. */ 358 1.5.2.2 snj reg |= ATPHY_SCR_AUTO_X_MODE; 359 1.5.2.2 snj /* Disable power down. */ 360 1.5.2.2 snj reg &= ~ATPHY_SCR_MAC_PDOWN; 361 1.5.2.2 snj /* Enable CRS on Tx. */ 362 1.5.2.2 snj reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 363 1.5.2.2 snj /* Auto correction for reversed cable polarity. */ 364 1.5.2.2 snj reg |= ATPHY_SCR_POLARITY_REVERSAL; 365 1.5.2.2 snj PHY_WRITE(sc, ATPHY_SCR, reg); 366 1.5.2.2 snj 367 1.5.2.2 snj /* Workaround F1 bug to reset phy. */ 368 1.5.2.2 snj atphy_mii_phy_auto(sc); 369 1.5.2.2 snj 370 1.5.2.2 snj for (i = 0; i < 1000; i++) { 371 1.5.2.2 snj DELAY(1); 372 1.5.2.2 snj if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 373 1.5.2.2 snj break; 374 1.5.2.2 snj } 375 1.5.2.2 snj } 376 1.5.2.2 snj 377 1.5.2.2 snj static int 378 1.5.2.2 snj atphy_mii_phy_auto(struct mii_softc *sc) 379 1.5.2.2 snj { 380 1.5.2.2 snj uint16_t anar; 381 1.5.2.2 snj 382 1.5.2.2 snj anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 383 1.5.2.2 snj if (sc->mii_flags & MIIF_DOPAUSE) 384 1.5.2.2 snj anar |= (3 << 10); 385 1.5.2.2 snj PHY_WRITE(sc, MII_ANAR, anar); 386 1.5.2.2 snj if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 387 1.5.2.2 snj PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 388 1.5.2.2 snj GTCR_ADV_1000THDX); 389 1.5.2.2 snj PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 390 1.5.2.2 snj 391 1.5.2.2 snj return EJUSTRETURN; 392 1.5.2.2 snj } 393
Indexes created Mon Oct 27 02:09:54 GMT 2025