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atphy.c revision 1.7.4.1
      1  1.7.4.1  bouyer /*	$NetBSD: atphy.c,v 1.7.4.1 2011/02/08 16:19:49 bouyer Exp $ */
      2      1.1  cegger /*	$OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $	*/
      3      1.1  cegger 
      4      1.1  cegger /*-
      5      1.1  cegger  * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org>
      6      1.1  cegger  * All rights reserved.
      7      1.1  cegger  *
      8      1.1  cegger  * Redistribution and use in source and binary forms, with or without
      9      1.1  cegger  * modification, are permitted provided that the following conditions
     10      1.1  cegger  * are met:
     11      1.1  cegger  * 1. Redistributions of source code must retain the above copyright
     12      1.1  cegger  *    notice unmodified, this list of conditions, and the following
     13      1.1  cegger  *    disclaimer.
     14      1.1  cegger  * 2. Redistributions in binary form must reproduce the above copyright
     15      1.1  cegger  *    notice, this list of conditions and the following disclaimer in the
     16      1.1  cegger  *    documentation and/or other materials provided with the distribution.
     17      1.1  cegger  *
     18      1.1  cegger  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     19      1.1  cegger  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20      1.1  cegger  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21      1.1  cegger  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     22      1.1  cegger  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     23      1.1  cegger  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     24      1.1  cegger  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     25      1.1  cegger  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     26      1.1  cegger  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27      1.1  cegger  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28      1.1  cegger  * SUCH DAMAGE.
     29      1.1  cegger  */
     30      1.1  cegger 
     31      1.1  cegger /*
     32      1.1  cegger  * Driver for the Attansic F1 10/100/1000 PHY.
     33      1.1  cegger  */
     34      1.1  cegger 
     35      1.2  cegger #include <sys/cdefs.h>
     36  1.7.4.1  bouyer __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.7.4.1 2011/02/08 16:19:49 bouyer Exp $");
     37      1.2  cegger 
     38      1.1  cegger #include <sys/param.h>
     39      1.1  cegger #include <sys/systm.h>
     40      1.1  cegger #include <sys/kernel.h>
     41      1.1  cegger #include <sys/device.h>
     42      1.1  cegger #include <sys/socket.h>
     43      1.1  cegger 
     44      1.1  cegger #include <net/if.h>
     45      1.1  cegger #include <net/if_media.h>
     46      1.1  cegger 
     47      1.1  cegger #include <dev/mii/mii.h>
     48      1.1  cegger #include <dev/mii/miivar.h>
     49      1.1  cegger #include <dev/mii/miidevs.h>
     50      1.1  cegger 
     51      1.1  cegger /* Special Control Register */
     52      1.1  cegger #define ATPHY_SCR			0x10
     53      1.1  cegger #define ATPHY_SCR_JABBER_DISABLE	0x0001
     54      1.1  cegger #define ATPHY_SCR_POLARITY_REVERSAL	0x0002
     55      1.1  cegger #define ATPHY_SCR_SQE_TEST		0x0004
     56      1.1  cegger #define ATPHY_SCR_MAC_PDOWN		0x0008
     57      1.1  cegger #define ATPHY_SCR_CLK125_DISABLE	0x0010
     58      1.1  cegger #define ATPHY_SCR_MDI_MANUAL_MODE	0x0000
     59      1.1  cegger #define ATPHY_SCR_MDIX_MANUAL_MODE	0x0020
     60      1.1  cegger #define ATPHY_SCR_AUTO_X_1000T		0x0040
     61      1.1  cegger #define ATPHY_SCR_AUTO_X_MODE		0x0060
     62      1.1  cegger #define ATPHY_SCR_10BT_EXT_ENABLE	0x0080
     63      1.1  cegger #define ATPHY_SCR_MII_5BIT_ENABLE	0x0100
     64      1.1  cegger #define ATPHY_SCR_SCRAMBLER_DISABLE	0x0200
     65      1.1  cegger #define ATPHY_SCR_FORCE_LINK_GOOD	0x0400
     66      1.1  cegger #define ATPHY_SCR_ASSERT_CRS_ON_TX	0x0800
     67      1.1  cegger 
     68      1.1  cegger /* Special Status Register. */
     69      1.1  cegger #define ATPHY_SSR			0x11
     70      1.1  cegger #define ATPHY_SSR_SPD_DPLX_RESOLVED	0x0800
     71      1.1  cegger #define ATPHY_SSR_DUPLEX		0x2000
     72      1.1  cegger #define ATPHY_SSR_SPEED_MASK		0xC000
     73      1.1  cegger #define ATPHY_SSR_10MBS			0x0000
     74      1.1  cegger #define ATPHY_SSR_100MBS		0x4000
     75      1.1  cegger #define ATPHY_SSR_1000MBS		0x8000
     76      1.1  cegger 
     77      1.1  cegger static int atphy_match(device_t, cfdata_t, void *);
     78      1.1  cegger static void atphy_attach(device_t, device_t, void *);
     79      1.1  cegger 
     80      1.1  cegger static int atphy_service(struct mii_softc *, struct mii_data *, int);
     81      1.1  cegger static void atphy_reset(struct mii_softc *);
     82      1.1  cegger static void atphy_status(struct mii_softc *);
     83      1.1  cegger static int atphy_mii_phy_auto(struct mii_softc *);
     84      1.1  cegger 
     85      1.1  cegger CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc),
     86      1.1  cegger 	atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate);
     87      1.1  cegger 
     88      1.1  cegger const struct mii_phy_funcs atphy_funcs = {
     89      1.1  cegger         atphy_service, atphy_status, atphy_reset,
     90      1.1  cegger };
     91      1.1  cegger 
     92      1.1  cegger static const struct mii_phydesc etphys[] = {
     93      1.1  cegger 	{ MII_OUI_ATHEROS,	MII_MODEL_ATHEROS_F1,
     94      1.1  cegger 	  MII_STR_ATHEROS_F1 },
     95      1.3  cegger 	{ MII_OUI_ATTANSIC,	MII_MODEL_ATTANSIC_L1,
     96      1.3  cegger 	  MII_STR_ATTANSIC_L1 },
     97      1.7    matt 	{ MII_OUI_ATTANSIC,	MII_MODEL_ATTANSIC_AR8021,
     98      1.7    matt 	  MII_STR_ATTANSIC_AR8021 },
     99      1.1  cegger 	{ 0,			0,
    100      1.1  cegger 	  NULL },
    101      1.1  cegger };
    102      1.1  cegger 
    103      1.1  cegger static int
    104      1.1  cegger atphy_match(device_t parent, cfdata_t match, void *aux)
    105      1.1  cegger {
    106      1.1  cegger 	struct mii_attach_args *ma = aux;
    107      1.1  cegger 
    108      1.1  cegger 	if (mii_phy_match(ma, etphys) != NULL)
    109      1.1  cegger 		return 10;
    110      1.1  cegger 
    111      1.1  cegger 	return 0;
    112      1.1  cegger }
    113      1.1  cegger 
    114      1.1  cegger void
    115      1.1  cegger atphy_attach(device_t parent, device_t self, void *aux)
    116      1.1  cegger {
    117      1.1  cegger 	struct mii_softc *sc = device_private(self);
    118      1.1  cegger 	struct mii_attach_args *ma = aux;
    119      1.1  cegger 	struct mii_data *mii = ma->mii_data;
    120      1.1  cegger 	const struct mii_phydesc *mpd;
    121  1.7.4.1  bouyer 	uint16_t bmsr;
    122      1.1  cegger 
    123      1.1  cegger 	mpd = mii_phy_match(ma, etphys);
    124      1.1  cegger 	aprint_naive(": Media interface\n");
    125      1.1  cegger 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    126      1.1  cegger 
    127      1.1  cegger 	sc->mii_dev = self;
    128      1.1  cegger 	sc->mii_inst = mii->mii_instance;
    129      1.1  cegger 	sc->mii_phy = ma->mii_phyno;
    130      1.1  cegger 	sc->mii_funcs = &atphy_funcs;
    131      1.1  cegger 	sc->mii_pdata = mii;
    132      1.1  cegger 	sc->mii_flags = ma->mii_flags;
    133      1.1  cegger 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
    134      1.1  cegger 
    135      1.1  cegger 	sc->mii_flags |= MIIF_NOLOOP;
    136      1.1  cegger 
    137      1.1  cegger 	PHY_RESET(sc);
    138      1.1  cegger 
    139  1.7.4.1  bouyer 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    140  1.7.4.1  bouyer 	sc->mii_capabilities = bmsr & ma->mii_capmask;
    141      1.1  cegger 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    142      1.1  cegger 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
    143      1.1  cegger 
    144      1.4  cegger 	aprint_normal_dev(self, "");
    145      1.1  cegger 	mii_phy_add_media(sc);
    146      1.4  cegger 	aprint_normal("\n");
    147      1.1  cegger }
    148      1.1  cegger 
    149      1.1  cegger int
    150      1.1  cegger atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    151      1.1  cegger {
    152      1.1  cegger 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    153      1.1  cegger 	uint16_t anar, bmcr, bmsr;
    154      1.1  cegger 
    155      1.1  cegger 	switch (cmd) {
    156      1.1  cegger 	case MII_POLLSTAT:
    157      1.1  cegger 		/*
    158      1.1  cegger 		 * If we're not polling our PHY instance, just return.
    159      1.1  cegger 		 */
    160      1.1  cegger 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    161      1.1  cegger 			return 0;
    162      1.1  cegger 		break;
    163      1.1  cegger 
    164      1.1  cegger 	case MII_MEDIACHG:
    165      1.1  cegger 		/*
    166      1.1  cegger 		 * If the media indicates a different PHY instance,
    167      1.1  cegger 		 * isolate ourselves.
    168      1.1  cegger 		 */
    169      1.1  cegger 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    170      1.1  cegger 			bmcr = PHY_READ(sc, MII_BMCR);
    171      1.1  cegger 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    172      1.1  cegger 			return 0;
    173      1.1  cegger 		}
    174      1.1  cegger 
    175      1.1  cegger 		/*
    176      1.1  cegger 		 * If the interface is not up, don't do anything.
    177      1.1  cegger 		 */
    178      1.1  cegger 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    179      1.1  cegger 			break;
    180      1.1  cegger 
    181      1.1  cegger 		bmcr = 0;
    182      1.1  cegger 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    183      1.1  cegger 		case IFM_AUTO:
    184      1.1  cegger 		case IFM_1000_T:
    185      1.1  cegger 			atphy_mii_phy_auto(sc);
    186      1.1  cegger 			goto done;
    187      1.1  cegger 		case IFM_100_TX:
    188      1.1  cegger 			bmcr = BMCR_S100;
    189      1.1  cegger 			break;
    190      1.1  cegger 		case IFM_10_T:
    191      1.1  cegger 			bmcr = BMCR_S10;
    192      1.1  cegger 			break;
    193      1.1  cegger 		case IFM_NONE:
    194      1.1  cegger 			bmcr = PHY_READ(sc, MII_BMCR);
    195      1.1  cegger 			/*
    196      1.1  cegger 			 * XXX
    197      1.1  cegger 			 * Due to an unknown reason powering down PHY resulted
    198      1.6  cegger 			 * in unexpected results such as inaccessibility of
    199      1.1  cegger 			 * hardware of freshly rebooted system. Disable
    200      1.1  cegger 			 * powering down PHY until I got more information for
    201      1.1  cegger 			 * Attansic/Atheros PHY hardwares.
    202      1.1  cegger 			 */
    203      1.1  cegger 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    204      1.1  cegger 			goto done;
    205      1.1  cegger 		default:
    206      1.1  cegger 			return EINVAL;
    207      1.1  cegger 		}
    208      1.1  cegger 
    209      1.1  cegger 		anar = mii_anar(ife->ifm_media);
    210      1.1  cegger 		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
    211      1.1  cegger 			bmcr |= BMCR_FDX;
    212      1.1  cegger 			/* Enable pause. */
    213      1.1  cegger 			if (sc->mii_flags & MIIF_DOPAUSE)
    214      1.6  cegger 				anar |= ANAR_X_PAUSE_TOWARDS;
    215      1.1  cegger 		}
    216      1.1  cegger 
    217      1.1  cegger 		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
    218      1.1  cegger 		    EXTSR_1000THDX)) != 0)
    219      1.1  cegger 			PHY_WRITE(sc, MII_100T2CR, 0);
    220      1.1  cegger 		PHY_WRITE(sc, MII_ANAR, anar);
    221      1.1  cegger 
    222      1.1  cegger 		/*
    223  1.7.4.1  bouyer 		 * Start autonegotiation.
    224      1.1  cegger 		 */
    225  1.7.4.1  bouyer 		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
    226      1.1  cegger done:
    227      1.1  cegger 		break;
    228      1.1  cegger 
    229      1.1  cegger 	case MII_TICK:
    230      1.1  cegger 		/*
    231      1.1  cegger 		 * If we're not currently selected, just return.
    232      1.1  cegger 		 */
    233      1.1  cegger 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    234      1.1  cegger 			return 0;
    235      1.1  cegger 
    236      1.1  cegger 		/*
    237      1.1  cegger 		 * Is the interface even up?
    238      1.1  cegger 		 */
    239      1.1  cegger 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    240      1.1  cegger 			return 0;
    241      1.1  cegger 
    242      1.1  cegger 		/*
    243      1.1  cegger 		 * Only used for autonegotiation.
    244      1.1  cegger 		 */
    245      1.1  cegger 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
    246      1.1  cegger 			sc->mii_ticks = 0;
    247      1.1  cegger 			break;
    248      1.1  cegger 		}
    249      1.1  cegger 
    250      1.1  cegger 		/*
    251      1.1  cegger 		 * Check for link.
    252      1.1  cegger 		 * Read the status register twice; BMSR_LINK is latch-low.
    253      1.1  cegger 		 */
    254      1.1  cegger 		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    255      1.1  cegger 		if (bmsr & BMSR_LINK) {
    256      1.1  cegger 			sc->mii_ticks = 0;
    257      1.1  cegger 			break;
    258      1.1  cegger 		}
    259      1.1  cegger 
    260      1.1  cegger 		/* Announce link loss right after it happens. */
    261      1.1  cegger 		if (sc->mii_ticks++ == 0)
    262      1.1  cegger 			break;
    263      1.1  cegger 
    264      1.1  cegger 		/*
    265      1.1  cegger 		 * Only retry autonegotiation every mii_anegticks seconds.
    266      1.1  cegger 		 */
    267      1.1  cegger 		if (sc->mii_ticks <= sc->mii_anegticks)
    268      1.1  cegger 			break;
    269      1.1  cegger 
    270      1.1  cegger 		sc->mii_ticks = 0;
    271      1.1  cegger 		atphy_mii_phy_auto(sc);
    272      1.1  cegger 		break;
    273      1.1  cegger 	}
    274      1.1  cegger 
    275      1.1  cegger 	/* Update the media status. */
    276      1.1  cegger 	mii_phy_status(sc);
    277      1.1  cegger 
    278      1.1  cegger 	/* Callback if something changed. */
    279      1.1  cegger 	mii_phy_update(sc, cmd);
    280      1.1  cegger 	return 0;
    281      1.1  cegger }
    282      1.1  cegger 
    283      1.1  cegger static void
    284      1.1  cegger atphy_status(struct mii_softc *sc)
    285      1.1  cegger {
    286      1.1  cegger 	struct mii_data *mii = sc->mii_pdata;
    287      1.1  cegger 	uint32_t bmsr, bmcr, gsr, ssr;
    288      1.1  cegger 
    289      1.1  cegger 	mii->mii_media_status = IFM_AVALID;
    290      1.1  cegger 	mii->mii_media_active = IFM_ETHER;
    291      1.1  cegger 
    292      1.1  cegger 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    293      1.1  cegger 	if (bmsr & BMSR_LINK)
    294      1.1  cegger 		mii->mii_media_status |= IFM_ACTIVE;
    295      1.1  cegger 
    296      1.1  cegger 	bmcr = PHY_READ(sc, MII_BMCR);
    297      1.1  cegger 	if (bmcr & BMCR_ISO) {
    298      1.1  cegger 		mii->mii_media_active |= IFM_NONE;
    299      1.1  cegger 		mii->mii_media_status = 0;
    300      1.1  cegger 		return;
    301      1.1  cegger 	}
    302      1.1  cegger 
    303      1.1  cegger 	if (bmcr & BMCR_LOOP)
    304      1.1  cegger 		mii->mii_media_active |= IFM_LOOP;
    305      1.1  cegger 
    306      1.1  cegger 	ssr = PHY_READ(sc, ATPHY_SSR);
    307      1.1  cegger 	if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
    308      1.1  cegger 		/* Erg, still trying, I guess... */
    309      1.1  cegger 		mii->mii_media_active |= IFM_NONE;
    310      1.1  cegger 		return;
    311      1.1  cegger 	}
    312      1.1  cegger 
    313      1.1  cegger 	switch (ssr & ATPHY_SSR_SPEED_MASK) {
    314      1.1  cegger 	case ATPHY_SSR_1000MBS:
    315      1.1  cegger 		mii->mii_media_active |= IFM_1000_T;
    316      1.1  cegger 		/*
    317      1.1  cegger 		 * atphy(4) has a valid link so reset mii_ticks.
    318      1.1  cegger 		 * Resetting mii_ticks is needed in order to
    319      1.1  cegger 		 * detect link loss after auto-negotiation.
    320      1.1  cegger 		 */
    321      1.1  cegger 		sc->mii_ticks = 0;
    322      1.1  cegger 		break;
    323      1.1  cegger 	case ATPHY_SSR_100MBS:
    324      1.1  cegger 		mii->mii_media_active |= IFM_100_TX;
    325      1.1  cegger 		sc->mii_ticks = 0;
    326      1.1  cegger 		break;
    327      1.1  cegger 	case ATPHY_SSR_10MBS:
    328      1.1  cegger 		mii->mii_media_active |= IFM_10_T;
    329      1.1  cegger 		sc->mii_ticks = 0;
    330      1.1  cegger 		break;
    331      1.1  cegger 	default:
    332      1.1  cegger 		mii->mii_media_active |= IFM_NONE;
    333      1.1  cegger 		return;
    334      1.1  cegger 	}
    335      1.1  cegger 
    336      1.1  cegger 	if (ssr & ATPHY_SSR_DUPLEX)
    337      1.1  cegger 		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
    338      1.1  cegger 	else
    339      1.1  cegger 		mii->mii_media_active |= IFM_HDX;
    340      1.1  cegger 
    341      1.1  cegger 	gsr = PHY_READ(sc, MII_100T2SR);
    342      1.1  cegger 	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
    343      1.1  cegger 	    gsr & GTSR_MS_RES)
    344      1.1  cegger 		mii->mii_media_active |= IFM_ETH_MASTER;
    345      1.1  cegger }
    346      1.1  cegger 
    347      1.1  cegger static void
    348      1.1  cegger atphy_reset(struct mii_softc *sc)
    349      1.1  cegger {
    350      1.1  cegger 	uint32_t reg;
    351      1.1  cegger 	int i;
    352      1.1  cegger 
    353      1.1  cegger 	/* Take PHY out of power down mode. */
    354      1.1  cegger 	PHY_WRITE(sc, 29, 0x29);
    355      1.1  cegger 	PHY_WRITE(sc, 30, 0);
    356      1.1  cegger 
    357      1.1  cegger 	reg = PHY_READ(sc, ATPHY_SCR);
    358      1.1  cegger 	/* Enable automatic crossover. */
    359      1.1  cegger 	reg |= ATPHY_SCR_AUTO_X_MODE;
    360      1.1  cegger 	/* Disable power down. */
    361      1.1  cegger 	reg &= ~ATPHY_SCR_MAC_PDOWN;
    362      1.1  cegger 	/* Enable CRS on Tx. */
    363      1.1  cegger 	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
    364      1.1  cegger 	/* Auto correction for reversed cable polarity. */
    365      1.1  cegger 	reg |= ATPHY_SCR_POLARITY_REVERSAL;
    366      1.1  cegger 	PHY_WRITE(sc, ATPHY_SCR, reg);
    367      1.1  cegger 
    368      1.1  cegger 	atphy_mii_phy_auto(sc);
    369      1.1  cegger 
    370  1.7.4.1  bouyer 	/* Workaround F1 bug to reset phy. */
    371  1.7.4.1  bouyer 	reg = PHY_READ(sc, MII_BMCR) | BMCR_RESET;
    372  1.7.4.1  bouyer 	PHY_WRITE(sc, MII_BMCR, reg);
    373  1.7.4.1  bouyer 
    374      1.1  cegger 	for (i = 0; i < 1000; i++) {
    375      1.1  cegger 		DELAY(1);
    376      1.1  cegger 		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
    377      1.1  cegger 			break;
    378      1.1  cegger 	}
    379      1.1  cegger }
    380      1.1  cegger 
    381      1.1  cegger static int
    382      1.1  cegger atphy_mii_phy_auto(struct mii_softc *sc)
    383      1.1  cegger {
    384      1.1  cegger 	uint16_t anar;
    385      1.1  cegger 
    386      1.1  cegger 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    387      1.1  cegger 	if (sc->mii_flags & MIIF_DOPAUSE)
    388      1.6  cegger 		anar |= ANAR_X_PAUSE_TOWARDS;
    389      1.1  cegger 	PHY_WRITE(sc, MII_ANAR, anar);
    390      1.1  cegger 	if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
    391      1.1  cegger 		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
    392      1.1  cegger 		    GTCR_ADV_1000THDX);
    393  1.7.4.1  bouyer 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
    394      1.1  cegger 
    395      1.1  cegger 	return EJUSTRETURN;
    396      1.1  cegger }
    397