atphy.c revision 1.18.16.2
1 /* $NetBSD: atphy.c,v 1.18.16.2 2020/04/13 08:04:24 martin Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.18.16.2 2020/04/13 08:04:24 martin Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 #define ATPHY_DEBUG_PORT_ADDR 0x1d 78 #define ATPHY_DEBUG_PORT_DATA 0x1e 79 #define ATPHY_RGMII_RX_CLK_DLY __BIT(15) 80 #define ATPHY_RGMII_TX_CLK_DLY __BIT(8) 81 82 static int atphy_match(device_t, cfdata_t, void *); 83 static void atphy_attach(device_t, device_t, void *); 84 85 static int atphy_service(struct mii_softc *, struct mii_data *, int); 86 static void atphy_reset(struct mii_softc *); 87 static void atphy_status(struct mii_softc *); 88 static int atphy_mii_phy_auto(struct mii_softc *); 89 static bool atphy_is_gige(const struct mii_phydesc *); 90 91 struct atphy_softc { 92 struct mii_softc mii_sc; 93 int mii_clk_25m; 94 bool rgmii_tx_internal_delay; 95 bool rgmii_rx_internal_delay; 96 }; 97 98 CFATTACH_DECL_NEW(atphy, sizeof(struct atphy_softc), 99 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 100 101 const struct mii_phy_funcs atphy_funcs = { 102 atphy_service, atphy_status, atphy_reset, 103 }; 104 105 static const struct mii_phydesc atphys[] = { 106 MII_PHY_DESC(ATTANSIC, L1), 107 MII_PHY_DESC(ATTANSIC, L2), 108 MII_PHY_DESC(ATTANSIC, AR8021), 109 MII_PHY_DESC(ATTANSIC, AR8035), 110 MII_PHY_END, 111 }; 112 113 static void 114 atphy_clk_25m(struct atphy_softc *asc) 115 { 116 struct mii_softc *sc = &asc->mii_sc; 117 struct { 118 uint32_t hz; 119 uint16_t data; 120 } select_clk[] = { 121 { 25000000, 0x0 }, 122 { 50000000, 0x1 }, 123 { 62500000, 0x2 }, 124 { 125000000, 0x3 } 125 }; 126 uint16_t data = 0; 127 uint16_t reg = 0; 128 129 for (int i = 0; i < __arraycount(select_clk); i++) { 130 if (asc->mii_clk_25m <= select_clk[i].hz) 131 data = select_clk[i].data; 132 } 133 134 PHY_WRITE(sc, 0x0d, 0x0007); 135 PHY_WRITE(sc, 0x0e, 0x8016); 136 PHY_WRITE(sc, 0x0d, 0x4007); 137 PHY_READ(sc, 0x0e, ®); 138 PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3))); 139 } 140 141 142 static bool 143 atphy_is_gige(const struct mii_phydesc *mpd) 144 { 145 switch (mpd->mpd_oui) { 146 case MII_OUI_ATTANSIC: 147 switch (mpd->mpd_model) { 148 case MII_MODEL_ATTANSIC_L2: 149 return false; 150 } 151 } 152 153 return true; 154 } 155 156 static int 157 atphy_match(device_t parent, cfdata_t match, void *aux) 158 { 159 struct mii_attach_args *ma = aux; 160 161 if (mii_phy_match(ma, atphys) != NULL) 162 return 10; 163 164 return 0; 165 } 166 167 void 168 atphy_attach(device_t parent, device_t self, void *aux) 169 { 170 struct atphy_softc *asc = device_private(self); 171 prop_dictionary_t parent_prop = device_properties(parent); 172 prop_dictionary_t prop = device_properties(self); 173 struct mii_softc *sc = &asc->mii_sc; 174 struct mii_attach_args *ma = aux; 175 struct mii_data *mii = ma->mii_data; 176 const struct mii_phydesc *mpd; 177 uint16_t bmsr; 178 179 mpd = mii_phy_match(ma, atphys); 180 aprint_naive(": Media interface\n"); 181 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 182 183 sc->mii_dev = self; 184 sc->mii_inst = mii->mii_instance; 185 sc->mii_phy = ma->mii_phyno; 186 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 187 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 188 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 189 sc->mii_funcs = &atphy_funcs; 190 sc->mii_pdata = mii; 191 sc->mii_flags = ma->mii_flags; 192 sc->mii_flags |= MIIF_NOLOOP; 193 194 prop_dictionary_get_bool(parent_prop, "tx_internal_delay", 195 &asc->rgmii_tx_internal_delay); 196 prop_dictionary_get_bool(parent_prop, "rx_internal_delay", 197 &asc->rgmii_rx_internal_delay); 198 199 prop_dictionary_get_uint32(prop, "clk_25m", &asc->mii_clk_25m); 200 if (asc->mii_clk_25m != 0) 201 atphy_clk_25m(asc); 202 203 mii_lock(mii); 204 205 PHY_RESET(sc); 206 207 PHY_READ(sc, MII_BMSR, &bmsr); 208 PHY_READ(sc, MII_BMSR, &bmsr); 209 sc->mii_capabilities = bmsr & ma->mii_capmask; 210 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 211 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 212 213 mii_unlock(mii); 214 215 mii_phy_add_media(sc); 216 } 217 218 int 219 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 220 { 221 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 222 uint16_t anar, bmcr, bmsr; 223 224 KASSERT(mii_locked(mii)); 225 226 switch (cmd) { 227 case MII_POLLSTAT: 228 /* If we're not polling our PHY instance, just return. */ 229 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 230 return 0; 231 break; 232 233 case MII_MEDIACHG: 234 /* 235 * If the media indicates a different PHY instance, 236 * isolate ourselves. 237 */ 238 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 239 PHY_READ(sc, MII_BMCR, &bmcr); 240 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 241 return 0; 242 } 243 244 /* If the interface is not up, don't do anything. */ 245 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 246 break; 247 248 bmcr = 0; 249 switch (IFM_SUBTYPE(ife->ifm_media)) { 250 case IFM_AUTO: 251 case IFM_1000_T: 252 atphy_mii_phy_auto(sc); 253 goto done; 254 case IFM_100_TX: 255 bmcr = BMCR_S100; 256 break; 257 case IFM_10_T: 258 bmcr = BMCR_S10; 259 break; 260 case IFM_NONE: 261 PHY_READ(sc, MII_BMCR, &bmcr); 262 /* 263 * XXX 264 * Due to an unknown reason powering down PHY resulted 265 * in unexpected results such as inaccessibility of 266 * hardware of freshly rebooted system. Disable 267 * powering down PHY until I got more information for 268 * Attansic/Atheros PHY hardwares. 269 */ 270 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 271 goto done; 272 default: 273 return EINVAL; 274 } 275 276 anar = mii_anar(ife); 277 if ((ife->ifm_media & IFM_FDX) != 0) { 278 bmcr |= BMCR_FDX; 279 /* Enable pause. */ 280 if (sc->mii_flags & MIIF_DOPAUSE) 281 anar |= ANAR_PAUSE_TOWARDS; 282 } 283 284 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 285 EXTSR_1000THDX)) != 0) 286 PHY_WRITE(sc, MII_100T2CR, 0); 287 PHY_WRITE(sc, MII_ANAR, anar); 288 289 /* Start autonegotiation. */ 290 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 291 done: 292 break; 293 294 case MII_TICK: 295 /* If we're not currently selected, just return. */ 296 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 297 return 0; 298 299 /* Is the interface even up? */ 300 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 301 return 0; 302 303 /* Only used for autonegotiation. */ 304 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 305 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 306 sc->mii_ticks = 0; 307 break; 308 } 309 310 /* 311 * Check for link. 312 * Read the status register twice; BMSR_LINK is latch-low. 313 */ 314 PHY_READ(sc, MII_BMSR, &bmsr); 315 PHY_READ(sc, MII_BMSR, &bmsr); 316 if (bmsr & BMSR_LINK) { 317 sc->mii_ticks = 0; 318 break; 319 } 320 321 /* Announce link loss right after it happens. */ 322 if (sc->mii_ticks++ == 0) 323 break; 324 325 /* Only retry autonegotiation every mii_anegticks seconds. */ 326 if (sc->mii_ticks <= sc->mii_anegticks) 327 break; 328 329 atphy_mii_phy_auto(sc); 330 break; 331 } 332 333 /* Update the media status. */ 334 mii_phy_status(sc); 335 336 /* Callback if something changed. */ 337 mii_phy_update(sc, cmd); 338 return 0; 339 } 340 341 static void 342 atphy_status(struct mii_softc *sc) 343 { 344 struct mii_data *mii = sc->mii_pdata; 345 uint16_t bmsr, bmcr, gsr, ssr; 346 347 KASSERT(mii_locked(mii)); 348 349 mii->mii_media_status = IFM_AVALID; 350 mii->mii_media_active = IFM_ETHER; 351 352 PHY_READ(sc, MII_BMSR, &bmsr); 353 PHY_READ(sc, MII_BMSR, &bmsr); 354 if (bmsr & BMSR_LINK) 355 mii->mii_media_status |= IFM_ACTIVE; 356 357 PHY_READ(sc, MII_BMCR, &bmcr); 358 if (bmcr & BMCR_ISO) { 359 mii->mii_media_active |= IFM_NONE; 360 mii->mii_media_status = 0; 361 return; 362 } 363 364 if (bmcr & BMCR_LOOP) 365 mii->mii_media_active |= IFM_LOOP; 366 367 PHY_READ(sc, ATPHY_SSR, &ssr); 368 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 369 /* Erg, still trying, I guess... */ 370 mii->mii_media_active |= IFM_NONE; 371 return; 372 } 373 374 switch (ssr & ATPHY_SSR_SPEED_MASK) { 375 case ATPHY_SSR_1000MBS: 376 mii->mii_media_active |= IFM_1000_T; 377 /* 378 * atphy(4) has a valid link so reset mii_ticks. 379 * Resetting mii_ticks is needed in order to 380 * detect link loss after auto-negotiation. 381 */ 382 sc->mii_ticks = 0; 383 break; 384 case ATPHY_SSR_100MBS: 385 mii->mii_media_active |= IFM_100_TX; 386 sc->mii_ticks = 0; 387 break; 388 case ATPHY_SSR_10MBS: 389 mii->mii_media_active |= IFM_10_T; 390 sc->mii_ticks = 0; 391 break; 392 default: 393 mii->mii_media_active |= IFM_NONE; 394 return; 395 } 396 397 if (ssr & ATPHY_SSR_DUPLEX) 398 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 399 else 400 mii->mii_media_active |= IFM_HDX; 401 402 PHY_READ(sc, MII_100T2SR, &gsr); 403 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 404 gsr & GTSR_MS_RES) 405 mii->mii_media_active |= IFM_ETH_MASTER; 406 } 407 408 static void 409 atphy_reset(struct mii_softc *sc) 410 { 411 struct atphy_softc *asc = (struct atphy_softc *)sc; 412 uint16_t reg; 413 int i; 414 415 KASSERT(mii_locked(sc->mii_pdata)); 416 417 /* 418 * Take PHY out of power down mode. 419 * 420 * XXX AR8021 document has no description about the power saving 421 * control register. Shouldn't we write it? 422 */ 423 PHY_WRITE(sc, 29, 0x29); 424 /* 425 * XXX AR8031 document says the lower 14 bits are reserved and the 426 * default value is 0x36d0. Shouldn't we clear those bits? 427 * I have no document neither L1(F1) nor L2(F2). 428 */ 429 PHY_WRITE(sc, 30, 0); 430 431 if ((sc->mii_mpd_model == MII_MODEL_ATTANSIC_L2) 432 && (sc->mii_mpd_rev == 1)) { 433 /* 434 * On NVIDIA MCP61 with Attansic L2 rev. 1, changing debug 435 * port 0x29's value makes the next PHY read fail with error. 436 * This is observed on ASUS M2N-MX SE Plus. Read any register 437 * to ignore this problem. 438 */ 439 (void)PHY_READ(sc, ATPHY_SCR, ®); 440 } 441 PHY_READ(sc, ATPHY_SCR, ®); 442 /* Enable automatic crossover. */ 443 reg |= ATPHY_SCR_AUTO_X_MODE; 444 /* Disable power down. */ 445 reg &= ~ATPHY_SCR_MAC_PDOWN; 446 /* Enable CRS on Tx. */ 447 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 448 /* Auto correction for reversed cable polarity. */ 449 reg |= ATPHY_SCR_POLARITY_REVERSAL; 450 PHY_WRITE(sc, ATPHY_SCR, reg); 451 452 atphy_mii_phy_auto(sc); 453 454 /* Workaround F1 bug to reset phy. */ 455 PHY_READ(sc, MII_BMCR, ®); 456 reg |= BMCR_RESET; 457 PHY_WRITE(sc, MII_BMCR, reg); 458 459 for (i = 0; i < 1000; i++) { 460 DELAY(1); 461 PHY_READ(sc, MII_BMCR, ®); 462 if ((reg & BMCR_RESET) == 0) 463 break; 464 } 465 466 if (asc->rgmii_tx_internal_delay) { 467 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x05); 468 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_TX_CLK_DLY); 469 } 470 if (asc->rgmii_rx_internal_delay) { 471 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x00); 472 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_RX_CLK_DLY); 473 } 474 } 475 476 static int 477 atphy_mii_phy_auto(struct mii_softc *sc) 478 { 479 uint16_t anar; 480 481 KASSERT(mii_locked(sc->mii_pdata)); 482 483 sc->mii_ticks = 0; 484 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 485 if (sc->mii_flags & MIIF_DOPAUSE) 486 anar |= ANAR_PAUSE_TOWARDS; 487 PHY_WRITE(sc, MII_ANAR, anar); 488 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 489 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 490 GTCR_ADV_1000THDX); 491 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 492 493 return EJUSTRETURN; 494 } 495
Indexes created Thu Oct 23 22:10:10 GMT 2025