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atphy.c revision 1.2.4.2 
      1 /*	$NetBSD: atphy.c,v 1.2.4.2 2009/01/19 13:18:14 skrll Exp $ */
      2 /*	$OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $	*/
      3 
      4 /*-
      5  * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org>
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice unmodified, this list of conditions, and the following
     13  *    disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28  * SUCH DAMAGE.
     29  */
     30 
     31 /*
     32  * Driver for the Attansic F1 10/100/1000 PHY.
     33  */
     34 
     35 #include <sys/cdefs.h>
     36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.2.4.2 2009/01/19 13:18:14 skrll Exp $");
     37 
     38 #include <sys/param.h>
     39 #include <sys/systm.h>
     40 #include <sys/kernel.h>
     41 #include <sys/device.h>
     42 #include <sys/socket.h>
     43 
     44 #include <net/if.h>
     45 #include <net/if_media.h>
     46 
     47 #include <dev/mii/mii.h>
     48 #include <dev/mii/miivar.h>
     49 #include <dev/mii/miidevs.h>
     50 
     51 /* Special Control Register */
     52 #define ATPHY_SCR			0x10
     53 #define ATPHY_SCR_JABBER_DISABLE	0x0001
     54 #define ATPHY_SCR_POLARITY_REVERSAL	0x0002
     55 #define ATPHY_SCR_SQE_TEST		0x0004
     56 #define ATPHY_SCR_MAC_PDOWN		0x0008
     57 #define ATPHY_SCR_CLK125_DISABLE	0x0010
     58 #define ATPHY_SCR_MDI_MANUAL_MODE	0x0000
     59 #define ATPHY_SCR_MDIX_MANUAL_MODE	0x0020
     60 #define ATPHY_SCR_AUTO_X_1000T		0x0040
     61 #define ATPHY_SCR_AUTO_X_MODE		0x0060
     62 #define ATPHY_SCR_10BT_EXT_ENABLE	0x0080
     63 #define ATPHY_SCR_MII_5BIT_ENABLE	0x0100
     64 #define ATPHY_SCR_SCRAMBLER_DISABLE	0x0200
     65 #define ATPHY_SCR_FORCE_LINK_GOOD	0x0400
     66 #define ATPHY_SCR_ASSERT_CRS_ON_TX	0x0800
     67 
     68 /* Special Status Register. */
     69 #define ATPHY_SSR			0x11
     70 #define ATPHY_SSR_SPD_DPLX_RESOLVED	0x0800
     71 #define ATPHY_SSR_DUPLEX		0x2000
     72 #define ATPHY_SSR_SPEED_MASK		0xC000
     73 #define ATPHY_SSR_10MBS			0x0000
     74 #define ATPHY_SSR_100MBS		0x4000
     75 #define ATPHY_SSR_1000MBS		0x8000
     76 
     77 static int atphy_match(device_t, cfdata_t, void *);
     78 static void atphy_attach(device_t, device_t, void *);
     79 
     80 static int atphy_service(struct mii_softc *, struct mii_data *, int);
     81 static void atphy_reset(struct mii_softc *);
     82 static void atphy_status(struct mii_softc *);
     83 static int atphy_mii_phy_auto(struct mii_softc *);
     84 
     85 CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc),
     86 	atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate);
     87 
     88 const struct mii_phy_funcs atphy_funcs = {
     89         atphy_service, atphy_status, atphy_reset,
     90 };
     91 
     92 static const struct mii_phydesc etphys[] = {
     93 	{ MII_OUI_ATHEROS,	MII_MODEL_ATHEROS_F1,
     94 	  MII_STR_ATHEROS_F1 },
     95 	{ 0,			0,
     96 	  NULL },
     97 };
     98 
     99 static int
    100 atphy_match(device_t parent, cfdata_t match, void *aux)
    101 {
    102 	struct mii_attach_args *ma = aux;
    103 
    104 	if (mii_phy_match(ma, etphys) != NULL)
    105 		return 10;
    106 
    107 	return 0;
    108 }
    109 
    110 void
    111 atphy_attach(device_t parent, device_t self, void *aux)
    112 {
    113 	struct mii_softc *sc = device_private(self);
    114 	struct mii_attach_args *ma = aux;
    115 	struct mii_data *mii = ma->mii_data;
    116 	const struct mii_phydesc *mpd;
    117 
    118 	mpd = mii_phy_match(ma, etphys);
    119 	aprint_naive(": Media interface\n");
    120 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    121 
    122 	sc->mii_dev = self;
    123 	sc->mii_inst = mii->mii_instance;
    124 	sc->mii_phy = ma->mii_phyno;
    125 	sc->mii_funcs = &atphy_funcs;
    126 	sc->mii_pdata = mii;
    127 	sc->mii_flags = ma->mii_flags;
    128 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
    129 
    130 	sc->mii_flags |= MIIF_NOLOOP;
    131 
    132 	PHY_RESET(sc);
    133 
    134 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
    135 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    136 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
    137 
    138 	mii_phy_add_media(sc);
    139 }
    140 
    141 int
    142 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    143 {
    144 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    145 	uint16_t anar, bmcr, bmsr;
    146 
    147 	switch (cmd) {
    148 	case MII_POLLSTAT:
    149 		/*
    150 		 * If we're not polling our PHY instance, just return.
    151 		 */
    152 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    153 			return 0;
    154 		break;
    155 
    156 	case MII_MEDIACHG:
    157 		/*
    158 		 * If the media indicates a different PHY instance,
    159 		 * isolate ourselves.
    160 		 */
    161 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    162 			bmcr = PHY_READ(sc, MII_BMCR);
    163 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    164 			return 0;
    165 		}
    166 
    167 		/*
    168 		 * If the interface is not up, don't do anything.
    169 		 */
    170 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    171 			break;
    172 
    173 		bmcr = 0;
    174 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    175 		case IFM_AUTO:
    176 		case IFM_1000_T:
    177 			atphy_mii_phy_auto(sc);
    178 			goto done;
    179 		case IFM_100_TX:
    180 			bmcr = BMCR_S100;
    181 			break;
    182 		case IFM_10_T:
    183 			bmcr = BMCR_S10;
    184 			break;
    185 		case IFM_NONE:
    186 			bmcr = PHY_READ(sc, MII_BMCR);
    187 			/*
    188 			 * XXX
    189 			 * Due to an unknown reason powering down PHY resulted
    190 			 * in unexpected results such as inaccessbility of
    191 			 * hardware of freshly rebooted system. Disable
    192 			 * powering down PHY until I got more information for
    193 			 * Attansic/Atheros PHY hardwares.
    194 			 */
    195 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    196 			goto done;
    197 		default:
    198 			return EINVAL;
    199 		}
    200 
    201 		anar = mii_anar(ife->ifm_media);
    202 		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
    203 			bmcr |= BMCR_FDX;
    204 			/* Enable pause. */
    205 			if (sc->mii_flags & MIIF_DOPAUSE)
    206 				anar |= (3 << 10);
    207 		}
    208 
    209 		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
    210 		    EXTSR_1000THDX)) != 0)
    211 			PHY_WRITE(sc, MII_100T2CR, 0);
    212 		PHY_WRITE(sc, MII_ANAR, anar);
    213 
    214 		/*
    215 		 * Reset the PHY so all changes take effect.
    216 		 */
    217 		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET);
    218 done:
    219 		break;
    220 
    221 	case MII_TICK:
    222 		/*
    223 		 * If we're not currently selected, just return.
    224 		 */
    225 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    226 			return 0;
    227 
    228 		/*
    229 		 * Is the interface even up?
    230 		 */
    231 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    232 			return 0;
    233 
    234 		/*
    235 		 * Only used for autonegotiation.
    236 		 */
    237 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
    238 			sc->mii_ticks = 0;
    239 			break;
    240 		}
    241 
    242 		/*
    243 		 * Check for link.
    244 		 * Read the status register twice; BMSR_LINK is latch-low.
    245 		 */
    246 		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    247 		if (bmsr & BMSR_LINK) {
    248 			sc->mii_ticks = 0;
    249 			break;
    250 		}
    251 
    252 		/* Announce link loss right after it happens. */
    253 		if (sc->mii_ticks++ == 0)
    254 			break;
    255 
    256 		/*
    257 		 * Only retry autonegotiation every mii_anegticks seconds.
    258 		 */
    259 		if (sc->mii_ticks <= sc->mii_anegticks)
    260 			break;
    261 
    262 		sc->mii_ticks = 0;
    263 		atphy_mii_phy_auto(sc);
    264 		break;
    265 	}
    266 
    267 	/* Update the media status. */
    268 	mii_phy_status(sc);
    269 
    270 	/* Callback if something changed. */
    271 	mii_phy_update(sc, cmd);
    272 	return 0;
    273 }
    274 
    275 static void
    276 atphy_status(struct mii_softc *sc)
    277 {
    278 	struct mii_data *mii = sc->mii_pdata;
    279 	uint32_t bmsr, bmcr, gsr, ssr;
    280 
    281 	mii->mii_media_status = IFM_AVALID;
    282 	mii->mii_media_active = IFM_ETHER;
    283 
    284 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    285 	if (bmsr & BMSR_LINK)
    286 		mii->mii_media_status |= IFM_ACTIVE;
    287 
    288 	bmcr = PHY_READ(sc, MII_BMCR);
    289 	if (bmcr & BMCR_ISO) {
    290 		mii->mii_media_active |= IFM_NONE;
    291 		mii->mii_media_status = 0;
    292 		return;
    293 	}
    294 
    295 	if (bmcr & BMCR_LOOP)
    296 		mii->mii_media_active |= IFM_LOOP;
    297 
    298 	ssr = PHY_READ(sc, ATPHY_SSR);
    299 	if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
    300 		/* Erg, still trying, I guess... */
    301 		mii->mii_media_active |= IFM_NONE;
    302 		return;
    303 	}
    304 
    305 	switch (ssr & ATPHY_SSR_SPEED_MASK) {
    306 	case ATPHY_SSR_1000MBS:
    307 		mii->mii_media_active |= IFM_1000_T;
    308 		/*
    309 		 * atphy(4) has a valid link so reset mii_ticks.
    310 		 * Resetting mii_ticks is needed in order to
    311 		 * detect link loss after auto-negotiation.
    312 		 */
    313 		sc->mii_ticks = 0;
    314 		break;
    315 	case ATPHY_SSR_100MBS:
    316 		mii->mii_media_active |= IFM_100_TX;
    317 		sc->mii_ticks = 0;
    318 		break;
    319 	case ATPHY_SSR_10MBS:
    320 		mii->mii_media_active |= IFM_10_T;
    321 		sc->mii_ticks = 0;
    322 		break;
    323 	default:
    324 		mii->mii_media_active |= IFM_NONE;
    325 		return;
    326 	}
    327 
    328 	if (ssr & ATPHY_SSR_DUPLEX)
    329 		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
    330 	else
    331 		mii->mii_media_active |= IFM_HDX;
    332 
    333 	gsr = PHY_READ(sc, MII_100T2SR);
    334 	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
    335 	    gsr & GTSR_MS_RES)
    336 		mii->mii_media_active |= IFM_ETH_MASTER;
    337 }
    338 
    339 static void
    340 atphy_reset(struct mii_softc *sc)
    341 {
    342 	uint32_t reg;
    343 	int i;
    344 
    345 	/* Take PHY out of power down mode. */
    346 	PHY_WRITE(sc, 29, 0x29);
    347 	PHY_WRITE(sc, 30, 0);
    348 
    349 	reg = PHY_READ(sc, ATPHY_SCR);
    350 	/* Enable automatic crossover. */
    351 	reg |= ATPHY_SCR_AUTO_X_MODE;
    352 	/* Disable power down. */
    353 	reg &= ~ATPHY_SCR_MAC_PDOWN;
    354 	/* Enable CRS on Tx. */
    355 	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
    356 	/* Auto correction for reversed cable polarity. */
    357 	reg |= ATPHY_SCR_POLARITY_REVERSAL;
    358 	PHY_WRITE(sc, ATPHY_SCR, reg);
    359 
    360 	/* Workaround F1 bug to reset phy. */
    361 	atphy_mii_phy_auto(sc);
    362 
    363 	for (i = 0; i < 1000; i++) {
    364 		DELAY(1);
    365 		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
    366 			break;
    367 	}
    368 }
    369 
    370 static int
    371 atphy_mii_phy_auto(struct mii_softc *sc)
    372 {
    373 	uint16_t anar;
    374 
    375 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    376 	if (sc->mii_flags & MIIF_DOPAUSE)
    377 		anar |= (3 << 10);
    378 	PHY_WRITE(sc, MII_ANAR, anar);
    379 	if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
    380 		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
    381 		    GTCR_ADV_1000THDX);
    382 	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
    383 
    384 	return EJUSTRETURN;
    385 }
    386