atphy.c revision 1.22.4.2
1 /* $NetBSD: atphy.c,v 1.22.4.2 2020/03/19 19:21:37 martin Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.22.4.2 2020/03/19 19:21:37 martin Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 static int atphy_match(device_t, cfdata_t, void *); 78 static void atphy_attach(device_t, device_t, void *); 79 80 static int atphy_service(struct mii_softc *, struct mii_data *, int); 81 static void atphy_reset(struct mii_softc *); 82 static void atphy_status(struct mii_softc *); 83 static int atphy_mii_phy_auto(struct mii_softc *); 84 static bool atphy_is_gige(const struct mii_phydesc *); 85 86 CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc), 87 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 88 89 const struct mii_phy_funcs atphy_funcs = { 90 atphy_service, atphy_status, atphy_reset, 91 }; 92 93 static const struct mii_phydesc atphys[] = { 94 MII_PHY_DESC(ATTANSIC, L1), 95 MII_PHY_DESC(ATTANSIC, L2), 96 MII_PHY_DESC(ATTANSIC, AR8021), 97 MII_PHY_DESC(ATTANSIC, AR8035), 98 MII_PHY_END, 99 }; 100 101 static bool 102 atphy_is_gige(const struct mii_phydesc *mpd) 103 { 104 switch (mpd->mpd_oui) { 105 case MII_OUI_ATTANSIC: 106 switch (mpd->mpd_model) { 107 case MII_MODEL_ATTANSIC_L2: 108 return false; 109 } 110 } 111 112 return true; 113 } 114 115 static int 116 atphy_match(device_t parent, cfdata_t match, void *aux) 117 { 118 struct mii_attach_args *ma = aux; 119 120 if (mii_phy_match(ma, atphys) != NULL) 121 return 10; 122 123 return 0; 124 } 125 126 void 127 atphy_attach(device_t parent, device_t self, void *aux) 128 { 129 struct mii_softc *sc = device_private(self); 130 struct mii_attach_args *ma = aux; 131 struct mii_data *mii = ma->mii_data; 132 const struct mii_phydesc *mpd; 133 uint16_t bmsr; 134 135 mpd = mii_phy_match(ma, atphys); 136 aprint_naive(": Media interface\n"); 137 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 138 139 sc->mii_dev = self; 140 sc->mii_inst = mii->mii_instance; 141 sc->mii_phy = ma->mii_phyno; 142 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 143 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 144 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 145 sc->mii_funcs = &atphy_funcs; 146 sc->mii_pdata = mii; 147 sc->mii_flags = ma->mii_flags; 148 if (atphy_is_gige(mpd)) 149 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 150 else 151 sc->mii_anegticks = MII_ANEGTICKS; 152 153 sc->mii_flags |= MIIF_NOLOOP; 154 155 PHY_RESET(sc); 156 157 PHY_READ(sc, MII_BMSR, &bmsr); 158 PHY_READ(sc, MII_BMSR, &bmsr); 159 sc->mii_capabilities = bmsr & ma->mii_capmask; 160 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 161 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 162 163 aprint_normal_dev(self, ""); 164 mii_phy_add_media(sc); 165 aprint_normal("\n"); 166 } 167 168 int 169 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 170 { 171 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 172 uint16_t anar, bmcr, bmsr; 173 174 switch (cmd) { 175 case MII_POLLSTAT: 176 /* If we're not polling our PHY instance, just return. */ 177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 178 return 0; 179 break; 180 181 case MII_MEDIACHG: 182 /* 183 * If the media indicates a different PHY instance, 184 * isolate ourselves. 185 */ 186 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 187 PHY_READ(sc, MII_BMCR, &bmcr); 188 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 189 return 0; 190 } 191 192 /* If the interface is not up, don't do anything. */ 193 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 194 break; 195 196 bmcr = 0; 197 switch (IFM_SUBTYPE(ife->ifm_media)) { 198 case IFM_AUTO: 199 case IFM_1000_T: 200 atphy_mii_phy_auto(sc); 201 goto done; 202 case IFM_100_TX: 203 bmcr = BMCR_S100; 204 break; 205 case IFM_10_T: 206 bmcr = BMCR_S10; 207 break; 208 case IFM_NONE: 209 PHY_READ(sc, MII_BMCR, &bmcr); 210 /* 211 * XXX 212 * Due to an unknown reason powering down PHY resulted 213 * in unexpected results such as inaccessibility of 214 * hardware of freshly rebooted system. Disable 215 * powering down PHY until I got more information for 216 * Attansic/Atheros PHY hardwares. 217 */ 218 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 219 goto done; 220 default: 221 return EINVAL; 222 } 223 224 anar = mii_anar(ife); 225 if ((ife->ifm_media & IFM_FDX) != 0) { 226 bmcr |= BMCR_FDX; 227 /* Enable pause. */ 228 if (sc->mii_flags & MIIF_DOPAUSE) 229 anar |= ANAR_PAUSE_TOWARDS; 230 } 231 232 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 233 EXTSR_1000THDX)) != 0) 234 PHY_WRITE(sc, MII_100T2CR, 0); 235 PHY_WRITE(sc, MII_ANAR, anar); 236 237 /* Start autonegotiation. */ 238 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 239 done: 240 break; 241 242 case MII_TICK: 243 /* If we're not currently selected, just return. */ 244 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 245 return 0; 246 247 /* Is the interface even up? */ 248 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 249 return 0; 250 251 /* Only used for autonegotiation. */ 252 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 253 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 254 sc->mii_ticks = 0; 255 break; 256 } 257 258 /* 259 * Check for link. 260 * Read the status register twice; BMSR_LINK is latch-low. 261 */ 262 PHY_READ(sc, MII_BMSR, &bmsr); 263 PHY_READ(sc, MII_BMSR, &bmsr); 264 if (bmsr & BMSR_LINK) { 265 sc->mii_ticks = 0; 266 break; 267 } 268 269 /* Announce link loss right after it happens. */ 270 if (sc->mii_ticks++ == 0) 271 break; 272 273 /* Only retry autonegotiation every mii_anegticks seconds. */ 274 if (sc->mii_ticks <= sc->mii_anegticks) 275 break; 276 277 atphy_mii_phy_auto(sc); 278 break; 279 } 280 281 /* Update the media status. */ 282 mii_phy_status(sc); 283 284 /* Callback if something changed. */ 285 mii_phy_update(sc, cmd); 286 return 0; 287 } 288 289 static void 290 atphy_status(struct mii_softc *sc) 291 { 292 struct mii_data *mii = sc->mii_pdata; 293 uint16_t bmsr, bmcr, gsr, ssr; 294 295 mii->mii_media_status = IFM_AVALID; 296 mii->mii_media_active = IFM_ETHER; 297 298 PHY_READ(sc, MII_BMSR, &bmsr); 299 PHY_READ(sc, MII_BMSR, &bmsr); 300 if (bmsr & BMSR_LINK) 301 mii->mii_media_status |= IFM_ACTIVE; 302 303 PHY_READ(sc, MII_BMCR, &bmcr); 304 if (bmcr & BMCR_ISO) { 305 mii->mii_media_active |= IFM_NONE; 306 mii->mii_media_status = 0; 307 return; 308 } 309 310 if (bmcr & BMCR_LOOP) 311 mii->mii_media_active |= IFM_LOOP; 312 313 PHY_READ(sc, ATPHY_SSR, &ssr); 314 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 315 /* Erg, still trying, I guess... */ 316 mii->mii_media_active |= IFM_NONE; 317 return; 318 } 319 320 switch (ssr & ATPHY_SSR_SPEED_MASK) { 321 case ATPHY_SSR_1000MBS: 322 mii->mii_media_active |= IFM_1000_T; 323 /* 324 * atphy(4) has a valid link so reset mii_ticks. 325 * Resetting mii_ticks is needed in order to 326 * detect link loss after auto-negotiation. 327 */ 328 sc->mii_ticks = 0; 329 break; 330 case ATPHY_SSR_100MBS: 331 mii->mii_media_active |= IFM_100_TX; 332 sc->mii_ticks = 0; 333 break; 334 case ATPHY_SSR_10MBS: 335 mii->mii_media_active |= IFM_10_T; 336 sc->mii_ticks = 0; 337 break; 338 default: 339 mii->mii_media_active |= IFM_NONE; 340 return; 341 } 342 343 if (ssr & ATPHY_SSR_DUPLEX) 344 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 345 else 346 mii->mii_media_active |= IFM_HDX; 347 348 PHY_READ(sc, MII_100T2SR, &gsr); 349 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 350 gsr & GTSR_MS_RES) 351 mii->mii_media_active |= IFM_ETH_MASTER; 352 } 353 354 static void 355 atphy_reset(struct mii_softc *sc) 356 { 357 uint16_t reg; 358 int i; 359 360 /* 361 * Take PHY out of power down mode. 362 * 363 * XXX AR8021 document has no description about the power saving 364 * control register. Shouldn't we write it? 365 */ 366 PHY_WRITE(sc, 29, 0x29); 367 /* 368 * XXX AR8031 document says the lower 14 bits are reserved and the 369 * default value is 0x36d0. Shouldn't we clear those bits? 370 * I have no document neither L1(F1) nor L2(F2). 371 */ 372 PHY_WRITE(sc, 30, 0); 373 374 if ((sc->mii_mpd_model == MII_MODEL_ATTANSIC_L2) 375 && (sc->mii_mpd_rev == 1)) { 376 /* 377 * On NVIDIA MCP61 with Attansic L2 rev. 1, changing debug 378 * port 0x29's value makes the next PHY read fail with error. 379 * This is observed on ASUS M2N-MX SE Plus. Read any register 380 * to ignore this problem. 381 */ 382 (void)PHY_READ(sc, ATPHY_SCR, ®); 383 } 384 PHY_READ(sc, ATPHY_SCR, ®); 385 /* Enable automatic crossover. */ 386 reg |= ATPHY_SCR_AUTO_X_MODE; 387 /* Disable power down. */ 388 reg &= ~ATPHY_SCR_MAC_PDOWN; 389 /* Enable CRS on Tx. */ 390 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 391 /* Auto correction for reversed cable polarity. */ 392 reg |= ATPHY_SCR_POLARITY_REVERSAL; 393 PHY_WRITE(sc, ATPHY_SCR, reg); 394 395 atphy_mii_phy_auto(sc); 396 397 /* Workaround F1 bug to reset phy. */ 398 PHY_READ(sc, MII_BMCR, ®); 399 reg |= BMCR_RESET; 400 PHY_WRITE(sc, MII_BMCR, reg); 401 402 for (i = 0; i < 1000; i++) { 403 DELAY(1); 404 PHY_READ(sc, MII_BMCR, ®); 405 if ((reg & BMCR_RESET) == 0) 406 break; 407 } 408 } 409 410 static int 411 atphy_mii_phy_auto(struct mii_softc *sc) 412 { 413 uint16_t anar; 414 415 sc->mii_ticks = 0; 416 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 417 if (sc->mii_flags & MIIF_DOPAUSE) 418 anar |= ANAR_PAUSE_TOWARDS; 419 PHY_WRITE(sc, MII_ANAR, anar); 420 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 421 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 422 GTCR_ADV_1000THDX); 423 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 424 425 return EJUSTRETURN; 426 } 427
Indexes created Mon Oct 27 08:10:08 GMT 2025