atphy.c revision 1.25
1 /* $NetBSD: atphy.c,v 1.25 2019/11/20 08:50:59 msaitoh Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.25 2019/11/20 08:50:59 msaitoh Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 #define ATPHY_DEBUG_PORT_ADDR 0x1d 78 #define ATPHY_DEBUG_PORT_DATA 0x1e 79 #define ATPHY_RGMII_RX_CLK_DLY __BIT(15) 80 #define ATPHY_RGMII_TX_CLK_DLY __BIT(8) 81 82 static int atphy_match(device_t, cfdata_t, void *); 83 static void atphy_attach(device_t, device_t, void *); 84 85 static int atphy_service(struct mii_softc *, struct mii_data *, int); 86 static void atphy_reset(struct mii_softc *); 87 static void atphy_status(struct mii_softc *); 88 static int atphy_mii_phy_auto(struct mii_softc *); 89 static bool atphy_is_gige(const struct mii_phydesc *); 90 91 struct atphy_softc { 92 struct mii_softc mii_sc; 93 int mii_clk_25m; 94 bool rgmii_tx_internal_delay; 95 bool rgmii_rx_internal_delay; 96 }; 97 98 CFATTACH_DECL_NEW(atphy, sizeof(struct atphy_softc), 99 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 100 101 const struct mii_phy_funcs atphy_funcs = { 102 atphy_service, atphy_status, atphy_reset, 103 }; 104 105 static const struct mii_phydesc atphys[] = { 106 MII_PHY_DESC(ATHEROS, F1), 107 MII_PHY_DESC(ATTANSIC, L1), 108 MII_PHY_DESC(ATTANSIC, L2), 109 MII_PHY_DESC(ATTANSIC, AR8021), 110 MII_PHY_DESC(ATTANSIC, AR8035), 111 MII_PHY_END, 112 }; 113 114 static void 115 atphy_clk_25m(struct atphy_softc *asc) 116 { 117 struct mii_softc *sc = &asc->mii_sc; 118 struct { 119 uint32_t hz; 120 uint16_t data; 121 } select_clk[] = { 122 { 25000000, 0x0 }, 123 { 50000000, 0x1 }, 124 { 62500000, 0x2 }, 125 { 125000000, 0x3 } 126 }; 127 uint16_t data = 0; 128 uint16_t reg = 0; 129 130 for (int i = 0; i < __arraycount(select_clk); i++) { 131 if (asc->mii_clk_25m <= select_clk[i].hz) 132 data = select_clk[i].data; 133 } 134 135 PHY_WRITE(sc, 0x0d, 0x0007); 136 PHY_WRITE(sc, 0x0e, 0x8016); 137 PHY_WRITE(sc, 0x0d, 0x4007); 138 PHY_READ(sc, 0x0e, ®); 139 PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3))); 140 } 141 142 143 static bool 144 atphy_is_gige(const struct mii_phydesc *mpd) 145 { 146 switch (mpd->mpd_oui) { 147 case MII_OUI_ATTANSIC: 148 switch (mpd->mpd_model) { 149 case MII_MODEL_ATTANSIC_L2: 150 return false; 151 } 152 } 153 154 return true; 155 } 156 157 static int 158 atphy_match(device_t parent, cfdata_t match, void *aux) 159 { 160 struct mii_attach_args *ma = aux; 161 162 if (mii_phy_match(ma, atphys) != NULL) 163 return 10; 164 165 return 0; 166 } 167 168 void 169 atphy_attach(device_t parent, device_t self, void *aux) 170 { 171 struct atphy_softc *asc = device_private(self); 172 prop_dictionary_t parent_prop = device_properties(parent); 173 prop_dictionary_t prop = device_properties(self); 174 struct mii_softc *sc = &asc->mii_sc; 175 struct mii_attach_args *ma = aux; 176 struct mii_data *mii = ma->mii_data; 177 const struct mii_phydesc *mpd; 178 uint16_t bmsr; 179 180 mpd = mii_phy_match(ma, atphys); 181 aprint_naive(": Media interface\n"); 182 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 183 184 sc->mii_dev = self; 185 sc->mii_inst = mii->mii_instance; 186 sc->mii_phy = ma->mii_phyno; 187 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 188 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 189 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 190 sc->mii_funcs = &atphy_funcs; 191 sc->mii_pdata = mii; 192 sc->mii_flags = ma->mii_flags; 193 if (atphy_is_gige(mpd)) 194 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 195 else 196 sc->mii_anegticks = MII_ANEGTICKS; 197 198 sc->mii_flags |= MIIF_NOLOOP; 199 200 prop_dictionary_get_bool(parent_prop, "tx_internal_delay", &asc->rgmii_tx_internal_delay); 201 prop_dictionary_get_bool(parent_prop, "rx_internal_delay", &asc->rgmii_rx_internal_delay); 202 203 prop_dictionary_get_uint32(prop, "clk_25m", &asc->mii_clk_25m); 204 if (asc->mii_clk_25m != 0) 205 atphy_clk_25m(asc); 206 207 PHY_RESET(sc); 208 209 PHY_READ(sc, MII_BMSR, &bmsr); 210 PHY_READ(sc, MII_BMSR, &bmsr); 211 sc->mii_capabilities = bmsr & ma->mii_capmask; 212 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 213 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 214 215 aprint_normal_dev(self, ""); 216 mii_phy_add_media(sc); 217 aprint_normal("\n"); 218 } 219 220 int 221 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 222 { 223 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 224 uint16_t anar, bmcr, bmsr; 225 226 switch (cmd) { 227 case MII_POLLSTAT: 228 /* If we're not polling our PHY instance, just return. */ 229 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 230 return 0; 231 break; 232 233 case MII_MEDIACHG: 234 /* 235 * If the media indicates a different PHY instance, 236 * isolate ourselves. 237 */ 238 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 239 PHY_READ(sc, MII_BMCR, &bmcr); 240 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 241 return 0; 242 } 243 244 /* If the interface is not up, don't do anything. */ 245 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 246 break; 247 248 bmcr = 0; 249 switch (IFM_SUBTYPE(ife->ifm_media)) { 250 case IFM_AUTO: 251 case IFM_1000_T: 252 atphy_mii_phy_auto(sc); 253 goto done; 254 case IFM_100_TX: 255 bmcr = BMCR_S100; 256 break; 257 case IFM_10_T: 258 bmcr = BMCR_S10; 259 break; 260 case IFM_NONE: 261 PHY_READ(sc, MII_BMCR, &bmcr); 262 /* 263 * XXX 264 * Due to an unknown reason powering down PHY resulted 265 * in unexpected results such as inaccessibility of 266 * hardware of freshly rebooted system. Disable 267 * powering down PHY until I got more information for 268 * Attansic/Atheros PHY hardwares. 269 */ 270 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 271 goto done; 272 default: 273 return EINVAL; 274 } 275 276 anar = mii_anar(ife); 277 if ((ife->ifm_media & IFM_FDX) != 0) { 278 bmcr |= BMCR_FDX; 279 /* Enable pause. */ 280 if (sc->mii_flags & MIIF_DOPAUSE) 281 anar |= ANAR_PAUSE_TOWARDS; 282 } 283 284 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 285 EXTSR_1000THDX)) != 0) 286 PHY_WRITE(sc, MII_100T2CR, 0); 287 PHY_WRITE(sc, MII_ANAR, anar); 288 289 /* Start autonegotiation. */ 290 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 291 done: 292 break; 293 294 case MII_TICK: 295 /* If we're not currently selected, just return. */ 296 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 297 return 0; 298 299 /* Is the interface even up? */ 300 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 301 return 0; 302 303 /* Only used for autonegotiation. */ 304 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 305 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 306 sc->mii_ticks = 0; 307 break; 308 } 309 310 /* 311 * Check for link. 312 * Read the status register twice; BMSR_LINK is latch-low. 313 */ 314 PHY_READ(sc, MII_BMSR, &bmsr); 315 PHY_READ(sc, MII_BMSR, &bmsr); 316 if (bmsr & BMSR_LINK) { 317 sc->mii_ticks = 0; 318 break; 319 } 320 321 /* Announce link loss right after it happens. */ 322 if (sc->mii_ticks++ == 0) 323 break; 324 325 /* Only retry autonegotiation every mii_anegticks seconds. */ 326 if (sc->mii_ticks <= sc->mii_anegticks) 327 break; 328 329 atphy_mii_phy_auto(sc); 330 break; 331 } 332 333 /* Update the media status. */ 334 mii_phy_status(sc); 335 336 /* Callback if something changed. */ 337 mii_phy_update(sc, cmd); 338 return 0; 339 } 340 341 static void 342 atphy_status(struct mii_softc *sc) 343 { 344 struct mii_data *mii = sc->mii_pdata; 345 uint16_t bmsr, bmcr, gsr, ssr; 346 347 mii->mii_media_status = IFM_AVALID; 348 mii->mii_media_active = IFM_ETHER; 349 350 PHY_READ(sc, MII_BMSR, &bmsr); 351 PHY_READ(sc, MII_BMSR, &bmsr); 352 if (bmsr & BMSR_LINK) 353 mii->mii_media_status |= IFM_ACTIVE; 354 355 PHY_READ(sc, MII_BMCR, &bmcr); 356 if (bmcr & BMCR_ISO) { 357 mii->mii_media_active |= IFM_NONE; 358 mii->mii_media_status = 0; 359 return; 360 } 361 362 if (bmcr & BMCR_LOOP) 363 mii->mii_media_active |= IFM_LOOP; 364 365 PHY_READ(sc, ATPHY_SSR, &ssr); 366 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 367 /* Erg, still trying, I guess... */ 368 mii->mii_media_active |= IFM_NONE; 369 return; 370 } 371 372 switch (ssr & ATPHY_SSR_SPEED_MASK) { 373 case ATPHY_SSR_1000MBS: 374 mii->mii_media_active |= IFM_1000_T; 375 /* 376 * atphy(4) has a valid link so reset mii_ticks. 377 * Resetting mii_ticks is needed in order to 378 * detect link loss after auto-negotiation. 379 */ 380 sc->mii_ticks = 0; 381 break; 382 case ATPHY_SSR_100MBS: 383 mii->mii_media_active |= IFM_100_TX; 384 sc->mii_ticks = 0; 385 break; 386 case ATPHY_SSR_10MBS: 387 mii->mii_media_active |= IFM_10_T; 388 sc->mii_ticks = 0; 389 break; 390 default: 391 mii->mii_media_active |= IFM_NONE; 392 return; 393 } 394 395 if (ssr & ATPHY_SSR_DUPLEX) 396 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 397 else 398 mii->mii_media_active |= IFM_HDX; 399 400 PHY_READ(sc, MII_100T2SR, &gsr); 401 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 402 gsr & GTSR_MS_RES) 403 mii->mii_media_active |= IFM_ETH_MASTER; 404 } 405 406 static void 407 atphy_reset(struct mii_softc *sc) 408 { 409 struct atphy_softc *asc = (struct atphy_softc *)sc; 410 uint16_t reg; 411 int i; 412 413 /* Take PHY out of power down mode. */ 414 PHY_WRITE(sc, 29, 0x29); 415 PHY_WRITE(sc, 30, 0); 416 417 PHY_READ(sc, ATPHY_SCR, ®); 418 /* Enable automatic crossover. */ 419 reg |= ATPHY_SCR_AUTO_X_MODE; 420 /* Disable power down. */ 421 reg &= ~ATPHY_SCR_MAC_PDOWN; 422 /* Enable CRS on Tx. */ 423 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 424 /* Auto correction for reversed cable polarity. */ 425 reg |= ATPHY_SCR_POLARITY_REVERSAL; 426 PHY_WRITE(sc, ATPHY_SCR, reg); 427 428 atphy_mii_phy_auto(sc); 429 430 /* Workaround F1 bug to reset phy. */ 431 PHY_READ(sc, MII_BMCR, ®); 432 reg |= BMCR_RESET; 433 PHY_WRITE(sc, MII_BMCR, reg); 434 435 for (i = 0; i < 1000; i++) { 436 DELAY(1); 437 PHY_READ(sc, MII_BMCR, ®); 438 if ((reg & BMCR_RESET) == 0) 439 break; 440 } 441 442 if (asc->rgmii_tx_internal_delay) { 443 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x05); 444 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_TX_CLK_DLY); 445 } 446 if (asc->rgmii_rx_internal_delay) { 447 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x00); 448 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_RX_CLK_DLY); 449 } 450 } 451 452 static int 453 atphy_mii_phy_auto(struct mii_softc *sc) 454 { 455 uint16_t anar; 456 457 sc->mii_ticks = 0; 458 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 459 if (sc->mii_flags & MIIF_DOPAUSE) 460 anar |= ANAR_PAUSE_TOWARDS; 461 PHY_WRITE(sc, MII_ANAR, anar); 462 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 463 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 464 GTCR_ADV_1000THDX); 465 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 466 467 return EJUSTRETURN; 468 } 469
Indexes created Sun Oct 26 13:09:57 GMT 2025