atphy.c revision 1.26
1 /* $NetBSD: atphy.c,v 1.26 2019/11/27 10:19:20 msaitoh Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.26 2019/11/27 10:19:20 msaitoh Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 #define ATPHY_DEBUG_PORT_ADDR 0x1d 78 #define ATPHY_DEBUG_PORT_DATA 0x1e 79 #define ATPHY_RGMII_RX_CLK_DLY __BIT(15) 80 #define ATPHY_RGMII_TX_CLK_DLY __BIT(8) 81 82 static int atphy_match(device_t, cfdata_t, void *); 83 static void atphy_attach(device_t, device_t, void *); 84 85 static int atphy_service(struct mii_softc *, struct mii_data *, int); 86 static void atphy_reset(struct mii_softc *); 87 static void atphy_status(struct mii_softc *); 88 static int atphy_mii_phy_auto(struct mii_softc *); 89 static bool atphy_is_gige(const struct mii_phydesc *); 90 91 struct atphy_softc { 92 struct mii_softc mii_sc; 93 int mii_clk_25m; 94 bool rgmii_tx_internal_delay; 95 bool rgmii_rx_internal_delay; 96 }; 97 98 CFATTACH_DECL_NEW(atphy, sizeof(struct atphy_softc), 99 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 100 101 const struct mii_phy_funcs atphy_funcs = { 102 atphy_service, atphy_status, atphy_reset, 103 }; 104 105 static const struct mii_phydesc atphys[] = { 106 MII_PHY_DESC(ATHEROS, F1), 107 MII_PHY_DESC(ATTANSIC, L1), 108 MII_PHY_DESC(ATTANSIC, L2), 109 MII_PHY_DESC(ATTANSIC, AR8021), 110 MII_PHY_DESC(ATTANSIC, AR8035), 111 MII_PHY_END, 112 }; 113 114 static void 115 atphy_clk_25m(struct atphy_softc *asc) 116 { 117 struct mii_softc *sc = &asc->mii_sc; 118 struct { 119 uint32_t hz; 120 uint16_t data; 121 } select_clk[] = { 122 { 25000000, 0x0 }, 123 { 50000000, 0x1 }, 124 { 62500000, 0x2 }, 125 { 125000000, 0x3 } 126 }; 127 uint16_t data = 0; 128 uint16_t reg = 0; 129 130 for (int i = 0; i < __arraycount(select_clk); i++) { 131 if (asc->mii_clk_25m <= select_clk[i].hz) 132 data = select_clk[i].data; 133 } 134 135 PHY_WRITE(sc, 0x0d, 0x0007); 136 PHY_WRITE(sc, 0x0e, 0x8016); 137 PHY_WRITE(sc, 0x0d, 0x4007); 138 PHY_READ(sc, 0x0e, ®); 139 PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3))); 140 } 141 142 143 static bool 144 atphy_is_gige(const struct mii_phydesc *mpd) 145 { 146 switch (mpd->mpd_oui) { 147 case MII_OUI_ATTANSIC: 148 switch (mpd->mpd_model) { 149 case MII_MODEL_ATTANSIC_L2: 150 return false; 151 } 152 } 153 154 return true; 155 } 156 157 static int 158 atphy_match(device_t parent, cfdata_t match, void *aux) 159 { 160 struct mii_attach_args *ma = aux; 161 162 if (mii_phy_match(ma, atphys) != NULL) 163 return 10; 164 165 return 0; 166 } 167 168 void 169 atphy_attach(device_t parent, device_t self, void *aux) 170 { 171 struct atphy_softc *asc = device_private(self); 172 prop_dictionary_t parent_prop = device_properties(parent); 173 prop_dictionary_t prop = device_properties(self); 174 struct mii_softc *sc = &asc->mii_sc; 175 struct mii_attach_args *ma = aux; 176 struct mii_data *mii = ma->mii_data; 177 const struct mii_phydesc *mpd; 178 uint16_t bmsr; 179 180 mpd = mii_phy_match(ma, atphys); 181 aprint_naive(": Media interface\n"); 182 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 183 184 sc->mii_dev = self; 185 sc->mii_inst = mii->mii_instance; 186 sc->mii_phy = ma->mii_phyno; 187 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 188 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 189 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 190 sc->mii_funcs = &atphy_funcs; 191 sc->mii_pdata = mii; 192 sc->mii_flags = ma->mii_flags; 193 sc->mii_flags |= MIIF_NOLOOP; 194 195 prop_dictionary_get_bool(parent_prop, "tx_internal_delay", &asc->rgmii_tx_internal_delay); 196 prop_dictionary_get_bool(parent_prop, "rx_internal_delay", &asc->rgmii_rx_internal_delay); 197 198 prop_dictionary_get_uint32(prop, "clk_25m", &asc->mii_clk_25m); 199 if (asc->mii_clk_25m != 0) 200 atphy_clk_25m(asc); 201 202 PHY_RESET(sc); 203 204 PHY_READ(sc, MII_BMSR, &bmsr); 205 PHY_READ(sc, MII_BMSR, &bmsr); 206 sc->mii_capabilities = bmsr & ma->mii_capmask; 207 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 208 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 209 210 mii_phy_add_media(sc); 211 } 212 213 int 214 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 215 { 216 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 217 uint16_t anar, bmcr, bmsr; 218 219 switch (cmd) { 220 case MII_POLLSTAT: 221 /* If we're not polling our PHY instance, just return. */ 222 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 223 return 0; 224 break; 225 226 case MII_MEDIACHG: 227 /* 228 * If the media indicates a different PHY instance, 229 * isolate ourselves. 230 */ 231 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 232 PHY_READ(sc, MII_BMCR, &bmcr); 233 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 234 return 0; 235 } 236 237 /* If the interface is not up, don't do anything. */ 238 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 239 break; 240 241 bmcr = 0; 242 switch (IFM_SUBTYPE(ife->ifm_media)) { 243 case IFM_AUTO: 244 case IFM_1000_T: 245 atphy_mii_phy_auto(sc); 246 goto done; 247 case IFM_100_TX: 248 bmcr = BMCR_S100; 249 break; 250 case IFM_10_T: 251 bmcr = BMCR_S10; 252 break; 253 case IFM_NONE: 254 PHY_READ(sc, MII_BMCR, &bmcr); 255 /* 256 * XXX 257 * Due to an unknown reason powering down PHY resulted 258 * in unexpected results such as inaccessibility of 259 * hardware of freshly rebooted system. Disable 260 * powering down PHY until I got more information for 261 * Attansic/Atheros PHY hardwares. 262 */ 263 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 264 goto done; 265 default: 266 return EINVAL; 267 } 268 269 anar = mii_anar(ife); 270 if ((ife->ifm_media & IFM_FDX) != 0) { 271 bmcr |= BMCR_FDX; 272 /* Enable pause. */ 273 if (sc->mii_flags & MIIF_DOPAUSE) 274 anar |= ANAR_PAUSE_TOWARDS; 275 } 276 277 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 278 EXTSR_1000THDX)) != 0) 279 PHY_WRITE(sc, MII_100T2CR, 0); 280 PHY_WRITE(sc, MII_ANAR, anar); 281 282 /* Start autonegotiation. */ 283 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 284 done: 285 break; 286 287 case MII_TICK: 288 /* If we're not currently selected, just return. */ 289 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 290 return 0; 291 292 /* Is the interface even up? */ 293 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 294 return 0; 295 296 /* Only used for autonegotiation. */ 297 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 298 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 299 sc->mii_ticks = 0; 300 break; 301 } 302 303 /* 304 * Check for link. 305 * Read the status register twice; BMSR_LINK is latch-low. 306 */ 307 PHY_READ(sc, MII_BMSR, &bmsr); 308 PHY_READ(sc, MII_BMSR, &bmsr); 309 if (bmsr & BMSR_LINK) { 310 sc->mii_ticks = 0; 311 break; 312 } 313 314 /* Announce link loss right after it happens. */ 315 if (sc->mii_ticks++ == 0) 316 break; 317 318 /* Only retry autonegotiation every mii_anegticks seconds. */ 319 if (sc->mii_ticks <= sc->mii_anegticks) 320 break; 321 322 atphy_mii_phy_auto(sc); 323 break; 324 } 325 326 /* Update the media status. */ 327 mii_phy_status(sc); 328 329 /* Callback if something changed. */ 330 mii_phy_update(sc, cmd); 331 return 0; 332 } 333 334 static void 335 atphy_status(struct mii_softc *sc) 336 { 337 struct mii_data *mii = sc->mii_pdata; 338 uint16_t bmsr, bmcr, gsr, ssr; 339 340 mii->mii_media_status = IFM_AVALID; 341 mii->mii_media_active = IFM_ETHER; 342 343 PHY_READ(sc, MII_BMSR, &bmsr); 344 PHY_READ(sc, MII_BMSR, &bmsr); 345 if (bmsr & BMSR_LINK) 346 mii->mii_media_status |= IFM_ACTIVE; 347 348 PHY_READ(sc, MII_BMCR, &bmcr); 349 if (bmcr & BMCR_ISO) { 350 mii->mii_media_active |= IFM_NONE; 351 mii->mii_media_status = 0; 352 return; 353 } 354 355 if (bmcr & BMCR_LOOP) 356 mii->mii_media_active |= IFM_LOOP; 357 358 PHY_READ(sc, ATPHY_SSR, &ssr); 359 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 360 /* Erg, still trying, I guess... */ 361 mii->mii_media_active |= IFM_NONE; 362 return; 363 } 364 365 switch (ssr & ATPHY_SSR_SPEED_MASK) { 366 case ATPHY_SSR_1000MBS: 367 mii->mii_media_active |= IFM_1000_T; 368 /* 369 * atphy(4) has a valid link so reset mii_ticks. 370 * Resetting mii_ticks is needed in order to 371 * detect link loss after auto-negotiation. 372 */ 373 sc->mii_ticks = 0; 374 break; 375 case ATPHY_SSR_100MBS: 376 mii->mii_media_active |= IFM_100_TX; 377 sc->mii_ticks = 0; 378 break; 379 case ATPHY_SSR_10MBS: 380 mii->mii_media_active |= IFM_10_T; 381 sc->mii_ticks = 0; 382 break; 383 default: 384 mii->mii_media_active |= IFM_NONE; 385 return; 386 } 387 388 if (ssr & ATPHY_SSR_DUPLEX) 389 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 390 else 391 mii->mii_media_active |= IFM_HDX; 392 393 PHY_READ(sc, MII_100T2SR, &gsr); 394 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 395 gsr & GTSR_MS_RES) 396 mii->mii_media_active |= IFM_ETH_MASTER; 397 } 398 399 static void 400 atphy_reset(struct mii_softc *sc) 401 { 402 struct atphy_softc *asc = (struct atphy_softc *)sc; 403 uint16_t reg; 404 int i; 405 406 /* Take PHY out of power down mode. */ 407 PHY_WRITE(sc, 29, 0x29); 408 PHY_WRITE(sc, 30, 0); 409 410 PHY_READ(sc, ATPHY_SCR, ®); 411 /* Enable automatic crossover. */ 412 reg |= ATPHY_SCR_AUTO_X_MODE; 413 /* Disable power down. */ 414 reg &= ~ATPHY_SCR_MAC_PDOWN; 415 /* Enable CRS on Tx. */ 416 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 417 /* Auto correction for reversed cable polarity. */ 418 reg |= ATPHY_SCR_POLARITY_REVERSAL; 419 PHY_WRITE(sc, ATPHY_SCR, reg); 420 421 atphy_mii_phy_auto(sc); 422 423 /* Workaround F1 bug to reset phy. */ 424 PHY_READ(sc, MII_BMCR, ®); 425 reg |= BMCR_RESET; 426 PHY_WRITE(sc, MII_BMCR, reg); 427 428 for (i = 0; i < 1000; i++) { 429 DELAY(1); 430 PHY_READ(sc, MII_BMCR, ®); 431 if ((reg & BMCR_RESET) == 0) 432 break; 433 } 434 435 if (asc->rgmii_tx_internal_delay) { 436 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x05); 437 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_TX_CLK_DLY); 438 } 439 if (asc->rgmii_rx_internal_delay) { 440 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x00); 441 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_RX_CLK_DLY); 442 } 443 } 444 445 static int 446 atphy_mii_phy_auto(struct mii_softc *sc) 447 { 448 uint16_t anar; 449 450 sc->mii_ticks = 0; 451 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 452 if (sc->mii_flags & MIIF_DOPAUSE) 453 anar |= ANAR_PAUSE_TOWARDS; 454 PHY_WRITE(sc, MII_ANAR, anar); 455 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 456 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 457 GTCR_ADV_1000THDX); 458 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 459 460 return EJUSTRETURN; 461 } 462
Indexes created Sat Nov 01 05:10:12 GMT 2025