atphy.c revision 1.28
1 /* $NetBSD: atphy.c,v 1.28 2020/03/13 04:44:34 msaitoh Exp $ */ 2 /* $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the Attansic F1 10/100/1000 PHY. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.28 2020/03/13 04:44:34 msaitoh Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 #include <dev/mii/miidevs.h> 50 51 /* Special Control Register */ 52 #define ATPHY_SCR 0x10 53 #define ATPHY_SCR_JABBER_DISABLE 0x0001 54 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 55 #define ATPHY_SCR_SQE_TEST 0x0004 56 #define ATPHY_SCR_MAC_PDOWN 0x0008 57 #define ATPHY_SCR_CLK125_DISABLE 0x0010 58 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 59 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 60 #define ATPHY_SCR_AUTO_X_1000T 0x0040 61 #define ATPHY_SCR_AUTO_X_MODE 0x0060 62 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 63 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 64 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 65 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 66 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 67 68 /* Special Status Register. */ 69 #define ATPHY_SSR 0x11 70 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 71 #define ATPHY_SSR_DUPLEX 0x2000 72 #define ATPHY_SSR_SPEED_MASK 0xC000 73 #define ATPHY_SSR_10MBS 0x0000 74 #define ATPHY_SSR_100MBS 0x4000 75 #define ATPHY_SSR_1000MBS 0x8000 76 77 #define ATPHY_DEBUG_PORT_ADDR 0x1d 78 #define ATPHY_DEBUG_PORT_DATA 0x1e 79 #define ATPHY_RGMII_RX_CLK_DLY __BIT(15) 80 #define ATPHY_RGMII_TX_CLK_DLY __BIT(8) 81 82 static int atphy_match(device_t, cfdata_t, void *); 83 static void atphy_attach(device_t, device_t, void *); 84 85 static int atphy_service(struct mii_softc *, struct mii_data *, int); 86 static void atphy_reset(struct mii_softc *); 87 static void atphy_status(struct mii_softc *); 88 static int atphy_mii_phy_auto(struct mii_softc *); 89 static bool atphy_is_gige(const struct mii_phydesc *); 90 91 struct atphy_softc { 92 struct mii_softc mii_sc; 93 int mii_clk_25m; 94 bool rgmii_tx_internal_delay; 95 bool rgmii_rx_internal_delay; 96 }; 97 98 CFATTACH_DECL_NEW(atphy, sizeof(struct atphy_softc), 99 atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate); 100 101 const struct mii_phy_funcs atphy_funcs = { 102 atphy_service, atphy_status, atphy_reset, 103 }; 104 105 static const struct mii_phydesc atphys[] = { 106 MII_PHY_DESC(ATTANSIC, L1), 107 MII_PHY_DESC(ATTANSIC, L2), 108 MII_PHY_DESC(ATTANSIC, AR8021), 109 MII_PHY_DESC(ATTANSIC, AR8035), 110 MII_PHY_END, 111 }; 112 113 static void 114 atphy_clk_25m(struct atphy_softc *asc) 115 { 116 struct mii_softc *sc = &asc->mii_sc; 117 struct { 118 uint32_t hz; 119 uint16_t data; 120 } select_clk[] = { 121 { 25000000, 0x0 }, 122 { 50000000, 0x1 }, 123 { 62500000, 0x2 }, 124 { 125000000, 0x3 } 125 }; 126 uint16_t data = 0; 127 uint16_t reg = 0; 128 129 for (int i = 0; i < __arraycount(select_clk); i++) { 130 if (asc->mii_clk_25m <= select_clk[i].hz) 131 data = select_clk[i].data; 132 } 133 134 PHY_WRITE(sc, 0x0d, 0x0007); 135 PHY_WRITE(sc, 0x0e, 0x8016); 136 PHY_WRITE(sc, 0x0d, 0x4007); 137 PHY_READ(sc, 0x0e, ®); 138 PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3))); 139 } 140 141 142 static bool 143 atphy_is_gige(const struct mii_phydesc *mpd) 144 { 145 switch (mpd->mpd_oui) { 146 case MII_OUI_ATTANSIC: 147 switch (mpd->mpd_model) { 148 case MII_MODEL_ATTANSIC_L2: 149 return false; 150 } 151 } 152 153 return true; 154 } 155 156 static int 157 atphy_match(device_t parent, cfdata_t match, void *aux) 158 { 159 struct mii_attach_args *ma = aux; 160 161 if (mii_phy_match(ma, atphys) != NULL) 162 return 10; 163 164 return 0; 165 } 166 167 void 168 atphy_attach(device_t parent, device_t self, void *aux) 169 { 170 struct atphy_softc *asc = device_private(self); 171 prop_dictionary_t parent_prop = device_properties(parent); 172 prop_dictionary_t prop = device_properties(self); 173 struct mii_softc *sc = &asc->mii_sc; 174 struct mii_attach_args *ma = aux; 175 struct mii_data *mii = ma->mii_data; 176 const struct mii_phydesc *mpd; 177 uint16_t bmsr; 178 179 mpd = mii_phy_match(ma, atphys); 180 aprint_naive(": Media interface\n"); 181 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 182 183 sc->mii_dev = self; 184 sc->mii_inst = mii->mii_instance; 185 sc->mii_phy = ma->mii_phyno; 186 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 187 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 188 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 189 sc->mii_funcs = &atphy_funcs; 190 sc->mii_pdata = mii; 191 sc->mii_flags = ma->mii_flags; 192 sc->mii_flags |= MIIF_NOLOOP; 193 194 prop_dictionary_get_bool(parent_prop, "tx_internal_delay", 195 &asc->rgmii_tx_internal_delay); 196 prop_dictionary_get_bool(parent_prop, "rx_internal_delay", 197 &asc->rgmii_rx_internal_delay); 198 199 prop_dictionary_get_uint32(prop, "clk_25m", &asc->mii_clk_25m); 200 if (asc->mii_clk_25m != 0) 201 atphy_clk_25m(asc); 202 203 PHY_RESET(sc); 204 205 PHY_READ(sc, MII_BMSR, &bmsr); 206 PHY_READ(sc, MII_BMSR, &bmsr); 207 sc->mii_capabilities = bmsr & ma->mii_capmask; 208 if (atphy_is_gige(mpd) && (sc->mii_capabilities & BMSR_EXTSTAT)) 209 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 210 211 mii_phy_add_media(sc); 212 } 213 214 int 215 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 216 { 217 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 218 uint16_t anar, bmcr, bmsr; 219 220 switch (cmd) { 221 case MII_POLLSTAT: 222 /* If we're not polling our PHY instance, just return. */ 223 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 224 return 0; 225 break; 226 227 case MII_MEDIACHG: 228 /* 229 * If the media indicates a different PHY instance, 230 * isolate ourselves. 231 */ 232 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 233 PHY_READ(sc, MII_BMCR, &bmcr); 234 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 235 return 0; 236 } 237 238 /* If the interface is not up, don't do anything. */ 239 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 240 break; 241 242 bmcr = 0; 243 switch (IFM_SUBTYPE(ife->ifm_media)) { 244 case IFM_AUTO: 245 case IFM_1000_T: 246 atphy_mii_phy_auto(sc); 247 goto done; 248 case IFM_100_TX: 249 bmcr = BMCR_S100; 250 break; 251 case IFM_10_T: 252 bmcr = BMCR_S10; 253 break; 254 case IFM_NONE: 255 PHY_READ(sc, MII_BMCR, &bmcr); 256 /* 257 * XXX 258 * Due to an unknown reason powering down PHY resulted 259 * in unexpected results such as inaccessibility of 260 * hardware of freshly rebooted system. Disable 261 * powering down PHY until I got more information for 262 * Attansic/Atheros PHY hardwares. 263 */ 264 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 265 goto done; 266 default: 267 return EINVAL; 268 } 269 270 anar = mii_anar(ife); 271 if ((ife->ifm_media & IFM_FDX) != 0) { 272 bmcr |= BMCR_FDX; 273 /* Enable pause. */ 274 if (sc->mii_flags & MIIF_DOPAUSE) 275 anar |= ANAR_PAUSE_TOWARDS; 276 } 277 278 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 279 EXTSR_1000THDX)) != 0) 280 PHY_WRITE(sc, MII_100T2CR, 0); 281 PHY_WRITE(sc, MII_ANAR, anar); 282 283 /* Start autonegotiation. */ 284 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); 285 done: 286 break; 287 288 case MII_TICK: 289 /* If we're not currently selected, just return. */ 290 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 291 return 0; 292 293 /* Is the interface even up? */ 294 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 295 return 0; 296 297 /* Only used for autonegotiation. */ 298 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 299 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 300 sc->mii_ticks = 0; 301 break; 302 } 303 304 /* 305 * Check for link. 306 * Read the status register twice; BMSR_LINK is latch-low. 307 */ 308 PHY_READ(sc, MII_BMSR, &bmsr); 309 PHY_READ(sc, MII_BMSR, &bmsr); 310 if (bmsr & BMSR_LINK) { 311 sc->mii_ticks = 0; 312 break; 313 } 314 315 /* Announce link loss right after it happens. */ 316 if (sc->mii_ticks++ == 0) 317 break; 318 319 /* Only retry autonegotiation every mii_anegticks seconds. */ 320 if (sc->mii_ticks <= sc->mii_anegticks) 321 break; 322 323 atphy_mii_phy_auto(sc); 324 break; 325 } 326 327 /* Update the media status. */ 328 mii_phy_status(sc); 329 330 /* Callback if something changed. */ 331 mii_phy_update(sc, cmd); 332 return 0; 333 } 334 335 static void 336 atphy_status(struct mii_softc *sc) 337 { 338 struct mii_data *mii = sc->mii_pdata; 339 uint16_t bmsr, bmcr, gsr, ssr; 340 341 mii->mii_media_status = IFM_AVALID; 342 mii->mii_media_active = IFM_ETHER; 343 344 PHY_READ(sc, MII_BMSR, &bmsr); 345 PHY_READ(sc, MII_BMSR, &bmsr); 346 if (bmsr & BMSR_LINK) 347 mii->mii_media_status |= IFM_ACTIVE; 348 349 PHY_READ(sc, MII_BMCR, &bmcr); 350 if (bmcr & BMCR_ISO) { 351 mii->mii_media_active |= IFM_NONE; 352 mii->mii_media_status = 0; 353 return; 354 } 355 356 if (bmcr & BMCR_LOOP) 357 mii->mii_media_active |= IFM_LOOP; 358 359 PHY_READ(sc, ATPHY_SSR, &ssr); 360 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 361 /* Erg, still trying, I guess... */ 362 mii->mii_media_active |= IFM_NONE; 363 return; 364 } 365 366 switch (ssr & ATPHY_SSR_SPEED_MASK) { 367 case ATPHY_SSR_1000MBS: 368 mii->mii_media_active |= IFM_1000_T; 369 /* 370 * atphy(4) has a valid link so reset mii_ticks. 371 * Resetting mii_ticks is needed in order to 372 * detect link loss after auto-negotiation. 373 */ 374 sc->mii_ticks = 0; 375 break; 376 case ATPHY_SSR_100MBS: 377 mii->mii_media_active |= IFM_100_TX; 378 sc->mii_ticks = 0; 379 break; 380 case ATPHY_SSR_10MBS: 381 mii->mii_media_active |= IFM_10_T; 382 sc->mii_ticks = 0; 383 break; 384 default: 385 mii->mii_media_active |= IFM_NONE; 386 return; 387 } 388 389 if (ssr & ATPHY_SSR_DUPLEX) 390 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 391 else 392 mii->mii_media_active |= IFM_HDX; 393 394 PHY_READ(sc, MII_100T2SR, &gsr); 395 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 396 gsr & GTSR_MS_RES) 397 mii->mii_media_active |= IFM_ETH_MASTER; 398 } 399 400 static void 401 atphy_reset(struct mii_softc *sc) 402 { 403 struct atphy_softc *asc = (struct atphy_softc *)sc; 404 uint16_t reg; 405 int i; 406 407 /* Take PHY out of power down mode. */ 408 PHY_WRITE(sc, 29, 0x29); 409 PHY_WRITE(sc, 30, 0); 410 411 PHY_READ(sc, ATPHY_SCR, ®); 412 /* Enable automatic crossover. */ 413 reg |= ATPHY_SCR_AUTO_X_MODE; 414 /* Disable power down. */ 415 reg &= ~ATPHY_SCR_MAC_PDOWN; 416 /* Enable CRS on Tx. */ 417 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 418 /* Auto correction for reversed cable polarity. */ 419 reg |= ATPHY_SCR_POLARITY_REVERSAL; 420 PHY_WRITE(sc, ATPHY_SCR, reg); 421 422 atphy_mii_phy_auto(sc); 423 424 /* Workaround F1 bug to reset phy. */ 425 PHY_READ(sc, MII_BMCR, ®); 426 reg |= BMCR_RESET; 427 PHY_WRITE(sc, MII_BMCR, reg); 428 429 for (i = 0; i < 1000; i++) { 430 DELAY(1); 431 PHY_READ(sc, MII_BMCR, ®); 432 if ((reg & BMCR_RESET) == 0) 433 break; 434 } 435 436 if (asc->rgmii_tx_internal_delay) { 437 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x05); 438 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_TX_CLK_DLY); 439 } 440 if (asc->rgmii_rx_internal_delay) { 441 PHY_WRITE(sc, ATPHY_DEBUG_PORT_ADDR, 0x00); 442 PHY_WRITE(sc, ATPHY_DEBUG_PORT_DATA, ATPHY_RGMII_RX_CLK_DLY); 443 } 444 } 445 446 static int 447 atphy_mii_phy_auto(struct mii_softc *sc) 448 { 449 uint16_t anar; 450 451 sc->mii_ticks = 0; 452 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 453 if (sc->mii_flags & MIIF_DOPAUSE) 454 anar |= ANAR_PAUSE_TOWARDS; 455 PHY_WRITE(sc, MII_ANAR, anar); 456 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 457 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 458 GTCR_ADV_1000THDX); 459 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 460 461 return EJUSTRETURN; 462 } 463
Indexes created Thu Oct 23 22:10:10 GMT 2025