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atphy.c revision 1.5.2.2.4.1 
      1 /*	$NetBSD: atphy.c,v 1.5.2.2.4.1 2011/01/07 02:20:27 matt Exp $ */
      2 /*	$OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $	*/
      3 
      4 /*-
      5  * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org>
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice unmodified, this list of conditions, and the following
     13  *    disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28  * SUCH DAMAGE.
     29  */
     30 
     31 /*
     32  * Driver for the Attansic F1 10/100/1000 PHY.
     33  */
     34 
     35 #include <sys/cdefs.h>
     36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.5.2.2.4.1 2011/01/07 02:20:27 matt Exp $");
     37 
     38 #include <sys/param.h>
     39 #include <sys/systm.h>
     40 #include <sys/kernel.h>
     41 #include <sys/device.h>
     42 #include <sys/socket.h>
     43 
     44 #include <net/if.h>
     45 #include <net/if_media.h>
     46 
     47 #include <dev/mii/mii.h>
     48 #include <dev/mii/miivar.h>
     49 #include <dev/mii/miidevs.h>
     50 
     51 /* Special Control Register */
     52 #define ATPHY_SCR			0x10
     53 #define ATPHY_SCR_JABBER_DISABLE	0x0001
     54 #define ATPHY_SCR_POLARITY_REVERSAL	0x0002
     55 #define ATPHY_SCR_SQE_TEST		0x0004
     56 #define ATPHY_SCR_MAC_PDOWN		0x0008
     57 #define ATPHY_SCR_CLK125_DISABLE	0x0010
     58 #define ATPHY_SCR_MDI_MANUAL_MODE	0x0000
     59 #define ATPHY_SCR_MDIX_MANUAL_MODE	0x0020
     60 #define ATPHY_SCR_AUTO_X_1000T		0x0040
     61 #define ATPHY_SCR_AUTO_X_MODE		0x0060
     62 #define ATPHY_SCR_10BT_EXT_ENABLE	0x0080
     63 #define ATPHY_SCR_MII_5BIT_ENABLE	0x0100
     64 #define ATPHY_SCR_SCRAMBLER_DISABLE	0x0200
     65 #define ATPHY_SCR_FORCE_LINK_GOOD	0x0400
     66 #define ATPHY_SCR_ASSERT_CRS_ON_TX	0x0800
     67 
     68 /* Special Status Register. */
     69 #define ATPHY_SSR			0x11
     70 #define ATPHY_SSR_SPD_DPLX_RESOLVED	0x0800
     71 #define ATPHY_SSR_DUPLEX		0x2000
     72 #define ATPHY_SSR_SPEED_MASK		0xC000
     73 #define ATPHY_SSR_10MBS			0x0000
     74 #define ATPHY_SSR_100MBS		0x4000
     75 #define ATPHY_SSR_1000MBS		0x8000
     76 
     77 static int atphy_match(device_t, cfdata_t, void *);
     78 static void atphy_attach(device_t, device_t, void *);
     79 
     80 static int atphy_service(struct mii_softc *, struct mii_data *, int);
     81 static void atphy_reset(struct mii_softc *);
     82 static void atphy_status(struct mii_softc *);
     83 static int atphy_mii_phy_auto(struct mii_softc *);
     84 
     85 CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc),
     86 	atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate);
     87 
     88 const struct mii_phy_funcs atphy_funcs = {
     89         atphy_service, atphy_status, atphy_reset,
     90 };
     91 
     92 static const struct mii_phydesc etphys[] = {
     93 	{ MII_OUI_ATHEROS,	MII_MODEL_ATHEROS_F1,
     94 	  MII_STR_ATHEROS_F1 },
     95 	{ MII_OUI_ATTANSIC,	MII_MODEL_ATTANSIC_L1,
     96 	  MII_STR_ATTANSIC_L1 },
     97 	{ MII_OUI_ATTANSIC,	MII_MODEL_ATTANSIC_AR8021,
     98 	  MII_STR_ATTANSIC_AR8021 },
     99 	{ 0,			0,
    100 	  NULL },
    101 };
    102 
    103 static int
    104 atphy_match(device_t parent, cfdata_t match, void *aux)
    105 {
    106 	struct mii_attach_args *ma = aux;
    107 
    108 	if (mii_phy_match(ma, etphys) != NULL)
    109 		return 10;
    110 
    111 	return 0;
    112 }
    113 
    114 void
    115 atphy_attach(device_t parent, device_t self, void *aux)
    116 {
    117 	struct mii_softc *sc = device_private(self);
    118 	struct mii_attach_args *ma = aux;
    119 	struct mii_data *mii = ma->mii_data;
    120 	const struct mii_phydesc *mpd;
    121 
    122 	mpd = mii_phy_match(ma, etphys);
    123 	aprint_naive(": Media interface\n");
    124 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    125 
    126 	sc->mii_dev = self;
    127 	sc->mii_inst = mii->mii_instance;
    128 	sc->mii_phy = ma->mii_phyno;
    129 	sc->mii_funcs = &atphy_funcs;
    130 	sc->mii_pdata = mii;
    131 	sc->mii_flags = ma->mii_flags;
    132 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
    133 
    134 	sc->mii_flags |= MIIF_NOLOOP;
    135 
    136 	PHY_RESET(sc);
    137 
    138 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
    139 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    140 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
    141 
    142 	aprint_normal_dev(self, "");
    143 	mii_phy_add_media(sc);
    144 	aprint_normal("\n");
    145 }
    146 
    147 int
    148 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    149 {
    150 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    151 	uint16_t anar, bmcr, bmsr;
    152 
    153 	switch (cmd) {
    154 	case MII_POLLSTAT:
    155 		/*
    156 		 * If we're not polling our PHY instance, just return.
    157 		 */
    158 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    159 			return 0;
    160 		break;
    161 
    162 	case MII_MEDIACHG:
    163 		/*
    164 		 * If the media indicates a different PHY instance,
    165 		 * isolate ourselves.
    166 		 */
    167 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    168 			bmcr = PHY_READ(sc, MII_BMCR);
    169 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    170 			return 0;
    171 		}
    172 
    173 		/*
    174 		 * If the interface is not up, don't do anything.
    175 		 */
    176 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    177 			break;
    178 
    179 		bmcr = 0;
    180 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    181 		case IFM_AUTO:
    182 		case IFM_1000_T:
    183 			atphy_mii_phy_auto(sc);
    184 			goto done;
    185 		case IFM_100_TX:
    186 			bmcr = BMCR_S100;
    187 			break;
    188 		case IFM_10_T:
    189 			bmcr = BMCR_S10;
    190 			break;
    191 		case IFM_NONE:
    192 			bmcr = PHY_READ(sc, MII_BMCR);
    193 			/*
    194 			 * XXX
    195 			 * Due to an unknown reason powering down PHY resulted
    196 			 * in unexpected results such as inaccessbility of
    197 			 * hardware of freshly rebooted system. Disable
    198 			 * powering down PHY until I got more information for
    199 			 * Attansic/Atheros PHY hardwares.
    200 			 */
    201 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    202 			goto done;
    203 		default:
    204 			return EINVAL;
    205 		}
    206 
    207 		anar = mii_anar(ife->ifm_media);
    208 		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
    209 			bmcr |= BMCR_FDX;
    210 			/* Enable pause. */
    211 			if (sc->mii_flags & MIIF_DOPAUSE)
    212 				anar |= (3 << 10);
    213 		}
    214 
    215 		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
    216 		    EXTSR_1000THDX)) != 0)
    217 			PHY_WRITE(sc, MII_100T2CR, 0);
    218 		PHY_WRITE(sc, MII_ANAR, anar);
    219 
    220 		/*
    221 		 * Reset the PHY so all changes take effect.
    222 		 */
    223 		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
    224 		    BMCR_STARTNEG);
    225 done:
    226 		break;
    227 
    228 	case MII_TICK:
    229 		/*
    230 		 * If we're not currently selected, just return.
    231 		 */
    232 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    233 			return 0;
    234 
    235 		/*
    236 		 * Is the interface even up?
    237 		 */
    238 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    239 			return 0;
    240 
    241 		/*
    242 		 * Only used for autonegotiation.
    243 		 */
    244 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
    245 			sc->mii_ticks = 0;
    246 			break;
    247 		}
    248 
    249 		/*
    250 		 * Check for link.
    251 		 * Read the status register twice; BMSR_LINK is latch-low.
    252 		 */
    253 		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    254 		if (bmsr & BMSR_LINK) {
    255 			sc->mii_ticks = 0;
    256 			break;
    257 		}
    258 
    259 		/* Announce link loss right after it happens. */
    260 		if (sc->mii_ticks++ == 0)
    261 			break;
    262 
    263 		/*
    264 		 * Only retry autonegotiation every mii_anegticks seconds.
    265 		 */
    266 		if (sc->mii_ticks <= sc->mii_anegticks)
    267 			break;
    268 
    269 		sc->mii_ticks = 0;
    270 		atphy_mii_phy_auto(sc);
    271 		break;
    272 	}
    273 
    274 	/* Update the media status. */
    275 	mii_phy_status(sc);
    276 
    277 	/* Callback if something changed. */
    278 	mii_phy_update(sc, cmd);
    279 	return 0;
    280 }
    281 
    282 static void
    283 atphy_status(struct mii_softc *sc)
    284 {
    285 	struct mii_data *mii = sc->mii_pdata;
    286 	uint32_t bmsr, bmcr, gsr, ssr;
    287 
    288 	mii->mii_media_status = IFM_AVALID;
    289 	mii->mii_media_active = IFM_ETHER;
    290 
    291 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    292 	if (bmsr & BMSR_LINK)
    293 		mii->mii_media_status |= IFM_ACTIVE;
    294 
    295 	bmcr = PHY_READ(sc, MII_BMCR);
    296 	if (bmcr & BMCR_ISO) {
    297 		mii->mii_media_active |= IFM_NONE;
    298 		mii->mii_media_status = 0;
    299 		return;
    300 	}
    301 
    302 	if (bmcr & BMCR_LOOP)
    303 		mii->mii_media_active |= IFM_LOOP;
    304 
    305 	ssr = PHY_READ(sc, ATPHY_SSR);
    306 	if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
    307 		/* Erg, still trying, I guess... */
    308 		mii->mii_media_active |= IFM_NONE;
    309 		return;
    310 	}
    311 
    312 	switch (ssr & ATPHY_SSR_SPEED_MASK) {
    313 	case ATPHY_SSR_1000MBS:
    314 		mii->mii_media_active |= IFM_1000_T;
    315 		/*
    316 		 * atphy(4) has a valid link so reset mii_ticks.
    317 		 * Resetting mii_ticks is needed in order to
    318 		 * detect link loss after auto-negotiation.
    319 		 */
    320 		sc->mii_ticks = 0;
    321 		break;
    322 	case ATPHY_SSR_100MBS:
    323 		mii->mii_media_active |= IFM_100_TX;
    324 		sc->mii_ticks = 0;
    325 		break;
    326 	case ATPHY_SSR_10MBS:
    327 		mii->mii_media_active |= IFM_10_T;
    328 		sc->mii_ticks = 0;
    329 		break;
    330 	default:
    331 		mii->mii_media_active |= IFM_NONE;
    332 		return;
    333 	}
    334 
    335 	if (ssr & ATPHY_SSR_DUPLEX)
    336 		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
    337 	else
    338 		mii->mii_media_active |= IFM_HDX;
    339 
    340 	gsr = PHY_READ(sc, MII_100T2SR);
    341 	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
    342 	    gsr & GTSR_MS_RES)
    343 		mii->mii_media_active |= IFM_ETH_MASTER;
    344 }
    345 
    346 static void
    347 atphy_reset(struct mii_softc *sc)
    348 {
    349 	uint32_t reg;
    350 	int i;
    351 
    352 	/* Take PHY out of power down mode. */
    353 	PHY_WRITE(sc, 29, 0x29);
    354 	PHY_WRITE(sc, 30, 0);
    355 
    356 	reg = PHY_READ(sc, ATPHY_SCR);
    357 	/* Enable automatic crossover. */
    358 	reg |= ATPHY_SCR_AUTO_X_MODE;
    359 	/* Disable power down. */
    360 	reg &= ~ATPHY_SCR_MAC_PDOWN;
    361 	/* Enable CRS on Tx. */
    362 	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
    363 	/* Auto correction for reversed cable polarity. */
    364 	reg |= ATPHY_SCR_POLARITY_REVERSAL;
    365 	PHY_WRITE(sc, ATPHY_SCR, reg);
    366 
    367 	/* Workaround F1 bug to reset phy. */
    368 	atphy_mii_phy_auto(sc);
    369 
    370 	for (i = 0; i < 1000; i++) {
    371 		DELAY(1);
    372 		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
    373 			break;
    374 	}
    375 }
    376 
    377 static int
    378 atphy_mii_phy_auto(struct mii_softc *sc)
    379 {
    380 	uint16_t anar;
    381 
    382 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    383 	if (sc->mii_flags & MIIF_DOPAUSE)
    384 		anar |= (3 << 10);
    385 	PHY_WRITE(sc, MII_ANAR, anar);
    386 	if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
    387 		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
    388 		    GTCR_ADV_1000THDX);
    389 	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
    390 
    391 	return EJUSTRETURN;
    392 }
    393