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atphy.c revision 1.7.4.1 
      1 /*	$NetBSD: atphy.c,v 1.7.4.1 2011/02/08 16:19:49 bouyer Exp $ */
      2 /*	$OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $	*/
      3 
      4 /*-
      5  * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org>
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice unmodified, this list of conditions, and the following
     13  *    disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28  * SUCH DAMAGE.
     29  */
     30 
     31 /*
     32  * Driver for the Attansic F1 10/100/1000 PHY.
     33  */
     34 
     35 #include <sys/cdefs.h>
     36 __KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.7.4.1 2011/02/08 16:19:49 bouyer Exp $");
     37 
     38 #include <sys/param.h>
     39 #include <sys/systm.h>
     40 #include <sys/kernel.h>
     41 #include <sys/device.h>
     42 #include <sys/socket.h>
     43 
     44 #include <net/if.h>
     45 #include <net/if_media.h>
     46 
     47 #include <dev/mii/mii.h>
     48 #include <dev/mii/miivar.h>
     49 #include <dev/mii/miidevs.h>
     50 
     51 /* Special Control Register */
     52 #define ATPHY_SCR			0x10
     53 #define ATPHY_SCR_JABBER_DISABLE	0x0001
     54 #define ATPHY_SCR_POLARITY_REVERSAL	0x0002
     55 #define ATPHY_SCR_SQE_TEST		0x0004
     56 #define ATPHY_SCR_MAC_PDOWN		0x0008
     57 #define ATPHY_SCR_CLK125_DISABLE	0x0010
     58 #define ATPHY_SCR_MDI_MANUAL_MODE	0x0000
     59 #define ATPHY_SCR_MDIX_MANUAL_MODE	0x0020
     60 #define ATPHY_SCR_AUTO_X_1000T		0x0040
     61 #define ATPHY_SCR_AUTO_X_MODE		0x0060
     62 #define ATPHY_SCR_10BT_EXT_ENABLE	0x0080
     63 #define ATPHY_SCR_MII_5BIT_ENABLE	0x0100
     64 #define ATPHY_SCR_SCRAMBLER_DISABLE	0x0200
     65 #define ATPHY_SCR_FORCE_LINK_GOOD	0x0400
     66 #define ATPHY_SCR_ASSERT_CRS_ON_TX	0x0800
     67 
     68 /* Special Status Register. */
     69 #define ATPHY_SSR			0x11
     70 #define ATPHY_SSR_SPD_DPLX_RESOLVED	0x0800
     71 #define ATPHY_SSR_DUPLEX		0x2000
     72 #define ATPHY_SSR_SPEED_MASK		0xC000
     73 #define ATPHY_SSR_10MBS			0x0000
     74 #define ATPHY_SSR_100MBS		0x4000
     75 #define ATPHY_SSR_1000MBS		0x8000
     76 
     77 static int atphy_match(device_t, cfdata_t, void *);
     78 static void atphy_attach(device_t, device_t, void *);
     79 
     80 static int atphy_service(struct mii_softc *, struct mii_data *, int);
     81 static void atphy_reset(struct mii_softc *);
     82 static void atphy_status(struct mii_softc *);
     83 static int atphy_mii_phy_auto(struct mii_softc *);
     84 
     85 CFATTACH_DECL_NEW(atphy, sizeof(struct mii_softc),
     86 	atphy_match, atphy_attach, mii_phy_detach, mii_phy_activate);
     87 
     88 const struct mii_phy_funcs atphy_funcs = {
     89         atphy_service, atphy_status, atphy_reset,
     90 };
     91 
     92 static const struct mii_phydesc etphys[] = {
     93 	{ MII_OUI_ATHEROS,	MII_MODEL_ATHEROS_F1,
     94 	  MII_STR_ATHEROS_F1 },
     95 	{ MII_OUI_ATTANSIC,	MII_MODEL_ATTANSIC_L1,
     96 	  MII_STR_ATTANSIC_L1 },
     97 	{ MII_OUI_ATTANSIC,	MII_MODEL_ATTANSIC_AR8021,
     98 	  MII_STR_ATTANSIC_AR8021 },
     99 	{ 0,			0,
    100 	  NULL },
    101 };
    102 
    103 static int
    104 atphy_match(device_t parent, cfdata_t match, void *aux)
    105 {
    106 	struct mii_attach_args *ma = aux;
    107 
    108 	if (mii_phy_match(ma, etphys) != NULL)
    109 		return 10;
    110 
    111 	return 0;
    112 }
    113 
    114 void
    115 atphy_attach(device_t parent, device_t self, void *aux)
    116 {
    117 	struct mii_softc *sc = device_private(self);
    118 	struct mii_attach_args *ma = aux;
    119 	struct mii_data *mii = ma->mii_data;
    120 	const struct mii_phydesc *mpd;
    121 	uint16_t bmsr;
    122 
    123 	mpd = mii_phy_match(ma, etphys);
    124 	aprint_naive(": Media interface\n");
    125 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    126 
    127 	sc->mii_dev = self;
    128 	sc->mii_inst = mii->mii_instance;
    129 	sc->mii_phy = ma->mii_phyno;
    130 	sc->mii_funcs = &atphy_funcs;
    131 	sc->mii_pdata = mii;
    132 	sc->mii_flags = ma->mii_flags;
    133 	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
    134 
    135 	sc->mii_flags |= MIIF_NOLOOP;
    136 
    137 	PHY_RESET(sc);
    138 
    139 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    140 	sc->mii_capabilities = bmsr & ma->mii_capmask;
    141 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    142 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
    143 
    144 	aprint_normal_dev(self, "");
    145 	mii_phy_add_media(sc);
    146 	aprint_normal("\n");
    147 }
    148 
    149 int
    150 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    151 {
    152 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    153 	uint16_t anar, bmcr, bmsr;
    154 
    155 	switch (cmd) {
    156 	case MII_POLLSTAT:
    157 		/*
    158 		 * If we're not polling our PHY instance, just return.
    159 		 */
    160 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    161 			return 0;
    162 		break;
    163 
    164 	case MII_MEDIACHG:
    165 		/*
    166 		 * If the media indicates a different PHY instance,
    167 		 * isolate ourselves.
    168 		 */
    169 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    170 			bmcr = PHY_READ(sc, MII_BMCR);
    171 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    172 			return 0;
    173 		}
    174 
    175 		/*
    176 		 * If the interface is not up, don't do anything.
    177 		 */
    178 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    179 			break;
    180 
    181 		bmcr = 0;
    182 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    183 		case IFM_AUTO:
    184 		case IFM_1000_T:
    185 			atphy_mii_phy_auto(sc);
    186 			goto done;
    187 		case IFM_100_TX:
    188 			bmcr = BMCR_S100;
    189 			break;
    190 		case IFM_10_T:
    191 			bmcr = BMCR_S10;
    192 			break;
    193 		case IFM_NONE:
    194 			bmcr = PHY_READ(sc, MII_BMCR);
    195 			/*
    196 			 * XXX
    197 			 * Due to an unknown reason powering down PHY resulted
    198 			 * in unexpected results such as inaccessibility of
    199 			 * hardware of freshly rebooted system. Disable
    200 			 * powering down PHY until I got more information for
    201 			 * Attansic/Atheros PHY hardwares.
    202 			 */
    203 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
    204 			goto done;
    205 		default:
    206 			return EINVAL;
    207 		}
    208 
    209 		anar = mii_anar(ife->ifm_media);
    210 		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
    211 			bmcr |= BMCR_FDX;
    212 			/* Enable pause. */
    213 			if (sc->mii_flags & MIIF_DOPAUSE)
    214 				anar |= ANAR_X_PAUSE_TOWARDS;
    215 		}
    216 
    217 		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
    218 		    EXTSR_1000THDX)) != 0)
    219 			PHY_WRITE(sc, MII_100T2CR, 0);
    220 		PHY_WRITE(sc, MII_ANAR, anar);
    221 
    222 		/*
    223 		 * Start autonegotiation.
    224 		 */
    225 		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
    226 done:
    227 		break;
    228 
    229 	case MII_TICK:
    230 		/*
    231 		 * If we're not currently selected, just return.
    232 		 */
    233 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    234 			return 0;
    235 
    236 		/*
    237 		 * Is the interface even up?
    238 		 */
    239 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    240 			return 0;
    241 
    242 		/*
    243 		 * Only used for autonegotiation.
    244 		 */
    245 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
    246 			sc->mii_ticks = 0;
    247 			break;
    248 		}
    249 
    250 		/*
    251 		 * Check for link.
    252 		 * Read the status register twice; BMSR_LINK is latch-low.
    253 		 */
    254 		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    255 		if (bmsr & BMSR_LINK) {
    256 			sc->mii_ticks = 0;
    257 			break;
    258 		}
    259 
    260 		/* Announce link loss right after it happens. */
    261 		if (sc->mii_ticks++ == 0)
    262 			break;
    263 
    264 		/*
    265 		 * Only retry autonegotiation every mii_anegticks seconds.
    266 		 */
    267 		if (sc->mii_ticks <= sc->mii_anegticks)
    268 			break;
    269 
    270 		sc->mii_ticks = 0;
    271 		atphy_mii_phy_auto(sc);
    272 		break;
    273 	}
    274 
    275 	/* Update the media status. */
    276 	mii_phy_status(sc);
    277 
    278 	/* Callback if something changed. */
    279 	mii_phy_update(sc, cmd);
    280 	return 0;
    281 }
    282 
    283 static void
    284 atphy_status(struct mii_softc *sc)
    285 {
    286 	struct mii_data *mii = sc->mii_pdata;
    287 	uint32_t bmsr, bmcr, gsr, ssr;
    288 
    289 	mii->mii_media_status = IFM_AVALID;
    290 	mii->mii_media_active = IFM_ETHER;
    291 
    292 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
    293 	if (bmsr & BMSR_LINK)
    294 		mii->mii_media_status |= IFM_ACTIVE;
    295 
    296 	bmcr = PHY_READ(sc, MII_BMCR);
    297 	if (bmcr & BMCR_ISO) {
    298 		mii->mii_media_active |= IFM_NONE;
    299 		mii->mii_media_status = 0;
    300 		return;
    301 	}
    302 
    303 	if (bmcr & BMCR_LOOP)
    304 		mii->mii_media_active |= IFM_LOOP;
    305 
    306 	ssr = PHY_READ(sc, ATPHY_SSR);
    307 	if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
    308 		/* Erg, still trying, I guess... */
    309 		mii->mii_media_active |= IFM_NONE;
    310 		return;
    311 	}
    312 
    313 	switch (ssr & ATPHY_SSR_SPEED_MASK) {
    314 	case ATPHY_SSR_1000MBS:
    315 		mii->mii_media_active |= IFM_1000_T;
    316 		/*
    317 		 * atphy(4) has a valid link so reset mii_ticks.
    318 		 * Resetting mii_ticks is needed in order to
    319 		 * detect link loss after auto-negotiation.
    320 		 */
    321 		sc->mii_ticks = 0;
    322 		break;
    323 	case ATPHY_SSR_100MBS:
    324 		mii->mii_media_active |= IFM_100_TX;
    325 		sc->mii_ticks = 0;
    326 		break;
    327 	case ATPHY_SSR_10MBS:
    328 		mii->mii_media_active |= IFM_10_T;
    329 		sc->mii_ticks = 0;
    330 		break;
    331 	default:
    332 		mii->mii_media_active |= IFM_NONE;
    333 		return;
    334 	}
    335 
    336 	if (ssr & ATPHY_SSR_DUPLEX)
    337 		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
    338 	else
    339 		mii->mii_media_active |= IFM_HDX;
    340 
    341 	gsr = PHY_READ(sc, MII_100T2SR);
    342 	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
    343 	    gsr & GTSR_MS_RES)
    344 		mii->mii_media_active |= IFM_ETH_MASTER;
    345 }
    346 
    347 static void
    348 atphy_reset(struct mii_softc *sc)
    349 {
    350 	uint32_t reg;
    351 	int i;
    352 
    353 	/* Take PHY out of power down mode. */
    354 	PHY_WRITE(sc, 29, 0x29);
    355 	PHY_WRITE(sc, 30, 0);
    356 
    357 	reg = PHY_READ(sc, ATPHY_SCR);
    358 	/* Enable automatic crossover. */
    359 	reg |= ATPHY_SCR_AUTO_X_MODE;
    360 	/* Disable power down. */
    361 	reg &= ~ATPHY_SCR_MAC_PDOWN;
    362 	/* Enable CRS on Tx. */
    363 	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
    364 	/* Auto correction for reversed cable polarity. */
    365 	reg |= ATPHY_SCR_POLARITY_REVERSAL;
    366 	PHY_WRITE(sc, ATPHY_SCR, reg);
    367 
    368 	atphy_mii_phy_auto(sc);
    369 
    370 	/* Workaround F1 bug to reset phy. */
    371 	reg = PHY_READ(sc, MII_BMCR) | BMCR_RESET;
    372 	PHY_WRITE(sc, MII_BMCR, reg);
    373 
    374 	for (i = 0; i < 1000; i++) {
    375 		DELAY(1);
    376 		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
    377 			break;
    378 	}
    379 }
    380 
    381 static int
    382 atphy_mii_phy_auto(struct mii_softc *sc)
    383 {
    384 	uint16_t anar;
    385 
    386 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    387 	if (sc->mii_flags & MIIF_DOPAUSE)
    388 		anar |= ANAR_X_PAUSE_TOWARDS;
    389 	PHY_WRITE(sc, MII_ANAR, anar);
    390 	if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
    391 		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
    392 		    GTCR_ADV_1000THDX);
    393 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
    394 
    395 	return EJUSTRETURN;
    396 }
    397