brgphy.c revision 1.34.14.2 1 1.34.14.2 markd /* $NetBSD: brgphy.c,v 1.34.14.2 2007/08/06 12:16:34 markd Exp $ */
2 1.34.14.2 markd
3 1.34.14.2 markd /*-
4 1.34.14.2 markd * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
5 1.34.14.2 markd * All rights reserved.
6 1.34.14.2 markd *
7 1.34.14.2 markd * This code is derived from software contributed to The NetBSD Foundation
8 1.34.14.2 markd * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.34.14.2 markd * NASA Ames Research Center.
10 1.34.14.2 markd *
11 1.34.14.2 markd * Redistribution and use in source and binary forms, with or without
12 1.34.14.2 markd * modification, are permitted provided that the following conditions
13 1.34.14.2 markd * are met:
14 1.34.14.2 markd * 1. Redistributions of source code must retain the above copyright
15 1.34.14.2 markd * notice, this list of conditions and the following disclaimer.
16 1.34.14.2 markd * 2. Redistributions in binary form must reproduce the above copyright
17 1.34.14.2 markd * notice, this list of conditions and the following disclaimer in the
18 1.34.14.2 markd * documentation and/or other materials provided with the distribution.
19 1.34.14.2 markd * 3. All advertising materials mentioning features or use of this software
20 1.34.14.2 markd * must display the following acknowledgement:
21 1.34.14.2 markd * This product includes software developed by the NetBSD
22 1.34.14.2 markd * Foundation, Inc. and its contributors.
23 1.34.14.2 markd * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.34.14.2 markd * contributors may be used to endorse or promote products derived
25 1.34.14.2 markd * from this software without specific prior written permission.
26 1.34.14.2 markd *
27 1.34.14.2 markd * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.34.14.2 markd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.34.14.2 markd * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.34.14.2 markd * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.34.14.2 markd * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.34.14.2 markd * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.34.14.2 markd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.34.14.2 markd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.34.14.2 markd * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.34.14.2 markd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.34.14.2 markd * POSSIBILITY OF SUCH DAMAGE.
38 1.34.14.2 markd */
39 1.34.14.2 markd
40 1.34.14.2 markd /*
41 1.34.14.2 markd * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
42 1.34.14.2 markd *
43 1.34.14.2 markd * Redistribution and use in source and binary forms, with or without
44 1.34.14.2 markd * modification, are permitted provided that the following conditions
45 1.34.14.2 markd * are met:
46 1.34.14.2 markd * 1. Redistributions of source code must retain the above copyright
47 1.34.14.2 markd * notice, this list of conditions and the following disclaimer.
48 1.34.14.2 markd * 2. Redistributions in binary form must reproduce the above copyright
49 1.34.14.2 markd * notice, this list of conditions and the following disclaimer in the
50 1.34.14.2 markd * documentation and/or other materials provided with the distribution.
51 1.34.14.2 markd * 3. All advertising materials mentioning features or use of this software
52 1.34.14.2 markd * must display the following acknowledgement:
53 1.34.14.2 markd * This product includes software developed by Manuel Bouyer.
54 1.34.14.2 markd * 4. The name of the author may not be used to endorse or promote products
55 1.34.14.2 markd * derived from this software without specific prior written permission.
56 1.34.14.2 markd *
57 1.34.14.2 markd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
58 1.34.14.2 markd * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 1.34.14.2 markd * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 1.34.14.2 markd * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
61 1.34.14.2 markd * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
62 1.34.14.2 markd * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 1.34.14.2 markd * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 1.34.14.2 markd * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 1.34.14.2 markd * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66 1.34.14.2 markd * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 1.34.14.2 markd */
68 1.34.14.2 markd
69 1.34.14.2 markd /*
70 1.34.14.2 markd * driver for the Broadcom BCM5400 Gig-E PHY.
71 1.34.14.2 markd *
72 1.34.14.2 markd * Programming information for this PHY was gleaned from FreeBSD
73 1.34.14.2 markd * (they were apparently able to get a datasheet from Broadcom).
74 1.34.14.2 markd */
75 1.34.14.2 markd
76 1.34.14.2 markd #include <sys/cdefs.h>
77 1.34.14.2 markd __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.34.14.2 2007/08/06 12:16:34 markd Exp $");
78 1.34.14.2 markd
79 1.34.14.2 markd #include <sys/param.h>
80 1.34.14.2 markd #include <sys/systm.h>
81 1.34.14.2 markd #include <sys/kernel.h>
82 1.34.14.2 markd #include <sys/device.h>
83 1.34.14.2 markd #include <sys/socket.h>
84 1.34.14.2 markd #include <sys/errno.h>
85 1.34.14.2 markd
86 1.34.14.2 markd #include <net/if.h>
87 1.34.14.2 markd #include <net/if_media.h>
88 1.34.14.2 markd
89 1.34.14.2 markd #include <dev/mii/mii.h>
90 1.34.14.2 markd #include <dev/mii/miivar.h>
91 1.34.14.2 markd #include <dev/mii/miidevs.h>
92 1.34.14.2 markd
93 1.34.14.2 markd #include <dev/mii/brgphyreg.h>
94 1.34.14.2 markd
95 1.34.14.2 markd static int brgphymatch(struct device *, struct cfdata *, void *);
96 1.34.14.2 markd static void brgphyattach(struct device *, struct device *, void *);
97 1.34.14.2 markd
98 1.34.14.2 markd CFATTACH_DECL(brgphy, sizeof(struct mii_softc),
99 1.34.14.2 markd brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate);
100 1.34.14.2 markd
101 1.34.14.2 markd static int brgphy_service(struct mii_softc *, struct mii_data *, int);
102 1.34.14.2 markd static void brgphy_status(struct mii_softc *);
103 1.34.14.2 markd static int brgphy_mii_phy_auto(struct mii_softc *);
104 1.34.14.2 markd static void brgphy_loop(struct mii_softc *);
105 1.34.14.2 markd
106 1.34.14.2 markd static void brgphy_5401_reset(struct mii_softc *);
107 1.34.14.2 markd static void brgphy_5411_reset(struct mii_softc *);
108 1.34.14.2 markd static void brgphy_5703_reset(struct mii_softc *);
109 1.34.14.2 markd static void brgphy_5704_reset(struct mii_softc *);
110 1.34.14.2 markd static void brgphy_5705_reset(struct mii_softc *);
111 1.34.14.2 markd static void brgphy_5750_reset(struct mii_softc *);
112 1.34.14.2 markd static void brgphy_5755_reset(struct mii_softc *);
113 1.34.14.2 markd
114 1.34.14.2 markd static const struct mii_phy_funcs brgphy_funcs = {
115 1.34.14.2 markd brgphy_service, brgphy_status, mii_phy_reset,
116 1.34.14.2 markd };
117 1.34.14.2 markd
118 1.34.14.2 markd static const struct mii_phy_funcs brgphy_5401_funcs = {
119 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5401_reset,
120 1.34.14.2 markd };
121 1.34.14.2 markd
122 1.34.14.2 markd static const struct mii_phy_funcs brgphy_5411_funcs = {
123 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5411_reset,
124 1.34.14.2 markd };
125 1.34.14.2 markd
126 1.34.14.2 markd static const struct mii_phy_funcs brgphy_5703_funcs = {
127 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5703_reset,
128 1.34.14.2 markd };
129 1.34.14.2 markd
130 1.34.14.2 markd static const struct mii_phy_funcs brgphy_5704_funcs = {
131 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5704_reset,
132 1.34.14.2 markd };
133 1.34.14.2 markd
134 1.34.14.2 markd static const struct mii_phy_funcs brgphy_5705_funcs = {
135 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5705_reset,
136 1.34.14.2 markd };
137 1.34.14.2 markd
138 1.34.14.2 markd const struct mii_phy_funcs brgphy_5750_funcs = {
139 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5750_reset,
140 1.34.14.2 markd };
141 1.34.14.2 markd
142 1.34.14.2 markd const struct mii_phy_funcs brgphy_5755_funcs = {
143 1.34.14.2 markd brgphy_service, brgphy_status, brgphy_5755_reset,
144 1.34.14.2 markd };
145 1.34.14.2 markd
146 1.34.14.2 markd
147 1.34.14.2 markd static const struct mii_phydesc brgphys[] = {
148 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400,
149 1.34.14.2 markd MII_STR_BROADCOM_BCM5400 },
150 1.34.14.2 markd
151 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401,
152 1.34.14.2 markd MII_STR_BROADCOM_BCM5401 },
153 1.34.14.2 markd
154 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411,
155 1.34.14.2 markd MII_STR_BROADCOM_BCM5411 },
156 1.34.14.2 markd
157 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421,
158 1.34.14.2 markd MII_STR_BROADCOM_BCM5421 },
159 1.34.14.2 markd
160 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701,
161 1.34.14.2 markd MII_STR_BROADCOM_BCM5701 },
162 1.34.14.2 markd
163 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703,
164 1.34.14.2 markd MII_STR_BROADCOM_BCM5703 },
165 1.34.14.2 markd
166 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704,
167 1.34.14.2 markd MII_STR_BROADCOM_BCM5704 },
168 1.34.14.2 markd
169 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705,
170 1.34.14.2 markd MII_STR_BROADCOM_BCM5705 },
171 1.34.14.2 markd
172 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714,
173 1.34.14.2 markd MII_STR_BROADCOM_BCM5714 },
174 1.34.14.2 markd
175 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750,
176 1.34.14.2 markd MII_STR_BROADCOM_BCM5750 },
177 1.34.14.2 markd
178 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752,
179 1.34.14.2 markd MII_STR_BROADCOM_BCM5752 },
180 1.34.14.2 markd
181 1.34.14.2 markd { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780,
182 1.34.14.2 markd MII_STR_BROADCOM_BCM5780 },
183 1.34.14.2 markd
184 1.34.14.2 markd { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755,
185 1.34.14.2 markd MII_STR_BROADCOM2_BCM5755 },
186 1.34.14.2 markd
187 1.34.14.2 markd { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754,
188 1.34.14.2 markd MII_STR_BROADCOM2_BCM5754 },
189 1.34.14.2 markd
190 1.34.14.2 markd { 0, 0,
191 1.34.14.2 markd NULL },
192 1.34.14.2 markd };
193 1.34.14.2 markd
194 1.34.14.2 markd static void bcm5401_load_dspcode(struct mii_softc *);
195 1.34.14.2 markd static void bcm5411_load_dspcode(struct mii_softc *);
196 1.34.14.2 markd static void bcm5703_load_dspcode(struct mii_softc *);
197 1.34.14.2 markd static void bcm5704_load_dspcode(struct mii_softc *);
198 1.34.14.2 markd static void bcm5750_load_dspcode(struct mii_softc *);
199 1.34.14.2 markd static void bcm5755_load_dspcode(struct mii_softc *);
200 1.34.14.2 markd
201 1.34.14.2 markd static int
202 1.34.14.2 markd brgphymatch(struct device *parent, struct cfdata *match,
203 1.34.14.2 markd void *aux)
204 1.34.14.2 markd {
205 1.34.14.2 markd struct mii_attach_args *ma = aux;
206 1.34.14.2 markd
207 1.34.14.2 markd if (mii_phy_match(ma, brgphys) != NULL)
208 1.34.14.2 markd return (10);
209 1.34.14.2 markd
210 1.34.14.2 markd return (0);
211 1.34.14.2 markd }
212 1.34.14.2 markd
213 1.34.14.2 markd static void
214 1.34.14.2 markd brgphyattach(struct device *parent, struct device *self, void *aux)
215 1.34.14.2 markd {
216 1.34.14.2 markd struct mii_softc *sc = device_private(self);
217 1.34.14.2 markd struct mii_attach_args *ma = aux;
218 1.34.14.2 markd struct mii_data *mii = ma->mii_data;
219 1.34.14.2 markd const struct mii_phydesc *mpd;
220 1.34.14.2 markd
221 1.34.14.2 markd mpd = mii_phy_match(ma, brgphys);
222 1.34.14.2 markd aprint_naive(": Media interface\n");
223 1.34.14.2 markd aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
224 1.34.14.2 markd
225 1.34.14.2 markd sc->mii_inst = mii->mii_instance;
226 1.34.14.2 markd sc->mii_phy = ma->mii_phyno;
227 1.34.14.2 markd sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
228 1.34.14.2 markd sc->mii_pdata = mii;
229 1.34.14.2 markd sc->mii_flags = ma->mii_flags;
230 1.34.14.2 markd sc->mii_anegticks = MII_ANEGTICKS;
231 1.34.14.2 markd
232 1.34.14.2 markd switch (MII_MODEL(ma->mii_id2)) {
233 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5400:
234 1.34.14.2 markd sc->mii_funcs = &brgphy_5401_funcs;
235 1.34.14.2 markd aprint_normal("%s: using BCM5401 DSP patch\n",
236 1.34.14.2 markd sc->mii_dev.dv_xname);
237 1.34.14.2 markd break;
238 1.34.14.2 markd
239 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5401:
240 1.34.14.2 markd if (MII_REV(ma->mii_id2) == 1 || MII_REV(ma->mii_id2) == 3) {
241 1.34.14.2 markd sc->mii_funcs = &brgphy_5401_funcs;
242 1.34.14.2 markd aprint_normal("%s: using BCM5401 DSP patch\n",
243 1.34.14.2 markd sc->mii_dev.dv_xname);
244 1.34.14.2 markd } else
245 1.34.14.2 markd sc->mii_funcs = &brgphy_funcs;
246 1.34.14.2 markd break;
247 1.34.14.2 markd
248 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5411:
249 1.34.14.2 markd sc->mii_funcs = &brgphy_5411_funcs;
250 1.34.14.2 markd aprint_normal("%s: using BCM5411 DSP patch\n",
251 1.34.14.2 markd sc->mii_dev.dv_xname);
252 1.34.14.2 markd break;
253 1.34.14.2 markd
254 1.34.14.2 markd #ifdef notyet /* unverified, untested */
255 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5703:
256 1.34.14.2 markd sc->mii_funcs = &brgphy_5703_funcs;
257 1.34.14.2 markd aprint_normal("%s: using BCM5703 DSP patch\n",
258 1.34.14.2 markd sc->mii_dev.dv_xname);
259 1.34.14.2 markd break;
260 1.34.14.2 markd #endif
261 1.34.14.2 markd
262 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5704:
263 1.34.14.2 markd sc->mii_funcs = &brgphy_5704_funcs;
264 1.34.14.2 markd aprint_normal("%s: using BCM5704 DSP patch\n",
265 1.34.14.2 markd sc->mii_dev.dv_xname);
266 1.34.14.2 markd break;
267 1.34.14.2 markd
268 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5705:
269 1.34.14.2 markd sc->mii_funcs = &brgphy_5705_funcs;
270 1.34.14.2 markd break;
271 1.34.14.2 markd
272 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5714:
273 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5780:
274 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5750:
275 1.34.14.2 markd case MII_MODEL_BROADCOM_BCM5752:
276 1.34.14.2 markd sc->mii_funcs = &brgphy_5750_funcs;
277 1.34.14.2 markd break;
278 1.34.14.2 markd
279 1.34.14.2 markd case MII_MODEL_BROADCOM2_BCM5754:
280 1.34.14.2 markd case MII_MODEL_BROADCOM2_BCM5755:
281 1.34.14.2 markd sc->mii_funcs = &brgphy_5755_funcs;
282 1.34.14.2 markd break;
283 1.34.14.2 markd
284 1.34.14.2 markd default:
285 1.34.14.2 markd sc->mii_funcs = &brgphy_funcs;
286 1.34.14.2 markd break;
287 1.34.14.2 markd }
288 1.34.14.2 markd
289 1.34.14.2 markd PHY_RESET(sc);
290 1.34.14.2 markd
291 1.34.14.2 markd sc->mii_capabilities =
292 1.34.14.2 markd PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
293 1.34.14.2 markd if (sc->mii_capabilities & BMSR_EXTSTAT)
294 1.34.14.2 markd sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
295 1.34.14.2 markd
296 1.34.14.2 markd aprint_normal("%s: ", sc->mii_dev.dv_xname);
297 1.34.14.2 markd if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
298 1.34.14.2 markd (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
299 1.34.14.2 markd aprint_error("no media present");
300 1.34.14.2 markd else
301 1.34.14.2 markd mii_phy_add_media(sc);
302 1.34.14.2 markd aprint_normal("\n");
303 1.34.14.2 markd }
304 1.34.14.2 markd
305 1.34.14.2 markd static int
306 1.34.14.2 markd brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
307 1.34.14.2 markd {
308 1.34.14.2 markd struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
309 1.34.14.2 markd int reg, speed, gig;
310 1.34.14.2 markd
311 1.34.14.2 markd switch (cmd) {
312 1.34.14.2 markd case MII_POLLSTAT:
313 1.34.14.2 markd /*
314 1.34.14.2 markd * If we're not polling our PHY instance, just return.
315 1.34.14.2 markd */
316 1.34.14.2 markd if (IFM_INST(ife->ifm_media) != sc->mii_inst)
317 1.34.14.2 markd return (0);
318 1.34.14.2 markd break;
319 1.34.14.2 markd
320 1.34.14.2 markd case MII_MEDIACHG:
321 1.34.14.2 markd /*
322 1.34.14.2 markd * If the media indicates a different PHY instance,
323 1.34.14.2 markd * isolate ourselves.
324 1.34.14.2 markd */
325 1.34.14.2 markd if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
326 1.34.14.2 markd reg = PHY_READ(sc, MII_BMCR);
327 1.34.14.2 markd PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
328 1.34.14.2 markd return (0);
329 1.34.14.2 markd }
330 1.34.14.2 markd
331 1.34.14.2 markd /*
332 1.34.14.2 markd * If the interface is not up, don't do anything.
333 1.34.14.2 markd */
334 1.34.14.2 markd if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
335 1.34.14.2 markd break;
336 1.34.14.2 markd
337 1.34.14.2 markd PHY_RESET(sc); /* XXX hardware bug work-around */
338 1.34.14.2 markd
339 1.34.14.2 markd switch (IFM_SUBTYPE(ife->ifm_media)) {
340 1.34.14.2 markd case IFM_AUTO:
341 1.34.14.2 markd (void) brgphy_mii_phy_auto(sc);
342 1.34.14.2 markd break;
343 1.34.14.2 markd case IFM_1000_T:
344 1.34.14.2 markd speed = BMCR_S1000;
345 1.34.14.2 markd goto setit;
346 1.34.14.2 markd case IFM_100_TX:
347 1.34.14.2 markd speed = BMCR_S100;
348 1.34.14.2 markd goto setit;
349 1.34.14.2 markd case IFM_10_T:
350 1.34.14.2 markd speed = BMCR_S10;
351 1.34.14.2 markd setit:
352 1.34.14.2 markd brgphy_loop(sc);
353 1.34.14.2 markd if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
354 1.34.14.2 markd speed |= BMCR_FDX;
355 1.34.14.2 markd gig = GTCR_ADV_1000TFDX;
356 1.34.14.2 markd } else {
357 1.34.14.2 markd gig = GTCR_ADV_1000THDX;
358 1.34.14.2 markd }
359 1.34.14.2 markd
360 1.34.14.2 markd PHY_WRITE(sc, MII_100T2CR, 0);
361 1.34.14.2 markd PHY_WRITE(sc, MII_BMCR, speed);
362 1.34.14.2 markd PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
363 1.34.14.2 markd
364 1.34.14.2 markd if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
365 1.34.14.2 markd break;
366 1.34.14.2 markd
367 1.34.14.2 markd PHY_WRITE(sc, MII_100T2CR, gig);
368 1.34.14.2 markd PHY_WRITE(sc, MII_BMCR,
369 1.34.14.2 markd speed|BMCR_AUTOEN|BMCR_STARTNEG);
370 1.34.14.2 markd
371 1.34.14.2 markd if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)
372 1.34.14.2 markd break;
373 1.34.14.2 markd
374 1.34.14.2 markd if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
375 1.34.14.2 markd gig |= GTCR_MAN_MS | GTCR_ADV_MS;
376 1.34.14.2 markd PHY_WRITE(sc, MII_100T2CR, gig);
377 1.34.14.2 markd break;
378 1.34.14.2 markd default:
379 1.34.14.2 markd return (EINVAL);
380 1.34.14.2 markd }
381 1.34.14.2 markd break;
382 1.34.14.2 markd
383 1.34.14.2 markd case MII_TICK:
384 1.34.14.2 markd /*
385 1.34.14.2 markd * If we're not currently selected, just return.
386 1.34.14.2 markd */
387 1.34.14.2 markd if (IFM_INST(ife->ifm_media) != sc->mii_inst)
388 1.34.14.2 markd return (0);
389 1.34.14.2 markd
390 1.34.14.2 markd if (mii_phy_tick(sc) == EJUSTRETURN)
391 1.34.14.2 markd return (0);
392 1.34.14.2 markd break;
393 1.34.14.2 markd
394 1.34.14.2 markd case MII_DOWN:
395 1.34.14.2 markd mii_phy_down(sc);
396 1.34.14.2 markd return (0);
397 1.34.14.2 markd }
398 1.34.14.2 markd
399 1.34.14.2 markd /* Update the media status. */
400 1.34.14.2 markd mii_phy_status(sc);
401 1.34.14.2 markd
402 1.34.14.2 markd /*
403 1.34.14.2 markd * Callback if something changed. Note that we need to poke the DSP on
404 1.34.14.2 markd * the Broadcom PHYs if the media changes.
405 1.34.14.2 markd */
406 1.34.14.2 markd if (sc->mii_media_active != mii->mii_media_active ||
407 1.34.14.2 markd sc->mii_media_status != mii->mii_media_status ||
408 1.34.14.2 markd cmd == MII_MEDIACHG) {
409 1.34.14.2 markd mii_phy_update(sc, cmd);
410 1.34.14.2 markd if (sc->mii_funcs == &brgphy_5401_funcs)
411 1.34.14.2 markd bcm5401_load_dspcode(sc);
412 1.34.14.2 markd else if (sc->mii_funcs == &brgphy_5411_funcs)
413 1.34.14.2 markd bcm5411_load_dspcode(sc);
414 1.34.14.2 markd }
415 1.34.14.2 markd return (0);
416 1.34.14.2 markd }
417 1.34.14.2 markd
418 1.34.14.2 markd static void
419 1.34.14.2 markd brgphy_status(struct mii_softc *sc)
420 1.34.14.2 markd {
421 1.34.14.2 markd struct mii_data *mii = sc->mii_pdata;
422 1.34.14.2 markd struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
423 1.34.14.2 markd int bmcr, auxsts, gtsr;
424 1.34.14.2 markd
425 1.34.14.2 markd mii->mii_media_status = IFM_AVALID;
426 1.34.14.2 markd mii->mii_media_active = IFM_ETHER;
427 1.34.14.2 markd
428 1.34.14.2 markd auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS);
429 1.34.14.2 markd
430 1.34.14.2 markd if (auxsts & BRGPHY_AUXSTS_LINK)
431 1.34.14.2 markd mii->mii_media_status |= IFM_ACTIVE;
432 1.34.14.2 markd
433 1.34.14.2 markd bmcr = PHY_READ(sc, MII_BMCR);
434 1.34.14.2 markd if (bmcr & BMCR_ISO) {
435 1.34.14.2 markd mii->mii_media_active |= IFM_NONE;
436 1.34.14.2 markd mii->mii_media_status = 0;
437 1.34.14.2 markd return;
438 1.34.14.2 markd }
439 1.34.14.2 markd
440 1.34.14.2 markd if (bmcr & BMCR_LOOP)
441 1.34.14.2 markd mii->mii_media_active |= IFM_LOOP;
442 1.34.14.2 markd
443 1.34.14.2 markd if (bmcr & BMCR_AUTOEN) {
444 1.34.14.2 markd /*
445 1.34.14.2 markd * The media status bits are only valid of autonegotiation
446 1.34.14.2 markd * has completed (or it's disabled).
447 1.34.14.2 markd */
448 1.34.14.2 markd if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) {
449 1.34.14.2 markd /* Erg, still trying, I guess... */
450 1.34.14.2 markd mii->mii_media_active |= IFM_NONE;
451 1.34.14.2 markd return;
452 1.34.14.2 markd }
453 1.34.14.2 markd
454 1.34.14.2 markd switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
455 1.34.14.2 markd case BRGPHY_RES_1000FD:
456 1.34.14.2 markd mii->mii_media_active |= IFM_1000_T|IFM_FDX;
457 1.34.14.2 markd gtsr = PHY_READ(sc, MII_100T2SR);
458 1.34.14.2 markd if (gtsr & GTSR_MS_RES)
459 1.34.14.2 markd mii->mii_media_active |= IFM_ETH_MASTER;
460 1.34.14.2 markd break;
461 1.34.14.2 markd
462 1.34.14.2 markd case BRGPHY_RES_1000HD:
463 1.34.14.2 markd mii->mii_media_active |= IFM_1000_T;
464 1.34.14.2 markd gtsr = PHY_READ(sc, MII_100T2SR);
465 1.34.14.2 markd if (gtsr & GTSR_MS_RES)
466 1.34.14.2 markd mii->mii_media_active |= IFM_ETH_MASTER;
467 1.34.14.2 markd break;
468 1.34.14.2 markd
469 1.34.14.2 markd case BRGPHY_RES_100FD:
470 1.34.14.2 markd mii->mii_media_active |= IFM_100_TX|IFM_FDX;
471 1.34.14.2 markd break;
472 1.34.14.2 markd
473 1.34.14.2 markd case BRGPHY_RES_100T4:
474 1.34.14.2 markd mii->mii_media_active |= IFM_100_T4;
475 1.34.14.2 markd break;
476 1.34.14.2 markd
477 1.34.14.2 markd case BRGPHY_RES_100HD:
478 1.34.14.2 markd mii->mii_media_active |= IFM_100_TX;
479 1.34.14.2 markd break;
480 1.34.14.2 markd
481 1.34.14.2 markd case BRGPHY_RES_10FD:
482 1.34.14.2 markd mii->mii_media_active |= IFM_10_T|IFM_FDX;
483 1.34.14.2 markd break;
484 1.34.14.2 markd
485 1.34.14.2 markd case BRGPHY_RES_10HD:
486 1.34.14.2 markd mii->mii_media_active |= IFM_10_T;
487 1.34.14.2 markd break;
488 1.34.14.2 markd
489 1.34.14.2 markd default:
490 1.34.14.2 markd mii->mii_media_active |= IFM_NONE;
491 1.34.14.2 markd mii->mii_media_status = 0;
492 1.34.14.2 markd }
493 1.34.14.2 markd if (mii->mii_media_active & IFM_FDX)
494 1.34.14.2 markd mii->mii_media_active |= mii_phy_flowstatus(sc);
495 1.34.14.2 markd } else
496 1.34.14.2 markd mii->mii_media_active = ife->ifm_media;
497 1.34.14.2 markd }
498 1.34.14.2 markd
499 1.34.14.2 markd int
500 1.34.14.2 markd brgphy_mii_phy_auto(struct mii_softc *sc)
501 1.34.14.2 markd {
502 1.34.14.2 markd int anar, ktcr = 0;
503 1.34.14.2 markd
504 1.34.14.2 markd brgphy_loop(sc);
505 1.34.14.2 markd PHY_RESET(sc);
506 1.34.14.2 markd ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX;
507 1.34.14.2 markd if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
508 1.34.14.2 markd ktcr |= GTCR_MAN_MS|GTCR_ADV_MS;
509 1.34.14.2 markd PHY_WRITE(sc, MII_100T2CR, ktcr);
510 1.34.14.2 markd ktcr = PHY_READ(sc, MII_100T2CR);
511 1.34.14.2 markd DELAY(1000);
512 1.34.14.2 markd anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
513 1.34.14.2 markd if (sc->mii_flags & MIIF_DOPAUSE)
514 1.34.14.2 markd anar |= ANAR_FC| ANAR_X_PAUSE_ASYM;
515 1.34.14.2 markd
516 1.34.14.2 markd PHY_WRITE(sc, MII_ANAR, anar);
517 1.34.14.2 markd DELAY(1000);
518 1.34.14.2 markd PHY_WRITE(sc, MII_BMCR,
519 1.34.14.2 markd BMCR_AUTOEN | BMCR_STARTNEG);
520 1.34.14.2 markd PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
521 1.34.14.2 markd
522 1.34.14.2 markd return (EJUSTRETURN);
523 1.34.14.2 markd }
524 1.34.14.2 markd
525 1.34.14.2 markd void
526 1.34.14.2 markd brgphy_loop(struct mii_softc *sc)
527 1.34.14.2 markd {
528 1.34.14.2 markd u_int32_t bmsr;
529 1.34.14.2 markd int i;
530 1.34.14.2 markd
531 1.34.14.2 markd PHY_WRITE(sc, MII_BMCR, BMCR_LOOP);
532 1.34.14.2 markd for (i = 0; i < 15000; i++) {
533 1.34.14.2 markd bmsr = PHY_READ(sc, MII_BMSR);
534 1.34.14.2 markd if (!(bmsr & BMSR_LINK))
535 1.34.14.2 markd break;
536 1.34.14.2 markd DELAY(10);
537 1.34.14.2 markd }
538 1.34.14.2 markd }
539 1.34.14.2 markd
540 1.34.14.2 markd static void
541 1.34.14.2 markd brgphy_5401_reset(struct mii_softc *sc)
542 1.34.14.2 markd {
543 1.34.14.2 markd
544 1.34.14.2 markd mii_phy_reset(sc);
545 1.34.14.2 markd bcm5401_load_dspcode(sc);
546 1.34.14.2 markd }
547 1.34.14.2 markd
548 1.34.14.2 markd static void
549 1.34.14.2 markd brgphy_5411_reset(struct mii_softc *sc)
550 1.34.14.2 markd {
551 1.34.14.2 markd
552 1.34.14.2 markd mii_phy_reset(sc);
553 1.34.14.2 markd bcm5411_load_dspcode(sc);
554 1.34.14.2 markd }
555 1.34.14.2 markd
556 1.34.14.2 markd
557 1.34.14.2 markd static void
558 1.34.14.2 markd brgphy_5703_reset(struct mii_softc *sc)
559 1.34.14.2 markd {
560 1.34.14.2 markd
561 1.34.14.2 markd mii_phy_reset(sc);
562 1.34.14.2 markd bcm5703_load_dspcode(sc);
563 1.34.14.2 markd }
564 1.34.14.2 markd
565 1.34.14.2 markd static void
566 1.34.14.2 markd brgphy_5704_reset(struct mii_softc *sc)
567 1.34.14.2 markd {
568 1.34.14.2 markd
569 1.34.14.2 markd mii_phy_reset(sc);
570 1.34.14.2 markd bcm5704_load_dspcode(sc);
571 1.34.14.2 markd }
572 1.34.14.2 markd
573 1.34.14.2 markd /*
574 1.34.14.2 markd * Hardware bug workaround. Do nothing since after
575 1.34.14.2 markd * reset the 5705 PHY would get stuck in 10/100 MII mode.
576 1.34.14.2 markd */
577 1.34.14.2 markd
578 1.34.14.2 markd static void
579 1.34.14.2 markd brgphy_5705_reset(struct mii_softc *sc)
580 1.34.14.2 markd {
581 1.34.14.2 markd }
582 1.34.14.2 markd
583 1.34.14.2 markd static void
584 1.34.14.2 markd brgphy_5750_reset(struct mii_softc *sc)
585 1.34.14.2 markd {
586 1.34.14.2 markd mii_phy_reset(sc);
587 1.34.14.2 markd bcm5750_load_dspcode(sc);
588 1.34.14.2 markd }
589 1.34.14.2 markd
590 1.34.14.2 markd static void
591 1.34.14.2 markd brgphy_5755_reset(struct mii_softc *sc)
592 1.34.14.2 markd {
593 1.34.14.2 markd mii_phy_reset(sc);
594 1.34.14.2 markd bcm5755_load_dspcode(sc);
595 1.34.14.2 markd }
596 1.34.14.2 markd
597 1.34.14.2 markd /* Turn off tap power management on 5401. */
598 1.34.14.2 markd static void
599 1.34.14.2 markd bcm5401_load_dspcode(struct mii_softc *sc)
600 1.34.14.2 markd {
601 1.34.14.2 markd static const struct {
602 1.34.14.2 markd int reg;
603 1.34.14.2 markd uint16_t val;
604 1.34.14.2 markd } dspcode[] = {
605 1.34.14.2 markd { BRGPHY_MII_AUXCTL, 0x0c20 },
606 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
607 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
608 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
609 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
610 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
611 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
612 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
613 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
614 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
615 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
616 1.34.14.2 markd { 0, 0 },
617 1.34.14.2 markd };
618 1.34.14.2 markd int i;
619 1.34.14.2 markd
620 1.34.14.2 markd for (i = 0; dspcode[i].reg != 0; i++)
621 1.34.14.2 markd PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
622 1.34.14.2 markd delay(40);
623 1.34.14.2 markd }
624 1.34.14.2 markd
625 1.34.14.2 markd static void
626 1.34.14.2 markd bcm5411_load_dspcode(struct mii_softc *sc)
627 1.34.14.2 markd {
628 1.34.14.2 markd static const struct {
629 1.34.14.2 markd int reg;
630 1.34.14.2 markd uint16_t val;
631 1.34.14.2 markd } dspcode[] = {
632 1.34.14.2 markd { 0x1c, 0x8c23 },
633 1.34.14.2 markd { 0x1c, 0x8ca3 },
634 1.34.14.2 markd { 0x1c, 0x8c23 },
635 1.34.14.2 markd { 0, 0 },
636 1.34.14.2 markd };
637 1.34.14.2 markd int i;
638 1.34.14.2 markd
639 1.34.14.2 markd for (i = 0; dspcode[i].reg != 0; i++)
640 1.34.14.2 markd PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
641 1.34.14.2 markd }
642 1.34.14.2 markd
643 1.34.14.2 markd static void
644 1.34.14.2 markd bcm5703_load_dspcode(struct mii_softc *sc)
645 1.34.14.2 markd {
646 1.34.14.2 markd static const struct {
647 1.34.14.2 markd int reg;
648 1.34.14.2 markd uint16_t val;
649 1.34.14.2 markd } dspcode[] = {
650 1.34.14.2 markd { BRGPHY_MII_AUXCTL, 0x0c00 },
651 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
652 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
653 1.34.14.2 markd { 0, 0 },
654 1.34.14.2 markd };
655 1.34.14.2 markd int i;
656 1.34.14.2 markd
657 1.34.14.2 markd for (i = 0; dspcode[i].reg != 0; i++)
658 1.34.14.2 markd PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
659 1.34.14.2 markd }
660 1.34.14.2 markd
661 1.34.14.2 markd static void
662 1.34.14.2 markd bcm5704_load_dspcode(struct mii_softc *sc)
663 1.34.14.2 markd {
664 1.34.14.2 markd static const struct {
665 1.34.14.2 markd int reg;
666 1.34.14.2 markd uint16_t val;
667 1.34.14.2 markd } dspcode[] = {
668 1.34.14.2 markd { 0x1c, 0x8d68 },
669 1.34.14.2 markd { 0x1c, 0x8d68 },
670 1.34.14.2 markd { 0, 0 },
671 1.34.14.2 markd };
672 1.34.14.2 markd int i;
673 1.34.14.2 markd
674 1.34.14.2 markd for (i = 0; dspcode[i].reg != 0; i++)
675 1.34.14.2 markd PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
676 1.34.14.2 markd }
677 1.34.14.2 markd
678 1.34.14.2 markd static void
679 1.34.14.2 markd bcm5750_load_dspcode(struct mii_softc *sc)
680 1.34.14.2 markd {
681 1.34.14.2 markd static const struct {
682 1.34.14.2 markd int reg;
683 1.34.14.2 markd uint16_t val;
684 1.34.14.2 markd } dspcode[] = {
685 1.34.14.2 markd { BRGPHY_MII_AUXCTL, 0x0c00 },
686 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
687 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x310b },
688 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
689 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
690 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
691 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
692 1.34.14.2 markd { BRGPHY_MII_AUXCTL, 0x0400 },
693 1.34.14.2 markd { 0, 0 },
694 1.34.14.2 markd };
695 1.34.14.2 markd int i;
696 1.34.14.2 markd
697 1.34.14.2 markd for (i = 0; dspcode[i].reg != 0; i++)
698 1.34.14.2 markd PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
699 1.34.14.2 markd }
700 1.34.14.2 markd
701 1.34.14.2 markd static void
702 1.34.14.2 markd bcm5755_load_dspcode(struct mii_softc *sc)
703 1.34.14.2 markd {
704 1.34.14.2 markd static const struct {
705 1.34.14.2 markd int reg;
706 1.34.14.2 markd uint16_t val;
707 1.34.14.2 markd } dspcode[] = {
708 1.34.14.2 markd { BRGPHY_MII_AUXCTL, 0x0c00 },
709 1.34.14.2 markd { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
710 1.34.14.2 markd { BRGPHY_MII_DSP_RW_PORT, 0x010b },
711 1.34.14.2 markd
712 1.34.14.2 markd { BRGPHY_MII_AUXCTL, 0x0400 },
713 1.34.14.2 markd { 0, 0 },
714 1.34.14.2 markd };
715 1.34.14.2 markd int i;
716 1.34.14.2 markd
717 1.34.14.2 markd for (i = 0; dspcode[i].reg != 0; i++)
718 1.34.14.2 markd PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
719 1.34.14.2 markd }
720