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brgphy.c revision 1.40.8.1
      1  1.40.8.1      matt /*	$NetBSD: brgphy.c,v 1.40.8.1 2010/04/21 00:27:39 matt Exp $	*/
      2       1.1   thorpej 
      3       1.1   thorpej /*-
      4       1.1   thorpej  * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
      5       1.1   thorpej  * All rights reserved.
      6       1.1   thorpej  *
      7       1.1   thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1   thorpej  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9       1.1   thorpej  * NASA Ames Research Center.
     10       1.1   thorpej  *
     11       1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     12       1.1   thorpej  * modification, are permitted provided that the following conditions
     13       1.1   thorpej  * are met:
     14       1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     15       1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     16       1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     18       1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     19       1.1   thorpej  *
     20       1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21       1.1   thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22       1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23       1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24       1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25       1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26       1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27       1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28       1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29       1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30       1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     31       1.1   thorpej  */
     32       1.1   thorpej 
     33       1.1   thorpej /*
     34       1.1   thorpej  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
     35       1.1   thorpej  *
     36       1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     37       1.1   thorpej  * modification, are permitted provided that the following conditions
     38       1.1   thorpej  * are met:
     39       1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     40       1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     41       1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     42       1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     43       1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     44       1.1   thorpej  * 3. All advertising materials mentioning features or use of this software
     45       1.1   thorpej  *    must display the following acknowledgement:
     46       1.1   thorpej  *	This product includes software developed by Manuel Bouyer.
     47       1.1   thorpej  * 4. The name of the author may not be used to endorse or promote products
     48       1.1   thorpej  *    derived from this software without specific prior written permission.
     49       1.1   thorpej  *
     50       1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     51       1.1   thorpej  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     52       1.1   thorpej  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     53       1.1   thorpej  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     54       1.1   thorpej  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     55       1.1   thorpej  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     56       1.1   thorpej  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     57       1.1   thorpej  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     58       1.1   thorpej  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     59       1.1   thorpej  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     60       1.1   thorpej  */
     61       1.1   thorpej 
     62       1.1   thorpej /*
     63       1.1   thorpej  * driver for the Broadcom BCM5400 Gig-E PHY.
     64       1.1   thorpej  *
     65       1.1   thorpej  * Programming information for this PHY was gleaned from FreeBSD
     66       1.1   thorpej  * (they were apparently able to get a datasheet from Broadcom).
     67       1.1   thorpej  */
     68       1.5     lukem 
     69       1.5     lukem #include <sys/cdefs.h>
     70  1.40.8.1      matt __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.40.8.1 2010/04/21 00:27:39 matt Exp $");
     71       1.1   thorpej 
     72       1.1   thorpej #include <sys/param.h>
     73       1.1   thorpej #include <sys/systm.h>
     74       1.1   thorpej #include <sys/kernel.h>
     75       1.1   thorpej #include <sys/device.h>
     76       1.1   thorpej #include <sys/socket.h>
     77       1.1   thorpej #include <sys/errno.h>
     78  1.40.8.1      matt #include <prop/proplib.h>
     79       1.1   thorpej 
     80       1.1   thorpej #include <net/if.h>
     81       1.1   thorpej #include <net/if_media.h>
     82       1.1   thorpej 
     83       1.1   thorpej #include <dev/mii/mii.h>
     84       1.1   thorpej #include <dev/mii/miivar.h>
     85       1.1   thorpej #include <dev/mii/miidevs.h>
     86       1.1   thorpej 
     87       1.1   thorpej #include <dev/mii/brgphyreg.h>
     88  1.40.8.1      matt #include <dev/pci/if_bgereg.h>
     89       1.1   thorpej 
     90      1.39   xtraeme static int	brgphymatch(device_t, cfdata_t, void *);
     91      1.39   xtraeme static void	brgphyattach(device_t, device_t, void *);
     92       1.1   thorpej 
     93  1.40.8.1      matt struct brgphy_softc {
     94  1.40.8.1      matt 	struct mii_softc sc_mii;
     95  1.40.8.1      matt 	int sc_isbge;
     96  1.40.8.1      matt 	int sc_isbnx;
     97  1.40.8.1      matt 	int sc_bge_flags;
     98  1.40.8.1      matt 	int sc_bnx_flags;
     99  1.40.8.1      matt };
    100  1.40.8.1      matt 
    101  1.40.8.1      matt CFATTACH_DECL_NEW(brgphy, sizeof(struct brgphy_softc),
    102      1.13   thorpej     brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate);
    103       1.1   thorpej 
    104      1.21   thorpej static int	brgphy_service(struct mii_softc *, struct mii_data *, int);
    105      1.21   thorpej static void	brgphy_status(struct mii_softc *);
    106      1.32   msaitoh static int	brgphy_mii_phy_auto(struct mii_softc *);
    107      1.32   msaitoh static void	brgphy_loop(struct mii_softc *);
    108  1.40.8.1      matt static void	brgphy_reset(struct mii_softc *);
    109  1.40.8.1      matt static void	brgphy_bcm5401_dspcode(struct mii_softc *);
    110  1.40.8.1      matt static void	brgphy_bcm5411_dspcode(struct mii_softc *);
    111  1.40.8.1      matt static void	brgphy_bcm5421_dspcode(struct mii_softc *);
    112  1.40.8.1      matt static void	brgphy_bcm54k2_dspcode(struct mii_softc *);
    113  1.40.8.1      matt static void	brgphy_adc_bug(struct mii_softc *);
    114  1.40.8.1      matt static void	brgphy_5704_a0_bug(struct mii_softc *);
    115  1.40.8.1      matt static void	brgphy_ber_bug(struct mii_softc *);
    116  1.40.8.1      matt static void	brgphy_crc_bug(struct mii_softc *);
    117       1.1   thorpej 
    118      1.10   thorpej 
    119      1.21   thorpej static const struct mii_phy_funcs brgphy_funcs = {
    120  1.40.8.1      matt 	brgphy_service, brgphy_status, brgphy_reset,
    121       1.1   thorpej };
    122       1.1   thorpej 
    123      1.21   thorpej static const struct mii_phydesc brgphys[] = {
    124       1.1   thorpej 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5400,
    125       1.1   thorpej 	  MII_STR_BROADCOM_BCM5400 },
    126       1.2   thorpej 
    127       1.1   thorpej 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5401,
    128       1.1   thorpej 	  MII_STR_BROADCOM_BCM5401 },
    129       1.2   thorpej 
    130       1.1   thorpej 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5411,
    131       1.1   thorpej 	  MII_STR_BROADCOM_BCM5411 },
    132       1.9   thorpej 
    133       1.9   thorpej 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5421,
    134       1.9   thorpej 	  MII_STR_BROADCOM_BCM5421 },
    135       1.7      fvdl 
    136  1.40.8.1      matt 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM54K2,
    137  1.40.8.1      matt 	  MII_STR_BROADCOM_BCM54K2 },
    138  1.40.8.1      matt 
    139  1.40.8.1      matt 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5462,
    140  1.40.8.1      matt 	  MII_STR_BROADCOM_BCM5462 },
    141  1.40.8.1      matt 
    142       1.7      fvdl 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5701,
    143       1.7      fvdl 	  MII_STR_BROADCOM_BCM5701 },
    144      1.14      matt 
    145      1.14      matt 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5703,
    146      1.14      matt 	  MII_STR_BROADCOM_BCM5703 },
    147       1.1   thorpej 
    148      1.15  jonathan 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5704,
    149      1.15  jonathan 	  MII_STR_BROADCOM_BCM5704 },
    150      1.15  jonathan 
    151      1.25  jonathan 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5705,
    152      1.25  jonathan 	  MII_STR_BROADCOM_BCM5705 },
    153      1.25  jonathan 
    154      1.24  jonathan 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5714,
    155      1.24  jonathan 	  MII_STR_BROADCOM_BCM5714 },
    156      1.18   hannken 
    157      1.22      cube 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5750,
    158      1.22      cube 	  MII_STR_BROADCOM_BCM5750 },
    159      1.22      cube 
    160      1.31   tsutsui 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5752,
    161      1.31   tsutsui 	  MII_STR_BROADCOM_BCM5752 },
    162      1.31   tsutsui 
    163      1.27  jonathan 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5780,
    164      1.27  jonathan 	  MII_STR_BROADCOM_BCM5780 },
    165      1.27  jonathan 
    166      1.36     markd 	{ MII_OUI_BROADCOM,		MII_MODEL_BROADCOM_BCM5708C,
    167      1.36     markd 	  MII_STR_BROADCOM_BCM5708C },
    168      1.36     markd 
    169  1.40.8.1      matt 	{ MII_OUI_BROADCOM2,		MII_MODEL_BROADCOM2_BCM5709C,
    170  1.40.8.1      matt 	  MII_STR_BROADCOM2_BCM5709C },
    171  1.40.8.1      matt 
    172  1.40.8.1      matt 	{ MII_OUI_BROADCOM2,		MII_MODEL_BROADCOM2_BCM5709CAX,
    173  1.40.8.1      matt 	  MII_STR_BROADCOM2_BCM5709CAX },
    174  1.40.8.1      matt 
    175  1.40.8.1      matt 	{ MII_OUI_BROADCOM2,		MII_MODEL_BROADCOM2_BCM5722,
    176  1.40.8.1      matt 	  MII_STR_BROADCOM2_BCM5722 },
    177  1.40.8.1      matt 
    178      1.34     markd 	{ MII_OUI_BROADCOM2,		MII_MODEL_BROADCOM2_BCM5755,
    179      1.34     markd 	  MII_STR_BROADCOM2_BCM5755 },
    180      1.34     markd 
    181      1.34     markd 	{ MII_OUI_BROADCOM2,		MII_MODEL_BROADCOM2_BCM5754,
    182      1.34     markd 	  MII_STR_BROADCOM2_BCM5754 },
    183      1.34     markd 
    184      1.40    cegger 	{ MII_OUI_xxBROADCOM_ALT1,	MII_MODEL_xxBROADCOM_ALT1_BCM5906,
    185      1.40    cegger 	  MII_STR_xxBROADCOM_ALT1_BCM5906 },
    186      1.40    cegger 
    187       1.1   thorpej 	{ 0,				0,
    188       1.1   thorpej 	  NULL },
    189       1.1   thorpej };
    190       1.1   thorpej 
    191      1.21   thorpej static int
    192  1.40.8.1      matt brgphymatch(struct device *parent, struct cfdata *match, void *aux)
    193       1.1   thorpej {
    194       1.1   thorpej 	struct mii_attach_args *ma = aux;
    195       1.1   thorpej 
    196       1.2   thorpej 	if (mii_phy_match(ma, brgphys) != NULL)
    197       1.1   thorpej 		return (10);
    198       1.1   thorpej 
    199       1.1   thorpej 	return (0);
    200       1.1   thorpej }
    201       1.1   thorpej 
    202      1.21   thorpej static void
    203      1.29  christos brgphyattach(struct device *parent, struct device *self, void *aux)
    204       1.1   thorpej {
    205  1.40.8.1      matt 	struct brgphy_softc *bsc = device_private(self);
    206  1.40.8.1      matt 	struct mii_softc *sc = &bsc->sc_mii;
    207       1.1   thorpej 	struct mii_attach_args *ma = aux;
    208       1.1   thorpej 	struct mii_data *mii = ma->mii_data;
    209       1.2   thorpej 	const struct mii_phydesc *mpd;
    210  1.40.8.1      matt 	prop_dictionary_t dict;
    211       1.1   thorpej 
    212       1.2   thorpej 	mpd = mii_phy_match(ma, brgphys);
    213      1.17   thorpej 	aprint_naive(": Media interface\n");
    214      1.17   thorpej 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    215       1.1   thorpej 
    216      1.39   xtraeme 	sc->mii_dev = self;
    217       1.1   thorpej 	sc->mii_inst = mii->mii_instance;
    218       1.1   thorpej 	sc->mii_phy = ma->mii_phyno;
    219      1.32   msaitoh 	sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
    220  1.40.8.1      matt 	sc->mii_mpd_rev = MII_REV(ma->mii_id2);
    221       1.1   thorpej 	sc->mii_pdata = mii;
    222       1.6   thorpej 	sc->mii_flags = ma->mii_flags;
    223      1.30  christos 	sc->mii_anegticks = MII_ANEGTICKS;
    224  1.40.8.1      matt 	sc->mii_funcs = &brgphy_funcs;
    225      1.10   thorpej 
    226       1.1   thorpej 	PHY_RESET(sc);
    227       1.1   thorpej 
    228       1.1   thorpej 	sc->mii_capabilities =
    229       1.1   thorpej 	    PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
    230       1.1   thorpej 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    231       1.1   thorpej 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
    232       1.1   thorpej 
    233      1.39   xtraeme 	aprint_normal_dev(self, "");
    234       1.1   thorpej 	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
    235       1.1   thorpej 	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
    236      1.17   thorpej 		aprint_error("no media present");
    237       1.1   thorpej 	else
    238       1.1   thorpej 		mii_phy_add_media(sc);
    239      1.17   thorpej 	aprint_normal("\n");
    240      1.35  jmcneill 
    241  1.40.8.1      matt 	if (device_is_a(parent, "bge")) {
    242  1.40.8.1      matt 		bsc->sc_isbge = 1;
    243  1.40.8.1      matt 		dict = device_properties(parent);
    244  1.40.8.1      matt 		prop_dictionary_get_uint32(dict, "phyflags",
    245  1.40.8.1      matt 		    &bsc->sc_bge_flags);
    246  1.40.8.1      matt 	} else if (device_is_a(parent, "bnx")) {
    247  1.40.8.1      matt 		bsc->sc_isbnx = 1;
    248  1.40.8.1      matt 		dict = device_properties(parent);
    249  1.40.8.1      matt 		prop_dictionary_get_uint32(dict, "phyflags",
    250  1.40.8.1      matt 		    &bsc->sc_bnx_flags);
    251  1.40.8.1      matt 	}
    252  1.40.8.1      matt 
    253      1.35  jmcneill 	if (!pmf_device_register(self, NULL, mii_phy_resume))
    254      1.35  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
    255       1.1   thorpej }
    256       1.1   thorpej 
    257      1.21   thorpej static int
    258       1.4   thorpej brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    259       1.1   thorpej {
    260       1.1   thorpej 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    261      1.32   msaitoh 	int reg, speed, gig;
    262       1.1   thorpej 
    263       1.1   thorpej 	switch (cmd) {
    264       1.1   thorpej 	case MII_POLLSTAT:
    265       1.1   thorpej 		/*
    266       1.1   thorpej 		 * If we're not polling our PHY instance, just return.
    267       1.1   thorpej 		 */
    268       1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    269       1.1   thorpej 			return (0);
    270       1.1   thorpej 		break;
    271       1.1   thorpej 
    272       1.1   thorpej 	case MII_MEDIACHG:
    273       1.1   thorpej 		/*
    274       1.1   thorpej 		 * If the media indicates a different PHY instance,
    275       1.1   thorpej 		 * isolate ourselves.
    276       1.1   thorpej 		 */
    277       1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    278       1.1   thorpej 			reg = PHY_READ(sc, MII_BMCR);
    279       1.1   thorpej 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
    280       1.1   thorpej 			return (0);
    281       1.1   thorpej 		}
    282       1.1   thorpej 
    283       1.1   thorpej 		/*
    284       1.1   thorpej 		 * If the interface is not up, don't do anything.
    285       1.1   thorpej 		 */
    286       1.1   thorpej 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    287       1.1   thorpej 			break;
    288       1.1   thorpej 
    289      1.32   msaitoh 		PHY_RESET(sc); /* XXX hardware bug work-around */
    290      1.32   msaitoh 
    291      1.32   msaitoh 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    292      1.32   msaitoh 		case IFM_AUTO:
    293      1.32   msaitoh 			(void) brgphy_mii_phy_auto(sc);
    294      1.32   msaitoh 			break;
    295      1.32   msaitoh 		case IFM_1000_T:
    296      1.32   msaitoh 			speed = BMCR_S1000;
    297      1.32   msaitoh 			goto setit;
    298      1.32   msaitoh 		case IFM_100_TX:
    299      1.32   msaitoh 			speed = BMCR_S100;
    300      1.32   msaitoh 			goto setit;
    301      1.32   msaitoh 		case IFM_10_T:
    302      1.32   msaitoh 			speed = BMCR_S10;
    303      1.32   msaitoh setit:
    304      1.32   msaitoh 			brgphy_loop(sc);
    305      1.32   msaitoh 			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
    306      1.32   msaitoh 				speed |= BMCR_FDX;
    307      1.32   msaitoh 				gig = GTCR_ADV_1000TFDX;
    308      1.32   msaitoh 			} else {
    309      1.32   msaitoh 				gig = GTCR_ADV_1000THDX;
    310      1.32   msaitoh 			}
    311      1.32   msaitoh 
    312      1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, 0);
    313      1.32   msaitoh 			PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
    314  1.40.8.1      matt 			PHY_WRITE(sc, MII_BMCR, speed);
    315      1.32   msaitoh 
    316      1.32   msaitoh 			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
    317      1.32   msaitoh 				break;
    318      1.32   msaitoh 
    319      1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, gig);
    320      1.32   msaitoh 			PHY_WRITE(sc, MII_BMCR,
    321      1.32   msaitoh 			    speed|BMCR_AUTOEN|BMCR_STARTNEG);
    322      1.32   msaitoh 
    323      1.32   msaitoh 			if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)
    324      1.33   msaitoh 				break;
    325      1.32   msaitoh 
    326      1.32   msaitoh 			if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
    327      1.32   msaitoh 				gig |= GTCR_MAN_MS | GTCR_ADV_MS;
    328      1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, gig);
    329      1.32   msaitoh 			break;
    330      1.32   msaitoh 		default:
    331      1.32   msaitoh 			return (EINVAL);
    332      1.32   msaitoh 		}
    333       1.1   thorpej 		break;
    334       1.1   thorpej 
    335       1.1   thorpej 	case MII_TICK:
    336       1.1   thorpej 		/*
    337       1.1   thorpej 		 * If we're not currently selected, just return.
    338       1.1   thorpej 		 */
    339       1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    340       1.1   thorpej 			return (0);
    341       1.1   thorpej 
    342       1.1   thorpej 		if (mii_phy_tick(sc) == EJUSTRETURN)
    343       1.1   thorpej 			return (0);
    344       1.1   thorpej 		break;
    345       1.1   thorpej 
    346       1.1   thorpej 	case MII_DOWN:
    347       1.1   thorpej 		mii_phy_down(sc);
    348       1.1   thorpej 		return (0);
    349       1.1   thorpej 	}
    350       1.1   thorpej 
    351       1.1   thorpej 	/* Update the media status. */
    352       1.1   thorpej 	mii_phy_status(sc);
    353       1.1   thorpej 
    354      1.10   thorpej 	/*
    355      1.32   msaitoh 	 * Callback if something changed. Note that we need to poke the DSP on
    356      1.32   msaitoh 	 * the Broadcom PHYs if the media changes.
    357      1.10   thorpej 	 */
    358      1.23     perry 	if (sc->mii_media_active != mii->mii_media_active ||
    359      1.10   thorpej 	    sc->mii_media_status != mii->mii_media_status ||
    360      1.10   thorpej 	    cmd == MII_MEDIACHG) {
    361  1.40.8.1      matt 		switch (sc->mii_mpd_model) {
    362  1.40.8.1      matt 		case MII_MODEL_BROADCOM_BCM5400:
    363  1.40.8.1      matt 			brgphy_bcm5401_dspcode(sc);
    364  1.40.8.1      matt 			break;
    365  1.40.8.1      matt 		case MII_MODEL_BROADCOM_BCM5401:
    366  1.40.8.1      matt 			if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
    367  1.40.8.1      matt 				brgphy_bcm5401_dspcode(sc);
    368  1.40.8.1      matt 			break;
    369  1.40.8.1      matt 		case MII_MODEL_BROADCOM_BCM5411:
    370  1.40.8.1      matt 			brgphy_bcm5411_dspcode(sc);
    371  1.40.8.1      matt 			break;
    372  1.40.8.1      matt 		}
    373      1.10   thorpej 	}
    374  1.40.8.1      matt 
    375  1.40.8.1      matt 	/* Callback if something changed. */
    376  1.40.8.1      matt 	mii_phy_update(sc, cmd);
    377       1.1   thorpej 	return (0);
    378       1.1   thorpej }
    379       1.1   thorpej 
    380      1.21   thorpej static void
    381       1.4   thorpej brgphy_status(struct mii_softc *sc)
    382       1.1   thorpej {
    383       1.1   thorpej 	struct mii_data *mii = sc->mii_pdata;
    384       1.1   thorpej 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    385       1.1   thorpej 	int bmcr, auxsts, gtsr;
    386       1.1   thorpej 
    387       1.1   thorpej 	mii->mii_media_status = IFM_AVALID;
    388       1.1   thorpej 	mii->mii_media_active = IFM_ETHER;
    389       1.1   thorpej 
    390       1.1   thorpej 	auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS);
    391       1.1   thorpej 
    392       1.1   thorpej 	if (auxsts & BRGPHY_AUXSTS_LINK)
    393       1.1   thorpej 		mii->mii_media_status |= IFM_ACTIVE;
    394       1.1   thorpej 
    395       1.1   thorpej 	bmcr = PHY_READ(sc, MII_BMCR);
    396       1.1   thorpej 	if (bmcr & BMCR_ISO) {
    397       1.1   thorpej 		mii->mii_media_active |= IFM_NONE;
    398       1.1   thorpej 		mii->mii_media_status = 0;
    399       1.1   thorpej 		return;
    400       1.1   thorpej 	}
    401       1.1   thorpej 
    402       1.1   thorpej 	if (bmcr & BMCR_LOOP)
    403       1.1   thorpej 		mii->mii_media_active |= IFM_LOOP;
    404       1.1   thorpej 
    405       1.1   thorpej 	if (bmcr & BMCR_AUTOEN) {
    406       1.1   thorpej 		/*
    407       1.1   thorpej 		 * The media status bits are only valid of autonegotiation
    408       1.1   thorpej 		 * has completed (or it's disabled).
    409       1.1   thorpej 		 */
    410       1.1   thorpej 		if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) {
    411       1.1   thorpej 			/* Erg, still trying, I guess... */
    412       1.1   thorpej 			mii->mii_media_active |= IFM_NONE;
    413       1.1   thorpej 			return;
    414       1.1   thorpej 		}
    415       1.1   thorpej 
    416       1.1   thorpej 		switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
    417       1.1   thorpej 		case BRGPHY_RES_1000FD:
    418       1.3     bjh21 			mii->mii_media_active |= IFM_1000_T|IFM_FDX;
    419       1.1   thorpej 			gtsr = PHY_READ(sc, MII_100T2SR);
    420       1.1   thorpej 			if (gtsr & GTSR_MS_RES)
    421       1.1   thorpej 				mii->mii_media_active |= IFM_ETH_MASTER;
    422       1.1   thorpej 			break;
    423       1.1   thorpej 
    424       1.1   thorpej 		case BRGPHY_RES_1000HD:
    425       1.3     bjh21 			mii->mii_media_active |= IFM_1000_T;
    426       1.1   thorpej 			gtsr = PHY_READ(sc, MII_100T2SR);
    427       1.1   thorpej 			if (gtsr & GTSR_MS_RES)
    428       1.1   thorpej 				mii->mii_media_active |= IFM_ETH_MASTER;
    429       1.1   thorpej 			break;
    430       1.1   thorpej 
    431       1.1   thorpej 		case BRGPHY_RES_100FD:
    432       1.1   thorpej 			mii->mii_media_active |= IFM_100_TX|IFM_FDX;
    433       1.1   thorpej 			break;
    434       1.1   thorpej 
    435       1.1   thorpej 		case BRGPHY_RES_100T4:
    436       1.1   thorpej 			mii->mii_media_active |= IFM_100_T4;
    437       1.1   thorpej 			break;
    438       1.1   thorpej 
    439       1.1   thorpej 		case BRGPHY_RES_100HD:
    440       1.1   thorpej 			mii->mii_media_active |= IFM_100_TX;
    441       1.1   thorpej 			break;
    442       1.1   thorpej 
    443       1.1   thorpej 		case BRGPHY_RES_10FD:
    444       1.1   thorpej 			mii->mii_media_active |= IFM_10_T|IFM_FDX;
    445       1.1   thorpej 			break;
    446       1.1   thorpej 
    447       1.1   thorpej 		case BRGPHY_RES_10HD:
    448       1.1   thorpej 			mii->mii_media_active |= IFM_10_T;
    449       1.1   thorpej 			break;
    450       1.1   thorpej 
    451       1.1   thorpej 		default:
    452       1.1   thorpej 			mii->mii_media_active |= IFM_NONE;
    453       1.1   thorpej 			mii->mii_media_status = 0;
    454       1.1   thorpej 		}
    455      1.19   thorpej 		if (mii->mii_media_active & IFM_FDX)
    456      1.20   thorpej 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    457       1.1   thorpej 	} else
    458       1.1   thorpej 		mii->mii_media_active = ife->ifm_media;
    459      1.10   thorpej }
    460      1.10   thorpej 
    461      1.32   msaitoh int
    462      1.32   msaitoh brgphy_mii_phy_auto(struct mii_softc *sc)
    463      1.32   msaitoh {
    464      1.32   msaitoh 	int anar, ktcr = 0;
    465      1.32   msaitoh 
    466      1.32   msaitoh 	brgphy_loop(sc);
    467      1.32   msaitoh 	PHY_RESET(sc);
    468      1.32   msaitoh 	ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX;
    469      1.32   msaitoh 	if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
    470      1.32   msaitoh 		ktcr |= GTCR_MAN_MS|GTCR_ADV_MS;
    471      1.32   msaitoh 	PHY_WRITE(sc, MII_100T2CR, ktcr);
    472      1.32   msaitoh 	ktcr = PHY_READ(sc, MII_100T2CR);
    473      1.32   msaitoh 	DELAY(1000);
    474      1.32   msaitoh 	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    475      1.32   msaitoh 	if (sc->mii_flags & MIIF_DOPAUSE)
    476      1.32   msaitoh 		anar |= ANAR_FC| ANAR_X_PAUSE_ASYM;
    477      1.32   msaitoh 
    478      1.32   msaitoh 	PHY_WRITE(sc, MII_ANAR, anar);
    479      1.32   msaitoh 	DELAY(1000);
    480      1.32   msaitoh 	PHY_WRITE(sc, MII_BMCR,
    481      1.32   msaitoh 	    BMCR_AUTOEN | BMCR_STARTNEG);
    482      1.32   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
    483      1.32   msaitoh 
    484      1.32   msaitoh 	return (EJUSTRETURN);
    485      1.32   msaitoh }
    486      1.32   msaitoh 
    487      1.32   msaitoh void
    488      1.32   msaitoh brgphy_loop(struct mii_softc *sc)
    489      1.32   msaitoh {
    490      1.32   msaitoh 	u_int32_t bmsr;
    491      1.32   msaitoh 	int i;
    492      1.32   msaitoh 
    493      1.32   msaitoh 	PHY_WRITE(sc, MII_BMCR, BMCR_LOOP);
    494      1.33   msaitoh 	for (i = 0; i < 15000; i++) {
    495      1.32   msaitoh 		bmsr = PHY_READ(sc, MII_BMSR);
    496      1.32   msaitoh 		if (!(bmsr & BMSR_LINK))
    497      1.32   msaitoh 			break;
    498      1.32   msaitoh 		DELAY(10);
    499      1.32   msaitoh 	}
    500      1.32   msaitoh }
    501      1.32   msaitoh 
    502      1.21   thorpej static void
    503  1.40.8.1      matt brgphy_reset(struct mii_softc *sc)
    504      1.10   thorpej {
    505  1.40.8.1      matt 	struct brgphy_softc *bsc = (void *)sc;
    506      1.10   thorpej 
    507      1.10   thorpej 	mii_phy_reset(sc);
    508      1.15  jonathan 
    509  1.40.8.1      matt 	switch (sc->mii_mpd_model) {
    510  1.40.8.1      matt 	case MII_MODEL_BROADCOM_BCM5400:
    511  1.40.8.1      matt 		brgphy_bcm5401_dspcode(sc);
    512  1.40.8.1      matt 		break;
    513  1.40.8.1      matt 	case MII_MODEL_BROADCOM_BCM5401:
    514  1.40.8.1      matt 		if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
    515  1.40.8.1      matt 			brgphy_bcm5401_dspcode(sc);
    516  1.40.8.1      matt 		break;
    517  1.40.8.1      matt 	case MII_MODEL_BROADCOM_BCM5411:
    518  1.40.8.1      matt 		brgphy_bcm5411_dspcode(sc);
    519  1.40.8.1      matt 		break;
    520  1.40.8.1      matt 	case MII_MODEL_BROADCOM_BCM5421:
    521  1.40.8.1      matt 		brgphy_bcm5421_dspcode(sc);
    522  1.40.8.1      matt 		break;
    523  1.40.8.1      matt 	case MII_MODEL_BROADCOM_BCM54K2:
    524  1.40.8.1      matt 		brgphy_bcm54k2_dspcode(sc);
    525  1.40.8.1      matt 		break;
    526  1.40.8.1      matt 	}
    527      1.15  jonathan 
    528  1.40.8.1      matt 	/* Handle any bge (NetXtreme/NetLink) workarounds. */
    529  1.40.8.1      matt 	if (bsc->sc_isbge != 0) {
    530  1.40.8.1      matt 		if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
    531  1.40.8.1      matt 
    532  1.40.8.1      matt 			if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG)
    533  1.40.8.1      matt 				brgphy_adc_bug(sc);
    534  1.40.8.1      matt 			if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG)
    535  1.40.8.1      matt 				brgphy_5704_a0_bug(sc);
    536  1.40.8.1      matt 			if (bsc->sc_bge_flags & BGE_PHY_BER_BUG)
    537  1.40.8.1      matt 				brgphy_ber_bug(sc);
    538  1.40.8.1      matt 			else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) {
    539  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
    540  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG,
    541  1.40.8.1      matt 				    0x000a);
    542  1.40.8.1      matt 
    543  1.40.8.1      matt 				if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) {
    544  1.40.8.1      matt 					PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
    545  1.40.8.1      matt 					    0x110b);
    546  1.40.8.1      matt 					PHY_WRITE(sc, BRGPHY_TEST1,
    547  1.40.8.1      matt 					    BRGPHY_TEST1_TRIM_EN | 0x4);
    548  1.40.8.1      matt 				} else {
    549  1.40.8.1      matt 					PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
    550  1.40.8.1      matt 					    0x010b);
    551  1.40.8.1      matt 				}
    552      1.15  jonathan 
    553  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
    554  1.40.8.1      matt 			}
    555  1.40.8.1      matt 			if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG)
    556  1.40.8.1      matt 				brgphy_crc_bug(sc);
    557      1.18   hannken 
    558  1.40.8.1      matt #if 0
    559  1.40.8.1      matt 			/* Set Jumbo frame settings in the PHY. */
    560  1.40.8.1      matt 			if (bsc->sc_bge_flags & BGE_JUMBO_CAP)
    561  1.40.8.1      matt 				brgphy_jumbo_settings(sc);
    562  1.40.8.1      matt #endif
    563  1.40.8.1      matt 
    564  1.40.8.1      matt 			/* Adjust output voltage */
    565  1.40.8.1      matt 			if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)
    566  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
    567  1.40.8.1      matt 
    568  1.40.8.1      matt #if 0
    569  1.40.8.1      matt 			/* Enable Ethernet@Wirespeed */
    570  1.40.8.1      matt 			if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED))
    571  1.40.8.1      matt 				brgphy_eth_wirespeed(sc);
    572  1.40.8.1      matt 
    573  1.40.8.1      matt 			/* Enable Link LED on Dell boxes */
    574  1.40.8.1      matt 			if (bsc->sc_bge_flags & BGE_NO_3LED) {
    575  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
    576  1.40.8.1      matt 				PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
    577  1.40.8.1      matt 					& ~BRGPHY_PHY_EXTCTL_3_LED);
    578  1.40.8.1      matt 			}
    579  1.40.8.1      matt #endif
    580  1.40.8.1      matt 		}
    581  1.40.8.1      matt #if 0 /* not yet */
    582  1.40.8.1      matt 	/* Handle any bnx (NetXtreme II) workarounds. */
    583  1.40.8.1      matt 	} else if (sc->sc_isbnx != 0) {
    584  1.40.8.1      matt 		bnx_sc = sc->mii_pdata->mii_ifp->if_softc;
    585  1.40.8.1      matt 
    586  1.40.8.1      matt 		if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) {
    587  1.40.8.1      matt 			/* Store autoneg capabilities/results in digital block (Page 0) */
    588  1.40.8.1      matt 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
    589  1.40.8.1      matt 			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
    590  1.40.8.1      matt 				BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
    591  1.40.8.1      matt 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
    592  1.40.8.1      matt 
    593  1.40.8.1      matt 			/* Enable fiber mode and autodetection */
    594  1.40.8.1      matt 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
    595  1.40.8.1      matt 				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
    596  1.40.8.1      matt 				BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
    597  1.40.8.1      matt 				BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
    598  1.40.8.1      matt 
    599  1.40.8.1      matt 			/* Enable parallel detection */
    600  1.40.8.1      matt 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
    601  1.40.8.1      matt 				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
    602  1.40.8.1      matt 				BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
    603  1.40.8.1      matt 
    604  1.40.8.1      matt 			/* Advertise 2.5G support through next page during autoneg */
    605  1.40.8.1      matt 			if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG)
    606  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
    607  1.40.8.1      matt 					PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
    608  1.40.8.1      matt 					BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
    609  1.40.8.1      matt 
    610  1.40.8.1      matt 			/* Increase TX signal amplitude */
    611  1.40.8.1      matt 			if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) ||
    612  1.40.8.1      matt 			    (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) ||
    613  1.40.8.1      matt 			    (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) {
    614  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    615  1.40.8.1      matt 					BRGPHY_5708S_TX_MISC_PG5);
    616  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
    617  1.40.8.1      matt 					PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) &
    618  1.40.8.1      matt 					~BRGPHY_5708S_PG5_TXACTL1_VCM);
    619  1.40.8.1      matt 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    620  1.40.8.1      matt 					BRGPHY_5708S_DIG_PG0);
    621  1.40.8.1      matt 			}
    622      1.18   hannken 
    623  1.40.8.1      matt 			/* Backplanes use special driver/pre-driver/pre-emphasis values. */
    624  1.40.8.1      matt 			if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
    625  1.40.8.1      matt 			    (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
    626  1.40.8.1      matt 					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    627  1.40.8.1      matt 						BRGPHY_5708S_TX_MISC_PG5);
    628  1.40.8.1      matt 					PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
    629  1.40.8.1      matt 						bnx_sc->bnx_port_hw_cfg &
    630  1.40.8.1      matt 						BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
    631  1.40.8.1      matt 					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    632  1.40.8.1      matt 						BRGPHY_5708S_DIG_PG0);
    633  1.40.8.1      matt 			}
    634  1.40.8.1      matt 		} else {
    635  1.40.8.1      matt 			if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
    636  1.40.8.1      matt 				brgphy_ber_bug(sc);
    637      1.15  jonathan 
    638  1.40.8.1      matt 				/* Set Jumbo frame settings in the PHY. */
    639  1.40.8.1      matt 				brgphy_jumbo_settings(sc);
    640      1.22      cube 
    641  1.40.8.1      matt 				/* Enable Ethernet@Wirespeed */
    642  1.40.8.1      matt 				brgphy_eth_wirespeed(sc);
    643  1.40.8.1      matt 			}
    644  1.40.8.1      matt 		}
    645  1.40.8.1      matt #endif
    646  1.40.8.1      matt 	}
    647      1.34     markd }
    648      1.34     markd 
    649      1.16  jonathan /* Turn off tap power management on 5401. */
    650      1.10   thorpej static void
    651  1.40.8.1      matt brgphy_bcm5401_dspcode(struct mii_softc *sc)
    652      1.10   thorpej {
    653      1.10   thorpej 	static const struct {
    654      1.10   thorpej 		int		reg;
    655      1.10   thorpej 		uint16_t	val;
    656      1.10   thorpej 	} dspcode[] = {
    657      1.16  jonathan 		{ BRGPHY_MII_AUXCTL,		0x0c20 },
    658      1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0012 },
    659      1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x1804 },
    660      1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0013 },
    661      1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x1204 },
    662      1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
    663      1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0132 },
    664      1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
    665      1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0232 },
    666      1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
    667      1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a20 },
    668      1.10   thorpej 		{ 0,				0 },
    669      1.10   thorpej 	};
    670      1.10   thorpej 	int i;
    671      1.10   thorpej 
    672      1.10   thorpej 	for (i = 0; dspcode[i].reg != 0; i++)
    673      1.10   thorpej 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    674      1.16  jonathan     delay(40);
    675      1.10   thorpej }
    676      1.10   thorpej 
    677      1.10   thorpej static void
    678  1.40.8.1      matt brgphy_bcm5411_dspcode(struct mii_softc *sc)
    679      1.10   thorpej {
    680      1.10   thorpej 	static const struct {
    681      1.10   thorpej 		int		reg;
    682      1.10   thorpej 		uint16_t	val;
    683      1.10   thorpej 	} dspcode[] = {
    684      1.10   thorpej 		{ 0x1c,				0x8c23 },
    685      1.10   thorpej 		{ 0x1c,				0x8ca3 },
    686      1.10   thorpej 		{ 0x1c,				0x8c23 },
    687      1.15  jonathan 		{ 0,				0 },
    688      1.15  jonathan 	};
    689      1.15  jonathan 	int i;
    690      1.15  jonathan 
    691      1.15  jonathan 	for (i = 0; dspcode[i].reg != 0; i++)
    692      1.15  jonathan 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    693      1.15  jonathan }
    694      1.15  jonathan 
    695  1.40.8.1      matt void
    696  1.40.8.1      matt brgphy_bcm5421_dspcode(struct mii_softc *sc)
    697  1.40.8.1      matt {
    698  1.40.8.1      matt 	uint16_t data;
    699  1.40.8.1      matt 
    700  1.40.8.1      matt 	/* Set Class A mode */
    701  1.40.8.1      matt 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
    702  1.40.8.1      matt 	data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
    703  1.40.8.1      matt 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
    704  1.40.8.1      matt 
    705  1.40.8.1      matt 	/* Set FFE gamma override to -0.125 */
    706  1.40.8.1      matt 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
    707  1.40.8.1      matt 	data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
    708  1.40.8.1      matt 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
    709  1.40.8.1      matt 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
    710  1.40.8.1      matt 	data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
    711  1.40.8.1      matt 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
    712  1.40.8.1      matt }
    713  1.40.8.1      matt 
    714  1.40.8.1      matt void
    715  1.40.8.1      matt brgphy_bcm54k2_dspcode(struct mii_softc *sc)
    716  1.40.8.1      matt {
    717  1.40.8.1      matt 	static const struct {
    718  1.40.8.1      matt 		int		reg;
    719  1.40.8.1      matt 		uint16_t	val;
    720  1.40.8.1      matt 	} dspcode[] = {
    721  1.40.8.1      matt 		{ 4,				0x01e1 },
    722  1.40.8.1      matt 		{ 9,				0x0300 },
    723  1.40.8.1      matt 		{ 0,				0 },
    724  1.40.8.1      matt 	};
    725  1.40.8.1      matt 	int i;
    726  1.40.8.1      matt 
    727  1.40.8.1      matt 	for (i = 0; dspcode[i].reg != 0; i++)
    728  1.40.8.1      matt 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    729  1.40.8.1      matt }
    730  1.40.8.1      matt 
    731      1.15  jonathan static void
    732  1.40.8.1      matt brgphy_adc_bug(struct mii_softc *sc)
    733      1.15  jonathan {
    734      1.15  jonathan 	static const struct {
    735      1.15  jonathan 		int		reg;
    736      1.15  jonathan 		uint16_t	val;
    737      1.15  jonathan 	} dspcode[] = {
    738      1.15  jonathan 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
    739      1.15  jonathan 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
    740      1.15  jonathan 		{ BRGPHY_MII_DSP_RW_PORT,	0x2aaa },
    741  1.40.8.1      matt 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
    742  1.40.8.1      matt 		{ BRGPHY_MII_DSP_RW_PORT,	0x0323 },
    743  1.40.8.1      matt 		{ BRGPHY_MII_AUXCTL,		0x0400 },
    744      1.15  jonathan 		{ 0,				0 },
    745      1.15  jonathan 	};
    746      1.15  jonathan 	int i;
    747      1.15  jonathan 
    748      1.15  jonathan 	for (i = 0; dspcode[i].reg != 0; i++)
    749      1.15  jonathan 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    750      1.15  jonathan }
    751      1.15  jonathan 
    752      1.15  jonathan static void
    753  1.40.8.1      matt brgphy_5704_a0_bug(struct mii_softc *sc)
    754      1.15  jonathan {
    755      1.15  jonathan 	static const struct {
    756      1.15  jonathan 		int		reg;
    757      1.15  jonathan 		uint16_t	val;
    758      1.15  jonathan 	} dspcode[] = {
    759      1.15  jonathan 		{ 0x1c,				0x8d68 },
    760      1.33   msaitoh 		{ 0x1c,				0x8d68 },
    761      1.10   thorpej 		{ 0,				0 },
    762      1.10   thorpej 	};
    763      1.10   thorpej 	int i;
    764      1.10   thorpej 
    765      1.10   thorpej 	for (i = 0; dspcode[i].reg != 0; i++)
    766      1.10   thorpej 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    767       1.1   thorpej }
    768      1.22      cube 
    769      1.22      cube static void
    770  1.40.8.1      matt brgphy_ber_bug(struct mii_softc *sc)
    771      1.22      cube {
    772      1.22      cube 	static const struct {
    773      1.22      cube 		int		reg;
    774      1.22      cube 		uint16_t	val;
    775      1.22      cube 	} dspcode[] = {
    776      1.22      cube 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
    777      1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
    778      1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x310b },
    779      1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
    780      1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x9506 },
    781      1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x401f },
    782      1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x14e2 },
    783      1.22      cube 		{ BRGPHY_MII_AUXCTL,		0x0400 },
    784      1.22      cube 		{ 0,				0 },
    785      1.22      cube 	};
    786      1.22      cube 	int i;
    787      1.22      cube 
    788      1.22      cube 	for (i = 0; dspcode[i].reg != 0; i++)
    789      1.22      cube 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    790      1.22      cube }
    791      1.34     markd 
    792  1.40.8.1      matt /* BCM5701 A0/B0 CRC bug workaround */
    793  1.40.8.1      matt void
    794  1.40.8.1      matt brgphy_crc_bug(struct mii_softc *sc)
    795      1.34     markd {
    796      1.34     markd 	static const struct {
    797      1.34     markd 		int		reg;
    798      1.34     markd 		uint16_t	val;
    799      1.34     markd 	} dspcode[] = {
    800  1.40.8.1      matt 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0a75 },
    801  1.40.8.1      matt 		{ 0x1c,				0x8c68 },
    802  1.40.8.1      matt 		{ 0x1c,				0x8d68 },
    803  1.40.8.1      matt 		{ 0x1c,				0x8c68 },
    804      1.34     markd 		{ 0,				0 },
    805      1.34     markd 	};
    806      1.34     markd 	int i;
    807      1.34     markd 
    808      1.34     markd 	for (i = 0; dspcode[i].reg != 0; i++)
    809      1.34     markd 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
    810      1.34     markd }
    811