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brgphy.c revision 1.76.28.2
      1  1.76.28.2    martin /*	$NetBSD: brgphy.c,v 1.76.28.2 2020/04/08 14:08:08 martin Exp $	*/
      2        1.1   thorpej 
      3        1.1   thorpej /*-
      4        1.1   thorpej  * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
      5        1.1   thorpej  * All rights reserved.
      6        1.1   thorpej  *
      7        1.1   thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8        1.1   thorpej  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9        1.1   thorpej  * NASA Ames Research Center.
     10        1.1   thorpej  *
     11        1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     12        1.1   thorpej  * modification, are permitted provided that the following conditions
     13        1.1   thorpej  * are met:
     14        1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     15        1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     16        1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     17        1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     18        1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     19        1.1   thorpej  *
     20        1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21        1.1   thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22        1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23        1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24        1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25        1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26        1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27        1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28        1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29        1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30        1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     31        1.1   thorpej  */
     32        1.1   thorpej 
     33        1.1   thorpej /*
     34        1.1   thorpej  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
     35        1.1   thorpej  *
     36        1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     37        1.1   thorpej  * modification, are permitted provided that the following conditions
     38        1.1   thorpej  * are met:
     39        1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     40        1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     41        1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     42        1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     43        1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     44        1.1   thorpej  *
     45        1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     46        1.1   thorpej  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     47        1.1   thorpej  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     48        1.1   thorpej  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     49        1.1   thorpej  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     50        1.1   thorpej  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     51        1.1   thorpej  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     52        1.1   thorpej  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     53        1.1   thorpej  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     54        1.1   thorpej  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     55        1.1   thorpej  */
     56        1.1   thorpej 
     57        1.1   thorpej /*
     58       1.57       jym  * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs.
     59        1.1   thorpej  *
     60        1.1   thorpej  * Programming information for this PHY was gleaned from FreeBSD
     61        1.1   thorpej  * (they were apparently able to get a datasheet from Broadcom).
     62        1.1   thorpej  */
     63        1.5     lukem 
     64        1.5     lukem #include <sys/cdefs.h>
     65  1.76.28.2    martin __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.76.28.2 2020/04/08 14:08:08 martin Exp $");
     66        1.1   thorpej 
     67        1.1   thorpej #include <sys/param.h>
     68        1.1   thorpej #include <sys/systm.h>
     69        1.1   thorpej #include <sys/kernel.h>
     70        1.1   thorpej #include <sys/device.h>
     71        1.1   thorpej #include <sys/socket.h>
     72        1.1   thorpej #include <sys/errno.h>
     73       1.44   msaitoh #include <prop/proplib.h>
     74        1.1   thorpej 
     75        1.1   thorpej #include <net/if.h>
     76        1.1   thorpej #include <net/if_media.h>
     77        1.1   thorpej 
     78        1.1   thorpej #include <dev/mii/mii.h>
     79        1.1   thorpej #include <dev/mii/miivar.h>
     80        1.1   thorpej #include <dev/mii/miidevs.h>
     81        1.1   thorpej #include <dev/mii/brgphyreg.h>
     82        1.1   thorpej 
     83       1.43   msaitoh #include <dev/pci/if_bgereg.h>
     84       1.43   msaitoh #include <dev/pci/if_bnxreg.h>
     85       1.43   msaitoh 
     86       1.39   xtraeme static int	brgphymatch(device_t, cfdata_t, void *);
     87       1.39   xtraeme static void	brgphyattach(device_t, device_t, void *);
     88        1.1   thorpej 
     89       1.44   msaitoh struct brgphy_softc {
     90       1.44   msaitoh 	struct mii_softc sc_mii;
     91       1.54    dyoung 	bool sc_isbge;
     92       1.54    dyoung 	bool sc_isbnx;
     93       1.71   msaitoh 	uint32_t sc_chipid;	/* parent's chipid */
     94       1.71   msaitoh 	uint32_t sc_phyflags;	/* parent's phyflags */
     95       1.71   msaitoh 	uint32_t sc_shared_hwcfg; /* shared hw config */
     96       1.71   msaitoh 	uint32_t sc_port_hwcfg;	/* port specific hw config */
     97       1.44   msaitoh };
     98       1.44   msaitoh 
     99  1.76.28.2    martin CFATTACH_DECL_NEW(brgphy, sizeof(struct brgphy_softc),
    100  1.76.28.2    martin     brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate);
    101        1.1   thorpej 
    102       1.21   thorpej static int	brgphy_service(struct mii_softc *, struct mii_data *, int);
    103       1.71   msaitoh static void	brgphy_copper_status(struct mii_softc *);
    104       1.71   msaitoh static void	brgphy_fiber_status(struct mii_softc *);
    105       1.71   msaitoh static void	brgphy_5708s_status(struct mii_softc *);
    106       1.71   msaitoh static void	brgphy_5709s_status(struct mii_softc *);
    107       1.32   msaitoh static int	brgphy_mii_phy_auto(struct mii_softc *);
    108       1.32   msaitoh static void	brgphy_loop(struct mii_softc *);
    109       1.43   msaitoh static void	brgphy_reset(struct mii_softc *);
    110       1.43   msaitoh static void	brgphy_bcm5401_dspcode(struct mii_softc *);
    111       1.43   msaitoh static void	brgphy_bcm5411_dspcode(struct mii_softc *);
    112       1.43   msaitoh static void	brgphy_bcm5421_dspcode(struct mii_softc *);
    113       1.43   msaitoh static void	brgphy_bcm54k2_dspcode(struct mii_softc *);
    114       1.43   msaitoh static void	brgphy_adc_bug(struct mii_softc *);
    115       1.43   msaitoh static void	brgphy_5704_a0_bug(struct mii_softc *);
    116       1.43   msaitoh static void	brgphy_ber_bug(struct mii_softc *);
    117       1.43   msaitoh static void	brgphy_crc_bug(struct mii_softc *);
    118       1.58       jym static void	brgphy_disable_early_dac(struct mii_softc *);
    119       1.52   msaitoh static void	brgphy_jumbo_settings(struct mii_softc *);
    120       1.52   msaitoh static void	brgphy_eth_wirespeed(struct mii_softc *);
    121        1.1   thorpej 
    122       1.10   thorpej 
    123       1.71   msaitoh static const struct mii_phy_funcs brgphy_copper_funcs = {
    124       1.71   msaitoh 	brgphy_service, brgphy_copper_status, brgphy_reset,
    125       1.71   msaitoh };
    126       1.71   msaitoh 
    127       1.71   msaitoh static const struct mii_phy_funcs brgphy_fiber_funcs = {
    128       1.71   msaitoh 	brgphy_service, brgphy_fiber_status, brgphy_reset,
    129       1.71   msaitoh };
    130       1.71   msaitoh 
    131       1.71   msaitoh static const struct mii_phy_funcs brgphy_5708s_funcs = {
    132       1.71   msaitoh 	brgphy_service, brgphy_5708s_status, brgphy_reset,
    133       1.71   msaitoh };
    134       1.71   msaitoh 
    135       1.71   msaitoh static const struct mii_phy_funcs brgphy_5709s_funcs = {
    136       1.71   msaitoh 	brgphy_service, brgphy_5709s_status, brgphy_reset,
    137       1.34     markd };
    138       1.34     markd 
    139       1.21   thorpej static const struct mii_phydesc brgphys[] = {
    140  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5400),
    141  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5401),
    142  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5402),
    143  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5404),
    144  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5411),
    145  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5421),
    146  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5424),
    147  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5461),
    148  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5462),
    149  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5464),
    150  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5466),
    151  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM54K2),
    152  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5701),
    153  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5703),
    154  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5704),
    155  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5705),
    156  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5706),
    157  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5714),
    158  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5750),
    159  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5752),
    160  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5780),
    161  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM, BCM5708C),
    162  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5481),
    163  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5482),
    164  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5708S),
    165  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5709C),
    166  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5709S),
    167  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5709CAX),
    168  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5722),
    169  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5754),
    170  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5755),
    171  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5756),
    172  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5761),
    173  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5784),
    174  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM2, BCM5785),
    175  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM3, BCM5717C),
    176  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM3, BCM5719C),
    177  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM3, BCM5720C),
    178  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM3, BCM57765),
    179  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM3, BCM57780),
    180  1.76.28.2    martin 	MII_PHY_DESC(BROADCOM4, BCM54213PE),
    181  1.76.28.1  christos 	MII_PHY_DESC(BROADCOM4, BCM5725C),
    182  1.76.28.1  christos 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
    183  1.76.28.1  christos 	MII_PHY_END,
    184        1.1   thorpej };
    185        1.1   thorpej 
    186       1.21   thorpej static int
    187       1.48   tsutsui brgphymatch(device_t parent, cfdata_t match, void *aux)
    188        1.1   thorpej {
    189        1.1   thorpej 	struct mii_attach_args *ma = aux;
    190        1.1   thorpej 
    191        1.2   thorpej 	if (mii_phy_match(ma, brgphys) != NULL)
    192  1.76.28.1  christos 		return 10;
    193        1.1   thorpej 
    194  1.76.28.1  christos 	return 0;
    195        1.1   thorpej }
    196        1.1   thorpej 
    197       1.21   thorpej static void
    198       1.46    cegger brgphyattach(device_t parent, device_t self, void *aux)
    199        1.1   thorpej {
    200       1.44   msaitoh 	struct brgphy_softc *bsc = device_private(self);
    201       1.44   msaitoh 	struct mii_softc *sc = &bsc->sc_mii;
    202        1.1   thorpej 	struct mii_attach_args *ma = aux;
    203        1.1   thorpej 	struct mii_data *mii = ma->mii_data;
    204        1.2   thorpej 	const struct mii_phydesc *mpd;
    205       1.44   msaitoh 	prop_dictionary_t dict;
    206        1.1   thorpej 
    207        1.2   thorpej 	mpd = mii_phy_match(ma, brgphys);
    208       1.17   thorpej 	aprint_naive(": Media interface\n");
    209       1.17   thorpej 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    210        1.1   thorpej 
    211       1.39   xtraeme 	sc->mii_dev = self;
    212        1.1   thorpej 	sc->mii_inst = mii->mii_instance;
    213        1.1   thorpej 	sc->mii_phy = ma->mii_phyno;
    214       1.61   msaitoh 	sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
    215       1.32   msaitoh 	sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
    216       1.43   msaitoh 	sc->mii_mpd_rev = MII_REV(ma->mii_id2);
    217        1.1   thorpej 	sc->mii_pdata = mii;
    218        1.6   thorpej 	sc->mii_flags = ma->mii_flags;
    219       1.10   thorpej 
    220       1.58       jym 	if (device_is_a(parent, "bge"))
    221       1.54    dyoung 		bsc->sc_isbge = true;
    222       1.58       jym 	else if (device_is_a(parent, "bnx"))
    223       1.54    dyoung 		bsc->sc_isbnx = true;
    224       1.58       jym 
    225       1.72   msaitoh 	dict = device_properties(parent);
    226       1.58       jym 	if (bsc->sc_isbge || bsc->sc_isbnx) {
    227       1.57       jym 		if (!prop_dictionary_get_uint32(dict, "phyflags",
    228       1.58       jym 		    &bsc->sc_phyflags))
    229       1.58       jym 			aprint_error_dev(self, "failed to get phyflags\n");
    230       1.58       jym 		if (!prop_dictionary_get_uint32(dict, "chipid",
    231       1.58       jym 		    &bsc->sc_chipid))
    232       1.58       jym 			aprint_error_dev(self, "failed to get chipid\n");
    233       1.44   msaitoh 	}
    234       1.57       jym 
    235       1.71   msaitoh 	if (bsc->sc_isbnx) {
    236       1.71   msaitoh 		/* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */
    237       1.71   msaitoh 		if (!prop_dictionary_get_uint32(dict, "shared_hwcfg",
    238       1.71   msaitoh 			&bsc->sc_shared_hwcfg))
    239       1.71   msaitoh 			aprint_error_dev(self, "failed to get shared_hwcfg\n");
    240       1.71   msaitoh 		if (!prop_dictionary_get_uint32(dict, "port_hwcfg",
    241       1.71   msaitoh 			&bsc->sc_port_hwcfg))
    242       1.71   msaitoh 			aprint_error_dev(self, "failed to get port_hwcfg\n");
    243       1.71   msaitoh 	}
    244       1.71   msaitoh 
    245       1.71   msaitoh 	if (sc->mii_flags & MIIF_HAVEFIBER) {
    246       1.74   msaitoh 		if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    247       1.74   msaitoh 		    && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S)
    248       1.71   msaitoh 			sc->mii_funcs = &brgphy_5708s_funcs;
    249       1.74   msaitoh 		else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    250       1.75   msaitoh 		    && (sc->mii_mpd_model ==  MII_MODEL_BROADCOM2_BCM5709S)) {
    251       1.75   msaitoh 			if (bsc->sc_isbnx)
    252       1.75   msaitoh 				sc->mii_funcs = &brgphy_5709s_funcs;
    253       1.75   msaitoh 			else {
    254       1.75   msaitoh 				/*
    255       1.75   msaitoh 				 * XXX
    256       1.75   msaitoh 				 * 5720S and 5709S shares the same PHY id.
    257       1.75   msaitoh 				 * Assume 5720S PHY if parent device is bge(4).
    258       1.75   msaitoh 				 */
    259       1.75   msaitoh 				sc->mii_funcs = &brgphy_5708s_funcs;
    260       1.75   msaitoh 			}
    261       1.75   msaitoh 		} else
    262       1.71   msaitoh 			sc->mii_funcs = &brgphy_fiber_funcs;
    263       1.71   msaitoh 	} else
    264       1.71   msaitoh 		sc->mii_funcs = &brgphy_copper_funcs;
    265       1.71   msaitoh 
    266  1.76.28.2    martin 	mii_lock(mii);
    267  1.76.28.2    martin 
    268       1.63   msaitoh 	PHY_RESET(sc);
    269       1.63   msaitoh 
    270  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
    271  1.76.28.1  christos 	sc->mii_capabilities &= ma->mii_capmask;
    272       1.63   msaitoh 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    273  1.76.28.1  christos 		PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
    274       1.63   msaitoh 
    275  1.76.28.2    martin 	mii_unlock(mii);
    276  1.76.28.2    martin 
    277       1.75   msaitoh 	if (sc->mii_flags & MIIF_HAVEFIBER) {
    278  1.76.28.2    martin 		mii_lock(mii);
    279       1.75   msaitoh 		sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
    280       1.57       jym 
    281       1.75   msaitoh 		/*
    282       1.75   msaitoh 		 * Set the proper bits for capabilities so that the
    283       1.75   msaitoh 		 * correct media get selected by mii_phy_add_media()
    284       1.75   msaitoh 		 */
    285       1.75   msaitoh 		sc->mii_capabilities |= BMSR_ANEG;
    286       1.75   msaitoh 		sc->mii_capabilities &= ~BMSR_100T4;
    287       1.75   msaitoh 		sc->mii_extcapabilities |= EXTSR_1000XFDX;
    288  1.76.28.2    martin 		mii_unlock(mii);
    289       1.75   msaitoh 
    290       1.75   msaitoh 		if (bsc->sc_isbnx) {
    291       1.57       jym 			/*
    292       1.75   msaitoh 			 * 2.5Gb support is a software enabled feature
    293       1.75   msaitoh 			 * on the BCM5708S and BCM5709S controllers.
    294       1.57       jym 			 */
    295       1.57       jym #define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
    296       1.75   msaitoh 			if (bsc->sc_phyflags
    297       1.75   msaitoh 			    & BNX_PHY_2_5G_CAPABLE_FLAG) {
    298       1.75   msaitoh 				ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX,
    299       1.75   msaitoh 					IFM_FDX, sc->mii_inst), 0);
    300  1.76.28.2    martin 				aprint_normal_dev(self, "2500baseSX-FDX\n");
    301       1.57       jym #undef ADD
    302       1.57       jym 			}
    303       1.57       jym 		}
    304       1.57       jym 	}
    305       1.75   msaitoh 	mii_phy_add_media(sc);
    306        1.1   thorpej }
    307        1.1   thorpej 
    308       1.21   thorpej static int
    309        1.4   thorpej brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    310        1.1   thorpej {
    311        1.1   thorpej 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    312  1.76.28.1  christos 	uint16_t reg, speed, gig;
    313        1.1   thorpej 
    314  1.76.28.2    martin 	KASSERT(mii_locked(mii));
    315  1.76.28.2    martin 
    316        1.1   thorpej 	switch (cmd) {
    317        1.1   thorpej 	case MII_POLLSTAT:
    318       1.73   msaitoh 		/* If we're not polling our PHY instance, just return. */
    319        1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    320  1.76.28.1  christos 			return 0;
    321        1.1   thorpej 		break;
    322        1.1   thorpej 
    323        1.1   thorpej 	case MII_MEDIACHG:
    324        1.1   thorpej 		/*
    325        1.1   thorpej 		 * If the media indicates a different PHY instance,
    326        1.1   thorpej 		 * isolate ourselves.
    327        1.1   thorpej 		 */
    328        1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    329  1.76.28.1  christos 			PHY_READ(sc, MII_BMCR, &reg);
    330        1.1   thorpej 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
    331  1.76.28.1  christos 			return 0;
    332        1.1   thorpej 		}
    333        1.1   thorpej 
    334       1.73   msaitoh 		/* If the interface is not up, don't do anything. */
    335        1.1   thorpej 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    336        1.1   thorpej 			break;
    337        1.1   thorpej 
    338       1.32   msaitoh 		PHY_RESET(sc); /* XXX hardware bug work-around */
    339       1.32   msaitoh 
    340       1.32   msaitoh 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    341       1.32   msaitoh 		case IFM_AUTO:
    342       1.32   msaitoh 			(void) brgphy_mii_phy_auto(sc);
    343       1.32   msaitoh 			break;
    344       1.71   msaitoh 		case IFM_2500_SX:
    345       1.71   msaitoh 			speed = BRGPHY_5708S_BMCR_2500;
    346       1.71   msaitoh 			goto setit;
    347       1.71   msaitoh 		case IFM_1000_SX:
    348       1.32   msaitoh 		case IFM_1000_T:
    349       1.32   msaitoh 			speed = BMCR_S1000;
    350       1.32   msaitoh 			goto setit;
    351       1.32   msaitoh 		case IFM_100_TX:
    352       1.32   msaitoh 			speed = BMCR_S100;
    353       1.32   msaitoh 			goto setit;
    354       1.32   msaitoh 		case IFM_10_T:
    355       1.32   msaitoh 			speed = BMCR_S10;
    356       1.32   msaitoh setit:
    357       1.32   msaitoh 			brgphy_loop(sc);
    358  1.76.28.1  christos 			if ((ife->ifm_media & IFM_FDX) != 0) {
    359       1.32   msaitoh 				speed |= BMCR_FDX;
    360       1.32   msaitoh 				gig = GTCR_ADV_1000TFDX;
    361       1.69   msaitoh 			} else
    362       1.32   msaitoh 				gig = GTCR_ADV_1000THDX;
    363       1.32   msaitoh 
    364       1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, 0);
    365       1.51    bouyer 			PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
    366       1.32   msaitoh 			PHY_WRITE(sc, MII_BMCR, speed);
    367       1.32   msaitoh 
    368       1.71   msaitoh 			if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) &&
    369       1.71   msaitoh 			    (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) &&
    370       1.71   msaitoh 			    (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX))
    371       1.32   msaitoh 				break;
    372       1.32   msaitoh 
    373       1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, gig);
    374       1.32   msaitoh 			PHY_WRITE(sc, MII_BMCR,
    375       1.65   msaitoh 			    speed | BMCR_AUTOEN | BMCR_STARTNEG);
    376       1.32   msaitoh 
    377       1.61   msaitoh 			if ((sc->mii_mpd_oui != MII_OUI_BROADCOM)
    378       1.61   msaitoh 			    || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701))
    379       1.33   msaitoh 				break;
    380       1.32   msaitoh 
    381       1.32   msaitoh 			if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
    382       1.32   msaitoh 				gig |= GTCR_MAN_MS | GTCR_ADV_MS;
    383       1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, gig);
    384       1.32   msaitoh 			break;
    385       1.32   msaitoh 		default:
    386  1.76.28.1  christos 			return EINVAL;
    387       1.32   msaitoh 		}
    388        1.1   thorpej 		break;
    389        1.1   thorpej 
    390        1.1   thorpej 	case MII_TICK:
    391       1.73   msaitoh 		/* If we're not currently selected, just return. */
    392        1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    393  1.76.28.1  christos 			return 0;
    394        1.1   thorpej 
    395       1.73   msaitoh 		/* Is the interface even up? */
    396       1.67   msaitoh 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    397       1.67   msaitoh 			return 0;
    398       1.67   msaitoh 
    399       1.73   msaitoh 		/* Only used for autonegotiation. */
    400       1.67   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
    401       1.67   msaitoh 		    (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
    402       1.67   msaitoh 			sc->mii_ticks = 0;
    403       1.67   msaitoh 			break;
    404       1.67   msaitoh 		}
    405       1.67   msaitoh 
    406       1.67   msaitoh 		/*
    407       1.67   msaitoh 		 * Check for link.
    408       1.67   msaitoh 		 * Read the status register twice; BMSR_LINK is latch-low.
    409       1.67   msaitoh 		 */
    410  1.76.28.1  christos 		PHY_READ(sc, MII_BMSR, &reg);
    411  1.76.28.1  christos 		PHY_READ(sc, MII_BMSR, &reg);
    412       1.67   msaitoh 		if (reg & BMSR_LINK) {
    413       1.67   msaitoh 			sc->mii_ticks = 0;
    414       1.67   msaitoh 			break;
    415       1.67   msaitoh 		}
    416       1.67   msaitoh 
    417       1.67   msaitoh 		/*
    418       1.67   msaitoh 		 * mii_ticks == 0 means it's the first tick after changing the
    419       1.67   msaitoh 		 * media or the link became down since the last tick
    420       1.67   msaitoh 		 * (see above), so break to update the status.
    421       1.67   msaitoh 		 */
    422       1.67   msaitoh 		if (sc->mii_ticks++ == 0)
    423       1.67   msaitoh 			break;
    424       1.67   msaitoh 
    425       1.73   msaitoh 		/* Only retry autonegotiation every mii_anegticks seconds. */
    426       1.67   msaitoh 		KASSERT(sc->mii_anegticks != 0);
    427       1.67   msaitoh 		if (sc->mii_ticks <= sc->mii_anegticks)
    428       1.67   msaitoh 			break;
    429       1.67   msaitoh 
    430       1.67   msaitoh 		brgphy_mii_phy_auto(sc);
    431        1.1   thorpej 		break;
    432        1.1   thorpej 
    433        1.1   thorpej 	case MII_DOWN:
    434        1.1   thorpej 		mii_phy_down(sc);
    435  1.76.28.1  christos 		return 0;
    436        1.1   thorpej 	}
    437        1.1   thorpej 
    438        1.1   thorpej 	/* Update the media status. */
    439        1.1   thorpej 	mii_phy_status(sc);
    440        1.1   thorpej 
    441       1.10   thorpej 	/*
    442       1.32   msaitoh 	 * Callback if something changed. Note that we need to poke the DSP on
    443       1.32   msaitoh 	 * the Broadcom PHYs if the media changes.
    444       1.10   thorpej 	 */
    445       1.23     perry 	if (sc->mii_media_active != mii->mii_media_active ||
    446       1.10   thorpej 	    sc->mii_media_status != mii->mii_media_status ||
    447       1.10   thorpej 	    cmd == MII_MEDIACHG) {
    448       1.61   msaitoh 		switch (sc->mii_mpd_oui) {
    449       1.61   msaitoh 		case MII_OUI_BROADCOM:
    450       1.61   msaitoh 			switch (sc->mii_mpd_model) {
    451       1.61   msaitoh 			case MII_MODEL_BROADCOM_BCM5400:
    452       1.43   msaitoh 				brgphy_bcm5401_dspcode(sc);
    453       1.61   msaitoh 				break;
    454       1.61   msaitoh 			case MII_MODEL_BROADCOM_BCM5401:
    455       1.61   msaitoh 				if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
    456       1.61   msaitoh 					brgphy_bcm5401_dspcode(sc);
    457       1.61   msaitoh 				break;
    458       1.61   msaitoh 			case MII_MODEL_BROADCOM_BCM5411:
    459       1.61   msaitoh 				brgphy_bcm5411_dspcode(sc);
    460       1.61   msaitoh 				break;
    461       1.61   msaitoh 			}
    462       1.43   msaitoh 			break;
    463       1.43   msaitoh 		}
    464       1.10   thorpej 	}
    465       1.43   msaitoh 
    466       1.43   msaitoh 	/* Callback if something changed. */
    467       1.43   msaitoh 	mii_phy_update(sc, cmd);
    468  1.76.28.1  christos 	return 0;
    469        1.1   thorpej }
    470        1.1   thorpej 
    471       1.21   thorpej static void
    472       1.71   msaitoh brgphy_copper_status(struct mii_softc *sc)
    473        1.1   thorpej {
    474        1.1   thorpej 	struct mii_data *mii = sc->mii_pdata;
    475        1.1   thorpej 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    476  1.76.28.1  christos 	uint16_t bmcr, bmsr, auxsts, gtsr;
    477        1.1   thorpej 
    478  1.76.28.2    martin 	KASSERT(mii_locked(mii));
    479  1.76.28.2    martin 
    480        1.1   thorpej 	mii->mii_media_status = IFM_AVALID;
    481        1.1   thorpej 	mii->mii_media_active = IFM_ETHER;
    482        1.1   thorpej 
    483  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    484  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    485       1.57       jym 	if (bmsr & BMSR_LINK)
    486        1.1   thorpej 		mii->mii_media_status |= IFM_ACTIVE;
    487        1.1   thorpej 
    488  1.76.28.1  christos 	PHY_READ(sc, MII_BMCR, &bmcr);
    489        1.1   thorpej 	if (bmcr & BMCR_ISO) {
    490        1.1   thorpej 		mii->mii_media_active |= IFM_NONE;
    491        1.1   thorpej 		mii->mii_media_status = 0;
    492        1.1   thorpej 		return;
    493        1.1   thorpej 	}
    494        1.1   thorpej 
    495        1.1   thorpej 	if (bmcr & BMCR_LOOP)
    496        1.1   thorpej 		mii->mii_media_active |= IFM_LOOP;
    497        1.1   thorpej 
    498        1.1   thorpej 	if (bmcr & BMCR_AUTOEN) {
    499        1.1   thorpej 		/*
    500  1.76.28.2    martin 		 * The media status bits are only valid if autonegotiation
    501        1.1   thorpej 		 * has completed (or it's disabled).
    502        1.1   thorpej 		 */
    503       1.57       jym 		if ((bmsr & BMSR_ACOMP) == 0) {
    504        1.1   thorpej 			/* Erg, still trying, I guess... */
    505        1.1   thorpej 			mii->mii_media_active |= IFM_NONE;
    506        1.1   thorpej 			return;
    507        1.1   thorpej 		}
    508        1.1   thorpej 
    509  1.76.28.1  christos 		PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts);
    510       1.71   msaitoh 
    511       1.71   msaitoh 		switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
    512       1.71   msaitoh 		case BRGPHY_RES_1000FD:
    513       1.71   msaitoh 			mii->mii_media_active |= IFM_1000_T | IFM_FDX;
    514  1.76.28.1  christos 			PHY_READ(sc, MII_100T2SR, &gtsr);
    515       1.71   msaitoh 			if (gtsr & GTSR_MS_RES)
    516       1.71   msaitoh 				mii->mii_media_active |= IFM_ETH_MASTER;
    517       1.71   msaitoh 			break;
    518       1.71   msaitoh 
    519       1.71   msaitoh 		case BRGPHY_RES_1000HD:
    520       1.71   msaitoh 			mii->mii_media_active |= IFM_1000_T | IFM_HDX;
    521  1.76.28.1  christos 			PHY_READ(sc, MII_100T2SR, &gtsr);
    522       1.71   msaitoh 			if (gtsr & GTSR_MS_RES)
    523       1.71   msaitoh 				mii->mii_media_active |= IFM_ETH_MASTER;
    524       1.71   msaitoh 			break;
    525       1.71   msaitoh 
    526       1.71   msaitoh 		case BRGPHY_RES_100FD:
    527       1.71   msaitoh 			mii->mii_media_active |= IFM_100_TX | IFM_FDX;
    528       1.71   msaitoh 			break;
    529       1.71   msaitoh 
    530       1.71   msaitoh 		case BRGPHY_RES_100T4:
    531       1.71   msaitoh 			mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
    532       1.71   msaitoh 			break;
    533       1.71   msaitoh 
    534       1.71   msaitoh 		case BRGPHY_RES_100HD:
    535       1.71   msaitoh 			mii->mii_media_active |= IFM_100_TX | IFM_HDX;
    536       1.71   msaitoh 			break;
    537       1.71   msaitoh 
    538       1.71   msaitoh 		case BRGPHY_RES_10FD:
    539       1.71   msaitoh 			mii->mii_media_active |= IFM_10_T | IFM_FDX;
    540       1.71   msaitoh 			break;
    541       1.71   msaitoh 
    542       1.71   msaitoh 		case BRGPHY_RES_10HD:
    543       1.71   msaitoh 			mii->mii_media_active |= IFM_10_T | IFM_HDX;
    544       1.71   msaitoh 			break;
    545       1.71   msaitoh 
    546       1.71   msaitoh 		default:
    547       1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    548       1.71   msaitoh 			mii->mii_media_status = 0;
    549       1.71   msaitoh 		}
    550       1.71   msaitoh 
    551       1.71   msaitoh 		if (mii->mii_media_active & IFM_FDX)
    552       1.71   msaitoh 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    553       1.71   msaitoh 
    554       1.71   msaitoh 	} else
    555       1.71   msaitoh 		mii->mii_media_active = ife->ifm_media;
    556       1.71   msaitoh }
    557       1.71   msaitoh 
    558       1.71   msaitoh void
    559       1.71   msaitoh brgphy_fiber_status(struct mii_softc *sc)
    560       1.71   msaitoh {
    561       1.71   msaitoh 	struct mii_data *mii = sc->mii_pdata;
    562       1.71   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    563  1.76.28.1  christos 	uint16_t bmcr, bmsr, anar, anlpar, result;
    564       1.71   msaitoh 
    565  1.76.28.2    martin 	KASSERT(mii_locked(mii));
    566  1.76.28.2    martin 
    567       1.71   msaitoh 	mii->mii_media_status = IFM_AVALID;
    568       1.71   msaitoh 	mii->mii_media_active = IFM_ETHER;
    569       1.71   msaitoh 
    570  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    571  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    572       1.71   msaitoh 	if (bmsr & BMSR_LINK)
    573       1.71   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
    574       1.57       jym 
    575  1.76.28.1  christos 	PHY_READ(sc, MII_BMCR, &bmcr);
    576       1.71   msaitoh 	if (bmcr & BMCR_LOOP)
    577       1.71   msaitoh 		mii->mii_media_active |= IFM_LOOP;
    578       1.57       jym 
    579       1.71   msaitoh 	if (bmcr & BMCR_AUTOEN) {
    580       1.71   msaitoh 		if ((bmsr & BMSR_ACOMP) == 0) {
    581       1.71   msaitoh 			/* Erg, still trying, I guess... */
    582       1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    583       1.71   msaitoh 			return;
    584       1.71   msaitoh 		}
    585       1.57       jym 
    586       1.71   msaitoh 		mii->mii_media_active |= IFM_1000_SX;
    587       1.57       jym 
    588  1.76.28.1  christos 		PHY_READ(sc, MII_ANAR, &anar);
    589  1.76.28.1  christos 		PHY_READ(sc, MII_ANLPAR, &anlpar);
    590  1.76.28.1  christos 		result = anar & anlpar;
    591       1.57       jym 
    592  1.76.28.1  christos 		if (result & ANAR_X_FD)
    593       1.71   msaitoh 			mii->mii_media_active |= IFM_FDX;
    594       1.71   msaitoh 		else
    595       1.71   msaitoh 			mii->mii_media_active |= IFM_HDX;
    596        1.1   thorpej 
    597       1.71   msaitoh 		if (mii->mii_media_active & IFM_FDX)
    598       1.71   msaitoh 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    599       1.71   msaitoh 	} else
    600       1.71   msaitoh 		mii->mii_media_active = ife->ifm_media;
    601       1.71   msaitoh }
    602        1.1   thorpej 
    603       1.71   msaitoh void
    604       1.71   msaitoh brgphy_5708s_status(struct mii_softc *sc)
    605       1.71   msaitoh {
    606       1.71   msaitoh 	struct mii_data *mii = sc->mii_pdata;
    607       1.71   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    608  1.76.28.1  christos 	uint16_t bmcr, bmsr;
    609        1.1   thorpej 
    610  1.76.28.2    martin 	KASSERT(mii_locked(mii));
    611  1.76.28.2    martin 
    612       1.71   msaitoh 	mii->mii_media_status = IFM_AVALID;
    613       1.71   msaitoh 	mii->mii_media_active = IFM_ETHER;
    614        1.1   thorpej 
    615  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    616  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    617       1.71   msaitoh 	if (bmsr & BMSR_LINK)
    618       1.71   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
    619        1.1   thorpej 
    620  1.76.28.1  christos 	PHY_READ(sc, MII_BMCR, &bmcr);
    621       1.71   msaitoh 	if (bmcr & BMCR_LOOP)
    622       1.71   msaitoh 		mii->mii_media_active |= IFM_LOOP;
    623        1.1   thorpej 
    624       1.71   msaitoh 	if (bmcr & BMCR_AUTOEN) {
    625  1.76.28.1  christos 		uint16_t xstat;
    626        1.1   thorpej 
    627       1.71   msaitoh 		if ((bmsr & BMSR_ACOMP) == 0) {
    628       1.71   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    629       1.71   msaitoh 			    BRGPHY_5708S_DIG_PG0);
    630  1.76.28.1  christos 			PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
    631       1.71   msaitoh 			if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) {
    632       1.71   msaitoh 				/* Erg, still trying, I guess... */
    633       1.57       jym 				mii->mii_media_active |= IFM_NONE;
    634       1.71   msaitoh 				return;
    635       1.57       jym 			}
    636        1.1   thorpej 		}
    637       1.57       jym 
    638       1.71   msaitoh 		PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    639       1.71   msaitoh 		    BRGPHY_5708S_DIG_PG0);
    640  1.76.28.1  christos 		PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
    641       1.71   msaitoh 
    642       1.71   msaitoh 		switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
    643       1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
    644       1.71   msaitoh 			mii->mii_media_active |= IFM_10_FL;
    645       1.71   msaitoh 			break;
    646       1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
    647       1.71   msaitoh 			mii->mii_media_active |= IFM_100_FX;
    648       1.71   msaitoh 			break;
    649       1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
    650       1.71   msaitoh 			mii->mii_media_active |= IFM_1000_SX;
    651       1.71   msaitoh 			break;
    652       1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
    653       1.71   msaitoh 			mii->mii_media_active |= IFM_2500_SX;
    654       1.71   msaitoh 			break;
    655       1.71   msaitoh 		}
    656       1.71   msaitoh 
    657       1.71   msaitoh 		if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
    658       1.71   msaitoh 			mii->mii_media_active |= IFM_FDX;
    659       1.71   msaitoh 		else
    660       1.71   msaitoh 			mii->mii_media_active |= IFM_HDX;
    661       1.71   msaitoh 
    662       1.71   msaitoh 		if (mii->mii_media_active & IFM_FDX) {
    663       1.71   msaitoh 			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE)
    664  1.76.28.1  christos 				mii->mii_media_active
    665  1.76.28.1  christos 				    |= IFM_FLOW | IFM_ETH_TXPAUSE;
    666       1.71   msaitoh 			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE)
    667  1.76.28.1  christos 				mii->mii_media_active
    668  1.76.28.1  christos 				    |= IFM_FLOW | IFM_ETH_RXPAUSE;
    669       1.71   msaitoh 		}
    670       1.71   msaitoh 	} else
    671       1.71   msaitoh 		mii->mii_media_active = ife->ifm_media;
    672       1.71   msaitoh }
    673       1.71   msaitoh 
    674       1.71   msaitoh static void
    675       1.71   msaitoh brgphy_5709s_status(struct mii_softc *sc)
    676       1.71   msaitoh {
    677       1.71   msaitoh 	struct mii_data *mii = sc->mii_pdata;
    678       1.71   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    679  1.76.28.1  christos 	uint16_t bmcr, bmsr, auxsts;
    680       1.71   msaitoh 
    681  1.76.28.2    martin 	KASSERT(mii_locked(mii));
    682  1.76.28.2    martin 
    683       1.71   msaitoh 	mii->mii_media_status = IFM_AVALID;
    684       1.71   msaitoh 	mii->mii_media_active = IFM_ETHER;
    685       1.71   msaitoh 
    686  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    687  1.76.28.1  christos 	PHY_READ(sc, MII_BMSR, &bmsr);
    688       1.71   msaitoh 	if (bmsr & BMSR_LINK)
    689       1.71   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
    690       1.71   msaitoh 
    691  1.76.28.1  christos 	PHY_READ(sc, MII_BMCR, &bmcr);
    692       1.71   msaitoh 	if (bmcr & BMCR_ISO) {
    693       1.71   msaitoh 		mii->mii_media_active |= IFM_NONE;
    694       1.71   msaitoh 		mii->mii_media_status = 0;
    695       1.71   msaitoh 		return;
    696       1.71   msaitoh 	}
    697       1.71   msaitoh 
    698       1.71   msaitoh 	if (bmcr & BMCR_LOOP)
    699       1.71   msaitoh 		mii->mii_media_active |= IFM_LOOP;
    700       1.71   msaitoh 
    701       1.71   msaitoh 	if (bmcr & BMCR_AUTOEN) {
    702       1.71   msaitoh 		/*
    703       1.71   msaitoh 		 * The media status bits are only valid of autonegotiation
    704       1.71   msaitoh 		 * has completed (or it's disabled).
    705       1.71   msaitoh 		 */
    706       1.71   msaitoh 		if ((bmsr & BMSR_ACOMP) == 0) {
    707       1.71   msaitoh 			/* Erg, still trying, I guess... */
    708       1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    709       1.71   msaitoh 			return;
    710       1.71   msaitoh 		}
    711       1.71   msaitoh 
    712       1.71   msaitoh 		/* 5709S has its own general purpose status registers */
    713  1.76.28.1  christos 		PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
    714  1.76.28.1  christos 		PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts);
    715       1.71   msaitoh 
    716       1.71   msaitoh 		PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    717       1.71   msaitoh 		    BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
    718       1.71   msaitoh 
    719       1.71   msaitoh 		switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
    720       1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
    721       1.71   msaitoh 			mii->mii_media_active |= IFM_10_FL;
    722       1.71   msaitoh 			break;
    723       1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
    724       1.71   msaitoh 			mii->mii_media_active |= IFM_100_FX;
    725       1.71   msaitoh 			break;
    726       1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
    727       1.71   msaitoh 			mii->mii_media_active |= IFM_1000_SX;
    728       1.71   msaitoh 			break;
    729       1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
    730       1.71   msaitoh 			mii->mii_media_active |= IFM_2500_SX;
    731       1.71   msaitoh 			break;
    732       1.71   msaitoh 		default:
    733       1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    734       1.71   msaitoh 			mii->mii_media_status = 0;
    735       1.71   msaitoh 			break;
    736       1.71   msaitoh 		}
    737       1.71   msaitoh 
    738       1.71   msaitoh 		if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
    739       1.71   msaitoh 			mii->mii_media_active |= IFM_FDX;
    740       1.71   msaitoh 		else
    741       1.71   msaitoh 			mii->mii_media_active |= IFM_HDX;
    742       1.71   msaitoh 
    743       1.19   thorpej 		if (mii->mii_media_active & IFM_FDX)
    744       1.20   thorpej 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    745        1.1   thorpej 	} else
    746        1.1   thorpej 		mii->mii_media_active = ife->ifm_media;
    747       1.10   thorpej }
    748       1.10   thorpej 
    749  1.76.28.2    martin static int
    750       1.32   msaitoh brgphy_mii_phy_auto(struct mii_softc *sc)
    751       1.32   msaitoh {
    752  1.76.28.1  christos 	uint16_t anar, ktcr = 0;
    753       1.32   msaitoh 
    754  1.76.28.2    martin 	KASSERT(mii_locked(sc->mii_pdata));
    755  1.76.28.2    martin 
    756       1.64   msaitoh 	sc->mii_ticks = 0;
    757       1.32   msaitoh 	brgphy_loop(sc);
    758       1.32   msaitoh 	PHY_RESET(sc);
    759       1.57       jym 
    760       1.57       jym 	if (sc->mii_flags & MIIF_HAVEFIBER) {
    761       1.57       jym 		anar = ANAR_X_FD | ANAR_X_HD;
    762       1.57       jym 		if (sc->mii_flags & MIIF_DOPAUSE)
    763       1.69   msaitoh 			anar |= ANAR_X_PAUSE_TOWARDS;
    764       1.57       jym 	} else {
    765       1.57       jym 		anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    766       1.57       jym 		if (sc->mii_flags & MIIF_DOPAUSE)
    767       1.66   msaitoh 			anar |= ANAR_FC | ANAR_PAUSE_ASYM;
    768       1.71   msaitoh 		ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
    769       1.71   msaitoh 		if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
    770       1.71   msaitoh 		    && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701))
    771       1.71   msaitoh 			ktcr |= GTCR_MAN_MS | GTCR_ADV_MS;
    772       1.71   msaitoh 		PHY_WRITE(sc, MII_100T2CR, ktcr);
    773       1.57       jym 	}
    774       1.32   msaitoh 	PHY_WRITE(sc, MII_ANAR, anar);
    775       1.57       jym 
    776       1.57       jym 	/* Start autonegotiation */
    777       1.69   msaitoh 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
    778       1.32   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
    779       1.32   msaitoh 
    780  1.76.28.1  christos 	return EJUSTRETURN;
    781       1.32   msaitoh }
    782       1.32   msaitoh 
    783  1.76.28.2    martin static void
    784       1.32   msaitoh brgphy_loop(struct mii_softc *sc)
    785       1.32   msaitoh {
    786  1.76.28.1  christos 	uint16_t bmsr;
    787       1.32   msaitoh 	int i;
    788       1.32   msaitoh 
    789  1.76.28.2    martin 	KASSERT(mii_locked(sc->mii_pdata));
    790  1.76.28.2    martin 
    791       1.32   msaitoh 	PHY_WRITE(sc, MII_BMCR, BMCR_LOOP);
    792       1.33   msaitoh 	for (i = 0; i < 15000; i++) {
    793  1.76.28.1  christos 		PHY_READ(sc, MII_BMSR, &bmsr);
    794       1.32   msaitoh 		if (!(bmsr & BMSR_LINK))
    795       1.32   msaitoh 			break;
    796       1.32   msaitoh 		DELAY(10);
    797       1.32   msaitoh 	}
    798       1.32   msaitoh }
    799       1.32   msaitoh 
    800       1.21   thorpej static void
    801       1.43   msaitoh brgphy_reset(struct mii_softc *sc)
    802       1.10   thorpej {
    803       1.56       jym 	struct brgphy_softc *bsc = device_private(sc->mii_dev);
    804  1.76.28.1  christos 	uint16_t reg;
    805       1.10   thorpej 
    806  1.76.28.2    martin 	KASSERT(mii_locked(sc->mii_pdata));
    807  1.76.28.2    martin 
    808       1.10   thorpej 	mii_phy_reset(sc);
    809       1.61   msaitoh 	switch (sc->mii_mpd_oui) {
    810       1.61   msaitoh 	case MII_OUI_BROADCOM:
    811       1.61   msaitoh 		switch (sc->mii_mpd_model) {
    812       1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5400:
    813       1.43   msaitoh 			brgphy_bcm5401_dspcode(sc);
    814       1.61   msaitoh 			break;
    815       1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5401:
    816       1.61   msaitoh 			if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
    817       1.61   msaitoh 				brgphy_bcm5401_dspcode(sc);
    818       1.61   msaitoh 			break;
    819       1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5411:
    820       1.61   msaitoh 			brgphy_bcm5411_dspcode(sc);
    821       1.61   msaitoh 			break;
    822       1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5421:
    823       1.61   msaitoh 			brgphy_bcm5421_dspcode(sc);
    824       1.61   msaitoh 			break;
    825       1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM54K2:
    826       1.61   msaitoh 			brgphy_bcm54k2_dspcode(sc);
    827       1.61   msaitoh 			break;
    828       1.61   msaitoh 		}
    829       1.43   msaitoh 		break;
    830       1.61   msaitoh 	case MII_OUI_BROADCOM3:
    831       1.61   msaitoh 		switch (sc->mii_mpd_model) {
    832       1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM5717C:
    833       1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM5719C:
    834       1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM5720C:
    835       1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM57765:
    836       1.61   msaitoh 			return;
    837       1.61   msaitoh 		}
    838       1.43   msaitoh 		break;
    839       1.61   msaitoh 	default:
    840       1.43   msaitoh 		break;
    841       1.43   msaitoh 	}
    842       1.15  jonathan 
    843       1.43   msaitoh 	/* Handle any bge (NetXtreme/NetLink) workarounds. */
    844       1.54    dyoung 	if (bsc->sc_isbge) {
    845       1.43   msaitoh 		if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
    846       1.43   msaitoh 
    847       1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_ADC_BUG)
    848       1.43   msaitoh 				brgphy_adc_bug(sc);
    849       1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG)
    850       1.43   msaitoh 				brgphy_5704_a0_bug(sc);
    851       1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_BER_BUG)
    852       1.43   msaitoh 				brgphy_ber_bug(sc);
    853       1.68   msaitoh 			else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) {
    854       1.43   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
    855  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
    856       1.43   msaitoh 
    857  1.76.28.1  christos 				if (bsc->sc_phyflags
    858       1.68   msaitoh 				    & BGEPHYF_ADJUST_TRIM) {
    859       1.43   msaitoh 					PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
    860       1.43   msaitoh 					    0x110b);
    861       1.43   msaitoh 					PHY_WRITE(sc, BRGPHY_TEST1,
    862       1.43   msaitoh 					    BRGPHY_TEST1_TRIM_EN | 0x4);
    863       1.43   msaitoh 				} else {
    864       1.43   msaitoh 					PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
    865       1.43   msaitoh 					    0x010b);
    866       1.43   msaitoh 				}
    867       1.15  jonathan 
    868       1.43   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
    869       1.43   msaitoh 			}
    870       1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_CRC_BUG)
    871       1.43   msaitoh 				brgphy_crc_bug(sc);
    872       1.15  jonathan 
    873       1.43   msaitoh 			/* Set Jumbo frame settings in the PHY. */
    874       1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE)
    875       1.43   msaitoh 				brgphy_jumbo_settings(sc);
    876       1.43   msaitoh 
    877       1.43   msaitoh 			/* Adjust output voltage */
    878       1.61   msaitoh 			if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    879       1.61   msaitoh 			    && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906))
    880       1.43   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
    881       1.43   msaitoh 
    882       1.43   msaitoh 			/* Enable Ethernet@Wirespeed */
    883       1.68   msaitoh 			if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED))
    884       1.43   msaitoh 				brgphy_eth_wirespeed(sc);
    885       1.43   msaitoh 
    886       1.52   msaitoh #if 0
    887       1.43   msaitoh 			/* Enable Link LED on Dell boxes */
    888       1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_NO_3LED) {
    889  1.76.28.1  christos 				PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &reg);
    890  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
    891  1.76.28.1  christos 				    reg & ~BRGPHY_PHY_EXTCTL_3_LED);
    892       1.43   msaitoh 			}
    893       1.43   msaitoh #endif
    894       1.43   msaitoh 		}
    895       1.57       jym 	/* Handle any bnx (NetXtreme II) workarounds. */
    896       1.57       jym 	} else if (bsc->sc_isbnx) {
    897  1.76.28.1  christos 		uint32_t chip_num = _BNX_CHIP_NUM(bsc->sc_chipid);
    898  1.76.28.1  christos 		uint32_t chip_id = _BNX_CHIP_ID(bsc->sc_chipid);
    899  1.76.28.1  christos 		uint32_t chip_rev = _BNX_CHIP_REV(bsc->sc_chipid);
    900  1.76.28.1  christos 
    901       1.61   msaitoh 		if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    902       1.61   msaitoh 		    && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) {
    903  1.76.28.1  christos 			/*
    904  1.76.28.1  christos 			 * Store autoneg capabilities/results in digital block
    905  1.76.28.1  christos 			 * (Page 0)
    906  1.76.28.1  christos 			 */
    907  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    908  1.76.28.1  christos 			    BRGPHY_5708S_DIG3_PG2);
    909  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
    910  1.76.28.1  christos 			    BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
    911  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    912  1.76.28.1  christos 			    BRGPHY_5708S_DIG_PG0);
    913       1.43   msaitoh 
    914       1.43   msaitoh 			/* Enable fiber mode and autodetection */
    915  1.76.28.1  christos 			PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, &reg);
    916  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg |
    917  1.76.28.1  christos 			    BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
    918  1.76.28.1  christos 			    BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
    919       1.43   msaitoh 
    920       1.43   msaitoh 			/* Enable parallel detection */
    921  1.76.28.1  christos 			PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, &reg);
    922  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
    923  1.76.28.1  christos 			    reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
    924  1.76.28.1  christos 
    925  1.76.28.1  christos 			/*
    926  1.76.28.1  christos 			 * Advertise 2.5G support through next page during
    927  1.76.28.1  christos 			 * autoneg
    928  1.76.28.1  christos 			 */
    929  1.76.28.1  christos 			if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
    930  1.76.28.1  christos 				PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
    931  1.76.28.1  christos 				    &reg);
    932  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
    933  1.76.28.1  christos 				    reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
    934  1.76.28.1  christos 			}
    935       1.43   msaitoh 
    936       1.43   msaitoh 			/* Increase TX signal amplitude */
    937  1.76.28.1  christos 			if ((chip_id == BNX_CHIP_ID_5708_A0) ||
    938  1.76.28.1  christos 			    (chip_id == BNX_CHIP_ID_5708_B0) ||
    939  1.76.28.1  christos 			    (chip_id == BNX_CHIP_ID_5708_B1)) {
    940  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    941       1.43   msaitoh 					BRGPHY_5708S_TX_MISC_PG5);
    942  1.76.28.1  christos 				PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, &reg);
    943  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
    944  1.76.28.1  christos 				    reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM);
    945  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    946       1.43   msaitoh 					BRGPHY_5708S_DIG_PG0);
    947       1.43   msaitoh 			}
    948       1.15  jonathan 
    949  1.76.28.1  christos 			/*
    950  1.76.28.1  christos 			 * Backplanes use special
    951  1.76.28.1  christos 			 * driver/pre-driver/pre-emphasis values.
    952  1.76.28.1  christos 			 */
    953       1.71   msaitoh 			if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
    954       1.71   msaitoh 			    (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
    955  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    956  1.76.28.1  christos 				    BRGPHY_5708S_TX_MISC_PG5);
    957  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
    958  1.76.28.1  christos 				    bsc->sc_port_hwcfg &
    959  1.76.28.1  christos 				    BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
    960  1.76.28.1  christos 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    961  1.76.28.1  christos 				    BRGPHY_5708S_DIG_PG0);
    962       1.43   msaitoh 			}
    963       1.71   msaitoh 		} else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    964       1.61   msaitoh 		    && (sc->mii_mpd_model ==  MII_MODEL_BROADCOM2_BCM5709S)) {
    965       1.57       jym 			/* Select the SerDes Digital block of the AN MMD. */
    966       1.57       jym 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    967       1.57       jym 			    BRGPHY_BLOCK_ADDR_SERDES_DIG);
    968       1.57       jym 
    969  1.76.28.1  christos 			PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, &reg);
    970       1.57       jym 			PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,
    971  1.76.28.1  christos 			    (reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |
    972       1.57       jym 			    BRGPHY_SD_DIG_1000X_CTL1_FIBER);
    973       1.57       jym 
    974       1.58       jym 			if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
    975       1.57       jym 				/* Select the Over 1G block of the AN MMD. */
    976       1.57       jym 				PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    977       1.57       jym 				    BRGPHY_BLOCK_ADDR_OVER_1G);
    978       1.57       jym 
    979       1.57       jym 				/*
    980       1.57       jym 				 * Enable autoneg "Next Page" to advertise
    981       1.57       jym 				 * 2.5G support.
    982       1.57       jym 				 */
    983  1.76.28.1  christos 				PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
    984  1.76.28.1  christos 				    &reg);
    985       1.57       jym 				PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
    986  1.76.28.1  christos 				    reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
    987       1.57       jym 			}
    988       1.57       jym 
    989  1.76.28.1  christos 			/*
    990  1.76.28.1  christos 			 * Select the Multi-Rate Backplane Ethernet block of
    991  1.76.28.1  christos 			 * the AN MMD.
    992  1.76.28.1  christos 			 */
    993  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    994  1.76.28.1  christos 			    BRGPHY_BLOCK_ADDR_MRBE);
    995  1.76.28.1  christos 
    996  1.76.28.1  christos 			/* Enable MRBE speed autoneg. */
    997  1.76.28.1  christos 			PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, &reg);
    998  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
    999  1.76.28.1  christos 			    reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE |
   1000  1.76.28.1  christos 			    BRGPHY_MRBE_MSG_PG5_NP_T2);
   1001  1.76.28.1  christos 
   1002  1.76.28.1  christos 			/* Select the Clause 73 User B0 block of the AN MMD. */
   1003  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
   1004  1.76.28.1  christos 			    BRGPHY_BLOCK_ADDR_CL73_USER_B0);
   1005  1.76.28.1  christos 
   1006  1.76.28.1  christos 			/* Enable MRBE speed autoneg. */
   1007  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
   1008  1.76.28.1  christos 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
   1009  1.76.28.1  christos 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
   1010  1.76.28.1  christos 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
   1011  1.76.28.1  christos 
   1012  1.76.28.1  christos 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
   1013  1.76.28.1  christos 			    BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
   1014  1.76.28.1  christos 
   1015  1.76.28.1  christos 		} else if (chip_num == BNX_CHIP_NUM_5709) {
   1016  1.76.28.1  christos 			if ((chip_rev == BNX_CHIP_REV_Ax) ||
   1017  1.76.28.1  christos 			    (chip_rev == BNX_CHIP_REV_Bx))
   1018       1.58       jym 				brgphy_disable_early_dac(sc);
   1019       1.58       jym 
   1020       1.58       jym 			/* Set Jumbo frame settings in the PHY. */
   1021       1.58       jym 			brgphy_jumbo_settings(sc);
   1022       1.58       jym 
   1023       1.58       jym 			/* Enable Ethernet@Wirespeed */
   1024       1.58       jym 			brgphy_eth_wirespeed(sc);
   1025       1.43   msaitoh 		} else {
   1026       1.43   msaitoh 			if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
   1027       1.43   msaitoh 				brgphy_ber_bug(sc);
   1028       1.18   hannken 
   1029       1.43   msaitoh 				/* Set Jumbo frame settings in the PHY. */
   1030       1.43   msaitoh 				brgphy_jumbo_settings(sc);
   1031       1.18   hannken 
   1032       1.43   msaitoh 				/* Enable Ethernet@Wirespeed */
   1033       1.43   msaitoh 				brgphy_eth_wirespeed(sc);
   1034       1.43   msaitoh 			}
   1035       1.43   msaitoh 		}
   1036       1.43   msaitoh 	}
   1037       1.34     markd }
   1038       1.34     markd 
   1039       1.16  jonathan /* Turn off tap power management on 5401. */
   1040       1.10   thorpej static void
   1041       1.43   msaitoh brgphy_bcm5401_dspcode(struct mii_softc *sc)
   1042       1.10   thorpej {
   1043       1.10   thorpej 	static const struct {
   1044       1.10   thorpej 		int		reg;
   1045       1.10   thorpej 		uint16_t	val;
   1046       1.10   thorpej 	} dspcode[] = {
   1047       1.16  jonathan 		{ BRGPHY_MII_AUXCTL,		0x0c20 },
   1048       1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0012 },
   1049       1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x1804 },
   1050       1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0013 },
   1051       1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x1204 },
   1052       1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
   1053       1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0132 },
   1054       1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
   1055       1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0232 },
   1056       1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
   1057       1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a20 },
   1058       1.10   thorpej 		{ 0,				0 },
   1059       1.10   thorpej 	};
   1060       1.10   thorpej 	int i;
   1061       1.10   thorpej 
   1062       1.10   thorpej 	for (i = 0; dspcode[i].reg != 0; i++)
   1063       1.10   thorpej 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1064       1.61   msaitoh 	delay(40);
   1065       1.10   thorpej }
   1066       1.10   thorpej 
   1067       1.10   thorpej static void
   1068       1.43   msaitoh brgphy_bcm5411_dspcode(struct mii_softc *sc)
   1069       1.10   thorpej {
   1070       1.10   thorpej 	static const struct {
   1071       1.10   thorpej 		int		reg;
   1072       1.10   thorpej 		uint16_t	val;
   1073       1.10   thorpej 	} dspcode[] = {
   1074       1.10   thorpej 		{ 0x1c,				0x8c23 },
   1075       1.10   thorpej 		{ 0x1c,				0x8ca3 },
   1076       1.10   thorpej 		{ 0x1c,				0x8c23 },
   1077       1.15  jonathan 		{ 0,				0 },
   1078       1.15  jonathan 	};
   1079       1.15  jonathan 	int i;
   1080       1.15  jonathan 
   1081       1.15  jonathan 	for (i = 0; dspcode[i].reg != 0; i++)
   1082       1.15  jonathan 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1083       1.15  jonathan }
   1084       1.15  jonathan 
   1085  1.76.28.2    martin static void
   1086       1.43   msaitoh brgphy_bcm5421_dspcode(struct mii_softc *sc)
   1087       1.43   msaitoh {
   1088       1.43   msaitoh 	uint16_t data;
   1089       1.43   msaitoh 
   1090       1.43   msaitoh 	/* Set Class A mode */
   1091       1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
   1092  1.76.28.1  christos 	PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
   1093       1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
   1094       1.43   msaitoh 
   1095       1.43   msaitoh 	/* Set FFE gamma override to -0.125 */
   1096       1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
   1097  1.76.28.1  christos 	PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
   1098       1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
   1099       1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
   1100  1.76.28.1  christos 	PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data);
   1101       1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
   1102       1.43   msaitoh }
   1103       1.43   msaitoh 
   1104  1.76.28.2    martin static void
   1105       1.43   msaitoh brgphy_bcm54k2_dspcode(struct mii_softc *sc)
   1106       1.43   msaitoh {
   1107       1.43   msaitoh 	static const struct {
   1108       1.43   msaitoh 		int		reg;
   1109       1.43   msaitoh 		uint16_t	val;
   1110       1.43   msaitoh 	} dspcode[] = {
   1111       1.43   msaitoh 		{ 4,				0x01e1 },
   1112       1.43   msaitoh 		{ 9,				0x0300 },
   1113       1.43   msaitoh 		{ 0,				0 },
   1114       1.43   msaitoh 	};
   1115       1.43   msaitoh 	int i;
   1116       1.43   msaitoh 
   1117       1.43   msaitoh 	for (i = 0; dspcode[i].reg != 0; i++)
   1118       1.43   msaitoh 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1119       1.43   msaitoh }
   1120       1.43   msaitoh 
   1121       1.15  jonathan static void
   1122       1.43   msaitoh brgphy_adc_bug(struct mii_softc *sc)
   1123       1.15  jonathan {
   1124       1.15  jonathan 	static const struct {
   1125       1.15  jonathan 		int		reg;
   1126       1.15  jonathan 		uint16_t	val;
   1127       1.15  jonathan 	} dspcode[] = {
   1128       1.15  jonathan 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
   1129       1.15  jonathan 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
   1130       1.15  jonathan 		{ BRGPHY_MII_DSP_RW_PORT,	0x2aaa },
   1131       1.43   msaitoh 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
   1132       1.43   msaitoh 		{ BRGPHY_MII_DSP_RW_PORT,	0x0323 },
   1133       1.43   msaitoh 		{ BRGPHY_MII_AUXCTL,		0x0400 },
   1134       1.15  jonathan 		{ 0,				0 },
   1135       1.15  jonathan 	};
   1136       1.15  jonathan 	int i;
   1137       1.15  jonathan 
   1138       1.15  jonathan 	for (i = 0; dspcode[i].reg != 0; i++)
   1139       1.15  jonathan 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1140       1.15  jonathan }
   1141       1.15  jonathan 
   1142       1.15  jonathan static void
   1143       1.43   msaitoh brgphy_5704_a0_bug(struct mii_softc *sc)
   1144       1.15  jonathan {
   1145       1.15  jonathan 	static const struct {
   1146       1.15  jonathan 		int		reg;
   1147       1.15  jonathan 		uint16_t	val;
   1148       1.15  jonathan 	} dspcode[] = {
   1149       1.15  jonathan 		{ 0x1c,				0x8d68 },
   1150       1.33   msaitoh 		{ 0x1c,				0x8d68 },
   1151       1.10   thorpej 		{ 0,				0 },
   1152       1.10   thorpej 	};
   1153       1.10   thorpej 	int i;
   1154       1.10   thorpej 
   1155       1.10   thorpej 	for (i = 0; dspcode[i].reg != 0; i++)
   1156       1.10   thorpej 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1157        1.1   thorpej }
   1158       1.22      cube 
   1159       1.22      cube static void
   1160       1.43   msaitoh brgphy_ber_bug(struct mii_softc *sc)
   1161       1.22      cube {
   1162       1.22      cube 	static const struct {
   1163       1.22      cube 		int		reg;
   1164       1.22      cube 		uint16_t	val;
   1165       1.22      cube 	} dspcode[] = {
   1166       1.22      cube 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
   1167       1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
   1168       1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x310b },
   1169       1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
   1170       1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x9506 },
   1171       1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x401f },
   1172       1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x14e2 },
   1173       1.22      cube 		{ BRGPHY_MII_AUXCTL,		0x0400 },
   1174       1.22      cube 		{ 0,				0 },
   1175       1.22      cube 	};
   1176       1.22      cube 	int i;
   1177       1.22      cube 
   1178       1.22      cube 	for (i = 0; dspcode[i].reg != 0; i++)
   1179       1.22      cube 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1180       1.22      cube }
   1181       1.34     markd 
   1182       1.43   msaitoh /* BCM5701 A0/B0 CRC bug workaround */
   1183  1.76.28.2    martin static void
   1184       1.43   msaitoh brgphy_crc_bug(struct mii_softc *sc)
   1185       1.34     markd {
   1186       1.34     markd 	static const struct {
   1187       1.34     markd 		int		reg;
   1188       1.34     markd 		uint16_t	val;
   1189       1.34     markd 	} dspcode[] = {
   1190       1.43   msaitoh 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0a75 },
   1191       1.43   msaitoh 		{ 0x1c,				0x8c68 },
   1192       1.43   msaitoh 		{ 0x1c,				0x8d68 },
   1193       1.43   msaitoh 		{ 0x1c,				0x8c68 },
   1194       1.34     markd 		{ 0,				0 },
   1195       1.34     markd 	};
   1196       1.34     markd 	int i;
   1197       1.34     markd 
   1198       1.34     markd 	for (i = 0; dspcode[i].reg != 0; i++)
   1199       1.34     markd 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1200       1.34     markd }
   1201       1.52   msaitoh 
   1202       1.52   msaitoh static void
   1203       1.58       jym brgphy_disable_early_dac(struct mii_softc *sc)
   1204       1.58       jym {
   1205  1.76.28.1  christos 	uint16_t val;
   1206       1.58       jym 
   1207       1.58       jym 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
   1208  1.76.28.1  christos 	PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &val);
   1209       1.58       jym 	val &= ~(1 << 8);
   1210       1.58       jym 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
   1211       1.58       jym 
   1212       1.58       jym }
   1213       1.58       jym 
   1214       1.58       jym static void
   1215       1.52   msaitoh brgphy_jumbo_settings(struct mii_softc *sc)
   1216       1.52   msaitoh {
   1217  1.76.28.1  christos 	uint16_t val;
   1218       1.52   msaitoh 
   1219       1.52   msaitoh 	/* Set Jumbo frame settings in the PHY. */
   1220       1.61   msaitoh 	if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
   1221       1.61   msaitoh 	    && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) {
   1222       1.52   msaitoh 		/* Cannot do read-modify-write on the BCM5401 */
   1223       1.52   msaitoh 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
   1224       1.52   msaitoh 	} else {
   1225       1.52   msaitoh 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
   1226  1.76.28.1  christos 		PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
   1227       1.52   msaitoh 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
   1228  1.76.28.1  christos 		    val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
   1229       1.52   msaitoh 	}
   1230       1.52   msaitoh 
   1231  1.76.28.1  christos 	PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &val);
   1232  1.76.28.1  christos 	PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
   1233       1.52   msaitoh }
   1234       1.52   msaitoh 
   1235       1.52   msaitoh static void
   1236       1.52   msaitoh brgphy_eth_wirespeed(struct mii_softc *sc)
   1237       1.52   msaitoh {
   1238  1.76.28.1  christos 	uint16_t val;
   1239       1.52   msaitoh 
   1240       1.52   msaitoh 	/* Enable Ethernet@Wirespeed */
   1241       1.52   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
   1242  1.76.28.1  christos 	PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
   1243  1.76.28.1  christos 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
   1244       1.52   msaitoh }
   1245