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brgphy.c revision 1.86
      1  1.86   msaitoh /*	$NetBSD: brgphy.c,v 1.86 2019/11/27 10:19:20 msaitoh Exp $	*/
      2   1.1   thorpej 
      3   1.1   thorpej /*-
      4   1.1   thorpej  * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
      5   1.1   thorpej  * All rights reserved.
      6   1.1   thorpej  *
      7   1.1   thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1   thorpej  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9   1.1   thorpej  * NASA Ames Research Center.
     10   1.1   thorpej  *
     11   1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     12   1.1   thorpej  * modification, are permitted provided that the following conditions
     13   1.1   thorpej  * are met:
     14   1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     15   1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     16   1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     17   1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     18   1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     19   1.1   thorpej  *
     20   1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21   1.1   thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22   1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23   1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24   1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25   1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26   1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27   1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28   1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29   1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30   1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     31   1.1   thorpej  */
     32   1.1   thorpej 
     33   1.1   thorpej /*
     34   1.1   thorpej  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
     35   1.1   thorpej  *
     36   1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     37   1.1   thorpej  * modification, are permitted provided that the following conditions
     38   1.1   thorpej  * are met:
     39   1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     40   1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     41   1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     42   1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     43   1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     44   1.1   thorpej  *
     45   1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     46   1.1   thorpej  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     47   1.1   thorpej  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     48   1.1   thorpej  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     49   1.1   thorpej  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     50   1.1   thorpej  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     51   1.1   thorpej  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     52   1.1   thorpej  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     53   1.1   thorpej  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     54   1.1   thorpej  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     55   1.1   thorpej  */
     56   1.1   thorpej 
     57   1.1   thorpej /*
     58  1.57       jym  * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs.
     59   1.1   thorpej  *
     60   1.1   thorpej  * Programming information for this PHY was gleaned from FreeBSD
     61   1.1   thorpej  * (they were apparently able to get a datasheet from Broadcom).
     62   1.1   thorpej  */
     63   1.5     lukem 
     64   1.5     lukem #include <sys/cdefs.h>
     65  1.86   msaitoh __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.86 2019/11/27 10:19:20 msaitoh Exp $");
     66   1.1   thorpej 
     67   1.1   thorpej #include <sys/param.h>
     68   1.1   thorpej #include <sys/systm.h>
     69   1.1   thorpej #include <sys/kernel.h>
     70   1.1   thorpej #include <sys/device.h>
     71   1.1   thorpej #include <sys/socket.h>
     72   1.1   thorpej #include <sys/errno.h>
     73  1.44   msaitoh #include <prop/proplib.h>
     74   1.1   thorpej 
     75   1.1   thorpej #include <net/if.h>
     76   1.1   thorpej #include <net/if_media.h>
     77   1.1   thorpej 
     78   1.1   thorpej #include <dev/mii/mii.h>
     79   1.1   thorpej #include <dev/mii/miivar.h>
     80   1.1   thorpej #include <dev/mii/miidevs.h>
     81   1.1   thorpej #include <dev/mii/brgphyreg.h>
     82   1.1   thorpej 
     83  1.43   msaitoh #include <dev/pci/if_bgereg.h>
     84  1.43   msaitoh #include <dev/pci/if_bnxreg.h>
     85  1.43   msaitoh 
     86  1.39   xtraeme static int	brgphymatch(device_t, cfdata_t, void *);
     87  1.39   xtraeme static void	brgphyattach(device_t, device_t, void *);
     88   1.1   thorpej 
     89  1.44   msaitoh struct brgphy_softc {
     90  1.44   msaitoh 	struct mii_softc sc_mii;
     91  1.54    dyoung 	bool sc_isbge;
     92  1.54    dyoung 	bool sc_isbnx;
     93  1.71   msaitoh 	uint32_t sc_chipid;	/* parent's chipid */
     94  1.71   msaitoh 	uint32_t sc_phyflags;	/* parent's phyflags */
     95  1.71   msaitoh 	uint32_t sc_shared_hwcfg; /* shared hw config */
     96  1.71   msaitoh 	uint32_t sc_port_hwcfg;	/* port specific hw config */
     97  1.44   msaitoh };
     98  1.44   msaitoh 
     99  1.44   msaitoh CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc),
    100  1.42    dyoung     brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL,
    101  1.42    dyoung     DVF_DETACH_SHUTDOWN);
    102   1.1   thorpej 
    103  1.21   thorpej static int	brgphy_service(struct mii_softc *, struct mii_data *, int);
    104  1.71   msaitoh static void	brgphy_copper_status(struct mii_softc *);
    105  1.71   msaitoh static void	brgphy_fiber_status(struct mii_softc *);
    106  1.71   msaitoh static void	brgphy_5708s_status(struct mii_softc *);
    107  1.71   msaitoh static void	brgphy_5709s_status(struct mii_softc *);
    108  1.32   msaitoh static int	brgphy_mii_phy_auto(struct mii_softc *);
    109  1.32   msaitoh static void	brgphy_loop(struct mii_softc *);
    110  1.43   msaitoh static void	brgphy_reset(struct mii_softc *);
    111  1.43   msaitoh static void	brgphy_bcm5401_dspcode(struct mii_softc *);
    112  1.43   msaitoh static void	brgphy_bcm5411_dspcode(struct mii_softc *);
    113  1.43   msaitoh static void	brgphy_bcm5421_dspcode(struct mii_softc *);
    114  1.43   msaitoh static void	brgphy_bcm54k2_dspcode(struct mii_softc *);
    115  1.43   msaitoh static void	brgphy_adc_bug(struct mii_softc *);
    116  1.43   msaitoh static void	brgphy_5704_a0_bug(struct mii_softc *);
    117  1.43   msaitoh static void	brgphy_ber_bug(struct mii_softc *);
    118  1.43   msaitoh static void	brgphy_crc_bug(struct mii_softc *);
    119  1.58       jym static void	brgphy_disable_early_dac(struct mii_softc *);
    120  1.52   msaitoh static void	brgphy_jumbo_settings(struct mii_softc *);
    121  1.52   msaitoh static void	brgphy_eth_wirespeed(struct mii_softc *);
    122   1.1   thorpej 
    123  1.10   thorpej 
    124  1.71   msaitoh static const struct mii_phy_funcs brgphy_copper_funcs = {
    125  1.71   msaitoh 	brgphy_service, brgphy_copper_status, brgphy_reset,
    126  1.71   msaitoh };
    127  1.71   msaitoh 
    128  1.71   msaitoh static const struct mii_phy_funcs brgphy_fiber_funcs = {
    129  1.71   msaitoh 	brgphy_service, brgphy_fiber_status, brgphy_reset,
    130  1.71   msaitoh };
    131  1.71   msaitoh 
    132  1.71   msaitoh static const struct mii_phy_funcs brgphy_5708s_funcs = {
    133  1.71   msaitoh 	brgphy_service, brgphy_5708s_status, brgphy_reset,
    134  1.71   msaitoh };
    135  1.71   msaitoh 
    136  1.71   msaitoh static const struct mii_phy_funcs brgphy_5709s_funcs = {
    137  1.71   msaitoh 	brgphy_service, brgphy_5709s_status, brgphy_reset,
    138  1.34     markd };
    139  1.34     markd 
    140  1.21   thorpej static const struct mii_phydesc brgphys[] = {
    141  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5400),
    142  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5401),
    143  1.82   msaitoh 	MII_PHY_DESC(BROADCOM, BCM5402),
    144  1.82   msaitoh 	MII_PHY_DESC(BROADCOM, BCM5404),
    145  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5411),
    146  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5421),
    147  1.82   msaitoh 	MII_PHY_DESC(BROADCOM, BCM5424),
    148  1.82   msaitoh 	MII_PHY_DESC(BROADCOM, BCM5461),
    149  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5462),
    150  1.82   msaitoh 	MII_PHY_DESC(BROADCOM, BCM5464),
    151  1.82   msaitoh 	MII_PHY_DESC(BROADCOM, BCM5466),
    152  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM54K2),
    153  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5701),
    154  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5703),
    155  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5704),
    156  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5705),
    157  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5706),
    158  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5714),
    159  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5750),
    160  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5752),
    161  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5780),
    162  1.81  christos 	MII_PHY_DESC(BROADCOM, BCM5708C),
    163  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5481),
    164  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5482),
    165  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5708S),
    166  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5709C),
    167  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5709S),
    168  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5709CAX),
    169  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5722),
    170  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5754),
    171  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5755),
    172  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5756),
    173  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5761),
    174  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5784),
    175  1.81  christos 	MII_PHY_DESC(BROADCOM2, BCM5785),
    176  1.81  christos 	MII_PHY_DESC(BROADCOM3, BCM5717C),
    177  1.81  christos 	MII_PHY_DESC(BROADCOM3, BCM5719C),
    178  1.81  christos 	MII_PHY_DESC(BROADCOM3, BCM5720C),
    179  1.81  christos 	MII_PHY_DESC(BROADCOM3, BCM57765),
    180  1.81  christos 	MII_PHY_DESC(BROADCOM3, BCM57780),
    181  1.81  christos 	MII_PHY_DESC(BROADCOM4, BCM5725C),
    182  1.81  christos 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
    183  1.81  christos 	MII_PHY_END,
    184   1.1   thorpej };
    185   1.1   thorpej 
    186  1.21   thorpej static int
    187  1.48   tsutsui brgphymatch(device_t parent, cfdata_t match, void *aux)
    188   1.1   thorpej {
    189   1.1   thorpej 	struct mii_attach_args *ma = aux;
    190   1.1   thorpej 
    191   1.2   thorpej 	if (mii_phy_match(ma, brgphys) != NULL)
    192  1.83   msaitoh 		return 10;
    193   1.1   thorpej 
    194  1.83   msaitoh 	return 0;
    195   1.1   thorpej }
    196   1.1   thorpej 
    197  1.21   thorpej static void
    198  1.46    cegger brgphyattach(device_t parent, device_t self, void *aux)
    199   1.1   thorpej {
    200  1.44   msaitoh 	struct brgphy_softc *bsc = device_private(self);
    201  1.44   msaitoh 	struct mii_softc *sc = &bsc->sc_mii;
    202   1.1   thorpej 	struct mii_attach_args *ma = aux;
    203   1.1   thorpej 	struct mii_data *mii = ma->mii_data;
    204   1.2   thorpej 	const struct mii_phydesc *mpd;
    205  1.44   msaitoh 	prop_dictionary_t dict;
    206   1.1   thorpej 
    207   1.2   thorpej 	mpd = mii_phy_match(ma, brgphys);
    208  1.17   thorpej 	aprint_naive(": Media interface\n");
    209  1.17   thorpej 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
    210   1.1   thorpej 
    211  1.39   xtraeme 	sc->mii_dev = self;
    212   1.1   thorpej 	sc->mii_inst = mii->mii_instance;
    213   1.1   thorpej 	sc->mii_phy = ma->mii_phyno;
    214  1.61   msaitoh 	sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
    215  1.32   msaitoh 	sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
    216  1.43   msaitoh 	sc->mii_mpd_rev = MII_REV(ma->mii_id2);
    217   1.1   thorpej 	sc->mii_pdata = mii;
    218   1.6   thorpej 	sc->mii_flags = ma->mii_flags;
    219  1.10   thorpej 
    220  1.58       jym 	if (device_is_a(parent, "bge"))
    221  1.54    dyoung 		bsc->sc_isbge = true;
    222  1.58       jym 	else if (device_is_a(parent, "bnx"))
    223  1.54    dyoung 		bsc->sc_isbnx = true;
    224  1.58       jym 
    225  1.72   msaitoh 	dict = device_properties(parent);
    226  1.58       jym 	if (bsc->sc_isbge || bsc->sc_isbnx) {
    227  1.57       jym 		if (!prop_dictionary_get_uint32(dict, "phyflags",
    228  1.58       jym 		    &bsc->sc_phyflags))
    229  1.58       jym 			aprint_error_dev(self, "failed to get phyflags\n");
    230  1.58       jym 		if (!prop_dictionary_get_uint32(dict, "chipid",
    231  1.58       jym 		    &bsc->sc_chipid))
    232  1.58       jym 			aprint_error_dev(self, "failed to get chipid\n");
    233  1.44   msaitoh 	}
    234  1.57       jym 
    235  1.71   msaitoh 	if (bsc->sc_isbnx) {
    236  1.71   msaitoh 		/* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */
    237  1.71   msaitoh 		if (!prop_dictionary_get_uint32(dict, "shared_hwcfg",
    238  1.71   msaitoh 			&bsc->sc_shared_hwcfg))
    239  1.71   msaitoh 			aprint_error_dev(self, "failed to get shared_hwcfg\n");
    240  1.71   msaitoh 		if (!prop_dictionary_get_uint32(dict, "port_hwcfg",
    241  1.71   msaitoh 			&bsc->sc_port_hwcfg))
    242  1.71   msaitoh 			aprint_error_dev(self, "failed to get port_hwcfg\n");
    243  1.71   msaitoh 	}
    244  1.71   msaitoh 
    245  1.71   msaitoh 	if (sc->mii_flags & MIIF_HAVEFIBER) {
    246  1.74   msaitoh 		if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    247  1.74   msaitoh 		    && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S)
    248  1.71   msaitoh 			sc->mii_funcs = &brgphy_5708s_funcs;
    249  1.74   msaitoh 		else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    250  1.75   msaitoh 		    && (sc->mii_mpd_model ==  MII_MODEL_BROADCOM2_BCM5709S)) {
    251  1.75   msaitoh 			if (bsc->sc_isbnx)
    252  1.75   msaitoh 				sc->mii_funcs = &brgphy_5709s_funcs;
    253  1.75   msaitoh 			else {
    254  1.75   msaitoh 				/*
    255  1.75   msaitoh 				 * XXX
    256  1.75   msaitoh 				 * 5720S and 5709S shares the same PHY id.
    257  1.75   msaitoh 				 * Assume 5720S PHY if parent device is bge(4).
    258  1.75   msaitoh 				 */
    259  1.75   msaitoh 				sc->mii_funcs = &brgphy_5708s_funcs;
    260  1.75   msaitoh 			}
    261  1.75   msaitoh 		} else
    262  1.71   msaitoh 			sc->mii_funcs = &brgphy_fiber_funcs;
    263  1.71   msaitoh 	} else
    264  1.71   msaitoh 		sc->mii_funcs = &brgphy_copper_funcs;
    265  1.71   msaitoh 
    266  1.63   msaitoh 	PHY_RESET(sc);
    267  1.63   msaitoh 
    268  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
    269  1.79   msaitoh 	sc->mii_capabilities &= ma->mii_capmask;
    270  1.63   msaitoh 	if (sc->mii_capabilities & BMSR_EXTSTAT)
    271  1.79   msaitoh 		PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
    272  1.63   msaitoh 
    273  1.75   msaitoh 	if (sc->mii_flags & MIIF_HAVEFIBER) {
    274  1.75   msaitoh 		sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
    275  1.57       jym 
    276  1.75   msaitoh 		/*
    277  1.75   msaitoh 		 * Set the proper bits for capabilities so that the
    278  1.75   msaitoh 		 * correct media get selected by mii_phy_add_media()
    279  1.75   msaitoh 		 */
    280  1.75   msaitoh 		sc->mii_capabilities |= BMSR_ANEG;
    281  1.75   msaitoh 		sc->mii_capabilities &= ~BMSR_100T4;
    282  1.75   msaitoh 		sc->mii_extcapabilities |= EXTSR_1000XFDX;
    283  1.75   msaitoh 
    284  1.75   msaitoh 		if (bsc->sc_isbnx) {
    285  1.57       jym 			/*
    286  1.75   msaitoh 			 * 2.5Gb support is a software enabled feature
    287  1.75   msaitoh 			 * on the BCM5708S and BCM5709S controllers.
    288  1.57       jym 			 */
    289  1.57       jym #define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
    290  1.75   msaitoh 			if (bsc->sc_phyflags
    291  1.75   msaitoh 			    & BNX_PHY_2_5G_CAPABLE_FLAG) {
    292  1.75   msaitoh 				ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX,
    293  1.75   msaitoh 					IFM_FDX, sc->mii_inst), 0);
    294  1.86   msaitoh 				aprint_normal_dev(self, "2500baseSX-FDX\n");
    295  1.57       jym #undef ADD
    296  1.57       jym 			}
    297  1.57       jym 		}
    298  1.57       jym 	}
    299  1.75   msaitoh 	mii_phy_add_media(sc);
    300   1.1   thorpej }
    301   1.1   thorpej 
    302  1.21   thorpej static int
    303   1.4   thorpej brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
    304   1.1   thorpej {
    305   1.1   thorpej 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    306  1.79   msaitoh 	uint16_t reg, speed, gig;
    307   1.1   thorpej 
    308   1.1   thorpej 	switch (cmd) {
    309   1.1   thorpej 	case MII_POLLSTAT:
    310  1.73   msaitoh 		/* If we're not polling our PHY instance, just return. */
    311   1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    312  1.83   msaitoh 			return 0;
    313   1.1   thorpej 		break;
    314   1.1   thorpej 
    315   1.1   thorpej 	case MII_MEDIACHG:
    316   1.1   thorpej 		/*
    317   1.1   thorpej 		 * If the media indicates a different PHY instance,
    318   1.1   thorpej 		 * isolate ourselves.
    319   1.1   thorpej 		 */
    320   1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
    321  1.79   msaitoh 			PHY_READ(sc, MII_BMCR, &reg);
    322   1.1   thorpej 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
    323  1.83   msaitoh 			return 0;
    324   1.1   thorpej 		}
    325   1.1   thorpej 
    326  1.73   msaitoh 		/* If the interface is not up, don't do anything. */
    327   1.1   thorpej 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    328   1.1   thorpej 			break;
    329   1.1   thorpej 
    330  1.32   msaitoh 		PHY_RESET(sc); /* XXX hardware bug work-around */
    331  1.32   msaitoh 
    332  1.32   msaitoh 		switch (IFM_SUBTYPE(ife->ifm_media)) {
    333  1.32   msaitoh 		case IFM_AUTO:
    334  1.32   msaitoh 			(void) brgphy_mii_phy_auto(sc);
    335  1.32   msaitoh 			break;
    336  1.71   msaitoh 		case IFM_2500_SX:
    337  1.71   msaitoh 			speed = BRGPHY_5708S_BMCR_2500;
    338  1.71   msaitoh 			goto setit;
    339  1.71   msaitoh 		case IFM_1000_SX:
    340  1.32   msaitoh 		case IFM_1000_T:
    341  1.32   msaitoh 			speed = BMCR_S1000;
    342  1.32   msaitoh 			goto setit;
    343  1.32   msaitoh 		case IFM_100_TX:
    344  1.32   msaitoh 			speed = BMCR_S100;
    345  1.32   msaitoh 			goto setit;
    346  1.32   msaitoh 		case IFM_10_T:
    347  1.32   msaitoh 			speed = BMCR_S10;
    348  1.32   msaitoh setit:
    349  1.32   msaitoh 			brgphy_loop(sc);
    350  1.84   msaitoh 			if ((ife->ifm_media & IFM_FDX) != 0) {
    351  1.32   msaitoh 				speed |= BMCR_FDX;
    352  1.32   msaitoh 				gig = GTCR_ADV_1000TFDX;
    353  1.69   msaitoh 			} else
    354  1.32   msaitoh 				gig = GTCR_ADV_1000THDX;
    355  1.32   msaitoh 
    356  1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, 0);
    357  1.51    bouyer 			PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
    358  1.32   msaitoh 			PHY_WRITE(sc, MII_BMCR, speed);
    359  1.32   msaitoh 
    360  1.71   msaitoh 			if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) &&
    361  1.71   msaitoh 			    (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) &&
    362  1.71   msaitoh 			    (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX))
    363  1.32   msaitoh 				break;
    364  1.32   msaitoh 
    365  1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, gig);
    366  1.32   msaitoh 			PHY_WRITE(sc, MII_BMCR,
    367  1.65   msaitoh 			    speed | BMCR_AUTOEN | BMCR_STARTNEG);
    368  1.32   msaitoh 
    369  1.61   msaitoh 			if ((sc->mii_mpd_oui != MII_OUI_BROADCOM)
    370  1.61   msaitoh 			    || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701))
    371  1.33   msaitoh 				break;
    372  1.32   msaitoh 
    373  1.32   msaitoh 			if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
    374  1.32   msaitoh 				gig |= GTCR_MAN_MS | GTCR_ADV_MS;
    375  1.32   msaitoh 			PHY_WRITE(sc, MII_100T2CR, gig);
    376  1.32   msaitoh 			break;
    377  1.32   msaitoh 		default:
    378  1.83   msaitoh 			return EINVAL;
    379  1.32   msaitoh 		}
    380   1.1   thorpej 		break;
    381   1.1   thorpej 
    382   1.1   thorpej 	case MII_TICK:
    383  1.73   msaitoh 		/* If we're not currently selected, just return. */
    384   1.1   thorpej 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
    385  1.83   msaitoh 			return 0;
    386   1.1   thorpej 
    387  1.73   msaitoh 		/* Is the interface even up? */
    388  1.67   msaitoh 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
    389  1.67   msaitoh 			return 0;
    390  1.67   msaitoh 
    391  1.73   msaitoh 		/* Only used for autonegotiation. */
    392  1.67   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
    393  1.67   msaitoh 		    (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
    394  1.67   msaitoh 			sc->mii_ticks = 0;
    395  1.67   msaitoh 			break;
    396  1.67   msaitoh 		}
    397  1.67   msaitoh 
    398  1.67   msaitoh 		/*
    399  1.67   msaitoh 		 * Check for link.
    400  1.67   msaitoh 		 * Read the status register twice; BMSR_LINK is latch-low.
    401  1.67   msaitoh 		 */
    402  1.79   msaitoh 		PHY_READ(sc, MII_BMSR, &reg);
    403  1.79   msaitoh 		PHY_READ(sc, MII_BMSR, &reg);
    404  1.67   msaitoh 		if (reg & BMSR_LINK) {
    405  1.67   msaitoh 			sc->mii_ticks = 0;
    406  1.67   msaitoh 			break;
    407  1.67   msaitoh 		}
    408  1.67   msaitoh 
    409  1.67   msaitoh 		/*
    410  1.67   msaitoh 		 * mii_ticks == 0 means it's the first tick after changing the
    411  1.67   msaitoh 		 * media or the link became down since the last tick
    412  1.67   msaitoh 		 * (see above), so break to update the status.
    413  1.67   msaitoh 		 */
    414  1.67   msaitoh 		if (sc->mii_ticks++ == 0)
    415  1.67   msaitoh 			break;
    416  1.67   msaitoh 
    417  1.73   msaitoh 		/* Only retry autonegotiation every mii_anegticks seconds. */
    418  1.67   msaitoh 		KASSERT(sc->mii_anegticks != 0);
    419  1.67   msaitoh 		if (sc->mii_ticks <= sc->mii_anegticks)
    420  1.67   msaitoh 			break;
    421  1.67   msaitoh 
    422  1.67   msaitoh 		brgphy_mii_phy_auto(sc);
    423   1.1   thorpej 		break;
    424   1.1   thorpej 
    425   1.1   thorpej 	case MII_DOWN:
    426   1.1   thorpej 		mii_phy_down(sc);
    427  1.83   msaitoh 		return 0;
    428   1.1   thorpej 	}
    429   1.1   thorpej 
    430   1.1   thorpej 	/* Update the media status. */
    431   1.1   thorpej 	mii_phy_status(sc);
    432   1.1   thorpej 
    433  1.10   thorpej 	/*
    434  1.32   msaitoh 	 * Callback if something changed. Note that we need to poke the DSP on
    435  1.32   msaitoh 	 * the Broadcom PHYs if the media changes.
    436  1.10   thorpej 	 */
    437  1.23     perry 	if (sc->mii_media_active != mii->mii_media_active ||
    438  1.10   thorpej 	    sc->mii_media_status != mii->mii_media_status ||
    439  1.10   thorpej 	    cmd == MII_MEDIACHG) {
    440  1.61   msaitoh 		switch (sc->mii_mpd_oui) {
    441  1.61   msaitoh 		case MII_OUI_BROADCOM:
    442  1.61   msaitoh 			switch (sc->mii_mpd_model) {
    443  1.61   msaitoh 			case MII_MODEL_BROADCOM_BCM5400:
    444  1.43   msaitoh 				brgphy_bcm5401_dspcode(sc);
    445  1.61   msaitoh 				break;
    446  1.61   msaitoh 			case MII_MODEL_BROADCOM_BCM5401:
    447  1.61   msaitoh 				if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
    448  1.61   msaitoh 					brgphy_bcm5401_dspcode(sc);
    449  1.61   msaitoh 				break;
    450  1.61   msaitoh 			case MII_MODEL_BROADCOM_BCM5411:
    451  1.61   msaitoh 				brgphy_bcm5411_dspcode(sc);
    452  1.61   msaitoh 				break;
    453  1.61   msaitoh 			}
    454  1.43   msaitoh 			break;
    455  1.43   msaitoh 		}
    456  1.10   thorpej 	}
    457  1.43   msaitoh 
    458  1.43   msaitoh 	/* Callback if something changed. */
    459  1.43   msaitoh 	mii_phy_update(sc, cmd);
    460  1.83   msaitoh 	return 0;
    461   1.1   thorpej }
    462   1.1   thorpej 
    463  1.21   thorpej static void
    464  1.71   msaitoh brgphy_copper_status(struct mii_softc *sc)
    465   1.1   thorpej {
    466   1.1   thorpej 	struct mii_data *mii = sc->mii_pdata;
    467   1.1   thorpej 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    468  1.79   msaitoh 	uint16_t bmcr, bmsr, auxsts, gtsr;
    469   1.1   thorpej 
    470   1.1   thorpej 	mii->mii_media_status = IFM_AVALID;
    471   1.1   thorpej 	mii->mii_media_active = IFM_ETHER;
    472   1.1   thorpej 
    473  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    474  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    475  1.57       jym 	if (bmsr & BMSR_LINK)
    476   1.1   thorpej 		mii->mii_media_status |= IFM_ACTIVE;
    477   1.1   thorpej 
    478  1.79   msaitoh 	PHY_READ(sc, MII_BMCR, &bmcr);
    479   1.1   thorpej 	if (bmcr & BMCR_ISO) {
    480   1.1   thorpej 		mii->mii_media_active |= IFM_NONE;
    481   1.1   thorpej 		mii->mii_media_status = 0;
    482   1.1   thorpej 		return;
    483   1.1   thorpej 	}
    484   1.1   thorpej 
    485   1.1   thorpej 	if (bmcr & BMCR_LOOP)
    486   1.1   thorpej 		mii->mii_media_active |= IFM_LOOP;
    487   1.1   thorpej 
    488   1.1   thorpej 	if (bmcr & BMCR_AUTOEN) {
    489   1.1   thorpej 		/*
    490  1.85   msaitoh 		 * The media status bits are only valid if autonegotiation
    491   1.1   thorpej 		 * has completed (or it's disabled).
    492   1.1   thorpej 		 */
    493  1.57       jym 		if ((bmsr & BMSR_ACOMP) == 0) {
    494   1.1   thorpej 			/* Erg, still trying, I guess... */
    495   1.1   thorpej 			mii->mii_media_active |= IFM_NONE;
    496   1.1   thorpej 			return;
    497   1.1   thorpej 		}
    498   1.1   thorpej 
    499  1.79   msaitoh 		PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts);
    500  1.71   msaitoh 
    501  1.71   msaitoh 		switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
    502  1.71   msaitoh 		case BRGPHY_RES_1000FD:
    503  1.71   msaitoh 			mii->mii_media_active |= IFM_1000_T | IFM_FDX;
    504  1.79   msaitoh 			PHY_READ(sc, MII_100T2SR, &gtsr);
    505  1.71   msaitoh 			if (gtsr & GTSR_MS_RES)
    506  1.71   msaitoh 				mii->mii_media_active |= IFM_ETH_MASTER;
    507  1.71   msaitoh 			break;
    508  1.71   msaitoh 
    509  1.71   msaitoh 		case BRGPHY_RES_1000HD:
    510  1.71   msaitoh 			mii->mii_media_active |= IFM_1000_T | IFM_HDX;
    511  1.79   msaitoh 			PHY_READ(sc, MII_100T2SR, &gtsr);
    512  1.71   msaitoh 			if (gtsr & GTSR_MS_RES)
    513  1.71   msaitoh 				mii->mii_media_active |= IFM_ETH_MASTER;
    514  1.71   msaitoh 			break;
    515  1.71   msaitoh 
    516  1.71   msaitoh 		case BRGPHY_RES_100FD:
    517  1.71   msaitoh 			mii->mii_media_active |= IFM_100_TX | IFM_FDX;
    518  1.71   msaitoh 			break;
    519  1.71   msaitoh 
    520  1.71   msaitoh 		case BRGPHY_RES_100T4:
    521  1.71   msaitoh 			mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
    522  1.71   msaitoh 			break;
    523  1.71   msaitoh 
    524  1.71   msaitoh 		case BRGPHY_RES_100HD:
    525  1.71   msaitoh 			mii->mii_media_active |= IFM_100_TX | IFM_HDX;
    526  1.71   msaitoh 			break;
    527  1.71   msaitoh 
    528  1.71   msaitoh 		case BRGPHY_RES_10FD:
    529  1.71   msaitoh 			mii->mii_media_active |= IFM_10_T | IFM_FDX;
    530  1.71   msaitoh 			break;
    531  1.71   msaitoh 
    532  1.71   msaitoh 		case BRGPHY_RES_10HD:
    533  1.71   msaitoh 			mii->mii_media_active |= IFM_10_T | IFM_HDX;
    534  1.71   msaitoh 			break;
    535  1.71   msaitoh 
    536  1.71   msaitoh 		default:
    537  1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    538  1.71   msaitoh 			mii->mii_media_status = 0;
    539  1.71   msaitoh 		}
    540  1.71   msaitoh 
    541  1.71   msaitoh 		if (mii->mii_media_active & IFM_FDX)
    542  1.71   msaitoh 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    543  1.71   msaitoh 
    544  1.71   msaitoh 	} else
    545  1.71   msaitoh 		mii->mii_media_active = ife->ifm_media;
    546  1.71   msaitoh }
    547  1.71   msaitoh 
    548  1.71   msaitoh void
    549  1.71   msaitoh brgphy_fiber_status(struct mii_softc *sc)
    550  1.71   msaitoh {
    551  1.71   msaitoh 	struct mii_data *mii = sc->mii_pdata;
    552  1.71   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    553  1.79   msaitoh 	uint16_t bmcr, bmsr, anar, anlpar, result;
    554  1.71   msaitoh 
    555  1.71   msaitoh 	mii->mii_media_status = IFM_AVALID;
    556  1.71   msaitoh 	mii->mii_media_active = IFM_ETHER;
    557  1.71   msaitoh 
    558  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    559  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    560  1.71   msaitoh 	if (bmsr & BMSR_LINK)
    561  1.71   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
    562  1.57       jym 
    563  1.79   msaitoh 	PHY_READ(sc, MII_BMCR, &bmcr);
    564  1.71   msaitoh 	if (bmcr & BMCR_LOOP)
    565  1.71   msaitoh 		mii->mii_media_active |= IFM_LOOP;
    566  1.57       jym 
    567  1.71   msaitoh 	if (bmcr & BMCR_AUTOEN) {
    568  1.71   msaitoh 		if ((bmsr & BMSR_ACOMP) == 0) {
    569  1.71   msaitoh 			/* Erg, still trying, I guess... */
    570  1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    571  1.71   msaitoh 			return;
    572  1.71   msaitoh 		}
    573  1.57       jym 
    574  1.71   msaitoh 		mii->mii_media_active |= IFM_1000_SX;
    575  1.57       jym 
    576  1.79   msaitoh 		PHY_READ(sc, MII_ANAR, &anar);
    577  1.79   msaitoh 		PHY_READ(sc, MII_ANLPAR, &anlpar);
    578  1.79   msaitoh 		result = anar & anlpar;
    579  1.57       jym 
    580  1.79   msaitoh 		if (result & ANAR_X_FD)
    581  1.71   msaitoh 			mii->mii_media_active |= IFM_FDX;
    582  1.71   msaitoh 		else
    583  1.71   msaitoh 			mii->mii_media_active |= IFM_HDX;
    584   1.1   thorpej 
    585  1.71   msaitoh 		if (mii->mii_media_active & IFM_FDX)
    586  1.71   msaitoh 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    587  1.71   msaitoh 	} else
    588  1.71   msaitoh 		mii->mii_media_active = ife->ifm_media;
    589  1.71   msaitoh }
    590   1.1   thorpej 
    591  1.71   msaitoh void
    592  1.71   msaitoh brgphy_5708s_status(struct mii_softc *sc)
    593  1.71   msaitoh {
    594  1.71   msaitoh 	struct mii_data *mii = sc->mii_pdata;
    595  1.71   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    596  1.79   msaitoh 	uint16_t bmcr, bmsr;
    597   1.1   thorpej 
    598  1.71   msaitoh 	mii->mii_media_status = IFM_AVALID;
    599  1.71   msaitoh 	mii->mii_media_active = IFM_ETHER;
    600   1.1   thorpej 
    601  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    602  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    603  1.71   msaitoh 	if (bmsr & BMSR_LINK)
    604  1.71   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
    605   1.1   thorpej 
    606  1.79   msaitoh 	PHY_READ(sc, MII_BMCR, &bmcr);
    607  1.71   msaitoh 	if (bmcr & BMCR_LOOP)
    608  1.71   msaitoh 		mii->mii_media_active |= IFM_LOOP;
    609   1.1   thorpej 
    610  1.71   msaitoh 	if (bmcr & BMCR_AUTOEN) {
    611  1.79   msaitoh 		uint16_t xstat;
    612   1.1   thorpej 
    613  1.71   msaitoh 		if ((bmsr & BMSR_ACOMP) == 0) {
    614  1.71   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    615  1.71   msaitoh 			    BRGPHY_5708S_DIG_PG0);
    616  1.79   msaitoh 			PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
    617  1.71   msaitoh 			if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) {
    618  1.71   msaitoh 				/* Erg, still trying, I guess... */
    619  1.57       jym 				mii->mii_media_active |= IFM_NONE;
    620  1.71   msaitoh 				return;
    621  1.57       jym 			}
    622   1.1   thorpej 		}
    623  1.57       jym 
    624  1.71   msaitoh 		PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    625  1.71   msaitoh 		    BRGPHY_5708S_DIG_PG0);
    626  1.79   msaitoh 		PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
    627  1.71   msaitoh 
    628  1.71   msaitoh 		switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
    629  1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
    630  1.71   msaitoh 			mii->mii_media_active |= IFM_10_FL;
    631  1.71   msaitoh 			break;
    632  1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
    633  1.71   msaitoh 			mii->mii_media_active |= IFM_100_FX;
    634  1.71   msaitoh 			break;
    635  1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
    636  1.71   msaitoh 			mii->mii_media_active |= IFM_1000_SX;
    637  1.71   msaitoh 			break;
    638  1.71   msaitoh 		case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
    639  1.71   msaitoh 			mii->mii_media_active |= IFM_2500_SX;
    640  1.71   msaitoh 			break;
    641  1.71   msaitoh 		}
    642  1.71   msaitoh 
    643  1.71   msaitoh 		if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
    644  1.71   msaitoh 			mii->mii_media_active |= IFM_FDX;
    645  1.71   msaitoh 		else
    646  1.71   msaitoh 			mii->mii_media_active |= IFM_HDX;
    647  1.71   msaitoh 
    648  1.71   msaitoh 		if (mii->mii_media_active & IFM_FDX) {
    649  1.71   msaitoh 			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE)
    650  1.83   msaitoh 				mii->mii_media_active
    651  1.83   msaitoh 				    |= IFM_FLOW | IFM_ETH_TXPAUSE;
    652  1.71   msaitoh 			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE)
    653  1.83   msaitoh 				mii->mii_media_active
    654  1.83   msaitoh 				    |= IFM_FLOW | IFM_ETH_RXPAUSE;
    655  1.71   msaitoh 		}
    656  1.71   msaitoh 	} else
    657  1.71   msaitoh 		mii->mii_media_active = ife->ifm_media;
    658  1.71   msaitoh }
    659  1.71   msaitoh 
    660  1.71   msaitoh static void
    661  1.71   msaitoh brgphy_5709s_status(struct mii_softc *sc)
    662  1.71   msaitoh {
    663  1.71   msaitoh 	struct mii_data *mii = sc->mii_pdata;
    664  1.71   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
    665  1.79   msaitoh 	uint16_t bmcr, bmsr, auxsts;
    666  1.71   msaitoh 
    667  1.71   msaitoh 	mii->mii_media_status = IFM_AVALID;
    668  1.71   msaitoh 	mii->mii_media_active = IFM_ETHER;
    669  1.71   msaitoh 
    670  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    671  1.79   msaitoh 	PHY_READ(sc, MII_BMSR, &bmsr);
    672  1.71   msaitoh 	if (bmsr & BMSR_LINK)
    673  1.71   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
    674  1.71   msaitoh 
    675  1.79   msaitoh 	PHY_READ(sc, MII_BMCR, &bmcr);
    676  1.71   msaitoh 	if (bmcr & BMCR_ISO) {
    677  1.71   msaitoh 		mii->mii_media_active |= IFM_NONE;
    678  1.71   msaitoh 		mii->mii_media_status = 0;
    679  1.71   msaitoh 		return;
    680  1.71   msaitoh 	}
    681  1.71   msaitoh 
    682  1.71   msaitoh 	if (bmcr & BMCR_LOOP)
    683  1.71   msaitoh 		mii->mii_media_active |= IFM_LOOP;
    684  1.71   msaitoh 
    685  1.71   msaitoh 	if (bmcr & BMCR_AUTOEN) {
    686  1.71   msaitoh 		/*
    687  1.71   msaitoh 		 * The media status bits are only valid of autonegotiation
    688  1.71   msaitoh 		 * has completed (or it's disabled).
    689  1.71   msaitoh 		 */
    690  1.71   msaitoh 		if ((bmsr & BMSR_ACOMP) == 0) {
    691  1.71   msaitoh 			/* Erg, still trying, I guess... */
    692  1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    693  1.71   msaitoh 			return;
    694  1.71   msaitoh 		}
    695  1.71   msaitoh 
    696  1.71   msaitoh 		/* 5709S has its own general purpose status registers */
    697  1.79   msaitoh 		PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
    698  1.79   msaitoh 		PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts);
    699  1.71   msaitoh 
    700  1.71   msaitoh 		PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    701  1.71   msaitoh 		    BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
    702  1.71   msaitoh 
    703  1.71   msaitoh 		switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
    704  1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
    705  1.71   msaitoh 			mii->mii_media_active |= IFM_10_FL;
    706  1.71   msaitoh 			break;
    707  1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
    708  1.71   msaitoh 			mii->mii_media_active |= IFM_100_FX;
    709  1.71   msaitoh 			break;
    710  1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
    711  1.71   msaitoh 			mii->mii_media_active |= IFM_1000_SX;
    712  1.71   msaitoh 			break;
    713  1.71   msaitoh 		case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
    714  1.71   msaitoh 			mii->mii_media_active |= IFM_2500_SX;
    715  1.71   msaitoh 			break;
    716  1.71   msaitoh 		default:
    717  1.71   msaitoh 			mii->mii_media_active |= IFM_NONE;
    718  1.71   msaitoh 			mii->mii_media_status = 0;
    719  1.71   msaitoh 			break;
    720  1.71   msaitoh 		}
    721  1.71   msaitoh 
    722  1.71   msaitoh 		if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
    723  1.71   msaitoh 			mii->mii_media_active |= IFM_FDX;
    724  1.71   msaitoh 		else
    725  1.71   msaitoh 			mii->mii_media_active |= IFM_HDX;
    726  1.71   msaitoh 
    727  1.19   thorpej 		if (mii->mii_media_active & IFM_FDX)
    728  1.20   thorpej 			mii->mii_media_active |= mii_phy_flowstatus(sc);
    729   1.1   thorpej 	} else
    730   1.1   thorpej 		mii->mii_media_active = ife->ifm_media;
    731  1.10   thorpej }
    732  1.10   thorpej 
    733  1.32   msaitoh int
    734  1.32   msaitoh brgphy_mii_phy_auto(struct mii_softc *sc)
    735  1.32   msaitoh {
    736  1.79   msaitoh 	uint16_t anar, ktcr = 0;
    737  1.32   msaitoh 
    738  1.64   msaitoh 	sc->mii_ticks = 0;
    739  1.32   msaitoh 	brgphy_loop(sc);
    740  1.32   msaitoh 	PHY_RESET(sc);
    741  1.57       jym 
    742  1.57       jym 	if (sc->mii_flags & MIIF_HAVEFIBER) {
    743  1.57       jym 		anar = ANAR_X_FD | ANAR_X_HD;
    744  1.57       jym 		if (sc->mii_flags & MIIF_DOPAUSE)
    745  1.69   msaitoh 			anar |= ANAR_X_PAUSE_TOWARDS;
    746  1.57       jym 	} else {
    747  1.57       jym 		anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
    748  1.57       jym 		if (sc->mii_flags & MIIF_DOPAUSE)
    749  1.66   msaitoh 			anar |= ANAR_FC | ANAR_PAUSE_ASYM;
    750  1.71   msaitoh 		ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
    751  1.71   msaitoh 		if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
    752  1.71   msaitoh 		    && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701))
    753  1.71   msaitoh 			ktcr |= GTCR_MAN_MS | GTCR_ADV_MS;
    754  1.71   msaitoh 		PHY_WRITE(sc, MII_100T2CR, ktcr);
    755  1.57       jym 	}
    756  1.32   msaitoh 	PHY_WRITE(sc, MII_ANAR, anar);
    757  1.57       jym 
    758  1.57       jym 	/* Start autonegotiation */
    759  1.69   msaitoh 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
    760  1.32   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
    761  1.32   msaitoh 
    762  1.83   msaitoh 	return EJUSTRETURN;
    763  1.32   msaitoh }
    764  1.32   msaitoh 
    765  1.32   msaitoh void
    766  1.32   msaitoh brgphy_loop(struct mii_softc *sc)
    767  1.32   msaitoh {
    768  1.79   msaitoh 	uint16_t bmsr;
    769  1.32   msaitoh 	int i;
    770  1.32   msaitoh 
    771  1.32   msaitoh 	PHY_WRITE(sc, MII_BMCR, BMCR_LOOP);
    772  1.33   msaitoh 	for (i = 0; i < 15000; i++) {
    773  1.79   msaitoh 		PHY_READ(sc, MII_BMSR, &bmsr);
    774  1.32   msaitoh 		if (!(bmsr & BMSR_LINK))
    775  1.32   msaitoh 			break;
    776  1.32   msaitoh 		DELAY(10);
    777  1.32   msaitoh 	}
    778  1.32   msaitoh }
    779  1.32   msaitoh 
    780  1.21   thorpej static void
    781  1.43   msaitoh brgphy_reset(struct mii_softc *sc)
    782  1.10   thorpej {
    783  1.56       jym 	struct brgphy_softc *bsc = device_private(sc->mii_dev);
    784  1.79   msaitoh 	uint16_t reg;
    785  1.10   thorpej 
    786  1.10   thorpej 	mii_phy_reset(sc);
    787  1.61   msaitoh 	switch (sc->mii_mpd_oui) {
    788  1.61   msaitoh 	case MII_OUI_BROADCOM:
    789  1.61   msaitoh 		switch (sc->mii_mpd_model) {
    790  1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5400:
    791  1.43   msaitoh 			brgphy_bcm5401_dspcode(sc);
    792  1.61   msaitoh 			break;
    793  1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5401:
    794  1.61   msaitoh 			if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
    795  1.61   msaitoh 				brgphy_bcm5401_dspcode(sc);
    796  1.61   msaitoh 			break;
    797  1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5411:
    798  1.61   msaitoh 			brgphy_bcm5411_dspcode(sc);
    799  1.61   msaitoh 			break;
    800  1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM5421:
    801  1.61   msaitoh 			brgphy_bcm5421_dspcode(sc);
    802  1.61   msaitoh 			break;
    803  1.61   msaitoh 		case MII_MODEL_BROADCOM_BCM54K2:
    804  1.61   msaitoh 			brgphy_bcm54k2_dspcode(sc);
    805  1.61   msaitoh 			break;
    806  1.61   msaitoh 		}
    807  1.43   msaitoh 		break;
    808  1.61   msaitoh 	case MII_OUI_BROADCOM3:
    809  1.61   msaitoh 		switch (sc->mii_mpd_model) {
    810  1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM5717C:
    811  1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM5719C:
    812  1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM5720C:
    813  1.61   msaitoh 		case MII_MODEL_BROADCOM3_BCM57765:
    814  1.61   msaitoh 			return;
    815  1.61   msaitoh 		}
    816  1.43   msaitoh 		break;
    817  1.61   msaitoh 	default:
    818  1.43   msaitoh 		break;
    819  1.43   msaitoh 	}
    820  1.15  jonathan 
    821  1.43   msaitoh 	/* Handle any bge (NetXtreme/NetLink) workarounds. */
    822  1.54    dyoung 	if (bsc->sc_isbge) {
    823  1.43   msaitoh 		if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
    824  1.43   msaitoh 
    825  1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_ADC_BUG)
    826  1.43   msaitoh 				brgphy_adc_bug(sc);
    827  1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG)
    828  1.43   msaitoh 				brgphy_5704_a0_bug(sc);
    829  1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_BER_BUG)
    830  1.43   msaitoh 				brgphy_ber_bug(sc);
    831  1.68   msaitoh 			else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) {
    832  1.43   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
    833  1.79   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
    834  1.43   msaitoh 
    835  1.77   msaitoh 				if (bsc->sc_phyflags
    836  1.68   msaitoh 				    & BGEPHYF_ADJUST_TRIM) {
    837  1.43   msaitoh 					PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
    838  1.43   msaitoh 					    0x110b);
    839  1.43   msaitoh 					PHY_WRITE(sc, BRGPHY_TEST1,
    840  1.43   msaitoh 					    BRGPHY_TEST1_TRIM_EN | 0x4);
    841  1.43   msaitoh 				} else {
    842  1.43   msaitoh 					PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
    843  1.43   msaitoh 					    0x010b);
    844  1.43   msaitoh 				}
    845  1.15  jonathan 
    846  1.43   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
    847  1.43   msaitoh 			}
    848  1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_CRC_BUG)
    849  1.43   msaitoh 				brgphy_crc_bug(sc);
    850  1.15  jonathan 
    851  1.43   msaitoh 			/* Set Jumbo frame settings in the PHY. */
    852  1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE)
    853  1.43   msaitoh 				brgphy_jumbo_settings(sc);
    854  1.43   msaitoh 
    855  1.43   msaitoh 			/* Adjust output voltage */
    856  1.61   msaitoh 			if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    857  1.61   msaitoh 			    && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906))
    858  1.43   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
    859  1.43   msaitoh 
    860  1.43   msaitoh 			/* Enable Ethernet@Wirespeed */
    861  1.68   msaitoh 			if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED))
    862  1.43   msaitoh 				brgphy_eth_wirespeed(sc);
    863  1.43   msaitoh 
    864  1.52   msaitoh #if 0
    865  1.43   msaitoh 			/* Enable Link LED on Dell boxes */
    866  1.68   msaitoh 			if (bsc->sc_phyflags & BGEPHYF_NO_3LED) {
    867  1.79   msaitoh 				PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &reg);
    868  1.77   msaitoh 				PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
    869  1.79   msaitoh 				    reg & ~BRGPHY_PHY_EXTCTL_3_LED);
    870  1.43   msaitoh 			}
    871  1.43   msaitoh #endif
    872  1.43   msaitoh 		}
    873  1.57       jym 	/* Handle any bnx (NetXtreme II) workarounds. */
    874  1.57       jym 	} else if (bsc->sc_isbnx) {
    875  1.83   msaitoh 		uint32_t chip_num = _BNX_CHIP_NUM(bsc->sc_chipid);
    876  1.83   msaitoh 		uint32_t chip_id = _BNX_CHIP_ID(bsc->sc_chipid);
    877  1.83   msaitoh 		uint32_t chip_rev = _BNX_CHIP_REV(bsc->sc_chipid);
    878  1.83   msaitoh 
    879  1.61   msaitoh 		if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    880  1.61   msaitoh 		    && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) {
    881  1.83   msaitoh 			/*
    882  1.83   msaitoh 			 * Store autoneg capabilities/results in digital block
    883  1.83   msaitoh 			 * (Page 0)
    884  1.83   msaitoh 			 */
    885  1.83   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    886  1.83   msaitoh 			    BRGPHY_5708S_DIG3_PG2);
    887  1.77   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
    888  1.77   msaitoh 			    BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
    889  1.83   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    890  1.83   msaitoh 			    BRGPHY_5708S_DIG_PG0);
    891  1.43   msaitoh 
    892  1.43   msaitoh 			/* Enable fiber mode and autodetection */
    893  1.79   msaitoh 			PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, &reg);
    894  1.83   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg |
    895  1.83   msaitoh 			    BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
    896  1.77   msaitoh 			    BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
    897  1.43   msaitoh 
    898  1.43   msaitoh 			/* Enable parallel detection */
    899  1.79   msaitoh 			PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, &reg);
    900  1.83   msaitoh 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
    901  1.79   msaitoh 			    reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
    902  1.43   msaitoh 
    903  1.83   msaitoh 			/*
    904  1.83   msaitoh 			 * Advertise 2.5G support through next page during
    905  1.83   msaitoh 			 * autoneg
    906  1.83   msaitoh 			 */
    907  1.79   msaitoh 			if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
    908  1.79   msaitoh 				PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
    909  1.79   msaitoh 				    &reg);
    910  1.83   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
    911  1.79   msaitoh 				    reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
    912  1.79   msaitoh 			}
    913  1.43   msaitoh 
    914  1.43   msaitoh 			/* Increase TX signal amplitude */
    915  1.83   msaitoh 			if ((chip_id == BNX_CHIP_ID_5708_A0) ||
    916  1.83   msaitoh 			    (chip_id == BNX_CHIP_ID_5708_B0) ||
    917  1.83   msaitoh 			    (chip_id == BNX_CHIP_ID_5708_B1)) {
    918  1.83   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    919  1.79   msaitoh 					BRGPHY_5708S_TX_MISC_PG5);
    920  1.79   msaitoh 				PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, &reg);
    921  1.77   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
    922  1.79   msaitoh 				    reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM);
    923  1.83   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    924  1.79   msaitoh 					BRGPHY_5708S_DIG_PG0);
    925  1.43   msaitoh 			}
    926  1.15  jonathan 
    927  1.83   msaitoh 			/*
    928  1.83   msaitoh 			 * Backplanes use special
    929  1.83   msaitoh 			 * driver/pre-driver/pre-emphasis values.
    930  1.83   msaitoh 			 */
    931  1.71   msaitoh 			if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
    932  1.71   msaitoh 			    (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
    933  1.83   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    934  1.83   msaitoh 				    BRGPHY_5708S_TX_MISC_PG5);
    935  1.83   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
    936  1.83   msaitoh 				    bsc->sc_port_hwcfg &
    937  1.83   msaitoh 				    BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
    938  1.83   msaitoh 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
    939  1.83   msaitoh 				    BRGPHY_5708S_DIG_PG0);
    940  1.43   msaitoh 			}
    941  1.71   msaitoh 		} else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
    942  1.61   msaitoh 		    && (sc->mii_mpd_model ==  MII_MODEL_BROADCOM2_BCM5709S)) {
    943  1.57       jym 			/* Select the SerDes Digital block of the AN MMD. */
    944  1.57       jym 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    945  1.57       jym 			    BRGPHY_BLOCK_ADDR_SERDES_DIG);
    946  1.57       jym 
    947  1.79   msaitoh 			PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, &reg);
    948  1.57       jym 			PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,
    949  1.79   msaitoh 			    (reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |
    950  1.57       jym 			    BRGPHY_SD_DIG_1000X_CTL1_FIBER);
    951  1.57       jym 
    952  1.58       jym 			if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
    953  1.57       jym 				/* Select the Over 1G block of the AN MMD. */
    954  1.57       jym 				PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    955  1.57       jym 				    BRGPHY_BLOCK_ADDR_OVER_1G);
    956  1.57       jym 
    957  1.57       jym 				/*
    958  1.57       jym 				 * Enable autoneg "Next Page" to advertise
    959  1.57       jym 				 * 2.5G support.
    960  1.57       jym 				 */
    961  1.79   msaitoh 				PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
    962  1.79   msaitoh 				    &reg);
    963  1.57       jym 				PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
    964  1.79   msaitoh 				    reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
    965  1.57       jym 			}
    966  1.57       jym 
    967  1.77   msaitoh 			/*
    968  1.77   msaitoh 			 * Select the Multi-Rate Backplane Ethernet block of
    969  1.77   msaitoh 			 * the AN MMD.
    970  1.77   msaitoh 			 */
    971  1.77   msaitoh 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    972  1.77   msaitoh 			    BRGPHY_BLOCK_ADDR_MRBE);
    973  1.77   msaitoh 
    974  1.77   msaitoh 			/* Enable MRBE speed autoneg. */
    975  1.79   msaitoh 			PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, &reg);
    976  1.77   msaitoh 			PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
    977  1.79   msaitoh 			    reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE |
    978  1.77   msaitoh 			    BRGPHY_MRBE_MSG_PG5_NP_T2);
    979  1.77   msaitoh 
    980  1.77   msaitoh 			/* Select the Clause 73 User B0 block of the AN MMD. */
    981  1.77   msaitoh 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    982  1.77   msaitoh 			    BRGPHY_BLOCK_ADDR_CL73_USER_B0);
    983  1.57       jym 
    984  1.77   msaitoh 			/* Enable MRBE speed autoneg. */
    985  1.77   msaitoh 			PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
    986  1.77   msaitoh 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
    987  1.77   msaitoh 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
    988  1.77   msaitoh 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
    989  1.77   msaitoh 
    990  1.77   msaitoh 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
    991  1.77   msaitoh 			    BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
    992  1.57       jym 
    993  1.83   msaitoh 		} else if (chip_num == BNX_CHIP_NUM_5709) {
    994  1.83   msaitoh 			if ((chip_rev == BNX_CHIP_REV_Ax) ||
    995  1.83   msaitoh 			    (chip_rev == BNX_CHIP_REV_Bx))
    996  1.58       jym 				brgphy_disable_early_dac(sc);
    997  1.58       jym 
    998  1.58       jym 			/* Set Jumbo frame settings in the PHY. */
    999  1.58       jym 			brgphy_jumbo_settings(sc);
   1000  1.58       jym 
   1001  1.58       jym 			/* Enable Ethernet@Wirespeed */
   1002  1.58       jym 			brgphy_eth_wirespeed(sc);
   1003  1.43   msaitoh 		} else {
   1004  1.43   msaitoh 			if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
   1005  1.43   msaitoh 				brgphy_ber_bug(sc);
   1006  1.18   hannken 
   1007  1.43   msaitoh 				/* Set Jumbo frame settings in the PHY. */
   1008  1.43   msaitoh 				brgphy_jumbo_settings(sc);
   1009  1.18   hannken 
   1010  1.43   msaitoh 				/* Enable Ethernet@Wirespeed */
   1011  1.43   msaitoh 				brgphy_eth_wirespeed(sc);
   1012  1.43   msaitoh 			}
   1013  1.43   msaitoh 		}
   1014  1.43   msaitoh 	}
   1015  1.34     markd }
   1016  1.34     markd 
   1017  1.16  jonathan /* Turn off tap power management on 5401. */
   1018  1.10   thorpej static void
   1019  1.43   msaitoh brgphy_bcm5401_dspcode(struct mii_softc *sc)
   1020  1.10   thorpej {
   1021  1.10   thorpej 	static const struct {
   1022  1.10   thorpej 		int		reg;
   1023  1.10   thorpej 		uint16_t	val;
   1024  1.10   thorpej 	} dspcode[] = {
   1025  1.16  jonathan 		{ BRGPHY_MII_AUXCTL,		0x0c20 },
   1026  1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0012 },
   1027  1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x1804 },
   1028  1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0013 },
   1029  1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x1204 },
   1030  1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
   1031  1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0132 },
   1032  1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
   1033  1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0232 },
   1034  1.10   thorpej 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
   1035  1.10   thorpej 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a20 },
   1036  1.10   thorpej 		{ 0,				0 },
   1037  1.10   thorpej 	};
   1038  1.10   thorpej 	int i;
   1039  1.10   thorpej 
   1040  1.10   thorpej 	for (i = 0; dspcode[i].reg != 0; i++)
   1041  1.10   thorpej 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1042  1.61   msaitoh 	delay(40);
   1043  1.10   thorpej }
   1044  1.10   thorpej 
   1045  1.10   thorpej static void
   1046  1.43   msaitoh brgphy_bcm5411_dspcode(struct mii_softc *sc)
   1047  1.10   thorpej {
   1048  1.10   thorpej 	static const struct {
   1049  1.10   thorpej 		int		reg;
   1050  1.10   thorpej 		uint16_t	val;
   1051  1.10   thorpej 	} dspcode[] = {
   1052  1.10   thorpej 		{ 0x1c,				0x8c23 },
   1053  1.10   thorpej 		{ 0x1c,				0x8ca3 },
   1054  1.10   thorpej 		{ 0x1c,				0x8c23 },
   1055  1.15  jonathan 		{ 0,				0 },
   1056  1.15  jonathan 	};
   1057  1.15  jonathan 	int i;
   1058  1.15  jonathan 
   1059  1.15  jonathan 	for (i = 0; dspcode[i].reg != 0; i++)
   1060  1.15  jonathan 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1061  1.15  jonathan }
   1062  1.15  jonathan 
   1063  1.43   msaitoh void
   1064  1.43   msaitoh brgphy_bcm5421_dspcode(struct mii_softc *sc)
   1065  1.43   msaitoh {
   1066  1.43   msaitoh 	uint16_t data;
   1067  1.43   msaitoh 
   1068  1.43   msaitoh 	/* Set Class A mode */
   1069  1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
   1070  1.79   msaitoh 	PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
   1071  1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
   1072  1.43   msaitoh 
   1073  1.43   msaitoh 	/* Set FFE gamma override to -0.125 */
   1074  1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
   1075  1.79   msaitoh 	PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
   1076  1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
   1077  1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
   1078  1.79   msaitoh 	PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data);
   1079  1.43   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
   1080  1.43   msaitoh }
   1081  1.43   msaitoh 
   1082  1.43   msaitoh void
   1083  1.43   msaitoh brgphy_bcm54k2_dspcode(struct mii_softc *sc)
   1084  1.43   msaitoh {
   1085  1.43   msaitoh 	static const struct {
   1086  1.43   msaitoh 		int		reg;
   1087  1.43   msaitoh 		uint16_t	val;
   1088  1.43   msaitoh 	} dspcode[] = {
   1089  1.43   msaitoh 		{ 4,				0x01e1 },
   1090  1.43   msaitoh 		{ 9,				0x0300 },
   1091  1.43   msaitoh 		{ 0,				0 },
   1092  1.43   msaitoh 	};
   1093  1.43   msaitoh 	int i;
   1094  1.43   msaitoh 
   1095  1.43   msaitoh 	for (i = 0; dspcode[i].reg != 0; i++)
   1096  1.43   msaitoh 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1097  1.43   msaitoh }
   1098  1.43   msaitoh 
   1099  1.15  jonathan static void
   1100  1.43   msaitoh brgphy_adc_bug(struct mii_softc *sc)
   1101  1.15  jonathan {
   1102  1.15  jonathan 	static const struct {
   1103  1.15  jonathan 		int		reg;
   1104  1.15  jonathan 		uint16_t	val;
   1105  1.15  jonathan 	} dspcode[] = {
   1106  1.15  jonathan 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
   1107  1.15  jonathan 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
   1108  1.15  jonathan 		{ BRGPHY_MII_DSP_RW_PORT,	0x2aaa },
   1109  1.43   msaitoh 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
   1110  1.43   msaitoh 		{ BRGPHY_MII_DSP_RW_PORT,	0x0323 },
   1111  1.43   msaitoh 		{ BRGPHY_MII_AUXCTL,		0x0400 },
   1112  1.15  jonathan 		{ 0,				0 },
   1113  1.15  jonathan 	};
   1114  1.15  jonathan 	int i;
   1115  1.15  jonathan 
   1116  1.15  jonathan 	for (i = 0; dspcode[i].reg != 0; i++)
   1117  1.15  jonathan 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1118  1.15  jonathan }
   1119  1.15  jonathan 
   1120  1.15  jonathan static void
   1121  1.43   msaitoh brgphy_5704_a0_bug(struct mii_softc *sc)
   1122  1.15  jonathan {
   1123  1.15  jonathan 	static const struct {
   1124  1.15  jonathan 		int		reg;
   1125  1.15  jonathan 		uint16_t	val;
   1126  1.15  jonathan 	} dspcode[] = {
   1127  1.15  jonathan 		{ 0x1c,				0x8d68 },
   1128  1.33   msaitoh 		{ 0x1c,				0x8d68 },
   1129  1.10   thorpej 		{ 0,				0 },
   1130  1.10   thorpej 	};
   1131  1.10   thorpej 	int i;
   1132  1.10   thorpej 
   1133  1.10   thorpej 	for (i = 0; dspcode[i].reg != 0; i++)
   1134  1.10   thorpej 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1135   1.1   thorpej }
   1136  1.22      cube 
   1137  1.22      cube static void
   1138  1.43   msaitoh brgphy_ber_bug(struct mii_softc *sc)
   1139  1.22      cube {
   1140  1.22      cube 	static const struct {
   1141  1.22      cube 		int		reg;
   1142  1.22      cube 		uint16_t	val;
   1143  1.22      cube 	} dspcode[] = {
   1144  1.22      cube 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
   1145  1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
   1146  1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x310b },
   1147  1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
   1148  1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x9506 },
   1149  1.22      cube 		{ BRGPHY_MII_DSP_ADDR_REG,	0x401f },
   1150  1.22      cube 		{ BRGPHY_MII_DSP_RW_PORT,	0x14e2 },
   1151  1.22      cube 		{ BRGPHY_MII_AUXCTL,		0x0400 },
   1152  1.22      cube 		{ 0,				0 },
   1153  1.22      cube 	};
   1154  1.22      cube 	int i;
   1155  1.22      cube 
   1156  1.22      cube 	for (i = 0; dspcode[i].reg != 0; i++)
   1157  1.22      cube 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1158  1.22      cube }
   1159  1.34     markd 
   1160  1.43   msaitoh /* BCM5701 A0/B0 CRC bug workaround */
   1161  1.43   msaitoh void
   1162  1.43   msaitoh brgphy_crc_bug(struct mii_softc *sc)
   1163  1.34     markd {
   1164  1.34     markd 	static const struct {
   1165  1.34     markd 		int		reg;
   1166  1.34     markd 		uint16_t	val;
   1167  1.34     markd 	} dspcode[] = {
   1168  1.43   msaitoh 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0a75 },
   1169  1.43   msaitoh 		{ 0x1c,				0x8c68 },
   1170  1.43   msaitoh 		{ 0x1c,				0x8d68 },
   1171  1.43   msaitoh 		{ 0x1c,				0x8c68 },
   1172  1.34     markd 		{ 0,				0 },
   1173  1.34     markd 	};
   1174  1.34     markd 	int i;
   1175  1.34     markd 
   1176  1.34     markd 	for (i = 0; dspcode[i].reg != 0; i++)
   1177  1.34     markd 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
   1178  1.34     markd }
   1179  1.52   msaitoh 
   1180  1.52   msaitoh static void
   1181  1.58       jym brgphy_disable_early_dac(struct mii_softc *sc)
   1182  1.58       jym {
   1183  1.79   msaitoh 	uint16_t val;
   1184  1.58       jym 
   1185  1.58       jym 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
   1186  1.79   msaitoh 	PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &val);
   1187  1.58       jym 	val &= ~(1 << 8);
   1188  1.58       jym 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
   1189  1.58       jym 
   1190  1.58       jym }
   1191  1.58       jym 
   1192  1.58       jym static void
   1193  1.52   msaitoh brgphy_jumbo_settings(struct mii_softc *sc)
   1194  1.52   msaitoh {
   1195  1.79   msaitoh 	uint16_t val;
   1196  1.52   msaitoh 
   1197  1.52   msaitoh 	/* Set Jumbo frame settings in the PHY. */
   1198  1.61   msaitoh 	if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
   1199  1.61   msaitoh 	    && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) {
   1200  1.52   msaitoh 		/* Cannot do read-modify-write on the BCM5401 */
   1201  1.52   msaitoh 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
   1202  1.52   msaitoh 	} else {
   1203  1.52   msaitoh 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
   1204  1.79   msaitoh 		PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
   1205  1.52   msaitoh 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
   1206  1.79   msaitoh 		    val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
   1207  1.52   msaitoh 	}
   1208  1.52   msaitoh 
   1209  1.79   msaitoh 	PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &val);
   1210  1.79   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
   1211  1.52   msaitoh }
   1212  1.52   msaitoh 
   1213  1.52   msaitoh static void
   1214  1.52   msaitoh brgphy_eth_wirespeed(struct mii_softc *sc)
   1215  1.52   msaitoh {
   1216  1.79   msaitoh 	uint16_t val;
   1217  1.52   msaitoh 
   1218  1.52   msaitoh 	/* Enable Ethernet@Wirespeed */
   1219  1.52   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
   1220  1.79   msaitoh 	PHY_READ(sc, BRGPHY_MII_AUXCTL, &val);
   1221  1.79   msaitoh 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
   1222  1.52   msaitoh }
   1223