brgphy.c revision 1.23.2.4
1 /* $NetBSD: brgphy.c,v 1.23.2.4 2007/09/23 18:42:28 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Manuel Bouyer. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * driver for the Broadcom BCM5400 Gig-E PHY. 71 * 72 * Programming information for this PHY was gleaned from FreeBSD 73 * (they were apparently able to get a datasheet from Broadcom). 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.23.2.4 2007/09/23 18:42:28 bouyer Exp $"); 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/device.h> 83 #include <sys/socket.h> 84 #include <sys/errno.h> 85 86 #include <net/if.h> 87 #include <net/if_media.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 #include <dev/mii/miidevs.h> 92 93 #include <dev/mii/brgphyreg.h> 94 95 static int brgphymatch(struct device *, struct cfdata *, void *); 96 static void brgphyattach(struct device *, struct device *, void *); 97 98 CFATTACH_DECL(brgphy, sizeof(struct mii_softc), 99 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate); 100 101 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102 static void brgphy_status(struct mii_softc *); 103 static int brgphy_mii_phy_auto(struct mii_softc *); 104 static void brgphy_loop(struct mii_softc *); 105 106 static void brgphy_5401_reset(struct mii_softc *); 107 static void brgphy_5411_reset(struct mii_softc *); 108 static void brgphy_5703_reset(struct mii_softc *); 109 static void brgphy_5704_reset(struct mii_softc *); 110 static void brgphy_5705_reset(struct mii_softc *); 111 static void brgphy_5750_reset(struct mii_softc *); 112 static void brgphy_5755_reset(struct mii_softc *); 113 114 static const struct mii_phy_funcs brgphy_funcs = { 115 brgphy_service, brgphy_status, mii_phy_reset, 116 }; 117 118 static const struct mii_phy_funcs brgphy_5401_funcs = { 119 brgphy_service, brgphy_status, brgphy_5401_reset, 120 }; 121 122 static const struct mii_phy_funcs brgphy_5411_funcs = { 123 brgphy_service, brgphy_status, brgphy_5411_reset, 124 }; 125 126 static const struct mii_phy_funcs brgphy_5703_funcs = { 127 brgphy_service, brgphy_status, brgphy_5703_reset, 128 }; 129 130 static const struct mii_phy_funcs brgphy_5704_funcs = { 131 brgphy_service, brgphy_status, brgphy_5704_reset, 132 }; 133 134 static const struct mii_phy_funcs brgphy_5705_funcs = { 135 brgphy_service, brgphy_status, brgphy_5705_reset, 136 }; 137 138 const struct mii_phy_funcs brgphy_5750_funcs = { 139 brgphy_service, brgphy_status, brgphy_5750_reset, 140 }; 141 142 const struct mii_phy_funcs brgphy_5755_funcs = { 143 brgphy_service, brgphy_status, brgphy_5755_reset, 144 }; 145 146 147 static const struct mii_phydesc brgphys[] = { 148 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 149 MII_STR_BROADCOM_BCM5400 }, 150 151 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 152 MII_STR_BROADCOM_BCM5401 }, 153 154 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 155 MII_STR_BROADCOM_BCM5411 }, 156 157 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 158 MII_STR_BROADCOM_BCM5421 }, 159 160 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 161 MII_STR_BROADCOM_BCM5701 }, 162 163 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 164 MII_STR_BROADCOM_BCM5703 }, 165 166 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 167 MII_STR_BROADCOM_BCM5704 }, 168 169 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 170 MII_STR_BROADCOM_BCM5705 }, 171 172 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 173 MII_STR_BROADCOM_BCM5714 }, 174 175 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 176 MII_STR_BROADCOM_BCM5750 }, 177 178 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 179 MII_STR_BROADCOM_BCM5752 }, 180 181 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 182 MII_STR_BROADCOM_BCM5780 }, 183 184 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 185 MII_STR_BROADCOM2_BCM5755 }, 186 187 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 188 MII_STR_BROADCOM2_BCM5754 }, 189 190 { 0, 0, 191 NULL }, 192 }; 193 194 static void bcm5401_load_dspcode(struct mii_softc *); 195 static void bcm5411_load_dspcode(struct mii_softc *); 196 static void bcm5703_load_dspcode(struct mii_softc *); 197 static void bcm5704_load_dspcode(struct mii_softc *); 198 static void bcm5750_load_dspcode(struct mii_softc *); 199 static void bcm5755_load_dspcode(struct mii_softc *); 200 201 static int 202 brgphymatch(struct device *parent, struct cfdata *match, void *aux) 203 { 204 struct mii_attach_args *ma = aux; 205 206 if (mii_phy_match(ma, brgphys) != NULL) 207 return (10); 208 209 return (0); 210 } 211 212 static void 213 brgphyattach(struct device *parent, struct device *self, void *aux) 214 { 215 struct mii_softc *sc = (struct mii_softc *)self; 216 struct mii_attach_args *ma = aux; 217 struct mii_data *mii = ma->mii_data; 218 const struct mii_phydesc *mpd; 219 220 mpd = mii_phy_match(ma, brgphys); 221 aprint_naive(": Media interface\n"); 222 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 223 224 sc->mii_inst = mii->mii_instance; 225 sc->mii_phy = ma->mii_phyno; 226 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 227 sc->mii_pdata = mii; 228 sc->mii_flags = ma->mii_flags; 229 sc->mii_anegticks = 5; 230 231 switch (MII_MODEL(ma->mii_id2)) { 232 case MII_MODEL_BROADCOM_BCM5400: 233 sc->mii_funcs = &brgphy_5401_funcs; 234 aprint_normal("%s: using BCM5401 DSP patch\n", 235 sc->mii_dev.dv_xname); 236 break; 237 238 case MII_MODEL_BROADCOM_BCM5401: 239 if (MII_REV(ma->mii_id2) == 1 || MII_REV(ma->mii_id2) == 3) { 240 sc->mii_funcs = &brgphy_5401_funcs; 241 aprint_normal("%s: using BCM5401 DSP patch\n", 242 sc->mii_dev.dv_xname); 243 } else 244 sc->mii_funcs = &brgphy_funcs; 245 break; 246 247 case MII_MODEL_BROADCOM_BCM5411: 248 sc->mii_funcs = &brgphy_5411_funcs; 249 aprint_normal("%s: using BCM5411 DSP patch\n", 250 sc->mii_dev.dv_xname); 251 break; 252 253 #ifdef notyet /* unverified, untested */ 254 case MII_MODEL_BROADCOM_BCM5703: 255 sc->mii_funcs = &brgphy_5703_funcs; 256 aprint_normal("%s: using BCM5703 DSP patch\n", 257 sc->mii_dev.dv_xname); 258 break; 259 #endif 260 261 case MII_MODEL_BROADCOM_BCM5704: 262 sc->mii_funcs = &brgphy_5704_funcs; 263 aprint_normal("%s: using BCM5704 DSP patch\n", 264 sc->mii_dev.dv_xname); 265 break; 266 267 case MII_MODEL_BROADCOM_BCM5705: 268 sc->mii_funcs = &brgphy_5705_funcs; 269 break; 270 271 case MII_MODEL_BROADCOM_BCM5714: 272 case MII_MODEL_BROADCOM_BCM5780: 273 case MII_MODEL_BROADCOM_BCM5750: 274 case MII_MODEL_BROADCOM_BCM5752: 275 sc->mii_funcs = &brgphy_5750_funcs; 276 break; 277 278 case MII_MODEL_BROADCOM2_BCM5754: 279 case MII_MODEL_BROADCOM2_BCM5755: 280 sc->mii_funcs = &brgphy_5755_funcs; 281 break; 282 283 default: 284 sc->mii_funcs = &brgphy_funcs; 285 break; 286 } 287 288 PHY_RESET(sc); 289 290 sc->mii_capabilities = 291 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 292 if (sc->mii_capabilities & BMSR_EXTSTAT) 293 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 294 295 aprint_normal("%s: ", sc->mii_dev.dv_xname); 296 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 297 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 298 aprint_error("no media present"); 299 else 300 mii_phy_add_media(sc); 301 aprint_normal("\n"); 302 } 303 304 static int 305 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 306 { 307 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 308 int reg, speed, gig; 309 310 switch (cmd) { 311 case MII_POLLSTAT: 312 /* 313 * If we're not polling our PHY instance, just return. 314 */ 315 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 316 return (0); 317 break; 318 319 case MII_MEDIACHG: 320 /* 321 * If the media indicates a different PHY instance, 322 * isolate ourselves. 323 */ 324 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 325 reg = PHY_READ(sc, MII_BMCR); 326 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 327 return (0); 328 } 329 330 /* 331 * If the interface is not up, don't do anything. 332 */ 333 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 334 break; 335 336 PHY_RESET(sc); /* XXX hardware bug work-around */ 337 338 switch (IFM_SUBTYPE(ife->ifm_media)) { 339 case IFM_AUTO: 340 (void) brgphy_mii_phy_auto(sc); 341 break; 342 case IFM_1000_T: 343 speed = BMCR_S1000; 344 goto setit; 345 case IFM_100_TX: 346 speed = BMCR_S100; 347 goto setit; 348 case IFM_10_T: 349 speed = BMCR_S10; 350 setit: 351 brgphy_loop(sc); 352 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 353 speed |= BMCR_FDX; 354 gig = GTCR_ADV_1000TFDX; 355 } else { 356 gig = GTCR_ADV_1000THDX; 357 } 358 359 PHY_WRITE(sc, MII_100T2CR, 0); 360 PHY_WRITE(sc, MII_BMCR, speed); 361 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 362 363 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 364 break; 365 366 PHY_WRITE(sc, MII_100T2CR, gig); 367 PHY_WRITE(sc, MII_BMCR, 368 speed|BMCR_AUTOEN|BMCR_STARTNEG); 369 370 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 371 break; 372 373 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 374 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 375 PHY_WRITE(sc, MII_100T2CR, gig); 376 break; 377 default: 378 return (EINVAL); 379 } 380 break; 381 382 case MII_TICK: 383 /* 384 * If we're not currently selected, just return. 385 */ 386 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 387 return (0); 388 389 if (mii_phy_tick(sc) == EJUSTRETURN) 390 return (0); 391 break; 392 393 case MII_DOWN: 394 mii_phy_down(sc); 395 return (0); 396 } 397 398 /* Update the media status. */ 399 mii_phy_status(sc); 400 401 /* 402 * Callback if something changed. Note that we need to poke the DSP on 403 * the Broadcom PHYs if the media changes. 404 */ 405 if (sc->mii_media_active != mii->mii_media_active || 406 sc->mii_media_status != mii->mii_media_status || 407 cmd == MII_MEDIACHG) { 408 mii_phy_update(sc, cmd); 409 if (sc->mii_funcs == &brgphy_5401_funcs) 410 bcm5401_load_dspcode(sc); 411 else if (sc->mii_funcs == &brgphy_5411_funcs) 412 bcm5411_load_dspcode(sc); 413 } 414 return (0); 415 } 416 417 static void 418 brgphy_status(struct mii_softc *sc) 419 { 420 struct mii_data *mii = sc->mii_pdata; 421 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 422 int bmcr, auxsts, gtsr; 423 424 mii->mii_media_status = IFM_AVALID; 425 mii->mii_media_active = IFM_ETHER; 426 427 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 428 429 if (auxsts & BRGPHY_AUXSTS_LINK) 430 mii->mii_media_status |= IFM_ACTIVE; 431 432 bmcr = PHY_READ(sc, MII_BMCR); 433 if (bmcr & BMCR_ISO) { 434 mii->mii_media_active |= IFM_NONE; 435 mii->mii_media_status = 0; 436 return; 437 } 438 439 if (bmcr & BMCR_LOOP) 440 mii->mii_media_active |= IFM_LOOP; 441 442 if (bmcr & BMCR_AUTOEN) { 443 /* 444 * The media status bits are only valid of autonegotiation 445 * has completed (or it's disabled). 446 */ 447 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 448 /* Erg, still trying, I guess... */ 449 mii->mii_media_active |= IFM_NONE; 450 return; 451 } 452 453 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 454 case BRGPHY_RES_1000FD: 455 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 456 gtsr = PHY_READ(sc, MII_100T2SR); 457 if (gtsr & GTSR_MS_RES) 458 mii->mii_media_active |= IFM_ETH_MASTER; 459 break; 460 461 case BRGPHY_RES_1000HD: 462 mii->mii_media_active |= IFM_1000_T; 463 gtsr = PHY_READ(sc, MII_100T2SR); 464 if (gtsr & GTSR_MS_RES) 465 mii->mii_media_active |= IFM_ETH_MASTER; 466 break; 467 468 case BRGPHY_RES_100FD: 469 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 470 break; 471 472 case BRGPHY_RES_100T4: 473 mii->mii_media_active |= IFM_100_T4; 474 break; 475 476 case BRGPHY_RES_100HD: 477 mii->mii_media_active |= IFM_100_TX; 478 break; 479 480 case BRGPHY_RES_10FD: 481 mii->mii_media_active |= IFM_10_T|IFM_FDX; 482 break; 483 484 case BRGPHY_RES_10HD: 485 mii->mii_media_active |= IFM_10_T; 486 break; 487 488 default: 489 mii->mii_media_active |= IFM_NONE; 490 mii->mii_media_status = 0; 491 } 492 if (mii->mii_media_active & IFM_FDX) 493 mii->mii_media_active |= mii_phy_flowstatus(sc); 494 } else 495 mii->mii_media_active = ife->ifm_media; 496 } 497 498 int 499 brgphy_mii_phy_auto(struct mii_softc *sc) 500 { 501 int anar, ktcr = 0; 502 503 brgphy_loop(sc); 504 PHY_RESET(sc); 505 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 506 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 507 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 508 PHY_WRITE(sc, MII_100T2CR, ktcr); 509 ktcr = PHY_READ(sc, MII_100T2CR); 510 DELAY(1000); 511 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 512 if (sc->mii_flags & MIIF_DOPAUSE) 513 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 514 515 PHY_WRITE(sc, MII_ANAR, anar); 516 DELAY(1000); 517 PHY_WRITE(sc, MII_BMCR, 518 BMCR_AUTOEN | BMCR_STARTNEG); 519 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 520 521 return (EJUSTRETURN); 522 } 523 524 void 525 brgphy_loop(struct mii_softc *sc) 526 { 527 u_int32_t bmsr; 528 int i; 529 530 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 531 for (i = 0; i < 15000; i++) { 532 bmsr = PHY_READ(sc, MII_BMSR); 533 if (!(bmsr & BMSR_LINK)) 534 break; 535 DELAY(10); 536 } 537 } 538 539 static void 540 brgphy_5401_reset(struct mii_softc *sc) 541 { 542 543 mii_phy_reset(sc); 544 bcm5401_load_dspcode(sc); 545 } 546 547 static void 548 brgphy_5411_reset(struct mii_softc *sc) 549 { 550 551 mii_phy_reset(sc); 552 bcm5411_load_dspcode(sc); 553 } 554 555 556 static void 557 brgphy_5703_reset(struct mii_softc *sc) 558 { 559 560 mii_phy_reset(sc); 561 bcm5703_load_dspcode(sc); 562 } 563 564 static void 565 brgphy_5704_reset(struct mii_softc *sc) 566 { 567 568 mii_phy_reset(sc); 569 bcm5704_load_dspcode(sc); 570 } 571 572 /* 573 * Hardware bug workaround. Do nothing since after 574 * reset the 5705 PHY would get stuck in 10/100 MII mode. 575 */ 576 577 static void 578 brgphy_5705_reset(struct mii_softc *sc) 579 { 580 } 581 582 static void 583 brgphy_5750_reset(struct mii_softc *sc) 584 { 585 mii_phy_reset(sc); 586 bcm5750_load_dspcode(sc); 587 } 588 589 static void 590 brgphy_5755_reset(struct mii_softc *sc) 591 { 592 mii_phy_reset(sc); 593 bcm5755_load_dspcode(sc); 594 } 595 596 /* Turn off tap power management on 5401. */ 597 static void 598 bcm5401_load_dspcode(struct mii_softc *sc) 599 { 600 static const struct { 601 int reg; 602 uint16_t val; 603 } dspcode[] = { 604 { BRGPHY_MII_AUXCTL, 0x0c20 }, 605 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 606 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 607 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 608 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 609 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 610 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 611 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 612 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 613 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 614 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 615 { 0, 0 }, 616 }; 617 int i; 618 619 for (i = 0; dspcode[i].reg != 0; i++) 620 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 621 delay(40); 622 } 623 624 static void 625 bcm5411_load_dspcode(struct mii_softc *sc) 626 { 627 static const struct { 628 int reg; 629 uint16_t val; 630 } dspcode[] = { 631 { 0x1c, 0x8c23 }, 632 { 0x1c, 0x8ca3 }, 633 { 0x1c, 0x8c23 }, 634 { 0, 0 }, 635 }; 636 int i; 637 638 for (i = 0; dspcode[i].reg != 0; i++) 639 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 640 } 641 642 static void 643 bcm5703_load_dspcode(struct mii_softc *sc) 644 { 645 static const struct { 646 int reg; 647 uint16_t val; 648 } dspcode[] = { 649 { BRGPHY_MII_AUXCTL, 0x0c00 }, 650 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 651 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 652 { 0, 0 }, 653 }; 654 int i; 655 656 for (i = 0; dspcode[i].reg != 0; i++) 657 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 658 } 659 660 static void 661 bcm5704_load_dspcode(struct mii_softc *sc) 662 { 663 static const struct { 664 int reg; 665 uint16_t val; 666 } dspcode[] = { 667 { 0x1c, 0x8d68 }, 668 { 0x1c, 0x8d68 }, 669 { 0, 0 }, 670 }; 671 int i; 672 673 for (i = 0; dspcode[i].reg != 0; i++) 674 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 675 } 676 677 static void 678 bcm5750_load_dspcode(struct mii_softc *sc) 679 { 680 static const struct { 681 int reg; 682 uint16_t val; 683 } dspcode[] = { 684 { BRGPHY_MII_AUXCTL, 0x0c00 }, 685 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 686 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 687 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 688 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 689 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 690 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 691 { BRGPHY_MII_AUXCTL, 0x0400 }, 692 { 0, 0 }, 693 }; 694 int i; 695 696 for (i = 0; dspcode[i].reg != 0; i++) 697 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 698 } 699 700 static void 701 bcm5755_load_dspcode(struct mii_softc *sc) 702 { 703 static const struct { 704 int reg; 705 uint16_t val; 706 } dspcode[] = { 707 { BRGPHY_MII_AUXCTL, 0x0c00 }, 708 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 709 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 710 711 { BRGPHY_MII_AUXCTL, 0x0400 }, 712 { 0, 0 }, 713 }; 714 int i; 715 716 for (i = 0; dspcode[i].reg != 0; i++) 717 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 718 } 719
Indexes created Sun Oct 19 02:09:48 GMT 2025