brgphy.c revision 1.37.4.5
1 /* $NetBSD: brgphy.c,v 1.37.4.5 2009/08/19 18:47:09 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.37.4.5 2009/08/19 18:47:09 yamt Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 #include <prop/proplib.h> 79 80 #include <net/if.h> 81 #include <net/if_media.h> 82 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/mii/miidevs.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/if_bgereg.h> 89 #if 0 90 #include <dev/pci/if_bnxreg.h> 91 #endif 92 93 static int brgphymatch(device_t, cfdata_t, void *); 94 static void brgphyattach(device_t, device_t, void *); 95 96 struct brgphy_softc { 97 struct mii_softc sc_mii; 98 int sc_isbge; 99 int sc_isbnx; 100 int sc_bge_flags; 101 int sc_bnx_flags; 102 }; 103 104 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 105 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 106 DVF_DETACH_SHUTDOWN); 107 108 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 109 static void brgphy_status(struct mii_softc *); 110 static int brgphy_mii_phy_auto(struct mii_softc *); 111 static void brgphy_loop(struct mii_softc *); 112 static void brgphy_reset(struct mii_softc *); 113 static void brgphy_bcm5401_dspcode(struct mii_softc *); 114 static void brgphy_bcm5411_dspcode(struct mii_softc *); 115 static void brgphy_bcm5421_dspcode(struct mii_softc *); 116 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 117 static void brgphy_adc_bug(struct mii_softc *); 118 static void brgphy_5704_a0_bug(struct mii_softc *); 119 static void brgphy_ber_bug(struct mii_softc *); 120 static void brgphy_crc_bug(struct mii_softc *); 121 122 123 static const struct mii_phy_funcs brgphy_funcs = { 124 brgphy_service, brgphy_status, brgphy_reset, 125 }; 126 127 static const struct mii_phydesc brgphys[] = { 128 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 129 MII_STR_BROADCOM_BCM5400 }, 130 131 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 132 MII_STR_BROADCOM_BCM5401 }, 133 134 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 135 MII_STR_BROADCOM_BCM5411 }, 136 137 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 138 MII_STR_BROADCOM_BCM5421 }, 139 140 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 141 MII_STR_BROADCOM_BCM54K2 }, 142 143 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 144 MII_STR_BROADCOM_BCM5464 }, 145 146 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 147 MII_STR_BROADCOM_BCM5462 }, 148 149 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 150 MII_STR_BROADCOM_BCM5701 }, 151 152 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 153 MII_STR_BROADCOM_BCM5703 }, 154 155 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 156 MII_STR_BROADCOM_BCM5704 }, 157 158 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 159 MII_STR_BROADCOM_BCM5705 }, 160 161 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 162 MII_STR_BROADCOM_BCM5714 }, 163 164 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 165 MII_STR_BROADCOM_BCM5750 }, 166 167 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 168 MII_STR_BROADCOM_BCM5752 }, 169 170 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 171 MII_STR_BROADCOM_BCM5780 }, 172 173 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 174 MII_STR_BROADCOM_BCM5708C }, 175 176 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 177 MII_STR_BROADCOM2_BCM5722 }, 178 179 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 180 MII_STR_BROADCOM2_BCM5755 }, 181 182 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 183 MII_STR_BROADCOM2_BCM5754 }, 184 185 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 186 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 187 188 { 0, 0, 189 NULL }, 190 }; 191 192 static int 193 brgphymatch(device_t parent, cfdata_t match, void *aux) 194 { 195 struct mii_attach_args *ma = aux; 196 197 if (mii_phy_match(ma, brgphys) != NULL) 198 return (10); 199 200 return (0); 201 } 202 203 static void 204 brgphyattach(device_t parent, device_t self, void *aux) 205 { 206 struct brgphy_softc *bsc = device_private(self); 207 struct mii_softc *sc = &bsc->sc_mii; 208 struct mii_attach_args *ma = aux; 209 struct mii_data *mii = ma->mii_data; 210 const struct mii_phydesc *mpd; 211 prop_dictionary_t dict; 212 213 mpd = mii_phy_match(ma, brgphys); 214 aprint_naive(": Media interface\n"); 215 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 216 217 sc->mii_dev = self; 218 sc->mii_inst = mii->mii_instance; 219 sc->mii_phy = ma->mii_phyno; 220 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 221 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 222 sc->mii_pdata = mii; 223 sc->mii_flags = ma->mii_flags; 224 sc->mii_anegticks = MII_ANEGTICKS; 225 sc->mii_funcs = &brgphy_funcs; 226 227 PHY_RESET(sc); 228 229 sc->mii_capabilities = 230 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 231 if (sc->mii_capabilities & BMSR_EXTSTAT) 232 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 233 234 aprint_normal_dev(self, ""); 235 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 236 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 237 aprint_error("no media present"); 238 else 239 mii_phy_add_media(sc); 240 aprint_normal("\n"); 241 242 if (device_is_a(parent, "bge")) { 243 bsc->sc_isbge = 1; 244 dict = device_properties(parent); 245 prop_dictionary_get_uint32(dict, "phyflags", 246 &bsc->sc_bge_flags); 247 } else if (device_is_a(parent, "bnx")) { 248 bsc->sc_isbnx = 1; 249 dict = device_properties(parent); 250 prop_dictionary_get_uint32(dict, "phyflags", 251 &bsc->sc_bnx_flags); 252 } 253 } 254 255 static int 256 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 257 { 258 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 259 int reg, speed, gig; 260 261 switch (cmd) { 262 case MII_POLLSTAT: 263 /* 264 * If we're not polling our PHY instance, just return. 265 */ 266 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 267 return (0); 268 break; 269 270 case MII_MEDIACHG: 271 /* 272 * If the media indicates a different PHY instance, 273 * isolate ourselves. 274 */ 275 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 276 reg = PHY_READ(sc, MII_BMCR); 277 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 278 return (0); 279 } 280 281 /* 282 * If the interface is not up, don't do anything. 283 */ 284 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 285 break; 286 287 PHY_RESET(sc); /* XXX hardware bug work-around */ 288 289 switch (IFM_SUBTYPE(ife->ifm_media)) { 290 case IFM_AUTO: 291 (void) brgphy_mii_phy_auto(sc); 292 break; 293 case IFM_1000_T: 294 speed = BMCR_S1000; 295 goto setit; 296 case IFM_100_TX: 297 speed = BMCR_S100; 298 goto setit; 299 case IFM_10_T: 300 speed = BMCR_S10; 301 setit: 302 brgphy_loop(sc); 303 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 304 speed |= BMCR_FDX; 305 gig = GTCR_ADV_1000TFDX; 306 } else { 307 gig = GTCR_ADV_1000THDX; 308 } 309 310 PHY_WRITE(sc, MII_100T2CR, 0); 311 PHY_WRITE(sc, MII_BMCR, speed); 312 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 313 314 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 315 break; 316 317 PHY_WRITE(sc, MII_100T2CR, gig); 318 PHY_WRITE(sc, MII_BMCR, 319 speed|BMCR_AUTOEN|BMCR_STARTNEG); 320 321 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 322 break; 323 324 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 325 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 326 PHY_WRITE(sc, MII_100T2CR, gig); 327 break; 328 default: 329 return (EINVAL); 330 } 331 break; 332 333 case MII_TICK: 334 /* 335 * If we're not currently selected, just return. 336 */ 337 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 338 return (0); 339 340 if (mii_phy_tick(sc) == EJUSTRETURN) 341 return (0); 342 break; 343 344 case MII_DOWN: 345 mii_phy_down(sc); 346 return (0); 347 } 348 349 /* Update the media status. */ 350 mii_phy_status(sc); 351 352 /* 353 * Callback if something changed. Note that we need to poke the DSP on 354 * the Broadcom PHYs if the media changes. 355 */ 356 if (sc->mii_media_active != mii->mii_media_active || 357 sc->mii_media_status != mii->mii_media_status || 358 cmd == MII_MEDIACHG) { 359 switch (sc->mii_mpd_model) { 360 case MII_MODEL_BROADCOM_BCM5400: 361 brgphy_bcm5401_dspcode(sc); 362 break; 363 case MII_MODEL_BROADCOM_BCM5401: 364 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 365 brgphy_bcm5401_dspcode(sc); 366 break; 367 case MII_MODEL_BROADCOM_BCM5411: 368 brgphy_bcm5411_dspcode(sc); 369 break; 370 } 371 } 372 373 /* Callback if something changed. */ 374 mii_phy_update(sc, cmd); 375 return (0); 376 } 377 378 static void 379 brgphy_status(struct mii_softc *sc) 380 { 381 struct mii_data *mii = sc->mii_pdata; 382 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 383 int bmcr, auxsts, gtsr; 384 385 mii->mii_media_status = IFM_AVALID; 386 mii->mii_media_active = IFM_ETHER; 387 388 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 389 390 if (auxsts & BRGPHY_AUXSTS_LINK) 391 mii->mii_media_status |= IFM_ACTIVE; 392 393 bmcr = PHY_READ(sc, MII_BMCR); 394 if (bmcr & BMCR_ISO) { 395 mii->mii_media_active |= IFM_NONE; 396 mii->mii_media_status = 0; 397 return; 398 } 399 400 if (bmcr & BMCR_LOOP) 401 mii->mii_media_active |= IFM_LOOP; 402 403 if (bmcr & BMCR_AUTOEN) { 404 /* 405 * The media status bits are only valid of autonegotiation 406 * has completed (or it's disabled). 407 */ 408 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 409 /* Erg, still trying, I guess... */ 410 mii->mii_media_active |= IFM_NONE; 411 return; 412 } 413 414 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 415 case BRGPHY_RES_1000FD: 416 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 417 gtsr = PHY_READ(sc, MII_100T2SR); 418 if (gtsr & GTSR_MS_RES) 419 mii->mii_media_active |= IFM_ETH_MASTER; 420 break; 421 422 case BRGPHY_RES_1000HD: 423 mii->mii_media_active |= IFM_1000_T; 424 gtsr = PHY_READ(sc, MII_100T2SR); 425 if (gtsr & GTSR_MS_RES) 426 mii->mii_media_active |= IFM_ETH_MASTER; 427 break; 428 429 case BRGPHY_RES_100FD: 430 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 431 break; 432 433 case BRGPHY_RES_100T4: 434 mii->mii_media_active |= IFM_100_T4; 435 break; 436 437 case BRGPHY_RES_100HD: 438 mii->mii_media_active |= IFM_100_TX; 439 break; 440 441 case BRGPHY_RES_10FD: 442 mii->mii_media_active |= IFM_10_T|IFM_FDX; 443 break; 444 445 case BRGPHY_RES_10HD: 446 mii->mii_media_active |= IFM_10_T; 447 break; 448 449 default: 450 mii->mii_media_active |= IFM_NONE; 451 mii->mii_media_status = 0; 452 } 453 if (mii->mii_media_active & IFM_FDX) 454 mii->mii_media_active |= mii_phy_flowstatus(sc); 455 } else 456 mii->mii_media_active = ife->ifm_media; 457 } 458 459 int 460 brgphy_mii_phy_auto(struct mii_softc *sc) 461 { 462 int anar, ktcr = 0; 463 464 brgphy_loop(sc); 465 PHY_RESET(sc); 466 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 467 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 468 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 469 PHY_WRITE(sc, MII_100T2CR, ktcr); 470 ktcr = PHY_READ(sc, MII_100T2CR); 471 DELAY(1000); 472 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 473 if (sc->mii_flags & MIIF_DOPAUSE) 474 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 475 476 PHY_WRITE(sc, MII_ANAR, anar); 477 DELAY(1000); 478 PHY_WRITE(sc, MII_BMCR, 479 BMCR_AUTOEN | BMCR_STARTNEG); 480 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 481 482 return (EJUSTRETURN); 483 } 484 485 void 486 brgphy_loop(struct mii_softc *sc) 487 { 488 u_int32_t bmsr; 489 int i; 490 491 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 492 for (i = 0; i < 15000; i++) { 493 bmsr = PHY_READ(sc, MII_BMSR); 494 if (!(bmsr & BMSR_LINK)) 495 break; 496 DELAY(10); 497 } 498 } 499 500 static void 501 brgphy_reset(struct mii_softc *sc) 502 { 503 struct brgphy_softc *bsc = (void *)sc; 504 505 mii_phy_reset(sc); 506 507 switch (sc->mii_mpd_model) { 508 case MII_MODEL_BROADCOM_BCM5400: 509 brgphy_bcm5401_dspcode(sc); 510 break; 511 case MII_MODEL_BROADCOM_BCM5401: 512 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 513 brgphy_bcm5401_dspcode(sc); 514 break; 515 case MII_MODEL_BROADCOM_BCM5411: 516 brgphy_bcm5411_dspcode(sc); 517 break; 518 case MII_MODEL_BROADCOM_BCM5421: 519 brgphy_bcm5421_dspcode(sc); 520 break; 521 case MII_MODEL_BROADCOM_BCM54K2: 522 brgphy_bcm54k2_dspcode(sc); 523 break; 524 } 525 526 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 527 if (bsc->sc_isbge != 0) { 528 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 529 530 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 531 brgphy_adc_bug(sc); 532 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 533 brgphy_5704_a0_bug(sc); 534 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 535 brgphy_ber_bug(sc); 536 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 537 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 538 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 539 0x000a); 540 541 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 542 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 543 0x110b); 544 PHY_WRITE(sc, BRGPHY_TEST1, 545 BRGPHY_TEST1_TRIM_EN | 0x4); 546 } else { 547 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 548 0x010b); 549 } 550 551 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 552 } 553 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 554 brgphy_crc_bug(sc); 555 556 #if 0 557 /* Set Jumbo frame settings in the PHY. */ 558 if (bsc->sc_bge_flags & BGE_JUMBO_CAP) 559 brgphy_jumbo_settings(sc); 560 #endif 561 562 /* Adjust output voltage */ 563 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 564 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 565 566 #if 0 567 /* Enable Ethernet@Wirespeed */ 568 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 569 brgphy_eth_wirespeed(sc); 570 571 /* Enable Link LED on Dell boxes */ 572 if (bsc->sc_bge_flags & BGE_NO_3LED) { 573 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 574 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 575 & ~BRGPHY_PHY_EXTCTL_3_LED); 576 } 577 #endif 578 } 579 #if 0 /* not yet */ 580 /* Handle any bnx (NetXtreme II) workarounds. */ 581 } else if (sc->sc_isbnx != 0) { 582 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 583 584 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 585 /* Store autoneg capabilities/results in digital block (Page 0) */ 586 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 587 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 588 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 589 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 590 591 /* Enable fiber mode and autodetection */ 592 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 593 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 594 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 595 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 596 597 /* Enable parallel detection */ 598 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 599 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 600 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 601 602 /* Advertise 2.5G support through next page during autoneg */ 603 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 604 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 605 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 606 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 607 608 /* Increase TX signal amplitude */ 609 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 610 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 611 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 612 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 613 BRGPHY_5708S_TX_MISC_PG5); 614 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 615 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 616 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 617 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 618 BRGPHY_5708S_DIG_PG0); 619 } 620 621 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 622 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 623 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 624 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 625 BRGPHY_5708S_TX_MISC_PG5); 626 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 627 bnx_sc->bnx_port_hw_cfg & 628 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 629 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 630 BRGPHY_5708S_DIG_PG0); 631 } 632 } else { 633 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 634 brgphy_ber_bug(sc); 635 636 /* Set Jumbo frame settings in the PHY. */ 637 brgphy_jumbo_settings(sc); 638 639 /* Enable Ethernet@Wirespeed */ 640 brgphy_eth_wirespeed(sc); 641 } 642 } 643 #endif 644 } 645 } 646 647 /* Turn off tap power management on 5401. */ 648 static void 649 brgphy_bcm5401_dspcode(struct mii_softc *sc) 650 { 651 static const struct { 652 int reg; 653 uint16_t val; 654 } dspcode[] = { 655 { BRGPHY_MII_AUXCTL, 0x0c20 }, 656 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 657 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 658 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 659 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 660 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 661 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 662 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 663 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 664 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 665 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 666 { 0, 0 }, 667 }; 668 int i; 669 670 for (i = 0; dspcode[i].reg != 0; i++) 671 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 672 delay(40); 673 } 674 675 static void 676 brgphy_bcm5411_dspcode(struct mii_softc *sc) 677 { 678 static const struct { 679 int reg; 680 uint16_t val; 681 } dspcode[] = { 682 { 0x1c, 0x8c23 }, 683 { 0x1c, 0x8ca3 }, 684 { 0x1c, 0x8c23 }, 685 { 0, 0 }, 686 }; 687 int i; 688 689 for (i = 0; dspcode[i].reg != 0; i++) 690 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 691 } 692 693 void 694 brgphy_bcm5421_dspcode(struct mii_softc *sc) 695 { 696 uint16_t data; 697 698 /* Set Class A mode */ 699 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 700 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 701 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 702 703 /* Set FFE gamma override to -0.125 */ 704 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 705 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 706 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 707 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 708 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 709 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 710 } 711 712 void 713 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 714 { 715 static const struct { 716 int reg; 717 uint16_t val; 718 } dspcode[] = { 719 { 4, 0x01e1 }, 720 { 9, 0x0300 }, 721 { 0, 0 }, 722 }; 723 int i; 724 725 for (i = 0; dspcode[i].reg != 0; i++) 726 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 727 } 728 729 static void 730 brgphy_adc_bug(struct mii_softc *sc) 731 { 732 static const struct { 733 int reg; 734 uint16_t val; 735 } dspcode[] = { 736 { BRGPHY_MII_AUXCTL, 0x0c00 }, 737 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 738 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 739 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 740 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 741 { BRGPHY_MII_AUXCTL, 0x0400 }, 742 { 0, 0 }, 743 }; 744 int i; 745 746 for (i = 0; dspcode[i].reg != 0; i++) 747 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 748 } 749 750 static void 751 brgphy_5704_a0_bug(struct mii_softc *sc) 752 { 753 static const struct { 754 int reg; 755 uint16_t val; 756 } dspcode[] = { 757 { 0x1c, 0x8d68 }, 758 { 0x1c, 0x8d68 }, 759 { 0, 0 }, 760 }; 761 int i; 762 763 for (i = 0; dspcode[i].reg != 0; i++) 764 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 765 } 766 767 static void 768 brgphy_ber_bug(struct mii_softc *sc) 769 { 770 static const struct { 771 int reg; 772 uint16_t val; 773 } dspcode[] = { 774 { BRGPHY_MII_AUXCTL, 0x0c00 }, 775 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 776 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 777 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 778 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 779 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 780 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 781 { BRGPHY_MII_AUXCTL, 0x0400 }, 782 { 0, 0 }, 783 }; 784 int i; 785 786 for (i = 0; dspcode[i].reg != 0; i++) 787 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 788 } 789 790 /* BCM5701 A0/B0 CRC bug workaround */ 791 void 792 brgphy_crc_bug(struct mii_softc *sc) 793 { 794 static const struct { 795 int reg; 796 uint16_t val; 797 } dspcode[] = { 798 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 799 { 0x1c, 0x8c68 }, 800 { 0x1c, 0x8d68 }, 801 { 0x1c, 0x8c68 }, 802 { 0, 0 }, 803 }; 804 int i; 805 806 for (i = 0; dspcode[i].reg != 0; i++) 807 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 808 } 809
Indexes created Sun Oct 19 02:09:48 GMT 2025