brgphy.c revision 1.37.4.6
1 /* $NetBSD: brgphy.c,v 1.37.4.6 2010/03/11 15:03:41 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 Gig-E PHY. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.37.4.6 2010/03/11 15:03:41 yamt Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #if 0 85 #include <dev/pci/if_bnxreg.h> 86 #endif 87 88 static int brgphymatch(device_t, cfdata_t, void *); 89 static void brgphyattach(device_t, device_t, void *); 90 91 struct brgphy_softc { 92 struct mii_softc sc_mii; 93 int sc_isbge; 94 int sc_isbnx; 95 int sc_bge_flags; 96 int sc_bnx_flags; 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_status(struct mii_softc *); 105 static int brgphy_mii_phy_auto(struct mii_softc *); 106 static void brgphy_loop(struct mii_softc *); 107 static void brgphy_reset(struct mii_softc *); 108 static void brgphy_bcm5401_dspcode(struct mii_softc *); 109 static void brgphy_bcm5411_dspcode(struct mii_softc *); 110 static void brgphy_bcm5421_dspcode(struct mii_softc *); 111 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 112 static void brgphy_adc_bug(struct mii_softc *); 113 static void brgphy_5704_a0_bug(struct mii_softc *); 114 static void brgphy_ber_bug(struct mii_softc *); 115 static void brgphy_crc_bug(struct mii_softc *); 116 static void brgphy_jumbo_settings(struct mii_softc *); 117 static void brgphy_eth_wirespeed(struct mii_softc *); 118 119 120 static const struct mii_phy_funcs brgphy_funcs = { 121 brgphy_service, brgphy_status, brgphy_reset, 122 }; 123 124 static const struct mii_phydesc brgphys[] = { 125 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 126 MII_STR_BROADCOM_BCM5400 }, 127 128 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 129 MII_STR_BROADCOM_BCM5401 }, 130 131 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 132 MII_STR_BROADCOM_BCM5411 }, 133 134 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 135 MII_STR_BROADCOM_BCM5421 }, 136 137 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 138 MII_STR_BROADCOM_BCM54K2 }, 139 140 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 141 MII_STR_BROADCOM_BCM5461 }, 142 143 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 144 MII_STR_BROADCOM_BCM5462 }, 145 146 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 147 MII_STR_BROADCOM_BCM5464 }, 148 149 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 150 MII_STR_BROADCOM_BCM5701 }, 151 152 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 153 MII_STR_BROADCOM_BCM5703 }, 154 155 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 156 MII_STR_BROADCOM_BCM5704 }, 157 158 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 159 MII_STR_BROADCOM_BCM5705 }, 160 161 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 162 MII_STR_BROADCOM_BCM5714 }, 163 164 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 165 MII_STR_BROADCOM_BCM5750 }, 166 167 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 168 MII_STR_BROADCOM_BCM5752 }, 169 170 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 171 MII_STR_BROADCOM_BCM5780 }, 172 173 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 174 MII_STR_BROADCOM_BCM5708C }, 175 176 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 177 MII_STR_BROADCOM2_BCM5709C }, 178 179 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 180 MII_STR_BROADCOM2_BCM5709CAX }, 181 182 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 183 MII_STR_BROADCOM2_BCM5722 }, 184 185 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 186 MII_STR_BROADCOM2_BCM5755 }, 187 188 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 189 MII_STR_BROADCOM2_BCM5761 }, 190 191 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 192 MII_STR_BROADCOM2_BCM5754 }, 193 194 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 195 MII_STR_BROADCOM2_BCM5784 }, 196 197 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 198 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 199 200 { 0, 0, 201 NULL }, 202 }; 203 204 static int 205 brgphymatch(device_t parent, cfdata_t match, void *aux) 206 { 207 struct mii_attach_args *ma = aux; 208 209 if (mii_phy_match(ma, brgphys) != NULL) 210 return (10); 211 212 return (0); 213 } 214 215 static void 216 brgphyattach(device_t parent, device_t self, void *aux) 217 { 218 struct brgphy_softc *bsc = device_private(self); 219 struct mii_softc *sc = &bsc->sc_mii; 220 struct mii_attach_args *ma = aux; 221 struct mii_data *mii = ma->mii_data; 222 const struct mii_phydesc *mpd; 223 prop_dictionary_t dict; 224 225 mpd = mii_phy_match(ma, brgphys); 226 aprint_naive(": Media interface\n"); 227 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 228 229 sc->mii_dev = self; 230 sc->mii_inst = mii->mii_instance; 231 sc->mii_phy = ma->mii_phyno; 232 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 233 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 234 sc->mii_pdata = mii; 235 sc->mii_flags = ma->mii_flags; 236 sc->mii_anegticks = MII_ANEGTICKS; 237 sc->mii_funcs = &brgphy_funcs; 238 239 PHY_RESET(sc); 240 241 sc->mii_capabilities = 242 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 243 if (sc->mii_capabilities & BMSR_EXTSTAT) 244 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 245 246 aprint_normal_dev(self, ""); 247 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 248 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 249 aprint_error("no media present"); 250 else 251 mii_phy_add_media(sc); 252 aprint_normal("\n"); 253 254 if (device_is_a(parent, "bge")) { 255 bsc->sc_isbge = 1; 256 dict = device_properties(parent); 257 if (!prop_dictionary_get_uint32(dict, "phyflags", 258 &bsc->sc_bge_flags)) 259 aprint_error("failed to get phyflags"); 260 } else if (device_is_a(parent, "bnx")) { 261 bsc->sc_isbnx = 1; 262 dict = device_properties(parent); 263 prop_dictionary_get_uint32(dict, "phyflags", 264 &bsc->sc_bnx_flags); 265 } 266 } 267 268 static int 269 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 270 { 271 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 272 int reg, speed, gig; 273 274 switch (cmd) { 275 case MII_POLLSTAT: 276 /* 277 * If we're not polling our PHY instance, just return. 278 */ 279 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 280 return (0); 281 break; 282 283 case MII_MEDIACHG: 284 /* 285 * If the media indicates a different PHY instance, 286 * isolate ourselves. 287 */ 288 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 289 reg = PHY_READ(sc, MII_BMCR); 290 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 291 return (0); 292 } 293 294 /* 295 * If the interface is not up, don't do anything. 296 */ 297 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 298 break; 299 300 PHY_RESET(sc); /* XXX hardware bug work-around */ 301 302 switch (IFM_SUBTYPE(ife->ifm_media)) { 303 case IFM_AUTO: 304 (void) brgphy_mii_phy_auto(sc); 305 break; 306 case IFM_1000_T: 307 speed = BMCR_S1000; 308 goto setit; 309 case IFM_100_TX: 310 speed = BMCR_S100; 311 goto setit; 312 case IFM_10_T: 313 speed = BMCR_S10; 314 setit: 315 brgphy_loop(sc); 316 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 317 speed |= BMCR_FDX; 318 gig = GTCR_ADV_1000TFDX; 319 } else { 320 gig = GTCR_ADV_1000THDX; 321 } 322 323 PHY_WRITE(sc, MII_100T2CR, 0); 324 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 325 PHY_WRITE(sc, MII_BMCR, speed); 326 327 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 328 break; 329 330 PHY_WRITE(sc, MII_100T2CR, gig); 331 PHY_WRITE(sc, MII_BMCR, 332 speed|BMCR_AUTOEN|BMCR_STARTNEG); 333 334 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 335 break; 336 337 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 338 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 339 PHY_WRITE(sc, MII_100T2CR, gig); 340 break; 341 default: 342 return (EINVAL); 343 } 344 break; 345 346 case MII_TICK: 347 /* 348 * If we're not currently selected, just return. 349 */ 350 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 351 return (0); 352 353 if (mii_phy_tick(sc) == EJUSTRETURN) 354 return (0); 355 break; 356 357 case MII_DOWN: 358 mii_phy_down(sc); 359 return (0); 360 } 361 362 /* Update the media status. */ 363 mii_phy_status(sc); 364 365 /* 366 * Callback if something changed. Note that we need to poke the DSP on 367 * the Broadcom PHYs if the media changes. 368 */ 369 if (sc->mii_media_active != mii->mii_media_active || 370 sc->mii_media_status != mii->mii_media_status || 371 cmd == MII_MEDIACHG) { 372 switch (sc->mii_mpd_model) { 373 case MII_MODEL_BROADCOM_BCM5400: 374 brgphy_bcm5401_dspcode(sc); 375 break; 376 case MII_MODEL_BROADCOM_BCM5401: 377 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 378 brgphy_bcm5401_dspcode(sc); 379 break; 380 case MII_MODEL_BROADCOM_BCM5411: 381 brgphy_bcm5411_dspcode(sc); 382 break; 383 } 384 } 385 386 /* Callback if something changed. */ 387 mii_phy_update(sc, cmd); 388 return (0); 389 } 390 391 static void 392 brgphy_status(struct mii_softc *sc) 393 { 394 struct mii_data *mii = sc->mii_pdata; 395 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 396 int bmcr, auxsts, gtsr; 397 398 mii->mii_media_status = IFM_AVALID; 399 mii->mii_media_active = IFM_ETHER; 400 401 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 402 403 if (auxsts & BRGPHY_AUXSTS_LINK) 404 mii->mii_media_status |= IFM_ACTIVE; 405 406 bmcr = PHY_READ(sc, MII_BMCR); 407 if (bmcr & BMCR_ISO) { 408 mii->mii_media_active |= IFM_NONE; 409 mii->mii_media_status = 0; 410 return; 411 } 412 413 if (bmcr & BMCR_LOOP) 414 mii->mii_media_active |= IFM_LOOP; 415 416 if (bmcr & BMCR_AUTOEN) { 417 /* 418 * The media status bits are only valid of autonegotiation 419 * has completed (or it's disabled). 420 */ 421 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 422 /* Erg, still trying, I guess... */ 423 mii->mii_media_active |= IFM_NONE; 424 return; 425 } 426 427 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 428 case BRGPHY_RES_1000FD: 429 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 430 gtsr = PHY_READ(sc, MII_100T2SR); 431 if (gtsr & GTSR_MS_RES) 432 mii->mii_media_active |= IFM_ETH_MASTER; 433 break; 434 435 case BRGPHY_RES_1000HD: 436 mii->mii_media_active |= IFM_1000_T; 437 gtsr = PHY_READ(sc, MII_100T2SR); 438 if (gtsr & GTSR_MS_RES) 439 mii->mii_media_active |= IFM_ETH_MASTER; 440 break; 441 442 case BRGPHY_RES_100FD: 443 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 444 break; 445 446 case BRGPHY_RES_100T4: 447 mii->mii_media_active |= IFM_100_T4; 448 break; 449 450 case BRGPHY_RES_100HD: 451 mii->mii_media_active |= IFM_100_TX; 452 break; 453 454 case BRGPHY_RES_10FD: 455 mii->mii_media_active |= IFM_10_T|IFM_FDX; 456 break; 457 458 case BRGPHY_RES_10HD: 459 mii->mii_media_active |= IFM_10_T; 460 break; 461 462 default: 463 mii->mii_media_active |= IFM_NONE; 464 mii->mii_media_status = 0; 465 } 466 if (mii->mii_media_active & IFM_FDX) 467 mii->mii_media_active |= mii_phy_flowstatus(sc); 468 } else 469 mii->mii_media_active = ife->ifm_media; 470 } 471 472 int 473 brgphy_mii_phy_auto(struct mii_softc *sc) 474 { 475 int anar, ktcr = 0; 476 477 brgphy_loop(sc); 478 PHY_RESET(sc); 479 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 480 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 481 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 482 PHY_WRITE(sc, MII_100T2CR, ktcr); 483 ktcr = PHY_READ(sc, MII_100T2CR); 484 DELAY(1000); 485 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 486 if (sc->mii_flags & MIIF_DOPAUSE) 487 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 488 489 PHY_WRITE(sc, MII_ANAR, anar); 490 DELAY(1000); 491 PHY_WRITE(sc, MII_BMCR, 492 BMCR_AUTOEN | BMCR_STARTNEG); 493 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 494 495 return (EJUSTRETURN); 496 } 497 498 void 499 brgphy_loop(struct mii_softc *sc) 500 { 501 u_int32_t bmsr; 502 int i; 503 504 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 505 for (i = 0; i < 15000; i++) { 506 bmsr = PHY_READ(sc, MII_BMSR); 507 if (!(bmsr & BMSR_LINK)) 508 break; 509 DELAY(10); 510 } 511 } 512 513 static void 514 brgphy_reset(struct mii_softc *sc) 515 { 516 struct brgphy_softc *bsc = (void *)sc; 517 518 mii_phy_reset(sc); 519 520 switch (sc->mii_mpd_model) { 521 case MII_MODEL_BROADCOM_BCM5400: 522 brgphy_bcm5401_dspcode(sc); 523 break; 524 case MII_MODEL_BROADCOM_BCM5401: 525 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 526 brgphy_bcm5401_dspcode(sc); 527 break; 528 case MII_MODEL_BROADCOM_BCM5411: 529 brgphy_bcm5411_dspcode(sc); 530 break; 531 case MII_MODEL_BROADCOM_BCM5421: 532 brgphy_bcm5421_dspcode(sc); 533 break; 534 case MII_MODEL_BROADCOM_BCM54K2: 535 brgphy_bcm54k2_dspcode(sc); 536 break; 537 } 538 539 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 540 if (bsc->sc_isbge != 0) { 541 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 542 543 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 544 brgphy_adc_bug(sc); 545 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 546 brgphy_5704_a0_bug(sc); 547 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 548 brgphy_ber_bug(sc); 549 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 550 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 551 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 552 0x000a); 553 554 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 555 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 556 0x110b); 557 PHY_WRITE(sc, BRGPHY_TEST1, 558 BRGPHY_TEST1_TRIM_EN | 0x4); 559 } else { 560 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 561 0x010b); 562 } 563 564 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 565 } 566 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 567 brgphy_crc_bug(sc); 568 569 /* Set Jumbo frame settings in the PHY. */ 570 if (bsc->sc_bge_flags & BGE_JUMBO_CAPABLE) 571 brgphy_jumbo_settings(sc); 572 573 /* Adjust output voltage */ 574 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 575 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 576 577 /* Enable Ethernet@Wirespeed */ 578 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 579 brgphy_eth_wirespeed(sc); 580 581 #if 0 582 /* Enable Link LED on Dell boxes */ 583 if (bsc->sc_bge_flags & BGE_NO_3LED) { 584 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 585 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 586 & ~BRGPHY_PHY_EXTCTL_3_LED); 587 } 588 #endif 589 } 590 #if 0 /* not yet */ 591 /* Handle any bnx (NetXtreme II) workarounds. */ 592 } else if (sc->sc_isbnx != 0) { 593 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 594 595 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 596 /* Store autoneg capabilities/results in digital block (Page 0) */ 597 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 598 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 599 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 600 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 601 602 /* Enable fiber mode and autodetection */ 603 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 604 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 605 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 606 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 607 608 /* Enable parallel detection */ 609 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 610 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 611 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 612 613 /* Advertise 2.5G support through next page during autoneg */ 614 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 615 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 616 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 617 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 618 619 /* Increase TX signal amplitude */ 620 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 621 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 622 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 623 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 624 BRGPHY_5708S_TX_MISC_PG5); 625 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 626 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 627 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 628 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 629 BRGPHY_5708S_DIG_PG0); 630 } 631 632 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 633 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 634 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 635 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 636 BRGPHY_5708S_TX_MISC_PG5); 637 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 638 bnx_sc->bnx_port_hw_cfg & 639 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 640 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 641 BRGPHY_5708S_DIG_PG0); 642 } 643 } else { 644 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 645 brgphy_ber_bug(sc); 646 647 /* Set Jumbo frame settings in the PHY. */ 648 brgphy_jumbo_settings(sc); 649 650 /* Enable Ethernet@Wirespeed */ 651 brgphy_eth_wirespeed(sc); 652 } 653 } 654 #endif 655 } 656 } 657 658 /* Turn off tap power management on 5401. */ 659 static void 660 brgphy_bcm5401_dspcode(struct mii_softc *sc) 661 { 662 static const struct { 663 int reg; 664 uint16_t val; 665 } dspcode[] = { 666 { BRGPHY_MII_AUXCTL, 0x0c20 }, 667 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 668 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 669 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 670 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 671 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 672 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 673 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 674 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 675 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 676 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 677 { 0, 0 }, 678 }; 679 int i; 680 681 for (i = 0; dspcode[i].reg != 0; i++) 682 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 683 delay(40); 684 } 685 686 static void 687 brgphy_bcm5411_dspcode(struct mii_softc *sc) 688 { 689 static const struct { 690 int reg; 691 uint16_t val; 692 } dspcode[] = { 693 { 0x1c, 0x8c23 }, 694 { 0x1c, 0x8ca3 }, 695 { 0x1c, 0x8c23 }, 696 { 0, 0 }, 697 }; 698 int i; 699 700 for (i = 0; dspcode[i].reg != 0; i++) 701 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 702 } 703 704 void 705 brgphy_bcm5421_dspcode(struct mii_softc *sc) 706 { 707 uint16_t data; 708 709 /* Set Class A mode */ 710 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 711 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 712 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 713 714 /* Set FFE gamma override to -0.125 */ 715 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 716 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 717 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 718 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 719 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 720 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 721 } 722 723 void 724 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 725 { 726 static const struct { 727 int reg; 728 uint16_t val; 729 } dspcode[] = { 730 { 4, 0x01e1 }, 731 { 9, 0x0300 }, 732 { 0, 0 }, 733 }; 734 int i; 735 736 for (i = 0; dspcode[i].reg != 0; i++) 737 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 738 } 739 740 static void 741 brgphy_adc_bug(struct mii_softc *sc) 742 { 743 static const struct { 744 int reg; 745 uint16_t val; 746 } dspcode[] = { 747 { BRGPHY_MII_AUXCTL, 0x0c00 }, 748 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 749 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 750 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 751 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 752 { BRGPHY_MII_AUXCTL, 0x0400 }, 753 { 0, 0 }, 754 }; 755 int i; 756 757 for (i = 0; dspcode[i].reg != 0; i++) 758 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 759 } 760 761 static void 762 brgphy_5704_a0_bug(struct mii_softc *sc) 763 { 764 static const struct { 765 int reg; 766 uint16_t val; 767 } dspcode[] = { 768 { 0x1c, 0x8d68 }, 769 { 0x1c, 0x8d68 }, 770 { 0, 0 }, 771 }; 772 int i; 773 774 for (i = 0; dspcode[i].reg != 0; i++) 775 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 776 } 777 778 static void 779 brgphy_ber_bug(struct mii_softc *sc) 780 { 781 static const struct { 782 int reg; 783 uint16_t val; 784 } dspcode[] = { 785 { BRGPHY_MII_AUXCTL, 0x0c00 }, 786 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 787 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 788 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 789 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 790 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 791 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 792 { BRGPHY_MII_AUXCTL, 0x0400 }, 793 { 0, 0 }, 794 }; 795 int i; 796 797 for (i = 0; dspcode[i].reg != 0; i++) 798 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 799 } 800 801 /* BCM5701 A0/B0 CRC bug workaround */ 802 void 803 brgphy_crc_bug(struct mii_softc *sc) 804 { 805 static const struct { 806 int reg; 807 uint16_t val; 808 } dspcode[] = { 809 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 810 { 0x1c, 0x8c68 }, 811 { 0x1c, 0x8d68 }, 812 { 0x1c, 0x8c68 }, 813 { 0, 0 }, 814 }; 815 int i; 816 817 for (i = 0; dspcode[i].reg != 0; i++) 818 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 819 } 820 821 static void 822 brgphy_jumbo_settings(struct mii_softc *sc) 823 { 824 u_int32_t val; 825 826 /* Set Jumbo frame settings in the PHY. */ 827 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 828 /* Cannot do read-modify-write on the BCM5401 */ 829 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 830 } else { 831 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 832 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 833 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 834 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 835 } 836 837 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 838 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 839 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 840 } 841 842 static void 843 brgphy_eth_wirespeed(struct mii_softc *sc) 844 { 845 u_int32_t val; 846 847 /* Enable Ethernet@Wirespeed */ 848 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 849 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 850 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 851 (val | (1 << 15) | (1 << 4))); 852 } 853
Indexes created Thu Oct 23 22:10:10 GMT 2025