brgphy.c revision 1.38
1 /* $NetBSD: brgphy.c,v 1.38 2008/04/28 20:23:53 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.38 2008/04/28 20:23:53 martin Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 79 #include <net/if.h> 80 #include <net/if_media.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/miidevs.h> 85 86 #include <dev/mii/brgphyreg.h> 87 88 static int brgphymatch(struct device *, struct cfdata *, void *); 89 static void brgphyattach(struct device *, struct device *, void *); 90 91 CFATTACH_DECL(brgphy, sizeof(struct mii_softc), 92 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate); 93 94 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 95 static void brgphy_status(struct mii_softc *); 96 static int brgphy_mii_phy_auto(struct mii_softc *); 97 static void brgphy_loop(struct mii_softc *); 98 99 static void brgphy_5401_reset(struct mii_softc *); 100 static void brgphy_5411_reset(struct mii_softc *); 101 static void brgphy_5703_reset(struct mii_softc *); 102 static void brgphy_5704_reset(struct mii_softc *); 103 static void brgphy_5705_reset(struct mii_softc *); 104 static void brgphy_5750_reset(struct mii_softc *); 105 static void brgphy_5755_reset(struct mii_softc *); 106 107 static const struct mii_phy_funcs brgphy_funcs = { 108 brgphy_service, brgphy_status, mii_phy_reset, 109 }; 110 111 static const struct mii_phy_funcs brgphy_5401_funcs = { 112 brgphy_service, brgphy_status, brgphy_5401_reset, 113 }; 114 115 static const struct mii_phy_funcs brgphy_5411_funcs = { 116 brgphy_service, brgphy_status, brgphy_5411_reset, 117 }; 118 119 static const struct mii_phy_funcs brgphy_5703_funcs = { 120 brgphy_service, brgphy_status, brgphy_5703_reset, 121 }; 122 123 static const struct mii_phy_funcs brgphy_5704_funcs = { 124 brgphy_service, brgphy_status, brgphy_5704_reset, 125 }; 126 127 static const struct mii_phy_funcs brgphy_5705_funcs = { 128 brgphy_service, brgphy_status, brgphy_5705_reset, 129 }; 130 131 const struct mii_phy_funcs brgphy_5750_funcs = { 132 brgphy_service, brgphy_status, brgphy_5750_reset, 133 }; 134 135 const struct mii_phy_funcs brgphy_5755_funcs = { 136 brgphy_service, brgphy_status, brgphy_5755_reset, 137 }; 138 139 140 static const struct mii_phydesc brgphys[] = { 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 142 MII_STR_BROADCOM_BCM5400 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 145 MII_STR_BROADCOM_BCM5401 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 148 MII_STR_BROADCOM_BCM5411 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 151 MII_STR_BROADCOM_BCM5421 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 154 MII_STR_BROADCOM_BCM5701 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 157 MII_STR_BROADCOM_BCM5703 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 160 MII_STR_BROADCOM_BCM5704 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 163 MII_STR_BROADCOM_BCM5705 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 166 MII_STR_BROADCOM_BCM5714 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 169 MII_STR_BROADCOM_BCM5750 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 172 MII_STR_BROADCOM_BCM5752 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 175 MII_STR_BROADCOM_BCM5780 }, 176 177 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 178 MII_STR_BROADCOM_BCM5708C }, 179 180 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 181 MII_STR_BROADCOM2_BCM5755 }, 182 183 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 184 MII_STR_BROADCOM2_BCM5754 }, 185 186 { 0, 0, 187 NULL }, 188 }; 189 190 static void bcm5401_load_dspcode(struct mii_softc *); 191 static void bcm5411_load_dspcode(struct mii_softc *); 192 static void bcm5703_load_dspcode(struct mii_softc *); 193 static void bcm5704_load_dspcode(struct mii_softc *); 194 static void bcm5750_load_dspcode(struct mii_softc *); 195 static void bcm5755_load_dspcode(struct mii_softc *); 196 197 static int 198 brgphymatch(struct device *parent, struct cfdata *match, 199 void *aux) 200 { 201 struct mii_attach_args *ma = aux; 202 203 if (mii_phy_match(ma, brgphys) != NULL) 204 return (10); 205 206 return (0); 207 } 208 209 static void 210 brgphyattach(struct device *parent, struct device *self, void *aux) 211 { 212 struct mii_softc *sc = device_private(self); 213 struct mii_attach_args *ma = aux; 214 struct mii_data *mii = ma->mii_data; 215 const struct mii_phydesc *mpd; 216 217 mpd = mii_phy_match(ma, brgphys); 218 aprint_naive(": Media interface\n"); 219 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 220 221 sc->mii_inst = mii->mii_instance; 222 sc->mii_phy = ma->mii_phyno; 223 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 224 sc->mii_pdata = mii; 225 sc->mii_flags = ma->mii_flags; 226 sc->mii_anegticks = MII_ANEGTICKS; 227 228 switch (MII_MODEL(ma->mii_id2)) { 229 case MII_MODEL_BROADCOM_BCM5400: 230 sc->mii_funcs = &brgphy_5401_funcs; 231 aprint_normal_dev(&sc->mii_dev, "using BCM5401 DSP patch\n"); 232 break; 233 234 case MII_MODEL_BROADCOM_BCM5401: 235 if (MII_REV(ma->mii_id2) == 1 || MII_REV(ma->mii_id2) == 3) { 236 sc->mii_funcs = &brgphy_5401_funcs; 237 aprint_normal_dev(&sc->mii_dev, "using BCM5401 DSP patch\n"); 238 } else 239 sc->mii_funcs = &brgphy_funcs; 240 break; 241 242 case MII_MODEL_BROADCOM_BCM5411: 243 sc->mii_funcs = &brgphy_5411_funcs; 244 aprint_normal_dev(&sc->mii_dev, "using BCM5411 DSP patch\n"); 245 break; 246 247 #ifdef notyet /* unverified, untested */ 248 case MII_MODEL_BROADCOM_BCM5703: 249 sc->mii_funcs = &brgphy_5703_funcs; 250 aprint_normal_dev(&sc->mii_dev, "using BCM5703 DSP patch\n"); 251 break; 252 #endif 253 254 case MII_MODEL_BROADCOM_BCM5704: 255 sc->mii_funcs = &brgphy_5704_funcs; 256 aprint_normal_dev(&sc->mii_dev, "using BCM5704 DSP patch\n"); 257 break; 258 259 case MII_MODEL_BROADCOM_BCM5705: 260 sc->mii_funcs = &brgphy_5705_funcs; 261 break; 262 263 case MII_MODEL_BROADCOM_BCM5714: 264 case MII_MODEL_BROADCOM_BCM5780: 265 case MII_MODEL_BROADCOM_BCM5708C: 266 case MII_MODEL_BROADCOM_BCM5750: 267 case MII_MODEL_BROADCOM_BCM5752: 268 sc->mii_funcs = &brgphy_5750_funcs; 269 break; 270 271 case MII_MODEL_BROADCOM2_BCM5754: 272 case MII_MODEL_BROADCOM2_BCM5755: 273 sc->mii_funcs = &brgphy_5755_funcs; 274 break; 275 276 default: 277 sc->mii_funcs = &brgphy_funcs; 278 break; 279 } 280 281 PHY_RESET(sc); 282 283 sc->mii_capabilities = 284 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 285 if (sc->mii_capabilities & BMSR_EXTSTAT) 286 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 287 288 aprint_normal_dev(&sc->mii_dev, ""); 289 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 290 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 291 aprint_error("no media present"); 292 else 293 mii_phy_add_media(sc); 294 aprint_normal("\n"); 295 296 if (!pmf_device_register(self, NULL, mii_phy_resume)) 297 aprint_error_dev(self, "couldn't establish power handler\n"); 298 } 299 300 static int 301 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 302 { 303 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 304 int reg, speed, gig; 305 306 switch (cmd) { 307 case MII_POLLSTAT: 308 /* 309 * If we're not polling our PHY instance, just return. 310 */ 311 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 312 return (0); 313 break; 314 315 case MII_MEDIACHG: 316 /* 317 * If the media indicates a different PHY instance, 318 * isolate ourselves. 319 */ 320 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 321 reg = PHY_READ(sc, MII_BMCR); 322 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 323 return (0); 324 } 325 326 /* 327 * If the interface is not up, don't do anything. 328 */ 329 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 330 break; 331 332 PHY_RESET(sc); /* XXX hardware bug work-around */ 333 334 switch (IFM_SUBTYPE(ife->ifm_media)) { 335 case IFM_AUTO: 336 (void) brgphy_mii_phy_auto(sc); 337 break; 338 case IFM_1000_T: 339 speed = BMCR_S1000; 340 goto setit; 341 case IFM_100_TX: 342 speed = BMCR_S100; 343 goto setit; 344 case IFM_10_T: 345 speed = BMCR_S10; 346 setit: 347 brgphy_loop(sc); 348 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 349 speed |= BMCR_FDX; 350 gig = GTCR_ADV_1000TFDX; 351 } else { 352 gig = GTCR_ADV_1000THDX; 353 } 354 355 PHY_WRITE(sc, MII_100T2CR, 0); 356 PHY_WRITE(sc, MII_BMCR, speed); 357 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 358 359 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 360 break; 361 362 PHY_WRITE(sc, MII_100T2CR, gig); 363 PHY_WRITE(sc, MII_BMCR, 364 speed|BMCR_AUTOEN|BMCR_STARTNEG); 365 366 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 367 break; 368 369 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 370 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 371 PHY_WRITE(sc, MII_100T2CR, gig); 372 break; 373 default: 374 return (EINVAL); 375 } 376 break; 377 378 case MII_TICK: 379 /* 380 * If we're not currently selected, just return. 381 */ 382 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 383 return (0); 384 385 if (mii_phy_tick(sc) == EJUSTRETURN) 386 return (0); 387 break; 388 389 case MII_DOWN: 390 mii_phy_down(sc); 391 return (0); 392 } 393 394 /* Update the media status. */ 395 mii_phy_status(sc); 396 397 /* 398 * Callback if something changed. Note that we need to poke the DSP on 399 * the Broadcom PHYs if the media changes. 400 */ 401 if (sc->mii_media_active != mii->mii_media_active || 402 sc->mii_media_status != mii->mii_media_status || 403 cmd == MII_MEDIACHG) { 404 mii_phy_update(sc, cmd); 405 if (sc->mii_funcs == &brgphy_5401_funcs) 406 bcm5401_load_dspcode(sc); 407 else if (sc->mii_funcs == &brgphy_5411_funcs) 408 bcm5411_load_dspcode(sc); 409 } 410 return (0); 411 } 412 413 static void 414 brgphy_status(struct mii_softc *sc) 415 { 416 struct mii_data *mii = sc->mii_pdata; 417 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 418 int bmcr, auxsts, gtsr; 419 420 mii->mii_media_status = IFM_AVALID; 421 mii->mii_media_active = IFM_ETHER; 422 423 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 424 425 if (auxsts & BRGPHY_AUXSTS_LINK) 426 mii->mii_media_status |= IFM_ACTIVE; 427 428 bmcr = PHY_READ(sc, MII_BMCR); 429 if (bmcr & BMCR_ISO) { 430 mii->mii_media_active |= IFM_NONE; 431 mii->mii_media_status = 0; 432 return; 433 } 434 435 if (bmcr & BMCR_LOOP) 436 mii->mii_media_active |= IFM_LOOP; 437 438 if (bmcr & BMCR_AUTOEN) { 439 /* 440 * The media status bits are only valid of autonegotiation 441 * has completed (or it's disabled). 442 */ 443 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 444 /* Erg, still trying, I guess... */ 445 mii->mii_media_active |= IFM_NONE; 446 return; 447 } 448 449 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 450 case BRGPHY_RES_1000FD: 451 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 452 gtsr = PHY_READ(sc, MII_100T2SR); 453 if (gtsr & GTSR_MS_RES) 454 mii->mii_media_active |= IFM_ETH_MASTER; 455 break; 456 457 case BRGPHY_RES_1000HD: 458 mii->mii_media_active |= IFM_1000_T; 459 gtsr = PHY_READ(sc, MII_100T2SR); 460 if (gtsr & GTSR_MS_RES) 461 mii->mii_media_active |= IFM_ETH_MASTER; 462 break; 463 464 case BRGPHY_RES_100FD: 465 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 466 break; 467 468 case BRGPHY_RES_100T4: 469 mii->mii_media_active |= IFM_100_T4; 470 break; 471 472 case BRGPHY_RES_100HD: 473 mii->mii_media_active |= IFM_100_TX; 474 break; 475 476 case BRGPHY_RES_10FD: 477 mii->mii_media_active |= IFM_10_T|IFM_FDX; 478 break; 479 480 case BRGPHY_RES_10HD: 481 mii->mii_media_active |= IFM_10_T; 482 break; 483 484 default: 485 mii->mii_media_active |= IFM_NONE; 486 mii->mii_media_status = 0; 487 } 488 if (mii->mii_media_active & IFM_FDX) 489 mii->mii_media_active |= mii_phy_flowstatus(sc); 490 } else 491 mii->mii_media_active = ife->ifm_media; 492 } 493 494 int 495 brgphy_mii_phy_auto(struct mii_softc *sc) 496 { 497 int anar, ktcr = 0; 498 499 brgphy_loop(sc); 500 PHY_RESET(sc); 501 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 502 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 503 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 504 PHY_WRITE(sc, MII_100T2CR, ktcr); 505 ktcr = PHY_READ(sc, MII_100T2CR); 506 DELAY(1000); 507 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 508 if (sc->mii_flags & MIIF_DOPAUSE) 509 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 510 511 PHY_WRITE(sc, MII_ANAR, anar); 512 DELAY(1000); 513 PHY_WRITE(sc, MII_BMCR, 514 BMCR_AUTOEN | BMCR_STARTNEG); 515 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 516 517 return (EJUSTRETURN); 518 } 519 520 void 521 brgphy_loop(struct mii_softc *sc) 522 { 523 u_int32_t bmsr; 524 int i; 525 526 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 527 for (i = 0; i < 15000; i++) { 528 bmsr = PHY_READ(sc, MII_BMSR); 529 if (!(bmsr & BMSR_LINK)) 530 break; 531 DELAY(10); 532 } 533 } 534 535 static void 536 brgphy_5401_reset(struct mii_softc *sc) 537 { 538 539 mii_phy_reset(sc); 540 bcm5401_load_dspcode(sc); 541 } 542 543 static void 544 brgphy_5411_reset(struct mii_softc *sc) 545 { 546 547 mii_phy_reset(sc); 548 bcm5411_load_dspcode(sc); 549 } 550 551 552 static void 553 brgphy_5703_reset(struct mii_softc *sc) 554 { 555 556 mii_phy_reset(sc); 557 bcm5703_load_dspcode(sc); 558 } 559 560 static void 561 brgphy_5704_reset(struct mii_softc *sc) 562 { 563 564 mii_phy_reset(sc); 565 bcm5704_load_dspcode(sc); 566 } 567 568 /* 569 * Hardware bug workaround. Do nothing since after 570 * reset the 5705 PHY would get stuck in 10/100 MII mode. 571 */ 572 573 static void 574 brgphy_5705_reset(struct mii_softc *sc) 575 { 576 } 577 578 static void 579 brgphy_5750_reset(struct mii_softc *sc) 580 { 581 mii_phy_reset(sc); 582 bcm5750_load_dspcode(sc); 583 } 584 585 static void 586 brgphy_5755_reset(struct mii_softc *sc) 587 { 588 mii_phy_reset(sc); 589 bcm5755_load_dspcode(sc); 590 } 591 592 /* Turn off tap power management on 5401. */ 593 static void 594 bcm5401_load_dspcode(struct mii_softc *sc) 595 { 596 static const struct { 597 int reg; 598 uint16_t val; 599 } dspcode[] = { 600 { BRGPHY_MII_AUXCTL, 0x0c20 }, 601 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 602 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 603 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 604 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 605 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 606 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 607 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 608 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 609 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 610 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 611 { 0, 0 }, 612 }; 613 int i; 614 615 for (i = 0; dspcode[i].reg != 0; i++) 616 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 617 delay(40); 618 } 619 620 static void 621 bcm5411_load_dspcode(struct mii_softc *sc) 622 { 623 static const struct { 624 int reg; 625 uint16_t val; 626 } dspcode[] = { 627 { 0x1c, 0x8c23 }, 628 { 0x1c, 0x8ca3 }, 629 { 0x1c, 0x8c23 }, 630 { 0, 0 }, 631 }; 632 int i; 633 634 for (i = 0; dspcode[i].reg != 0; i++) 635 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 636 } 637 638 static void 639 bcm5703_load_dspcode(struct mii_softc *sc) 640 { 641 static const struct { 642 int reg; 643 uint16_t val; 644 } dspcode[] = { 645 { BRGPHY_MII_AUXCTL, 0x0c00 }, 646 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 647 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 648 { 0, 0 }, 649 }; 650 int i; 651 652 for (i = 0; dspcode[i].reg != 0; i++) 653 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 654 } 655 656 static void 657 bcm5704_load_dspcode(struct mii_softc *sc) 658 { 659 static const struct { 660 int reg; 661 uint16_t val; 662 } dspcode[] = { 663 { 0x1c, 0x8d68 }, 664 { 0x1c, 0x8d68 }, 665 { 0, 0 }, 666 }; 667 int i; 668 669 for (i = 0; dspcode[i].reg != 0; i++) 670 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 671 } 672 673 static void 674 bcm5750_load_dspcode(struct mii_softc *sc) 675 { 676 static const struct { 677 int reg; 678 uint16_t val; 679 } dspcode[] = { 680 { BRGPHY_MII_AUXCTL, 0x0c00 }, 681 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 682 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 683 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 684 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 685 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 686 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 687 { BRGPHY_MII_AUXCTL, 0x0400 }, 688 { 0, 0 }, 689 }; 690 int i; 691 692 for (i = 0; dspcode[i].reg != 0; i++) 693 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 694 } 695 696 static void 697 bcm5755_load_dspcode(struct mii_softc *sc) 698 { 699 static const struct { 700 int reg; 701 uint16_t val; 702 } dspcode[] = { 703 { BRGPHY_MII_AUXCTL, 0x0c00 }, 704 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 705 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 706 707 { BRGPHY_MII_AUXCTL, 0x0400 }, 708 { 0, 0 }, 709 }; 710 int i; 711 712 for (i = 0; dspcode[i].reg != 0; i++) 713 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 714 } 715
Indexes created Sun Oct 19 16:10:00 GMT 2025