brgphy.c revision 1.40
1 /* $NetBSD: brgphy.c,v 1.40 2008/08/25 08:15:05 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.40 2008/08/25 08:15:05 cegger Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 79 #include <net/if.h> 80 #include <net/if_media.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/miidevs.h> 85 86 #include <dev/mii/brgphyreg.h> 87 88 static int brgphymatch(device_t, cfdata_t, void *); 89 static void brgphyattach(device_t, device_t, void *); 90 91 CFATTACH_DECL_NEW(brgphy, sizeof(struct mii_softc), 92 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate); 93 94 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 95 static void brgphy_status(struct mii_softc *); 96 static int brgphy_mii_phy_auto(struct mii_softc *); 97 static void brgphy_loop(struct mii_softc *); 98 99 static void brgphy_5401_reset(struct mii_softc *); 100 static void brgphy_5411_reset(struct mii_softc *); 101 static void brgphy_5703_reset(struct mii_softc *); 102 static void brgphy_5704_reset(struct mii_softc *); 103 static void brgphy_5705_reset(struct mii_softc *); 104 static void brgphy_5750_reset(struct mii_softc *); 105 static void brgphy_5755_reset(struct mii_softc *); 106 107 static const struct mii_phy_funcs brgphy_funcs = { 108 brgphy_service, brgphy_status, mii_phy_reset, 109 }; 110 111 static const struct mii_phy_funcs brgphy_5401_funcs = { 112 brgphy_service, brgphy_status, brgphy_5401_reset, 113 }; 114 115 static const struct mii_phy_funcs brgphy_5411_funcs = { 116 brgphy_service, brgphy_status, brgphy_5411_reset, 117 }; 118 119 static const struct mii_phy_funcs brgphy_5703_funcs = { 120 brgphy_service, brgphy_status, brgphy_5703_reset, 121 }; 122 123 static const struct mii_phy_funcs brgphy_5704_funcs = { 124 brgphy_service, brgphy_status, brgphy_5704_reset, 125 }; 126 127 static const struct mii_phy_funcs brgphy_5705_funcs = { 128 brgphy_service, brgphy_status, brgphy_5705_reset, 129 }; 130 131 const struct mii_phy_funcs brgphy_5750_funcs = { 132 brgphy_service, brgphy_status, brgphy_5750_reset, 133 }; 134 135 const struct mii_phy_funcs brgphy_5755_funcs = { 136 brgphy_service, brgphy_status, brgphy_5755_reset, 137 }; 138 139 140 static const struct mii_phydesc brgphys[] = { 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 142 MII_STR_BROADCOM_BCM5400 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 145 MII_STR_BROADCOM_BCM5401 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 148 MII_STR_BROADCOM_BCM5411 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 151 MII_STR_BROADCOM_BCM5421 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 154 MII_STR_BROADCOM_BCM5701 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 157 MII_STR_BROADCOM_BCM5703 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 160 MII_STR_BROADCOM_BCM5704 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 163 MII_STR_BROADCOM_BCM5705 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 166 MII_STR_BROADCOM_BCM5714 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 169 MII_STR_BROADCOM_BCM5750 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 172 MII_STR_BROADCOM_BCM5752 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 175 MII_STR_BROADCOM_BCM5780 }, 176 177 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 178 MII_STR_BROADCOM_BCM5708C }, 179 180 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 181 MII_STR_BROADCOM2_BCM5755 }, 182 183 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 184 MII_STR_BROADCOM2_BCM5754 }, 185 186 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 187 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 188 189 { 0, 0, 190 NULL }, 191 }; 192 193 static void bcm5401_load_dspcode(struct mii_softc *); 194 static void bcm5411_load_dspcode(struct mii_softc *); 195 static void bcm5703_load_dspcode(struct mii_softc *); 196 static void bcm5704_load_dspcode(struct mii_softc *); 197 static void bcm5750_load_dspcode(struct mii_softc *); 198 static void bcm5755_load_dspcode(struct mii_softc *); 199 200 static int 201 brgphymatch(struct device *parent, struct cfdata *match, 202 void *aux) 203 { 204 struct mii_attach_args *ma = aux; 205 206 if (mii_phy_match(ma, brgphys) != NULL) 207 return (10); 208 209 return (0); 210 } 211 212 static void 213 brgphyattach(struct device *parent, struct device *self, void *aux) 214 { 215 struct mii_softc *sc = device_private(self); 216 struct mii_attach_args *ma = aux; 217 struct mii_data *mii = ma->mii_data; 218 const struct mii_phydesc *mpd; 219 220 mpd = mii_phy_match(ma, brgphys); 221 aprint_naive(": Media interface\n"); 222 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 223 224 sc->mii_dev = self; 225 sc->mii_inst = mii->mii_instance; 226 sc->mii_phy = ma->mii_phyno; 227 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 228 sc->mii_pdata = mii; 229 sc->mii_flags = ma->mii_flags; 230 sc->mii_anegticks = MII_ANEGTICKS; 231 232 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM_ALT1) { 233 sc->mii_funcs = &brgphy_5750_funcs; 234 aprint_normal_dev(self, "using BCM5750 DSP patch\n"); 235 } else { 236 switch (MII_MODEL(ma->mii_id2)) { 237 case MII_MODEL_BROADCOM_BCM5400: 238 sc->mii_funcs = &brgphy_5401_funcs; 239 aprint_normal_dev(self, "using BCM5401 DSP patch\n"); 240 break; 241 242 case MII_MODEL_BROADCOM_BCM5401: 243 if (MII_REV(ma->mii_id2) == 1 || MII_REV(ma->mii_id2) == 3) { 244 sc->mii_funcs = &brgphy_5401_funcs; 245 aprint_normal_dev(self, "using BCM5401 DSP patch\n"); 246 } else 247 sc->mii_funcs = &brgphy_funcs; 248 break; 249 250 case MII_MODEL_BROADCOM_BCM5411: 251 sc->mii_funcs = &brgphy_5411_funcs; 252 aprint_normal_dev(self, "using BCM5411 DSP patch\n"); 253 break; 254 255 #ifdef notyet /* unverified, untested */ 256 case MII_MODEL_BROADCOM_BCM5703: 257 sc->mii_funcs = &brgphy_5703_funcs; 258 aprint_normal_dev(self, "using BCM5703 DSP patch\n"); 259 break; 260 #endif 261 262 case MII_MODEL_BROADCOM_BCM5704: 263 sc->mii_funcs = &brgphy_5704_funcs; 264 aprint_normal_dev(self, "using BCM5704 DSP patch\n"); 265 break; 266 267 case MII_MODEL_BROADCOM_BCM5705: 268 sc->mii_funcs = &brgphy_5705_funcs; 269 break; 270 271 case MII_MODEL_BROADCOM_BCM5714: 272 case MII_MODEL_BROADCOM_BCM5780: 273 case MII_MODEL_BROADCOM_BCM5708C: 274 case MII_MODEL_BROADCOM_BCM5750: 275 case MII_MODEL_BROADCOM_BCM5752: 276 sc->mii_funcs = &brgphy_5750_funcs; 277 break; 278 279 case MII_MODEL_BROADCOM2_BCM5754: 280 case MII_MODEL_BROADCOM2_BCM5755: 281 sc->mii_funcs = &brgphy_5755_funcs; 282 break; 283 284 default: 285 sc->mii_funcs = &brgphy_funcs; 286 break; 287 } 288 } 289 290 PHY_RESET(sc); 291 292 sc->mii_capabilities = 293 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 294 if (sc->mii_capabilities & BMSR_EXTSTAT) 295 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 296 297 aprint_normal_dev(self, ""); 298 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 299 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 300 aprint_error("no media present"); 301 else 302 mii_phy_add_media(sc); 303 aprint_normal("\n"); 304 305 if (!pmf_device_register(self, NULL, mii_phy_resume)) 306 aprint_error_dev(self, "couldn't establish power handler\n"); 307 } 308 309 static int 310 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 311 { 312 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 313 int reg, speed, gig; 314 315 switch (cmd) { 316 case MII_POLLSTAT: 317 /* 318 * If we're not polling our PHY instance, just return. 319 */ 320 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 321 return (0); 322 break; 323 324 case MII_MEDIACHG: 325 /* 326 * If the media indicates a different PHY instance, 327 * isolate ourselves. 328 */ 329 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 330 reg = PHY_READ(sc, MII_BMCR); 331 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 332 return (0); 333 } 334 335 /* 336 * If the interface is not up, don't do anything. 337 */ 338 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 339 break; 340 341 PHY_RESET(sc); /* XXX hardware bug work-around */ 342 343 switch (IFM_SUBTYPE(ife->ifm_media)) { 344 case IFM_AUTO: 345 (void) brgphy_mii_phy_auto(sc); 346 break; 347 case IFM_1000_T: 348 speed = BMCR_S1000; 349 goto setit; 350 case IFM_100_TX: 351 speed = BMCR_S100; 352 goto setit; 353 case IFM_10_T: 354 speed = BMCR_S10; 355 setit: 356 brgphy_loop(sc); 357 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 358 speed |= BMCR_FDX; 359 gig = GTCR_ADV_1000TFDX; 360 } else { 361 gig = GTCR_ADV_1000THDX; 362 } 363 364 PHY_WRITE(sc, MII_100T2CR, 0); 365 PHY_WRITE(sc, MII_BMCR, speed); 366 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 367 368 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 369 break; 370 371 PHY_WRITE(sc, MII_100T2CR, gig); 372 PHY_WRITE(sc, MII_BMCR, 373 speed|BMCR_AUTOEN|BMCR_STARTNEG); 374 375 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 376 break; 377 378 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 379 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 380 PHY_WRITE(sc, MII_100T2CR, gig); 381 break; 382 default: 383 return (EINVAL); 384 } 385 break; 386 387 case MII_TICK: 388 /* 389 * If we're not currently selected, just return. 390 */ 391 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 392 return (0); 393 394 if (mii_phy_tick(sc) == EJUSTRETURN) 395 return (0); 396 break; 397 398 case MII_DOWN: 399 mii_phy_down(sc); 400 return (0); 401 } 402 403 /* Update the media status. */ 404 mii_phy_status(sc); 405 406 /* 407 * Callback if something changed. Note that we need to poke the DSP on 408 * the Broadcom PHYs if the media changes. 409 */ 410 if (sc->mii_media_active != mii->mii_media_active || 411 sc->mii_media_status != mii->mii_media_status || 412 cmd == MII_MEDIACHG) { 413 mii_phy_update(sc, cmd); 414 if (sc->mii_funcs == &brgphy_5401_funcs) 415 bcm5401_load_dspcode(sc); 416 else if (sc->mii_funcs == &brgphy_5411_funcs) 417 bcm5411_load_dspcode(sc); 418 } 419 return (0); 420 } 421 422 static void 423 brgphy_status(struct mii_softc *sc) 424 { 425 struct mii_data *mii = sc->mii_pdata; 426 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 427 int bmcr, auxsts, gtsr; 428 429 mii->mii_media_status = IFM_AVALID; 430 mii->mii_media_active = IFM_ETHER; 431 432 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 433 434 if (auxsts & BRGPHY_AUXSTS_LINK) 435 mii->mii_media_status |= IFM_ACTIVE; 436 437 bmcr = PHY_READ(sc, MII_BMCR); 438 if (bmcr & BMCR_ISO) { 439 mii->mii_media_active |= IFM_NONE; 440 mii->mii_media_status = 0; 441 return; 442 } 443 444 if (bmcr & BMCR_LOOP) 445 mii->mii_media_active |= IFM_LOOP; 446 447 if (bmcr & BMCR_AUTOEN) { 448 /* 449 * The media status bits are only valid of autonegotiation 450 * has completed (or it's disabled). 451 */ 452 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 453 /* Erg, still trying, I guess... */ 454 mii->mii_media_active |= IFM_NONE; 455 return; 456 } 457 458 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 459 case BRGPHY_RES_1000FD: 460 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 461 gtsr = PHY_READ(sc, MII_100T2SR); 462 if (gtsr & GTSR_MS_RES) 463 mii->mii_media_active |= IFM_ETH_MASTER; 464 break; 465 466 case BRGPHY_RES_1000HD: 467 mii->mii_media_active |= IFM_1000_T; 468 gtsr = PHY_READ(sc, MII_100T2SR); 469 if (gtsr & GTSR_MS_RES) 470 mii->mii_media_active |= IFM_ETH_MASTER; 471 break; 472 473 case BRGPHY_RES_100FD: 474 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 475 break; 476 477 case BRGPHY_RES_100T4: 478 mii->mii_media_active |= IFM_100_T4; 479 break; 480 481 case BRGPHY_RES_100HD: 482 mii->mii_media_active |= IFM_100_TX; 483 break; 484 485 case BRGPHY_RES_10FD: 486 mii->mii_media_active |= IFM_10_T|IFM_FDX; 487 break; 488 489 case BRGPHY_RES_10HD: 490 mii->mii_media_active |= IFM_10_T; 491 break; 492 493 default: 494 mii->mii_media_active |= IFM_NONE; 495 mii->mii_media_status = 0; 496 } 497 if (mii->mii_media_active & IFM_FDX) 498 mii->mii_media_active |= mii_phy_flowstatus(sc); 499 } else 500 mii->mii_media_active = ife->ifm_media; 501 } 502 503 int 504 brgphy_mii_phy_auto(struct mii_softc *sc) 505 { 506 int anar, ktcr = 0; 507 508 brgphy_loop(sc); 509 PHY_RESET(sc); 510 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 511 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 512 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 513 PHY_WRITE(sc, MII_100T2CR, ktcr); 514 ktcr = PHY_READ(sc, MII_100T2CR); 515 DELAY(1000); 516 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 517 if (sc->mii_flags & MIIF_DOPAUSE) 518 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 519 520 PHY_WRITE(sc, MII_ANAR, anar); 521 DELAY(1000); 522 PHY_WRITE(sc, MII_BMCR, 523 BMCR_AUTOEN | BMCR_STARTNEG); 524 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 525 526 return (EJUSTRETURN); 527 } 528 529 void 530 brgphy_loop(struct mii_softc *sc) 531 { 532 u_int32_t bmsr; 533 int i; 534 535 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 536 for (i = 0; i < 15000; i++) { 537 bmsr = PHY_READ(sc, MII_BMSR); 538 if (!(bmsr & BMSR_LINK)) 539 break; 540 DELAY(10); 541 } 542 } 543 544 static void 545 brgphy_5401_reset(struct mii_softc *sc) 546 { 547 548 mii_phy_reset(sc); 549 bcm5401_load_dspcode(sc); 550 } 551 552 static void 553 brgphy_5411_reset(struct mii_softc *sc) 554 { 555 556 mii_phy_reset(sc); 557 bcm5411_load_dspcode(sc); 558 } 559 560 561 static void 562 brgphy_5703_reset(struct mii_softc *sc) 563 { 564 565 mii_phy_reset(sc); 566 bcm5703_load_dspcode(sc); 567 } 568 569 static void 570 brgphy_5704_reset(struct mii_softc *sc) 571 { 572 573 mii_phy_reset(sc); 574 bcm5704_load_dspcode(sc); 575 } 576 577 /* 578 * Hardware bug workaround. Do nothing since after 579 * reset the 5705 PHY would get stuck in 10/100 MII mode. 580 */ 581 582 static void 583 brgphy_5705_reset(struct mii_softc *sc) 584 { 585 } 586 587 static void 588 brgphy_5750_reset(struct mii_softc *sc) 589 { 590 mii_phy_reset(sc); 591 bcm5750_load_dspcode(sc); 592 } 593 594 static void 595 brgphy_5755_reset(struct mii_softc *sc) 596 { 597 mii_phy_reset(sc); 598 bcm5755_load_dspcode(sc); 599 } 600 601 /* Turn off tap power management on 5401. */ 602 static void 603 bcm5401_load_dspcode(struct mii_softc *sc) 604 { 605 static const struct { 606 int reg; 607 uint16_t val; 608 } dspcode[] = { 609 { BRGPHY_MII_AUXCTL, 0x0c20 }, 610 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 611 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 612 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 613 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 614 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 615 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 616 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 617 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 618 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 619 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 620 { 0, 0 }, 621 }; 622 int i; 623 624 for (i = 0; dspcode[i].reg != 0; i++) 625 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 626 delay(40); 627 } 628 629 static void 630 bcm5411_load_dspcode(struct mii_softc *sc) 631 { 632 static const struct { 633 int reg; 634 uint16_t val; 635 } dspcode[] = { 636 { 0x1c, 0x8c23 }, 637 { 0x1c, 0x8ca3 }, 638 { 0x1c, 0x8c23 }, 639 { 0, 0 }, 640 }; 641 int i; 642 643 for (i = 0; dspcode[i].reg != 0; i++) 644 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 645 } 646 647 static void 648 bcm5703_load_dspcode(struct mii_softc *sc) 649 { 650 static const struct { 651 int reg; 652 uint16_t val; 653 } dspcode[] = { 654 { BRGPHY_MII_AUXCTL, 0x0c00 }, 655 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 656 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 657 { 0, 0 }, 658 }; 659 int i; 660 661 for (i = 0; dspcode[i].reg != 0; i++) 662 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 663 } 664 665 static void 666 bcm5704_load_dspcode(struct mii_softc *sc) 667 { 668 static const struct { 669 int reg; 670 uint16_t val; 671 } dspcode[] = { 672 { 0x1c, 0x8d68 }, 673 { 0x1c, 0x8d68 }, 674 { 0, 0 }, 675 }; 676 int i; 677 678 for (i = 0; dspcode[i].reg != 0; i++) 679 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 680 } 681 682 static void 683 bcm5750_load_dspcode(struct mii_softc *sc) 684 { 685 static const struct { 686 int reg; 687 uint16_t val; 688 } dspcode[] = { 689 { BRGPHY_MII_AUXCTL, 0x0c00 }, 690 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 691 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 692 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 693 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 694 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 695 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 696 { BRGPHY_MII_AUXCTL, 0x0400 }, 697 { 0, 0 }, 698 }; 699 int i; 700 701 for (i = 0; dspcode[i].reg != 0; i++) 702 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 703 } 704 705 static void 706 bcm5755_load_dspcode(struct mii_softc *sc) 707 { 708 static const struct { 709 int reg; 710 uint16_t val; 711 } dspcode[] = { 712 { BRGPHY_MII_AUXCTL, 0x0c00 }, 713 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 714 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 715 716 { BRGPHY_MII_AUXCTL, 0x0400 }, 717 { 0, 0 }, 718 }; 719 int i; 720 721 for (i = 0; dspcode[i].reg != 0; i++) 722 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 723 } 724
Indexes created Sat Sep 27 21:09:56 GMT 2025