brgphy.c revision 1.40.4.3
1 /* $NetBSD: brgphy.c,v 1.40.4.3 2010/11/19 23:58:41 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.40.4.3 2010/11/19 23:58:41 riz Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 #include <prop/proplib.h> 79 80 #include <net/if.h> 81 #include <net/if_media.h> 82 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/mii/miidevs.h> 86 87 #include <dev/mii/brgphyreg.h> 88 #include <dev/pci/if_bgereg.h> 89 90 static int brgphymatch(device_t, cfdata_t, void *); 91 static void brgphyattach(device_t, device_t, void *); 92 93 struct brgphy_softc { 94 struct mii_softc sc_mii; 95 int sc_isbge; 96 int sc_isbnx; 97 int sc_bge_flags; 98 int sc_bnx_flags; 99 }; 100 101 CFATTACH_DECL_NEW(brgphy, sizeof(struct brgphy_softc), 102 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate); 103 104 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 105 static void brgphy_status(struct mii_softc *); 106 static int brgphy_mii_phy_auto(struct mii_softc *); 107 static void brgphy_loop(struct mii_softc *); 108 static void brgphy_reset(struct mii_softc *); 109 static void brgphy_bcm5401_dspcode(struct mii_softc *); 110 static void brgphy_bcm5411_dspcode(struct mii_softc *); 111 static void brgphy_bcm5421_dspcode(struct mii_softc *); 112 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 113 static void brgphy_adc_bug(struct mii_softc *); 114 static void brgphy_5704_a0_bug(struct mii_softc *); 115 static void brgphy_ber_bug(struct mii_softc *); 116 static void brgphy_crc_bug(struct mii_softc *); 117 static void brgphy_jumbo_settings(struct mii_softc *); 118 static void brgphy_eth_wirespeed(struct mii_softc *); 119 120 121 static const struct mii_phy_funcs brgphy_funcs = { 122 brgphy_service, brgphy_status, brgphy_reset, 123 }; 124 125 static const struct mii_phydesc brgphys[] = { 126 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 127 MII_STR_BROADCOM_BCM5400 }, 128 129 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 130 MII_STR_BROADCOM_BCM5401 }, 131 132 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 133 MII_STR_BROADCOM_BCM5411 }, 134 135 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 136 MII_STR_BROADCOM_BCM5421 }, 137 138 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 139 MII_STR_BROADCOM_BCM54K2 }, 140 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 142 MII_STR_BROADCOM_BCM5461 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 145 MII_STR_BROADCOM_BCM5462 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 148 MII_STR_BROADCOM_BCM5464 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 151 MII_STR_BROADCOM_BCM5701 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 154 MII_STR_BROADCOM_BCM5703 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 157 MII_STR_BROADCOM_BCM5704 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 160 MII_STR_BROADCOM_BCM5705 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 163 MII_STR_BROADCOM_BCM5714 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 166 MII_STR_BROADCOM_BCM5750 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 169 MII_STR_BROADCOM_BCM5752 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 172 MII_STR_BROADCOM_BCM5780 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 175 MII_STR_BROADCOM_BCM5708C }, 176 177 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 178 MII_STR_BROADCOM2_BCM5709C }, 179 180 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 181 MII_STR_BROADCOM2_BCM5709CAX }, 182 183 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 184 MII_STR_BROADCOM2_BCM5722 }, 185 186 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 187 MII_STR_BROADCOM2_BCM5755 }, 188 189 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 190 MII_STR_BROADCOM2_BCM5761 }, 191 192 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 193 MII_STR_BROADCOM2_BCM5754 }, 194 195 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 196 MII_STR_BROADCOM2_BCM5784 }, 197 198 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 199 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 200 201 { 0, 0, 202 NULL }, 203 }; 204 205 static int 206 brgphymatch(struct device *parent, struct cfdata *match, void *aux) 207 { 208 struct mii_attach_args *ma = aux; 209 210 if (mii_phy_match(ma, brgphys) != NULL) 211 return (10); 212 213 return (0); 214 } 215 216 static void 217 brgphyattach(struct device *parent, struct device *self, void *aux) 218 { 219 struct brgphy_softc *bsc = device_private(self); 220 struct mii_softc *sc = &bsc->sc_mii; 221 struct mii_attach_args *ma = aux; 222 struct mii_data *mii = ma->mii_data; 223 const struct mii_phydesc *mpd; 224 prop_dictionary_t dict; 225 226 mpd = mii_phy_match(ma, brgphys); 227 aprint_naive(": Media interface\n"); 228 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 229 230 sc->mii_dev = self; 231 sc->mii_inst = mii->mii_instance; 232 sc->mii_phy = ma->mii_phyno; 233 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 234 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 235 sc->mii_pdata = mii; 236 sc->mii_flags = ma->mii_flags; 237 sc->mii_anegticks = MII_ANEGTICKS; 238 sc->mii_funcs = &brgphy_funcs; 239 240 PHY_RESET(sc); 241 242 sc->mii_capabilities = 243 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 244 if (sc->mii_capabilities & BMSR_EXTSTAT) 245 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 246 247 aprint_normal_dev(self, ""); 248 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 249 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 250 aprint_error("no media present"); 251 else 252 mii_phy_add_media(sc); 253 aprint_normal("\n"); 254 255 if (device_is_a(parent, "bge")) { 256 bsc->sc_isbge = 1; 257 dict = device_properties(parent); 258 if (!prop_dictionary_get_uint32(dict, "phyflags", 259 &bsc->sc_bge_flags)) 260 aprint_error("failed to get phyflags"); 261 } else if (device_is_a(parent, "bnx")) { 262 bsc->sc_isbnx = 1; 263 dict = device_properties(parent); 264 prop_dictionary_get_uint32(dict, "phyflags", 265 &bsc->sc_bnx_flags); 266 } 267 268 if (!pmf_device_register(self, NULL, mii_phy_resume)) 269 aprint_error_dev(self, "couldn't establish power handler\n"); 270 } 271 272 static int 273 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 274 { 275 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 276 int reg, speed, gig; 277 278 switch (cmd) { 279 case MII_POLLSTAT: 280 /* 281 * If we're not polling our PHY instance, just return. 282 */ 283 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 284 return (0); 285 break; 286 287 case MII_MEDIACHG: 288 /* 289 * If the media indicates a different PHY instance, 290 * isolate ourselves. 291 */ 292 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 293 reg = PHY_READ(sc, MII_BMCR); 294 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 295 return (0); 296 } 297 298 /* 299 * If the interface is not up, don't do anything. 300 */ 301 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 302 break; 303 304 PHY_RESET(sc); /* XXX hardware bug work-around */ 305 306 switch (IFM_SUBTYPE(ife->ifm_media)) { 307 case IFM_AUTO: 308 (void) brgphy_mii_phy_auto(sc); 309 break; 310 case IFM_1000_T: 311 speed = BMCR_S1000; 312 goto setit; 313 case IFM_100_TX: 314 speed = BMCR_S100; 315 goto setit; 316 case IFM_10_T: 317 speed = BMCR_S10; 318 setit: 319 brgphy_loop(sc); 320 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 321 speed |= BMCR_FDX; 322 gig = GTCR_ADV_1000TFDX; 323 } else { 324 gig = GTCR_ADV_1000THDX; 325 } 326 327 PHY_WRITE(sc, MII_100T2CR, 0); 328 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 329 PHY_WRITE(sc, MII_BMCR, speed); 330 331 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 332 break; 333 334 PHY_WRITE(sc, MII_100T2CR, gig); 335 PHY_WRITE(sc, MII_BMCR, 336 speed|BMCR_AUTOEN|BMCR_STARTNEG); 337 338 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 339 break; 340 341 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 342 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 343 PHY_WRITE(sc, MII_100T2CR, gig); 344 break; 345 default: 346 return (EINVAL); 347 } 348 break; 349 350 case MII_TICK: 351 /* 352 * If we're not currently selected, just return. 353 */ 354 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 355 return (0); 356 357 if (mii_phy_tick(sc) == EJUSTRETURN) 358 return (0); 359 break; 360 361 case MII_DOWN: 362 mii_phy_down(sc); 363 return (0); 364 } 365 366 /* Update the media status. */ 367 mii_phy_status(sc); 368 369 /* 370 * Callback if something changed. Note that we need to poke the DSP on 371 * the Broadcom PHYs if the media changes. 372 */ 373 if (sc->mii_media_active != mii->mii_media_active || 374 sc->mii_media_status != mii->mii_media_status || 375 cmd == MII_MEDIACHG) { 376 switch (sc->mii_mpd_model) { 377 case MII_MODEL_BROADCOM_BCM5400: 378 brgphy_bcm5401_dspcode(sc); 379 break; 380 case MII_MODEL_BROADCOM_BCM5401: 381 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 382 brgphy_bcm5401_dspcode(sc); 383 break; 384 case MII_MODEL_BROADCOM_BCM5411: 385 brgphy_bcm5411_dspcode(sc); 386 break; 387 } 388 } 389 390 /* Callback if something changed. */ 391 mii_phy_update(sc, cmd); 392 return (0); 393 } 394 395 static void 396 brgphy_status(struct mii_softc *sc) 397 { 398 struct mii_data *mii = sc->mii_pdata; 399 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 400 int bmcr, auxsts, gtsr; 401 402 mii->mii_media_status = IFM_AVALID; 403 mii->mii_media_active = IFM_ETHER; 404 405 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 406 407 if (auxsts & BRGPHY_AUXSTS_LINK) 408 mii->mii_media_status |= IFM_ACTIVE; 409 410 bmcr = PHY_READ(sc, MII_BMCR); 411 if (bmcr & BMCR_ISO) { 412 mii->mii_media_active |= IFM_NONE; 413 mii->mii_media_status = 0; 414 return; 415 } 416 417 if (bmcr & BMCR_LOOP) 418 mii->mii_media_active |= IFM_LOOP; 419 420 if (bmcr & BMCR_AUTOEN) { 421 /* 422 * The media status bits are only valid of autonegotiation 423 * has completed (or it's disabled). 424 */ 425 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 426 /* Erg, still trying, I guess... */ 427 mii->mii_media_active |= IFM_NONE; 428 return; 429 } 430 431 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 432 case BRGPHY_RES_1000FD: 433 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 434 gtsr = PHY_READ(sc, MII_100T2SR); 435 if (gtsr & GTSR_MS_RES) 436 mii->mii_media_active |= IFM_ETH_MASTER; 437 break; 438 439 case BRGPHY_RES_1000HD: 440 mii->mii_media_active |= IFM_1000_T; 441 gtsr = PHY_READ(sc, MII_100T2SR); 442 if (gtsr & GTSR_MS_RES) 443 mii->mii_media_active |= IFM_ETH_MASTER; 444 break; 445 446 case BRGPHY_RES_100FD: 447 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 448 break; 449 450 case BRGPHY_RES_100T4: 451 mii->mii_media_active |= IFM_100_T4; 452 break; 453 454 case BRGPHY_RES_100HD: 455 mii->mii_media_active |= IFM_100_TX; 456 break; 457 458 case BRGPHY_RES_10FD: 459 mii->mii_media_active |= IFM_10_T|IFM_FDX; 460 break; 461 462 case BRGPHY_RES_10HD: 463 mii->mii_media_active |= IFM_10_T; 464 break; 465 466 default: 467 mii->mii_media_active |= IFM_NONE; 468 mii->mii_media_status = 0; 469 } 470 if (mii->mii_media_active & IFM_FDX) 471 mii->mii_media_active |= mii_phy_flowstatus(sc); 472 } else 473 mii->mii_media_active = ife->ifm_media; 474 } 475 476 int 477 brgphy_mii_phy_auto(struct mii_softc *sc) 478 { 479 int anar, ktcr = 0; 480 481 brgphy_loop(sc); 482 PHY_RESET(sc); 483 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 484 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 485 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 486 PHY_WRITE(sc, MII_100T2CR, ktcr); 487 ktcr = PHY_READ(sc, MII_100T2CR); 488 DELAY(1000); 489 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 490 if (sc->mii_flags & MIIF_DOPAUSE) 491 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 492 493 PHY_WRITE(sc, MII_ANAR, anar); 494 DELAY(1000); 495 PHY_WRITE(sc, MII_BMCR, 496 BMCR_AUTOEN | BMCR_STARTNEG); 497 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 498 499 return (EJUSTRETURN); 500 } 501 502 void 503 brgphy_loop(struct mii_softc *sc) 504 { 505 u_int32_t bmsr; 506 int i; 507 508 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 509 for (i = 0; i < 15000; i++) { 510 bmsr = PHY_READ(sc, MII_BMSR); 511 if (!(bmsr & BMSR_LINK)) 512 break; 513 DELAY(10); 514 } 515 } 516 517 static void 518 brgphy_reset(struct mii_softc *sc) 519 { 520 struct brgphy_softc *bsc = (void *)sc; 521 522 mii_phy_reset(sc); 523 524 switch (sc->mii_mpd_model) { 525 case MII_MODEL_BROADCOM_BCM5400: 526 brgphy_bcm5401_dspcode(sc); 527 break; 528 case MII_MODEL_BROADCOM_BCM5401: 529 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 530 brgphy_bcm5401_dspcode(sc); 531 break; 532 case MII_MODEL_BROADCOM_BCM5411: 533 brgphy_bcm5411_dspcode(sc); 534 break; 535 case MII_MODEL_BROADCOM_BCM5421: 536 brgphy_bcm5421_dspcode(sc); 537 break; 538 case MII_MODEL_BROADCOM_BCM54K2: 539 brgphy_bcm54k2_dspcode(sc); 540 break; 541 } 542 543 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 544 if (bsc->sc_isbge != 0) { 545 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 546 547 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 548 brgphy_adc_bug(sc); 549 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 550 brgphy_5704_a0_bug(sc); 551 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 552 brgphy_ber_bug(sc); 553 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 554 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 555 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 556 0x000a); 557 558 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 559 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 560 0x110b); 561 PHY_WRITE(sc, BRGPHY_TEST1, 562 BRGPHY_TEST1_TRIM_EN | 0x4); 563 } else { 564 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 565 0x010b); 566 } 567 568 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 569 } 570 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 571 brgphy_crc_bug(sc); 572 573 /* Set Jumbo frame settings in the PHY. */ 574 if (bsc->sc_bge_flags & BGE_JUMBO_CAPABLE) 575 brgphy_jumbo_settings(sc); 576 577 /* Adjust output voltage */ 578 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 579 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 580 581 /* Enable Ethernet@Wirespeed */ 582 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 583 brgphy_eth_wirespeed(sc); 584 585 #if 0 586 /* Enable Link LED on Dell boxes */ 587 if (bsc->sc_bge_flags & BGE_NO_3LED) { 588 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 589 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 590 & ~BRGPHY_PHY_EXTCTL_3_LED); 591 } 592 #endif 593 } 594 #if 0 /* not yet */ 595 /* Handle any bnx (NetXtreme II) workarounds. */ 596 } else if (sc->sc_isbnx != 0) { 597 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 598 599 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 600 /* Store autoneg capabilities/results in digital block (Page 0) */ 601 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 602 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 603 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 604 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 605 606 /* Enable fiber mode and autodetection */ 607 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 608 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 609 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 610 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 611 612 /* Enable parallel detection */ 613 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 614 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 615 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 616 617 /* Advertise 2.5G support through next page during autoneg */ 618 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 619 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 620 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 621 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 622 623 /* Increase TX signal amplitude */ 624 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 625 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 626 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 627 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 628 BRGPHY_5708S_TX_MISC_PG5); 629 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 630 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 631 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 632 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 633 BRGPHY_5708S_DIG_PG0); 634 } 635 636 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 637 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 638 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 639 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 640 BRGPHY_5708S_TX_MISC_PG5); 641 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 642 bnx_sc->bnx_port_hw_cfg & 643 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 644 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 645 BRGPHY_5708S_DIG_PG0); 646 } 647 } else { 648 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 649 brgphy_ber_bug(sc); 650 651 /* Set Jumbo frame settings in the PHY. */ 652 brgphy_jumbo_settings(sc); 653 654 /* Enable Ethernet@Wirespeed */ 655 brgphy_eth_wirespeed(sc); 656 } 657 } 658 #endif 659 } 660 } 661 662 /* Turn off tap power management on 5401. */ 663 static void 664 brgphy_bcm5401_dspcode(struct mii_softc *sc) 665 { 666 static const struct { 667 int reg; 668 uint16_t val; 669 } dspcode[] = { 670 { BRGPHY_MII_AUXCTL, 0x0c20 }, 671 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 672 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 673 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 674 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 675 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 676 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 677 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 678 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 679 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 680 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 681 { 0, 0 }, 682 }; 683 int i; 684 685 for (i = 0; dspcode[i].reg != 0; i++) 686 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 687 delay(40); 688 } 689 690 static void 691 brgphy_bcm5411_dspcode(struct mii_softc *sc) 692 { 693 static const struct { 694 int reg; 695 uint16_t val; 696 } dspcode[] = { 697 { 0x1c, 0x8c23 }, 698 { 0x1c, 0x8ca3 }, 699 { 0x1c, 0x8c23 }, 700 { 0, 0 }, 701 }; 702 int i; 703 704 for (i = 0; dspcode[i].reg != 0; i++) 705 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 706 } 707 708 void 709 brgphy_bcm5421_dspcode(struct mii_softc *sc) 710 { 711 uint16_t data; 712 713 /* Set Class A mode */ 714 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 715 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 716 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 717 718 /* Set FFE gamma override to -0.125 */ 719 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 720 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 721 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 722 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 723 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 724 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 725 } 726 727 void 728 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 729 { 730 static const struct { 731 int reg; 732 uint16_t val; 733 } dspcode[] = { 734 { 4, 0x01e1 }, 735 { 9, 0x0300 }, 736 { 0, 0 }, 737 }; 738 int i; 739 740 for (i = 0; dspcode[i].reg != 0; i++) 741 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 742 } 743 744 static void 745 brgphy_adc_bug(struct mii_softc *sc) 746 { 747 static const struct { 748 int reg; 749 uint16_t val; 750 } dspcode[] = { 751 { BRGPHY_MII_AUXCTL, 0x0c00 }, 752 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 753 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 754 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 755 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 756 { BRGPHY_MII_AUXCTL, 0x0400 }, 757 { 0, 0 }, 758 }; 759 int i; 760 761 for (i = 0; dspcode[i].reg != 0; i++) 762 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 763 } 764 765 static void 766 brgphy_5704_a0_bug(struct mii_softc *sc) 767 { 768 static const struct { 769 int reg; 770 uint16_t val; 771 } dspcode[] = { 772 { 0x1c, 0x8d68 }, 773 { 0x1c, 0x8d68 }, 774 { 0, 0 }, 775 }; 776 int i; 777 778 for (i = 0; dspcode[i].reg != 0; i++) 779 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 780 } 781 782 static void 783 brgphy_ber_bug(struct mii_softc *sc) 784 { 785 static const struct { 786 int reg; 787 uint16_t val; 788 } dspcode[] = { 789 { BRGPHY_MII_AUXCTL, 0x0c00 }, 790 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 791 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 792 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 793 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 794 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 795 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 796 { BRGPHY_MII_AUXCTL, 0x0400 }, 797 { 0, 0 }, 798 }; 799 int i; 800 801 for (i = 0; dspcode[i].reg != 0; i++) 802 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 803 } 804 805 /* BCM5701 A0/B0 CRC bug workaround */ 806 void 807 brgphy_crc_bug(struct mii_softc *sc) 808 { 809 static const struct { 810 int reg; 811 uint16_t val; 812 } dspcode[] = { 813 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 814 { 0x1c, 0x8c68 }, 815 { 0x1c, 0x8d68 }, 816 { 0x1c, 0x8c68 }, 817 { 0, 0 }, 818 }; 819 int i; 820 821 for (i = 0; dspcode[i].reg != 0; i++) 822 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 823 } 824 825 static void 826 brgphy_jumbo_settings(struct mii_softc *sc) 827 { 828 u_int32_t val; 829 830 /* Set Jumbo frame settings in the PHY. */ 831 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 832 /* Cannot do read-modify-write on the BCM5401 */ 833 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 834 } else { 835 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 836 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 837 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 838 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 839 } 840 841 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 842 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 843 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 844 } 845 846 static void 847 brgphy_eth_wirespeed(struct mii_softc *sc) 848 { 849 u_int32_t val; 850 851 /* Enable Ethernet@Wirespeed */ 852 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 853 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 854 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 855 (val | (1 << 15) | (1 << 4))); 856 } 857
Indexes created Sun Oct 19 16:10:00 GMT 2025