brgphy.c revision 1.40.8.1
1 /* $NetBSD: brgphy.c,v 1.40.8.1 2010/04/21 00:27:39 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.40.8.1 2010/04/21 00:27:39 matt Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 #include <prop/proplib.h> 79 80 #include <net/if.h> 81 #include <net/if_media.h> 82 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/mii/miidevs.h> 86 87 #include <dev/mii/brgphyreg.h> 88 #include <dev/pci/if_bgereg.h> 89 90 static int brgphymatch(device_t, cfdata_t, void *); 91 static void brgphyattach(device_t, device_t, void *); 92 93 struct brgphy_softc { 94 struct mii_softc sc_mii; 95 int sc_isbge; 96 int sc_isbnx; 97 int sc_bge_flags; 98 int sc_bnx_flags; 99 }; 100 101 CFATTACH_DECL_NEW(brgphy, sizeof(struct brgphy_softc), 102 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate); 103 104 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 105 static void brgphy_status(struct mii_softc *); 106 static int brgphy_mii_phy_auto(struct mii_softc *); 107 static void brgphy_loop(struct mii_softc *); 108 static void brgphy_reset(struct mii_softc *); 109 static void brgphy_bcm5401_dspcode(struct mii_softc *); 110 static void brgphy_bcm5411_dspcode(struct mii_softc *); 111 static void brgphy_bcm5421_dspcode(struct mii_softc *); 112 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 113 static void brgphy_adc_bug(struct mii_softc *); 114 static void brgphy_5704_a0_bug(struct mii_softc *); 115 static void brgphy_ber_bug(struct mii_softc *); 116 static void brgphy_crc_bug(struct mii_softc *); 117 118 119 static const struct mii_phy_funcs brgphy_funcs = { 120 brgphy_service, brgphy_status, brgphy_reset, 121 }; 122 123 static const struct mii_phydesc brgphys[] = { 124 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 125 MII_STR_BROADCOM_BCM5400 }, 126 127 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 128 MII_STR_BROADCOM_BCM5401 }, 129 130 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 131 MII_STR_BROADCOM_BCM5411 }, 132 133 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 134 MII_STR_BROADCOM_BCM5421 }, 135 136 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 137 MII_STR_BROADCOM_BCM54K2 }, 138 139 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 140 MII_STR_BROADCOM_BCM5462 }, 141 142 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 143 MII_STR_BROADCOM_BCM5701 }, 144 145 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 146 MII_STR_BROADCOM_BCM5703 }, 147 148 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 149 MII_STR_BROADCOM_BCM5704 }, 150 151 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 152 MII_STR_BROADCOM_BCM5705 }, 153 154 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 155 MII_STR_BROADCOM_BCM5714 }, 156 157 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 158 MII_STR_BROADCOM_BCM5750 }, 159 160 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 161 MII_STR_BROADCOM_BCM5752 }, 162 163 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 164 MII_STR_BROADCOM_BCM5780 }, 165 166 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 167 MII_STR_BROADCOM_BCM5708C }, 168 169 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 170 MII_STR_BROADCOM2_BCM5709C }, 171 172 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 173 MII_STR_BROADCOM2_BCM5709CAX }, 174 175 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 176 MII_STR_BROADCOM2_BCM5722 }, 177 178 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 179 MII_STR_BROADCOM2_BCM5755 }, 180 181 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 182 MII_STR_BROADCOM2_BCM5754 }, 183 184 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 185 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 186 187 { 0, 0, 188 NULL }, 189 }; 190 191 static int 192 brgphymatch(struct device *parent, struct cfdata *match, void *aux) 193 { 194 struct mii_attach_args *ma = aux; 195 196 if (mii_phy_match(ma, brgphys) != NULL) 197 return (10); 198 199 return (0); 200 } 201 202 static void 203 brgphyattach(struct device *parent, struct device *self, void *aux) 204 { 205 struct brgphy_softc *bsc = device_private(self); 206 struct mii_softc *sc = &bsc->sc_mii; 207 struct mii_attach_args *ma = aux; 208 struct mii_data *mii = ma->mii_data; 209 const struct mii_phydesc *mpd; 210 prop_dictionary_t dict; 211 212 mpd = mii_phy_match(ma, brgphys); 213 aprint_naive(": Media interface\n"); 214 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 215 216 sc->mii_dev = self; 217 sc->mii_inst = mii->mii_instance; 218 sc->mii_phy = ma->mii_phyno; 219 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 220 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 221 sc->mii_pdata = mii; 222 sc->mii_flags = ma->mii_flags; 223 sc->mii_anegticks = MII_ANEGTICKS; 224 sc->mii_funcs = &brgphy_funcs; 225 226 PHY_RESET(sc); 227 228 sc->mii_capabilities = 229 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 230 if (sc->mii_capabilities & BMSR_EXTSTAT) 231 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 232 233 aprint_normal_dev(self, ""); 234 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 235 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 236 aprint_error("no media present"); 237 else 238 mii_phy_add_media(sc); 239 aprint_normal("\n"); 240 241 if (device_is_a(parent, "bge")) { 242 bsc->sc_isbge = 1; 243 dict = device_properties(parent); 244 prop_dictionary_get_uint32(dict, "phyflags", 245 &bsc->sc_bge_flags); 246 } else if (device_is_a(parent, "bnx")) { 247 bsc->sc_isbnx = 1; 248 dict = device_properties(parent); 249 prop_dictionary_get_uint32(dict, "phyflags", 250 &bsc->sc_bnx_flags); 251 } 252 253 if (!pmf_device_register(self, NULL, mii_phy_resume)) 254 aprint_error_dev(self, "couldn't establish power handler\n"); 255 } 256 257 static int 258 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 259 { 260 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 261 int reg, speed, gig; 262 263 switch (cmd) { 264 case MII_POLLSTAT: 265 /* 266 * If we're not polling our PHY instance, just return. 267 */ 268 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 269 return (0); 270 break; 271 272 case MII_MEDIACHG: 273 /* 274 * If the media indicates a different PHY instance, 275 * isolate ourselves. 276 */ 277 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 278 reg = PHY_READ(sc, MII_BMCR); 279 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 280 return (0); 281 } 282 283 /* 284 * If the interface is not up, don't do anything. 285 */ 286 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 287 break; 288 289 PHY_RESET(sc); /* XXX hardware bug work-around */ 290 291 switch (IFM_SUBTYPE(ife->ifm_media)) { 292 case IFM_AUTO: 293 (void) brgphy_mii_phy_auto(sc); 294 break; 295 case IFM_1000_T: 296 speed = BMCR_S1000; 297 goto setit; 298 case IFM_100_TX: 299 speed = BMCR_S100; 300 goto setit; 301 case IFM_10_T: 302 speed = BMCR_S10; 303 setit: 304 brgphy_loop(sc); 305 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 306 speed |= BMCR_FDX; 307 gig = GTCR_ADV_1000TFDX; 308 } else { 309 gig = GTCR_ADV_1000THDX; 310 } 311 312 PHY_WRITE(sc, MII_100T2CR, 0); 313 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 314 PHY_WRITE(sc, MII_BMCR, speed); 315 316 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 317 break; 318 319 PHY_WRITE(sc, MII_100T2CR, gig); 320 PHY_WRITE(sc, MII_BMCR, 321 speed|BMCR_AUTOEN|BMCR_STARTNEG); 322 323 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 324 break; 325 326 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 327 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 328 PHY_WRITE(sc, MII_100T2CR, gig); 329 break; 330 default: 331 return (EINVAL); 332 } 333 break; 334 335 case MII_TICK: 336 /* 337 * If we're not currently selected, just return. 338 */ 339 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 340 return (0); 341 342 if (mii_phy_tick(sc) == EJUSTRETURN) 343 return (0); 344 break; 345 346 case MII_DOWN: 347 mii_phy_down(sc); 348 return (0); 349 } 350 351 /* Update the media status. */ 352 mii_phy_status(sc); 353 354 /* 355 * Callback if something changed. Note that we need to poke the DSP on 356 * the Broadcom PHYs if the media changes. 357 */ 358 if (sc->mii_media_active != mii->mii_media_active || 359 sc->mii_media_status != mii->mii_media_status || 360 cmd == MII_MEDIACHG) { 361 switch (sc->mii_mpd_model) { 362 case MII_MODEL_BROADCOM_BCM5400: 363 brgphy_bcm5401_dspcode(sc); 364 break; 365 case MII_MODEL_BROADCOM_BCM5401: 366 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 367 brgphy_bcm5401_dspcode(sc); 368 break; 369 case MII_MODEL_BROADCOM_BCM5411: 370 brgphy_bcm5411_dspcode(sc); 371 break; 372 } 373 } 374 375 /* Callback if something changed. */ 376 mii_phy_update(sc, cmd); 377 return (0); 378 } 379 380 static void 381 brgphy_status(struct mii_softc *sc) 382 { 383 struct mii_data *mii = sc->mii_pdata; 384 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 385 int bmcr, auxsts, gtsr; 386 387 mii->mii_media_status = IFM_AVALID; 388 mii->mii_media_active = IFM_ETHER; 389 390 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 391 392 if (auxsts & BRGPHY_AUXSTS_LINK) 393 mii->mii_media_status |= IFM_ACTIVE; 394 395 bmcr = PHY_READ(sc, MII_BMCR); 396 if (bmcr & BMCR_ISO) { 397 mii->mii_media_active |= IFM_NONE; 398 mii->mii_media_status = 0; 399 return; 400 } 401 402 if (bmcr & BMCR_LOOP) 403 mii->mii_media_active |= IFM_LOOP; 404 405 if (bmcr & BMCR_AUTOEN) { 406 /* 407 * The media status bits are only valid of autonegotiation 408 * has completed (or it's disabled). 409 */ 410 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 411 /* Erg, still trying, I guess... */ 412 mii->mii_media_active |= IFM_NONE; 413 return; 414 } 415 416 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 417 case BRGPHY_RES_1000FD: 418 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 419 gtsr = PHY_READ(sc, MII_100T2SR); 420 if (gtsr & GTSR_MS_RES) 421 mii->mii_media_active |= IFM_ETH_MASTER; 422 break; 423 424 case BRGPHY_RES_1000HD: 425 mii->mii_media_active |= IFM_1000_T; 426 gtsr = PHY_READ(sc, MII_100T2SR); 427 if (gtsr & GTSR_MS_RES) 428 mii->mii_media_active |= IFM_ETH_MASTER; 429 break; 430 431 case BRGPHY_RES_100FD: 432 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 433 break; 434 435 case BRGPHY_RES_100T4: 436 mii->mii_media_active |= IFM_100_T4; 437 break; 438 439 case BRGPHY_RES_100HD: 440 mii->mii_media_active |= IFM_100_TX; 441 break; 442 443 case BRGPHY_RES_10FD: 444 mii->mii_media_active |= IFM_10_T|IFM_FDX; 445 break; 446 447 case BRGPHY_RES_10HD: 448 mii->mii_media_active |= IFM_10_T; 449 break; 450 451 default: 452 mii->mii_media_active |= IFM_NONE; 453 mii->mii_media_status = 0; 454 } 455 if (mii->mii_media_active & IFM_FDX) 456 mii->mii_media_active |= mii_phy_flowstatus(sc); 457 } else 458 mii->mii_media_active = ife->ifm_media; 459 } 460 461 int 462 brgphy_mii_phy_auto(struct mii_softc *sc) 463 { 464 int anar, ktcr = 0; 465 466 brgphy_loop(sc); 467 PHY_RESET(sc); 468 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 469 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 470 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 471 PHY_WRITE(sc, MII_100T2CR, ktcr); 472 ktcr = PHY_READ(sc, MII_100T2CR); 473 DELAY(1000); 474 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 475 if (sc->mii_flags & MIIF_DOPAUSE) 476 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 477 478 PHY_WRITE(sc, MII_ANAR, anar); 479 DELAY(1000); 480 PHY_WRITE(sc, MII_BMCR, 481 BMCR_AUTOEN | BMCR_STARTNEG); 482 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 483 484 return (EJUSTRETURN); 485 } 486 487 void 488 brgphy_loop(struct mii_softc *sc) 489 { 490 u_int32_t bmsr; 491 int i; 492 493 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 494 for (i = 0; i < 15000; i++) { 495 bmsr = PHY_READ(sc, MII_BMSR); 496 if (!(bmsr & BMSR_LINK)) 497 break; 498 DELAY(10); 499 } 500 } 501 502 static void 503 brgphy_reset(struct mii_softc *sc) 504 { 505 struct brgphy_softc *bsc = (void *)sc; 506 507 mii_phy_reset(sc); 508 509 switch (sc->mii_mpd_model) { 510 case MII_MODEL_BROADCOM_BCM5400: 511 brgphy_bcm5401_dspcode(sc); 512 break; 513 case MII_MODEL_BROADCOM_BCM5401: 514 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 515 brgphy_bcm5401_dspcode(sc); 516 break; 517 case MII_MODEL_BROADCOM_BCM5411: 518 brgphy_bcm5411_dspcode(sc); 519 break; 520 case MII_MODEL_BROADCOM_BCM5421: 521 brgphy_bcm5421_dspcode(sc); 522 break; 523 case MII_MODEL_BROADCOM_BCM54K2: 524 brgphy_bcm54k2_dspcode(sc); 525 break; 526 } 527 528 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 529 if (bsc->sc_isbge != 0) { 530 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 531 532 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 533 brgphy_adc_bug(sc); 534 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 535 brgphy_5704_a0_bug(sc); 536 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 537 brgphy_ber_bug(sc); 538 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 539 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 540 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 541 0x000a); 542 543 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 544 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 545 0x110b); 546 PHY_WRITE(sc, BRGPHY_TEST1, 547 BRGPHY_TEST1_TRIM_EN | 0x4); 548 } else { 549 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 550 0x010b); 551 } 552 553 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 554 } 555 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 556 brgphy_crc_bug(sc); 557 558 #if 0 559 /* Set Jumbo frame settings in the PHY. */ 560 if (bsc->sc_bge_flags & BGE_JUMBO_CAP) 561 brgphy_jumbo_settings(sc); 562 #endif 563 564 /* Adjust output voltage */ 565 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 566 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 567 568 #if 0 569 /* Enable Ethernet@Wirespeed */ 570 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 571 brgphy_eth_wirespeed(sc); 572 573 /* Enable Link LED on Dell boxes */ 574 if (bsc->sc_bge_flags & BGE_NO_3LED) { 575 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 576 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 577 & ~BRGPHY_PHY_EXTCTL_3_LED); 578 } 579 #endif 580 } 581 #if 0 /* not yet */ 582 /* Handle any bnx (NetXtreme II) workarounds. */ 583 } else if (sc->sc_isbnx != 0) { 584 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 585 586 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 587 /* Store autoneg capabilities/results in digital block (Page 0) */ 588 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 589 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 590 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 591 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 592 593 /* Enable fiber mode and autodetection */ 594 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 595 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 596 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 597 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 598 599 /* Enable parallel detection */ 600 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 601 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 602 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 603 604 /* Advertise 2.5G support through next page during autoneg */ 605 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 606 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 607 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 608 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 609 610 /* Increase TX signal amplitude */ 611 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 612 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 613 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 614 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 615 BRGPHY_5708S_TX_MISC_PG5); 616 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 617 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 618 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 619 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 620 BRGPHY_5708S_DIG_PG0); 621 } 622 623 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 624 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 625 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 626 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 627 BRGPHY_5708S_TX_MISC_PG5); 628 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 629 bnx_sc->bnx_port_hw_cfg & 630 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 631 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 632 BRGPHY_5708S_DIG_PG0); 633 } 634 } else { 635 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 636 brgphy_ber_bug(sc); 637 638 /* Set Jumbo frame settings in the PHY. */ 639 brgphy_jumbo_settings(sc); 640 641 /* Enable Ethernet@Wirespeed */ 642 brgphy_eth_wirespeed(sc); 643 } 644 } 645 #endif 646 } 647 } 648 649 /* Turn off tap power management on 5401. */ 650 static void 651 brgphy_bcm5401_dspcode(struct mii_softc *sc) 652 { 653 static const struct { 654 int reg; 655 uint16_t val; 656 } dspcode[] = { 657 { BRGPHY_MII_AUXCTL, 0x0c20 }, 658 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 659 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 660 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 661 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 662 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 663 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 664 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 665 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 666 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 667 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 668 { 0, 0 }, 669 }; 670 int i; 671 672 for (i = 0; dspcode[i].reg != 0; i++) 673 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 674 delay(40); 675 } 676 677 static void 678 brgphy_bcm5411_dspcode(struct mii_softc *sc) 679 { 680 static const struct { 681 int reg; 682 uint16_t val; 683 } dspcode[] = { 684 { 0x1c, 0x8c23 }, 685 { 0x1c, 0x8ca3 }, 686 { 0x1c, 0x8c23 }, 687 { 0, 0 }, 688 }; 689 int i; 690 691 for (i = 0; dspcode[i].reg != 0; i++) 692 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 693 } 694 695 void 696 brgphy_bcm5421_dspcode(struct mii_softc *sc) 697 { 698 uint16_t data; 699 700 /* Set Class A mode */ 701 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 702 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 703 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 704 705 /* Set FFE gamma override to -0.125 */ 706 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 707 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 708 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 709 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 710 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 711 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 712 } 713 714 void 715 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 716 { 717 static const struct { 718 int reg; 719 uint16_t val; 720 } dspcode[] = { 721 { 4, 0x01e1 }, 722 { 9, 0x0300 }, 723 { 0, 0 }, 724 }; 725 int i; 726 727 for (i = 0; dspcode[i].reg != 0; i++) 728 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 729 } 730 731 static void 732 brgphy_adc_bug(struct mii_softc *sc) 733 { 734 static const struct { 735 int reg; 736 uint16_t val; 737 } dspcode[] = { 738 { BRGPHY_MII_AUXCTL, 0x0c00 }, 739 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 740 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 741 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 742 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 743 { BRGPHY_MII_AUXCTL, 0x0400 }, 744 { 0, 0 }, 745 }; 746 int i; 747 748 for (i = 0; dspcode[i].reg != 0; i++) 749 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 750 } 751 752 static void 753 brgphy_5704_a0_bug(struct mii_softc *sc) 754 { 755 static const struct { 756 int reg; 757 uint16_t val; 758 } dspcode[] = { 759 { 0x1c, 0x8d68 }, 760 { 0x1c, 0x8d68 }, 761 { 0, 0 }, 762 }; 763 int i; 764 765 for (i = 0; dspcode[i].reg != 0; i++) 766 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 767 } 768 769 static void 770 brgphy_ber_bug(struct mii_softc *sc) 771 { 772 static const struct { 773 int reg; 774 uint16_t val; 775 } dspcode[] = { 776 { BRGPHY_MII_AUXCTL, 0x0c00 }, 777 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 778 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 779 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 780 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 781 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 782 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 783 { BRGPHY_MII_AUXCTL, 0x0400 }, 784 { 0, 0 }, 785 }; 786 int i; 787 788 for (i = 0; dspcode[i].reg != 0; i++) 789 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 790 } 791 792 /* BCM5701 A0/B0 CRC bug workaround */ 793 void 794 brgphy_crc_bug(struct mii_softc *sc) 795 { 796 static const struct { 797 int reg; 798 uint16_t val; 799 } dspcode[] = { 800 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 801 { 0x1c, 0x8c68 }, 802 { 0x1c, 0x8d68 }, 803 { 0x1c, 0x8c68 }, 804 { 0, 0 }, 805 }; 806 int i; 807 808 for (i = 0; dspcode[i].reg != 0; i++) 809 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 810 } 811
Indexes created Mon Oct 20 11:09:49 GMT 2025