brgphy.c revision 1.46
1 /* $NetBSD: brgphy.c,v 1.46 2009/05/12 14:31:27 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.46 2009/05/12 14:31:27 cegger Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 #include <prop/proplib.h> 79 80 #include <net/if.h> 81 #include <net/if_media.h> 82 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/mii/miidevs.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/if_bgereg.h> 89 #if 0 90 #include <dev/pci/if_bnxreg.h> 91 #endif 92 93 static int brgphymatch(device_t, cfdata_t, void *); 94 static void brgphyattach(device_t, device_t, void *); 95 96 struct brgphy_softc { 97 struct mii_softc sc_mii; 98 int sc_isbge; 99 int sc_isbnx; 100 int sc_bge_flags; 101 int sc_bnx_flags; 102 }; 103 104 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 105 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 106 DVF_DETACH_SHUTDOWN); 107 108 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 109 static void brgphy_status(struct mii_softc *); 110 static int brgphy_mii_phy_auto(struct mii_softc *); 111 static void brgphy_loop(struct mii_softc *); 112 static void brgphy_reset(struct mii_softc *); 113 static void brgphy_bcm5401_dspcode(struct mii_softc *); 114 static void brgphy_bcm5411_dspcode(struct mii_softc *); 115 static void brgphy_bcm5421_dspcode(struct mii_softc *); 116 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 117 static void brgphy_adc_bug(struct mii_softc *); 118 static void brgphy_5704_a0_bug(struct mii_softc *); 119 static void brgphy_ber_bug(struct mii_softc *); 120 static void brgphy_crc_bug(struct mii_softc *); 121 122 123 static const struct mii_phy_funcs brgphy_funcs = { 124 brgphy_service, brgphy_status, brgphy_reset, 125 }; 126 127 static const struct mii_phydesc brgphys[] = { 128 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 129 MII_STR_BROADCOM_BCM5400 }, 130 131 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 132 MII_STR_BROADCOM_BCM5401 }, 133 134 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 135 MII_STR_BROADCOM_BCM5411 }, 136 137 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 138 MII_STR_BROADCOM_BCM5421 }, 139 140 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 141 MII_STR_BROADCOM_BCM54K2 }, 142 143 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 144 MII_STR_BROADCOM_BCM5462 }, 145 146 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 147 MII_STR_BROADCOM_BCM5701 }, 148 149 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 150 MII_STR_BROADCOM_BCM5703 }, 151 152 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 153 MII_STR_BROADCOM_BCM5704 }, 154 155 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 156 MII_STR_BROADCOM_BCM5705 }, 157 158 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 159 MII_STR_BROADCOM_BCM5714 }, 160 161 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 162 MII_STR_BROADCOM_BCM5750 }, 163 164 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 165 MII_STR_BROADCOM_BCM5752 }, 166 167 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 168 MII_STR_BROADCOM_BCM5780 }, 169 170 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 171 MII_STR_BROADCOM_BCM5708C }, 172 173 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 174 MII_STR_BROADCOM2_BCM5722 }, 175 176 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 177 MII_STR_BROADCOM2_BCM5755 }, 178 179 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 180 MII_STR_BROADCOM2_BCM5754 }, 181 182 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 183 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 184 185 { 0, 0, 186 NULL }, 187 }; 188 189 static int 190 brgphymatch(device_t parent, cfdata_t match, 191 void *aux) 192 { 193 struct mii_attach_args *ma = aux; 194 195 if (mii_phy_match(ma, brgphys) != NULL) 196 return (10); 197 198 return (0); 199 } 200 201 static void 202 brgphyattach(device_t parent, device_t self, void *aux) 203 { 204 struct brgphy_softc *bsc = device_private(self); 205 struct mii_softc *sc = &bsc->sc_mii; 206 struct mii_attach_args *ma = aux; 207 struct mii_data *mii = ma->mii_data; 208 const struct mii_phydesc *mpd; 209 prop_dictionary_t dict; 210 const char *devname; 211 212 mpd = mii_phy_match(ma, brgphys); 213 aprint_naive(": Media interface\n"); 214 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 215 216 sc->mii_dev = self; 217 sc->mii_inst = mii->mii_instance; 218 sc->mii_phy = ma->mii_phyno; 219 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 220 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 221 sc->mii_pdata = mii; 222 sc->mii_flags = ma->mii_flags; 223 sc->mii_anegticks = MII_ANEGTICKS; 224 sc->mii_funcs = &brgphy_funcs; 225 226 PHY_RESET(sc); 227 228 sc->mii_capabilities = 229 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 230 if (sc->mii_capabilities & BMSR_EXTSTAT) 231 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 232 233 aprint_normal_dev(self, ""); 234 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 235 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 236 aprint_error("no media present"); 237 else 238 mii_phy_add_media(sc); 239 aprint_normal("\n"); 240 241 parent = device_parent(sc->mii_dev); 242 devname = parent->dv_cfdriver->cd_name; 243 if (strcmp(devname, "bge") == 0) { 244 bsc->sc_isbge = 1; 245 dict = device_properties(parent); 246 prop_dictionary_get_uint32(dict, "phyflags", 247 &bsc->sc_bge_flags); 248 } else if (strcmp(devname, "bnx") == 0) { 249 bsc->sc_isbnx = 1; 250 dict = device_properties(parent); 251 prop_dictionary_get_uint32(dict, "phyflags", 252 &bsc->sc_bnx_flags); 253 } 254 } 255 256 static int 257 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 258 { 259 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 260 int reg, speed, gig; 261 262 switch (cmd) { 263 case MII_POLLSTAT: 264 /* 265 * If we're not polling our PHY instance, just return. 266 */ 267 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 268 return (0); 269 break; 270 271 case MII_MEDIACHG: 272 /* 273 * If the media indicates a different PHY instance, 274 * isolate ourselves. 275 */ 276 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 277 reg = PHY_READ(sc, MII_BMCR); 278 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 279 return (0); 280 } 281 282 /* 283 * If the interface is not up, don't do anything. 284 */ 285 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 286 break; 287 288 PHY_RESET(sc); /* XXX hardware bug work-around */ 289 290 switch (IFM_SUBTYPE(ife->ifm_media)) { 291 case IFM_AUTO: 292 (void) brgphy_mii_phy_auto(sc); 293 break; 294 case IFM_1000_T: 295 speed = BMCR_S1000; 296 goto setit; 297 case IFM_100_TX: 298 speed = BMCR_S100; 299 goto setit; 300 case IFM_10_T: 301 speed = BMCR_S10; 302 setit: 303 brgphy_loop(sc); 304 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 305 speed |= BMCR_FDX; 306 gig = GTCR_ADV_1000TFDX; 307 } else { 308 gig = GTCR_ADV_1000THDX; 309 } 310 311 PHY_WRITE(sc, MII_100T2CR, 0); 312 PHY_WRITE(sc, MII_BMCR, speed); 313 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 314 315 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 316 break; 317 318 PHY_WRITE(sc, MII_100T2CR, gig); 319 PHY_WRITE(sc, MII_BMCR, 320 speed|BMCR_AUTOEN|BMCR_STARTNEG); 321 322 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 323 break; 324 325 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 326 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 327 PHY_WRITE(sc, MII_100T2CR, gig); 328 break; 329 default: 330 return (EINVAL); 331 } 332 break; 333 334 case MII_TICK: 335 /* 336 * If we're not currently selected, just return. 337 */ 338 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 339 return (0); 340 341 if (mii_phy_tick(sc) == EJUSTRETURN) 342 return (0); 343 break; 344 345 case MII_DOWN: 346 mii_phy_down(sc); 347 return (0); 348 } 349 350 /* Update the media status. */ 351 mii_phy_status(sc); 352 353 /* 354 * Callback if something changed. Note that we need to poke the DSP on 355 * the Broadcom PHYs if the media changes. 356 */ 357 if (sc->mii_media_active != mii->mii_media_active || 358 sc->mii_media_status != mii->mii_media_status || 359 cmd == MII_MEDIACHG) { 360 switch (sc->mii_mpd_model) { 361 case MII_MODEL_BROADCOM_BCM5400: 362 brgphy_bcm5401_dspcode(sc); 363 break; 364 case MII_MODEL_BROADCOM_BCM5401: 365 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 366 brgphy_bcm5401_dspcode(sc); 367 break; 368 case MII_MODEL_BROADCOM_BCM5411: 369 brgphy_bcm5411_dspcode(sc); 370 break; 371 } 372 } 373 374 /* Callback if something changed. */ 375 mii_phy_update(sc, cmd); 376 return (0); 377 } 378 379 static void 380 brgphy_status(struct mii_softc *sc) 381 { 382 struct mii_data *mii = sc->mii_pdata; 383 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 384 int bmcr, auxsts, gtsr; 385 386 mii->mii_media_status = IFM_AVALID; 387 mii->mii_media_active = IFM_ETHER; 388 389 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 390 391 if (auxsts & BRGPHY_AUXSTS_LINK) 392 mii->mii_media_status |= IFM_ACTIVE; 393 394 bmcr = PHY_READ(sc, MII_BMCR); 395 if (bmcr & BMCR_ISO) { 396 mii->mii_media_active |= IFM_NONE; 397 mii->mii_media_status = 0; 398 return; 399 } 400 401 if (bmcr & BMCR_LOOP) 402 mii->mii_media_active |= IFM_LOOP; 403 404 if (bmcr & BMCR_AUTOEN) { 405 /* 406 * The media status bits are only valid of autonegotiation 407 * has completed (or it's disabled). 408 */ 409 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 410 /* Erg, still trying, I guess... */ 411 mii->mii_media_active |= IFM_NONE; 412 return; 413 } 414 415 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 416 case BRGPHY_RES_1000FD: 417 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 418 gtsr = PHY_READ(sc, MII_100T2SR); 419 if (gtsr & GTSR_MS_RES) 420 mii->mii_media_active |= IFM_ETH_MASTER; 421 break; 422 423 case BRGPHY_RES_1000HD: 424 mii->mii_media_active |= IFM_1000_T; 425 gtsr = PHY_READ(sc, MII_100T2SR); 426 if (gtsr & GTSR_MS_RES) 427 mii->mii_media_active |= IFM_ETH_MASTER; 428 break; 429 430 case BRGPHY_RES_100FD: 431 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 432 break; 433 434 case BRGPHY_RES_100T4: 435 mii->mii_media_active |= IFM_100_T4; 436 break; 437 438 case BRGPHY_RES_100HD: 439 mii->mii_media_active |= IFM_100_TX; 440 break; 441 442 case BRGPHY_RES_10FD: 443 mii->mii_media_active |= IFM_10_T|IFM_FDX; 444 break; 445 446 case BRGPHY_RES_10HD: 447 mii->mii_media_active |= IFM_10_T; 448 break; 449 450 default: 451 mii->mii_media_active |= IFM_NONE; 452 mii->mii_media_status = 0; 453 } 454 if (mii->mii_media_active & IFM_FDX) 455 mii->mii_media_active |= mii_phy_flowstatus(sc); 456 } else 457 mii->mii_media_active = ife->ifm_media; 458 } 459 460 int 461 brgphy_mii_phy_auto(struct mii_softc *sc) 462 { 463 int anar, ktcr = 0; 464 465 brgphy_loop(sc); 466 PHY_RESET(sc); 467 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 468 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 469 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 470 PHY_WRITE(sc, MII_100T2CR, ktcr); 471 ktcr = PHY_READ(sc, MII_100T2CR); 472 DELAY(1000); 473 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 474 if (sc->mii_flags & MIIF_DOPAUSE) 475 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 476 477 PHY_WRITE(sc, MII_ANAR, anar); 478 DELAY(1000); 479 PHY_WRITE(sc, MII_BMCR, 480 BMCR_AUTOEN | BMCR_STARTNEG); 481 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 482 483 return (EJUSTRETURN); 484 } 485 486 void 487 brgphy_loop(struct mii_softc *sc) 488 { 489 u_int32_t bmsr; 490 int i; 491 492 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 493 for (i = 0; i < 15000; i++) { 494 bmsr = PHY_READ(sc, MII_BMSR); 495 if (!(bmsr & BMSR_LINK)) 496 break; 497 DELAY(10); 498 } 499 } 500 501 static void 502 brgphy_reset(struct mii_softc *sc) 503 { 504 struct brgphy_softc *bsc = (void *)sc; 505 506 mii_phy_reset(sc); 507 508 switch (sc->mii_mpd_model) { 509 case MII_MODEL_BROADCOM_BCM5400: 510 brgphy_bcm5401_dspcode(sc); 511 break; 512 case MII_MODEL_BROADCOM_BCM5401: 513 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 514 brgphy_bcm5401_dspcode(sc); 515 break; 516 case MII_MODEL_BROADCOM_BCM5411: 517 brgphy_bcm5411_dspcode(sc); 518 break; 519 case MII_MODEL_BROADCOM_BCM5421: 520 brgphy_bcm5421_dspcode(sc); 521 break; 522 case MII_MODEL_BROADCOM_BCM54K2: 523 brgphy_bcm54k2_dspcode(sc); 524 break; 525 } 526 527 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 528 if (bsc->sc_isbge != 0) { 529 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 530 531 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 532 brgphy_adc_bug(sc); 533 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 534 brgphy_5704_a0_bug(sc); 535 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 536 brgphy_ber_bug(sc); 537 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 538 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 539 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 540 0x000a); 541 542 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 543 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 544 0x110b); 545 PHY_WRITE(sc, BRGPHY_TEST1, 546 BRGPHY_TEST1_TRIM_EN | 0x4); 547 } else { 548 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 549 0x010b); 550 } 551 552 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 553 } 554 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 555 brgphy_crc_bug(sc); 556 557 #if 0 558 /* Set Jumbo frame settings in the PHY. */ 559 if (bsc->sc_bge_flags & BGE_JUMBO_CAP) 560 brgphy_jumbo_settings(sc); 561 #endif 562 563 /* Adjust output voltage */ 564 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 565 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 566 567 #if 0 568 /* Enable Ethernet@Wirespeed */ 569 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 570 brgphy_eth_wirespeed(sc); 571 572 /* Enable Link LED on Dell boxes */ 573 if (bsc->sc_bge_flags & BGE_NO_3LED) { 574 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 575 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 576 & ~BRGPHY_PHY_EXTCTL_3_LED); 577 } 578 #endif 579 } 580 #if 0 /* not yet */ 581 /* Handle any bnx (NetXtreme II) workarounds. */ 582 } else if (sc->sc_isbnx != 0) { 583 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 584 585 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 586 /* Store autoneg capabilities/results in digital block (Page 0) */ 587 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 588 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 589 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 590 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 591 592 /* Enable fiber mode and autodetection */ 593 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 594 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 595 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 596 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 597 598 /* Enable parallel detection */ 599 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 600 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 601 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 602 603 /* Advertise 2.5G support through next page during autoneg */ 604 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 605 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 606 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 607 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 608 609 /* Increase TX signal amplitude */ 610 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 611 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 612 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 613 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 614 BRGPHY_5708S_TX_MISC_PG5); 615 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 616 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 617 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 618 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 619 BRGPHY_5708S_DIG_PG0); 620 } 621 622 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 623 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 624 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 625 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 626 BRGPHY_5708S_TX_MISC_PG5); 627 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 628 bnx_sc->bnx_port_hw_cfg & 629 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 630 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 631 BRGPHY_5708S_DIG_PG0); 632 } 633 } else { 634 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 635 brgphy_ber_bug(sc); 636 637 /* Set Jumbo frame settings in the PHY. */ 638 brgphy_jumbo_settings(sc); 639 640 /* Enable Ethernet@Wirespeed */ 641 brgphy_eth_wirespeed(sc); 642 } 643 } 644 #endif 645 } 646 } 647 648 /* Turn off tap power management on 5401. */ 649 static void 650 brgphy_bcm5401_dspcode(struct mii_softc *sc) 651 { 652 static const struct { 653 int reg; 654 uint16_t val; 655 } dspcode[] = { 656 { BRGPHY_MII_AUXCTL, 0x0c20 }, 657 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 658 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 659 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 660 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 661 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 662 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 663 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 664 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 665 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 666 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 667 { 0, 0 }, 668 }; 669 int i; 670 671 for (i = 0; dspcode[i].reg != 0; i++) 672 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 673 delay(40); 674 } 675 676 static void 677 brgphy_bcm5411_dspcode(struct mii_softc *sc) 678 { 679 static const struct { 680 int reg; 681 uint16_t val; 682 } dspcode[] = { 683 { 0x1c, 0x8c23 }, 684 { 0x1c, 0x8ca3 }, 685 { 0x1c, 0x8c23 }, 686 { 0, 0 }, 687 }; 688 int i; 689 690 for (i = 0; dspcode[i].reg != 0; i++) 691 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 692 } 693 694 void 695 brgphy_bcm5421_dspcode(struct mii_softc *sc) 696 { 697 uint16_t data; 698 699 /* Set Class A mode */ 700 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 701 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 702 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 703 704 /* Set FFE gamma override to -0.125 */ 705 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 706 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 707 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 708 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 709 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 710 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 711 } 712 713 void 714 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 715 { 716 static const struct { 717 int reg; 718 uint16_t val; 719 } dspcode[] = { 720 { 4, 0x01e1 }, 721 { 9, 0x0300 }, 722 { 0, 0 }, 723 }; 724 int i; 725 726 for (i = 0; dspcode[i].reg != 0; i++) 727 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 728 } 729 730 static void 731 brgphy_adc_bug(struct mii_softc *sc) 732 { 733 static const struct { 734 int reg; 735 uint16_t val; 736 } dspcode[] = { 737 { BRGPHY_MII_AUXCTL, 0x0c00 }, 738 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 739 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 740 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 741 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 742 { BRGPHY_MII_AUXCTL, 0x0400 }, 743 { 0, 0 }, 744 }; 745 int i; 746 747 for (i = 0; dspcode[i].reg != 0; i++) 748 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 749 } 750 751 static void 752 brgphy_5704_a0_bug(struct mii_softc *sc) 753 { 754 static const struct { 755 int reg; 756 uint16_t val; 757 } dspcode[] = { 758 { 0x1c, 0x8d68 }, 759 { 0x1c, 0x8d68 }, 760 { 0, 0 }, 761 }; 762 int i; 763 764 for (i = 0; dspcode[i].reg != 0; i++) 765 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 766 } 767 768 static void 769 brgphy_ber_bug(struct mii_softc *sc) 770 { 771 static const struct { 772 int reg; 773 uint16_t val; 774 } dspcode[] = { 775 { BRGPHY_MII_AUXCTL, 0x0c00 }, 776 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 777 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 778 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 779 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 780 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 781 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 782 { BRGPHY_MII_AUXCTL, 0x0400 }, 783 { 0, 0 }, 784 }; 785 int i; 786 787 for (i = 0; dspcode[i].reg != 0; i++) 788 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 789 } 790 791 /* BCM5701 A0/B0 CRC bug workaround */ 792 void 793 brgphy_crc_bug(struct mii_softc *sc) 794 { 795 static const struct { 796 int reg; 797 uint16_t val; 798 } dspcode[] = { 799 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 800 { 0x1c, 0x8c68 }, 801 { 0x1c, 0x8d68 }, 802 { 0x1c, 0x8c68 }, 803 { 0, 0 }, 804 }; 805 int i; 806 807 for (i = 0; dspcode[i].reg != 0; i++) 808 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 809 } 810
Indexes created Sun Sep 28 16:09:52 GMT 2025