brgphy.c revision 1.47
1 /* $NetBSD: brgphy.c,v 1.47 2009/06/17 15:42:00 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Manuel Bouyer. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * driver for the Broadcom BCM5400 Gig-E PHY. 64 * 65 * Programming information for this PHY was gleaned from FreeBSD 66 * (they were apparently able to get a datasheet from Broadcom). 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.47 2009/06/17 15:42:00 tsutsui Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/socket.h> 77 #include <sys/errno.h> 78 #include <prop/proplib.h> 79 80 #include <net/if.h> 81 #include <net/if_media.h> 82 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/mii/miidevs.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/if_bgereg.h> 89 #if 0 90 #include <dev/pci/if_bnxreg.h> 91 #endif 92 93 static int brgphymatch(device_t, cfdata_t, void *); 94 static void brgphyattach(device_t, device_t, void *); 95 96 struct brgphy_softc { 97 struct mii_softc sc_mii; 98 int sc_isbge; 99 int sc_isbnx; 100 int sc_bge_flags; 101 int sc_bnx_flags; 102 }; 103 104 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 105 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 106 DVF_DETACH_SHUTDOWN); 107 108 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 109 static void brgphy_status(struct mii_softc *); 110 static int brgphy_mii_phy_auto(struct mii_softc *); 111 static void brgphy_loop(struct mii_softc *); 112 static void brgphy_reset(struct mii_softc *); 113 static void brgphy_bcm5401_dspcode(struct mii_softc *); 114 static void brgphy_bcm5411_dspcode(struct mii_softc *); 115 static void brgphy_bcm5421_dspcode(struct mii_softc *); 116 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 117 static void brgphy_adc_bug(struct mii_softc *); 118 static void brgphy_5704_a0_bug(struct mii_softc *); 119 static void brgphy_ber_bug(struct mii_softc *); 120 static void brgphy_crc_bug(struct mii_softc *); 121 122 123 static const struct mii_phy_funcs brgphy_funcs = { 124 brgphy_service, brgphy_status, brgphy_reset, 125 }; 126 127 static const struct mii_phydesc brgphys[] = { 128 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 129 MII_STR_BROADCOM_BCM5400 }, 130 131 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 132 MII_STR_BROADCOM_BCM5401 }, 133 134 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 135 MII_STR_BROADCOM_BCM5411 }, 136 137 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 138 MII_STR_BROADCOM_BCM5421 }, 139 140 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 141 MII_STR_BROADCOM_BCM54K2 }, 142 143 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 144 MII_STR_BROADCOM_BCM5462 }, 145 146 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 147 MII_STR_BROADCOM_BCM5701 }, 148 149 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 150 MII_STR_BROADCOM_BCM5703 }, 151 152 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 153 MII_STR_BROADCOM_BCM5704 }, 154 155 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 156 MII_STR_BROADCOM_BCM5705 }, 157 158 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 159 MII_STR_BROADCOM_BCM5714 }, 160 161 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 162 MII_STR_BROADCOM_BCM5750 }, 163 164 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 165 MII_STR_BROADCOM_BCM5752 }, 166 167 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 168 MII_STR_BROADCOM_BCM5780 }, 169 170 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 171 MII_STR_BROADCOM_BCM5708C }, 172 173 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 174 MII_STR_BROADCOM2_BCM5722 }, 175 176 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 177 MII_STR_BROADCOM2_BCM5755 }, 178 179 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 180 MII_STR_BROADCOM2_BCM5754 }, 181 182 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 183 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 184 185 { 0, 0, 186 NULL }, 187 }; 188 189 static int 190 brgphymatch(device_t parent, cfdata_t match, 191 void *aux) 192 { 193 struct mii_attach_args *ma = aux; 194 195 if (mii_phy_match(ma, brgphys) != NULL) 196 return (10); 197 198 return (0); 199 } 200 201 static void 202 brgphyattach(device_t parent, device_t self, void *aux) 203 { 204 struct brgphy_softc *bsc = device_private(self); 205 struct mii_softc *sc = &bsc->sc_mii; 206 struct mii_attach_args *ma = aux; 207 struct mii_data *mii = ma->mii_data; 208 const struct mii_phydesc *mpd; 209 prop_dictionary_t dict; 210 211 mpd = mii_phy_match(ma, brgphys); 212 aprint_naive(": Media interface\n"); 213 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 214 215 sc->mii_dev = self; 216 sc->mii_inst = mii->mii_instance; 217 sc->mii_phy = ma->mii_phyno; 218 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 219 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 220 sc->mii_pdata = mii; 221 sc->mii_flags = ma->mii_flags; 222 sc->mii_anegticks = MII_ANEGTICKS; 223 sc->mii_funcs = &brgphy_funcs; 224 225 PHY_RESET(sc); 226 227 sc->mii_capabilities = 228 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 229 if (sc->mii_capabilities & BMSR_EXTSTAT) 230 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 231 232 aprint_normal_dev(self, ""); 233 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 234 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 235 aprint_error("no media present"); 236 else 237 mii_phy_add_media(sc); 238 aprint_normal("\n"); 239 240 if (device_is_a(parent, "bge")) { 241 bsc->sc_isbge = 1; 242 dict = device_properties(parent); 243 prop_dictionary_get_uint32(dict, "phyflags", 244 &bsc->sc_bge_flags); 245 } else if (device_is_a(parent, "bnx")) { 246 bsc->sc_isbnx = 1; 247 dict = device_properties(parent); 248 prop_dictionary_get_uint32(dict, "phyflags", 249 &bsc->sc_bnx_flags); 250 } 251 } 252 253 static int 254 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 255 { 256 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 257 int reg, speed, gig; 258 259 switch (cmd) { 260 case MII_POLLSTAT: 261 /* 262 * If we're not polling our PHY instance, just return. 263 */ 264 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 265 return (0); 266 break; 267 268 case MII_MEDIACHG: 269 /* 270 * If the media indicates a different PHY instance, 271 * isolate ourselves. 272 */ 273 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 274 reg = PHY_READ(sc, MII_BMCR); 275 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 276 return (0); 277 } 278 279 /* 280 * If the interface is not up, don't do anything. 281 */ 282 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 283 break; 284 285 PHY_RESET(sc); /* XXX hardware bug work-around */ 286 287 switch (IFM_SUBTYPE(ife->ifm_media)) { 288 case IFM_AUTO: 289 (void) brgphy_mii_phy_auto(sc); 290 break; 291 case IFM_1000_T: 292 speed = BMCR_S1000; 293 goto setit; 294 case IFM_100_TX: 295 speed = BMCR_S100; 296 goto setit; 297 case IFM_10_T: 298 speed = BMCR_S10; 299 setit: 300 brgphy_loop(sc); 301 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 302 speed |= BMCR_FDX; 303 gig = GTCR_ADV_1000TFDX; 304 } else { 305 gig = GTCR_ADV_1000THDX; 306 } 307 308 PHY_WRITE(sc, MII_100T2CR, 0); 309 PHY_WRITE(sc, MII_BMCR, speed); 310 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 311 312 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 313 break; 314 315 PHY_WRITE(sc, MII_100T2CR, gig); 316 PHY_WRITE(sc, MII_BMCR, 317 speed|BMCR_AUTOEN|BMCR_STARTNEG); 318 319 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 320 break; 321 322 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 323 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 324 PHY_WRITE(sc, MII_100T2CR, gig); 325 break; 326 default: 327 return (EINVAL); 328 } 329 break; 330 331 case MII_TICK: 332 /* 333 * If we're not currently selected, just return. 334 */ 335 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 336 return (0); 337 338 if (mii_phy_tick(sc) == EJUSTRETURN) 339 return (0); 340 break; 341 342 case MII_DOWN: 343 mii_phy_down(sc); 344 return (0); 345 } 346 347 /* Update the media status. */ 348 mii_phy_status(sc); 349 350 /* 351 * Callback if something changed. Note that we need to poke the DSP on 352 * the Broadcom PHYs if the media changes. 353 */ 354 if (sc->mii_media_active != mii->mii_media_active || 355 sc->mii_media_status != mii->mii_media_status || 356 cmd == MII_MEDIACHG) { 357 switch (sc->mii_mpd_model) { 358 case MII_MODEL_BROADCOM_BCM5400: 359 brgphy_bcm5401_dspcode(sc); 360 break; 361 case MII_MODEL_BROADCOM_BCM5401: 362 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 363 brgphy_bcm5401_dspcode(sc); 364 break; 365 case MII_MODEL_BROADCOM_BCM5411: 366 brgphy_bcm5411_dspcode(sc); 367 break; 368 } 369 } 370 371 /* Callback if something changed. */ 372 mii_phy_update(sc, cmd); 373 return (0); 374 } 375 376 static void 377 brgphy_status(struct mii_softc *sc) 378 { 379 struct mii_data *mii = sc->mii_pdata; 380 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 381 int bmcr, auxsts, gtsr; 382 383 mii->mii_media_status = IFM_AVALID; 384 mii->mii_media_active = IFM_ETHER; 385 386 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 387 388 if (auxsts & BRGPHY_AUXSTS_LINK) 389 mii->mii_media_status |= IFM_ACTIVE; 390 391 bmcr = PHY_READ(sc, MII_BMCR); 392 if (bmcr & BMCR_ISO) { 393 mii->mii_media_active |= IFM_NONE; 394 mii->mii_media_status = 0; 395 return; 396 } 397 398 if (bmcr & BMCR_LOOP) 399 mii->mii_media_active |= IFM_LOOP; 400 401 if (bmcr & BMCR_AUTOEN) { 402 /* 403 * The media status bits are only valid of autonegotiation 404 * has completed (or it's disabled). 405 */ 406 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 407 /* Erg, still trying, I guess... */ 408 mii->mii_media_active |= IFM_NONE; 409 return; 410 } 411 412 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 413 case BRGPHY_RES_1000FD: 414 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 415 gtsr = PHY_READ(sc, MII_100T2SR); 416 if (gtsr & GTSR_MS_RES) 417 mii->mii_media_active |= IFM_ETH_MASTER; 418 break; 419 420 case BRGPHY_RES_1000HD: 421 mii->mii_media_active |= IFM_1000_T; 422 gtsr = PHY_READ(sc, MII_100T2SR); 423 if (gtsr & GTSR_MS_RES) 424 mii->mii_media_active |= IFM_ETH_MASTER; 425 break; 426 427 case BRGPHY_RES_100FD: 428 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 429 break; 430 431 case BRGPHY_RES_100T4: 432 mii->mii_media_active |= IFM_100_T4; 433 break; 434 435 case BRGPHY_RES_100HD: 436 mii->mii_media_active |= IFM_100_TX; 437 break; 438 439 case BRGPHY_RES_10FD: 440 mii->mii_media_active |= IFM_10_T|IFM_FDX; 441 break; 442 443 case BRGPHY_RES_10HD: 444 mii->mii_media_active |= IFM_10_T; 445 break; 446 447 default: 448 mii->mii_media_active |= IFM_NONE; 449 mii->mii_media_status = 0; 450 } 451 if (mii->mii_media_active & IFM_FDX) 452 mii->mii_media_active |= mii_phy_flowstatus(sc); 453 } else 454 mii->mii_media_active = ife->ifm_media; 455 } 456 457 int 458 brgphy_mii_phy_auto(struct mii_softc *sc) 459 { 460 int anar, ktcr = 0; 461 462 brgphy_loop(sc); 463 PHY_RESET(sc); 464 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 465 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 466 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 467 PHY_WRITE(sc, MII_100T2CR, ktcr); 468 ktcr = PHY_READ(sc, MII_100T2CR); 469 DELAY(1000); 470 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 471 if (sc->mii_flags & MIIF_DOPAUSE) 472 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 473 474 PHY_WRITE(sc, MII_ANAR, anar); 475 DELAY(1000); 476 PHY_WRITE(sc, MII_BMCR, 477 BMCR_AUTOEN | BMCR_STARTNEG); 478 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 479 480 return (EJUSTRETURN); 481 } 482 483 void 484 brgphy_loop(struct mii_softc *sc) 485 { 486 u_int32_t bmsr; 487 int i; 488 489 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 490 for (i = 0; i < 15000; i++) { 491 bmsr = PHY_READ(sc, MII_BMSR); 492 if (!(bmsr & BMSR_LINK)) 493 break; 494 DELAY(10); 495 } 496 } 497 498 static void 499 brgphy_reset(struct mii_softc *sc) 500 { 501 struct brgphy_softc *bsc = (void *)sc; 502 503 mii_phy_reset(sc); 504 505 switch (sc->mii_mpd_model) { 506 case MII_MODEL_BROADCOM_BCM5400: 507 brgphy_bcm5401_dspcode(sc); 508 break; 509 case MII_MODEL_BROADCOM_BCM5401: 510 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 511 brgphy_bcm5401_dspcode(sc); 512 break; 513 case MII_MODEL_BROADCOM_BCM5411: 514 brgphy_bcm5411_dspcode(sc); 515 break; 516 case MII_MODEL_BROADCOM_BCM5421: 517 brgphy_bcm5421_dspcode(sc); 518 break; 519 case MII_MODEL_BROADCOM_BCM54K2: 520 brgphy_bcm54k2_dspcode(sc); 521 break; 522 } 523 524 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 525 if (bsc->sc_isbge != 0) { 526 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 527 528 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 529 brgphy_adc_bug(sc); 530 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 531 brgphy_5704_a0_bug(sc); 532 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 533 brgphy_ber_bug(sc); 534 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 535 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 536 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 537 0x000a); 538 539 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 540 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 541 0x110b); 542 PHY_WRITE(sc, BRGPHY_TEST1, 543 BRGPHY_TEST1_TRIM_EN | 0x4); 544 } else { 545 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 546 0x010b); 547 } 548 549 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 550 } 551 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 552 brgphy_crc_bug(sc); 553 554 #if 0 555 /* Set Jumbo frame settings in the PHY. */ 556 if (bsc->sc_bge_flags & BGE_JUMBO_CAP) 557 brgphy_jumbo_settings(sc); 558 #endif 559 560 /* Adjust output voltage */ 561 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 562 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 563 564 #if 0 565 /* Enable Ethernet@Wirespeed */ 566 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 567 brgphy_eth_wirespeed(sc); 568 569 /* Enable Link LED on Dell boxes */ 570 if (bsc->sc_bge_flags & BGE_NO_3LED) { 571 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 572 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 573 & ~BRGPHY_PHY_EXTCTL_3_LED); 574 } 575 #endif 576 } 577 #if 0 /* not yet */ 578 /* Handle any bnx (NetXtreme II) workarounds. */ 579 } else if (sc->sc_isbnx != 0) { 580 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 581 582 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 583 /* Store autoneg capabilities/results in digital block (Page 0) */ 584 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 585 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 586 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 587 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 588 589 /* Enable fiber mode and autodetection */ 590 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 591 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 592 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 593 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 594 595 /* Enable parallel detection */ 596 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 597 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 598 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 599 600 /* Advertise 2.5G support through next page during autoneg */ 601 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 602 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 603 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 604 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 605 606 /* Increase TX signal amplitude */ 607 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 608 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 609 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 610 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 611 BRGPHY_5708S_TX_MISC_PG5); 612 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 613 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 614 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 615 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 616 BRGPHY_5708S_DIG_PG0); 617 } 618 619 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 620 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 621 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 622 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 623 BRGPHY_5708S_TX_MISC_PG5); 624 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 625 bnx_sc->bnx_port_hw_cfg & 626 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 627 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 628 BRGPHY_5708S_DIG_PG0); 629 } 630 } else { 631 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 632 brgphy_ber_bug(sc); 633 634 /* Set Jumbo frame settings in the PHY. */ 635 brgphy_jumbo_settings(sc); 636 637 /* Enable Ethernet@Wirespeed */ 638 brgphy_eth_wirespeed(sc); 639 } 640 } 641 #endif 642 } 643 } 644 645 /* Turn off tap power management on 5401. */ 646 static void 647 brgphy_bcm5401_dspcode(struct mii_softc *sc) 648 { 649 static const struct { 650 int reg; 651 uint16_t val; 652 } dspcode[] = { 653 { BRGPHY_MII_AUXCTL, 0x0c20 }, 654 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 655 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 656 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 657 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 658 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 659 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 660 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 661 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 662 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 663 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 664 { 0, 0 }, 665 }; 666 int i; 667 668 for (i = 0; dspcode[i].reg != 0; i++) 669 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 670 delay(40); 671 } 672 673 static void 674 brgphy_bcm5411_dspcode(struct mii_softc *sc) 675 { 676 static const struct { 677 int reg; 678 uint16_t val; 679 } dspcode[] = { 680 { 0x1c, 0x8c23 }, 681 { 0x1c, 0x8ca3 }, 682 { 0x1c, 0x8c23 }, 683 { 0, 0 }, 684 }; 685 int i; 686 687 for (i = 0; dspcode[i].reg != 0; i++) 688 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 689 } 690 691 void 692 brgphy_bcm5421_dspcode(struct mii_softc *sc) 693 { 694 uint16_t data; 695 696 /* Set Class A mode */ 697 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 698 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 699 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 700 701 /* Set FFE gamma override to -0.125 */ 702 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 703 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 704 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 705 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 706 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 707 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 708 } 709 710 void 711 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 712 { 713 static const struct { 714 int reg; 715 uint16_t val; 716 } dspcode[] = { 717 { 4, 0x01e1 }, 718 { 9, 0x0300 }, 719 { 0, 0 }, 720 }; 721 int i; 722 723 for (i = 0; dspcode[i].reg != 0; i++) 724 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 725 } 726 727 static void 728 brgphy_adc_bug(struct mii_softc *sc) 729 { 730 static const struct { 731 int reg; 732 uint16_t val; 733 } dspcode[] = { 734 { BRGPHY_MII_AUXCTL, 0x0c00 }, 735 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 736 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 737 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 738 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 739 { BRGPHY_MII_AUXCTL, 0x0400 }, 740 { 0, 0 }, 741 }; 742 int i; 743 744 for (i = 0; dspcode[i].reg != 0; i++) 745 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 746 } 747 748 static void 749 brgphy_5704_a0_bug(struct mii_softc *sc) 750 { 751 static const struct { 752 int reg; 753 uint16_t val; 754 } dspcode[] = { 755 { 0x1c, 0x8d68 }, 756 { 0x1c, 0x8d68 }, 757 { 0, 0 }, 758 }; 759 int i; 760 761 for (i = 0; dspcode[i].reg != 0; i++) 762 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 763 } 764 765 static void 766 brgphy_ber_bug(struct mii_softc *sc) 767 { 768 static const struct { 769 int reg; 770 uint16_t val; 771 } dspcode[] = { 772 { BRGPHY_MII_AUXCTL, 0x0c00 }, 773 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 774 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 775 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 776 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 777 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 778 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 779 { BRGPHY_MII_AUXCTL, 0x0400 }, 780 { 0, 0 }, 781 }; 782 int i; 783 784 for (i = 0; dspcode[i].reg != 0; i++) 785 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 786 } 787 788 /* BCM5701 A0/B0 CRC bug workaround */ 789 void 790 brgphy_crc_bug(struct mii_softc *sc) 791 { 792 static const struct { 793 int reg; 794 uint16_t val; 795 } dspcode[] = { 796 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 797 { 0x1c, 0x8c68 }, 798 { 0x1c, 0x8d68 }, 799 { 0x1c, 0x8c68 }, 800 { 0, 0 }, 801 }; 802 int i; 803 804 for (i = 0; dspcode[i].reg != 0; i++) 805 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 806 } 807
Indexes created Mon Sep 29 21:09:56 GMT 2025