brgphy.c revision 1.53
1 /* $NetBSD: brgphy.c,v 1.53 2010/03/13 12:57:23 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 Gig-E PHY. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.53 2010/03/13 12:57:23 kiyohara Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #if 0 85 #include <dev/pci/if_bnxreg.h> 86 #endif 87 88 static int brgphymatch(device_t, cfdata_t, void *); 89 static void brgphyattach(device_t, device_t, void *); 90 91 struct brgphy_softc { 92 struct mii_softc sc_mii; 93 int sc_isbge; 94 int sc_isbnx; 95 int sc_bge_flags; 96 int sc_bnx_flags; 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_status(struct mii_softc *); 105 static int brgphy_mii_phy_auto(struct mii_softc *); 106 static void brgphy_loop(struct mii_softc *); 107 static void brgphy_reset(struct mii_softc *); 108 static void brgphy_bcm5401_dspcode(struct mii_softc *); 109 static void brgphy_bcm5411_dspcode(struct mii_softc *); 110 static void brgphy_bcm5421_dspcode(struct mii_softc *); 111 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 112 static void brgphy_adc_bug(struct mii_softc *); 113 static void brgphy_5704_a0_bug(struct mii_softc *); 114 static void brgphy_ber_bug(struct mii_softc *); 115 static void brgphy_crc_bug(struct mii_softc *); 116 static void brgphy_jumbo_settings(struct mii_softc *); 117 static void brgphy_eth_wirespeed(struct mii_softc *); 118 119 120 static const struct mii_phy_funcs brgphy_funcs = { 121 brgphy_service, brgphy_status, brgphy_reset, 122 }; 123 124 static const struct mii_phydesc brgphys[] = { 125 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 126 MII_STR_BROADCOM_BCM5400 }, 127 128 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 129 MII_STR_BROADCOM_BCM5401 }, 130 131 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 132 MII_STR_BROADCOM_BCM5411 }, 133 134 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 135 MII_STR_BROADCOM_BCM5421 }, 136 137 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 138 MII_STR_BROADCOM_BCM5462 }, 139 140 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 141 MII_STR_BROADCOM_BCM5461 }, 142 143 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 144 MII_STR_BROADCOM_BCM54K2 }, 145 146 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 147 MII_STR_BROADCOM_BCM5464 }, 148 149 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 150 MII_STR_BROADCOM_BCM5701 }, 151 152 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 153 MII_STR_BROADCOM_BCM5703 }, 154 155 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 156 MII_STR_BROADCOM_BCM5704 }, 157 158 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 159 MII_STR_BROADCOM_BCM5705 }, 160 161 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 162 MII_STR_BROADCOM_BCM5714 }, 163 164 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 165 MII_STR_BROADCOM_BCM5750 }, 166 167 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 168 MII_STR_BROADCOM_BCM5752 }, 169 170 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 171 MII_STR_BROADCOM_BCM5780 }, 172 173 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 174 MII_STR_BROADCOM_BCM5708C }, 175 176 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 177 MII_STR_BROADCOM2_BCM5482 }, 178 179 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 180 MII_STR_BROADCOM2_BCM5709C }, 181 182 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 183 MII_STR_BROADCOM2_BCM5709CAX }, 184 185 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 186 MII_STR_BROADCOM2_BCM5722 }, 187 188 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 189 MII_STR_BROADCOM2_BCM5754 }, 190 191 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 192 MII_STR_BROADCOM2_BCM5755 }, 193 194 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 195 MII_STR_BROADCOM2_BCM5761 }, 196 197 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 198 MII_STR_BROADCOM2_BCM5784 }, 199 200 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 201 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 202 203 { 0, 0, 204 NULL }, 205 }; 206 207 static int 208 brgphymatch(device_t parent, cfdata_t match, void *aux) 209 { 210 struct mii_attach_args *ma = aux; 211 212 if (mii_phy_match(ma, brgphys) != NULL) 213 return (10); 214 215 return (0); 216 } 217 218 static void 219 brgphyattach(device_t parent, device_t self, void *aux) 220 { 221 struct brgphy_softc *bsc = device_private(self); 222 struct mii_softc *sc = &bsc->sc_mii; 223 struct mii_attach_args *ma = aux; 224 struct mii_data *mii = ma->mii_data; 225 const struct mii_phydesc *mpd; 226 prop_dictionary_t dict; 227 228 mpd = mii_phy_match(ma, brgphys); 229 aprint_naive(": Media interface\n"); 230 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 231 232 sc->mii_dev = self; 233 sc->mii_inst = mii->mii_instance; 234 sc->mii_phy = ma->mii_phyno; 235 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 236 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 237 sc->mii_pdata = mii; 238 sc->mii_flags = ma->mii_flags; 239 sc->mii_anegticks = MII_ANEGTICKS; 240 sc->mii_funcs = &brgphy_funcs; 241 242 PHY_RESET(sc); 243 244 sc->mii_capabilities = 245 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 246 if (sc->mii_capabilities & BMSR_EXTSTAT) 247 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 248 249 aprint_normal_dev(self, ""); 250 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 251 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 252 aprint_error("no media present"); 253 else 254 mii_phy_add_media(sc); 255 aprint_normal("\n"); 256 257 if (device_is_a(parent, "bge")) { 258 bsc->sc_isbge = 1; 259 dict = device_properties(parent); 260 if (!prop_dictionary_get_uint32(dict, "phyflags", 261 &bsc->sc_bge_flags)) 262 aprint_error("failed to get phyflags"); 263 } else if (device_is_a(parent, "bnx")) { 264 bsc->sc_isbnx = 1; 265 dict = device_properties(parent); 266 prop_dictionary_get_uint32(dict, "phyflags", 267 &bsc->sc_bnx_flags); 268 } 269 } 270 271 static int 272 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 273 { 274 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 275 int reg, speed, gig; 276 277 switch (cmd) { 278 case MII_POLLSTAT: 279 /* 280 * If we're not polling our PHY instance, just return. 281 */ 282 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 283 return (0); 284 break; 285 286 case MII_MEDIACHG: 287 /* 288 * If the media indicates a different PHY instance, 289 * isolate ourselves. 290 */ 291 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 292 reg = PHY_READ(sc, MII_BMCR); 293 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 294 return (0); 295 } 296 297 /* 298 * If the interface is not up, don't do anything. 299 */ 300 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 301 break; 302 303 PHY_RESET(sc); /* XXX hardware bug work-around */ 304 305 switch (IFM_SUBTYPE(ife->ifm_media)) { 306 case IFM_AUTO: 307 (void) brgphy_mii_phy_auto(sc); 308 break; 309 case IFM_1000_T: 310 speed = BMCR_S1000; 311 goto setit; 312 case IFM_100_TX: 313 speed = BMCR_S100; 314 goto setit; 315 case IFM_10_T: 316 speed = BMCR_S10; 317 setit: 318 brgphy_loop(sc); 319 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 320 speed |= BMCR_FDX; 321 gig = GTCR_ADV_1000TFDX; 322 } else { 323 gig = GTCR_ADV_1000THDX; 324 } 325 326 PHY_WRITE(sc, MII_100T2CR, 0); 327 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 328 PHY_WRITE(sc, MII_BMCR, speed); 329 330 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 331 break; 332 333 PHY_WRITE(sc, MII_100T2CR, gig); 334 PHY_WRITE(sc, MII_BMCR, 335 speed|BMCR_AUTOEN|BMCR_STARTNEG); 336 337 if (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701) 338 break; 339 340 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 341 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 342 PHY_WRITE(sc, MII_100T2CR, gig); 343 break; 344 default: 345 return (EINVAL); 346 } 347 break; 348 349 case MII_TICK: 350 /* 351 * If we're not currently selected, just return. 352 */ 353 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 354 return (0); 355 356 if (mii_phy_tick(sc) == EJUSTRETURN) 357 return (0); 358 break; 359 360 case MII_DOWN: 361 mii_phy_down(sc); 362 return (0); 363 } 364 365 /* Update the media status. */ 366 mii_phy_status(sc); 367 368 /* 369 * Callback if something changed. Note that we need to poke the DSP on 370 * the Broadcom PHYs if the media changes. 371 */ 372 if (sc->mii_media_active != mii->mii_media_active || 373 sc->mii_media_status != mii->mii_media_status || 374 cmd == MII_MEDIACHG) { 375 switch (sc->mii_mpd_model) { 376 case MII_MODEL_BROADCOM_BCM5400: 377 brgphy_bcm5401_dspcode(sc); 378 break; 379 case MII_MODEL_BROADCOM_BCM5401: 380 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 381 brgphy_bcm5401_dspcode(sc); 382 break; 383 case MII_MODEL_BROADCOM_BCM5411: 384 brgphy_bcm5411_dspcode(sc); 385 break; 386 } 387 } 388 389 /* Callback if something changed. */ 390 mii_phy_update(sc, cmd); 391 return (0); 392 } 393 394 static void 395 brgphy_status(struct mii_softc *sc) 396 { 397 struct mii_data *mii = sc->mii_pdata; 398 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 399 int bmcr, auxsts, gtsr; 400 401 mii->mii_media_status = IFM_AVALID; 402 mii->mii_media_active = IFM_ETHER; 403 404 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 405 406 if (auxsts & BRGPHY_AUXSTS_LINK) 407 mii->mii_media_status |= IFM_ACTIVE; 408 409 bmcr = PHY_READ(sc, MII_BMCR); 410 if (bmcr & BMCR_ISO) { 411 mii->mii_media_active |= IFM_NONE; 412 mii->mii_media_status = 0; 413 return; 414 } 415 416 if (bmcr & BMCR_LOOP) 417 mii->mii_media_active |= IFM_LOOP; 418 419 if (bmcr & BMCR_AUTOEN) { 420 /* 421 * The media status bits are only valid of autonegotiation 422 * has completed (or it's disabled). 423 */ 424 if ((auxsts & BRGPHY_AUXSTS_ACOMP) == 0) { 425 /* Erg, still trying, I guess... */ 426 mii->mii_media_active |= IFM_NONE; 427 return; 428 } 429 430 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 431 case BRGPHY_RES_1000FD: 432 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 433 gtsr = PHY_READ(sc, MII_100T2SR); 434 if (gtsr & GTSR_MS_RES) 435 mii->mii_media_active |= IFM_ETH_MASTER; 436 break; 437 438 case BRGPHY_RES_1000HD: 439 mii->mii_media_active |= IFM_1000_T; 440 gtsr = PHY_READ(sc, MII_100T2SR); 441 if (gtsr & GTSR_MS_RES) 442 mii->mii_media_active |= IFM_ETH_MASTER; 443 break; 444 445 case BRGPHY_RES_100FD: 446 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 447 break; 448 449 case BRGPHY_RES_100T4: 450 mii->mii_media_active |= IFM_100_T4; 451 break; 452 453 case BRGPHY_RES_100HD: 454 mii->mii_media_active |= IFM_100_TX; 455 break; 456 457 case BRGPHY_RES_10FD: 458 mii->mii_media_active |= IFM_10_T|IFM_FDX; 459 break; 460 461 case BRGPHY_RES_10HD: 462 mii->mii_media_active |= IFM_10_T; 463 break; 464 465 default: 466 mii->mii_media_active |= IFM_NONE; 467 mii->mii_media_status = 0; 468 } 469 if (mii->mii_media_active & IFM_FDX) 470 mii->mii_media_active |= mii_phy_flowstatus(sc); 471 } else 472 mii->mii_media_active = ife->ifm_media; 473 } 474 475 int 476 brgphy_mii_phy_auto(struct mii_softc *sc) 477 { 478 int anar, ktcr = 0; 479 480 brgphy_loop(sc); 481 PHY_RESET(sc); 482 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 483 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 484 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 485 PHY_WRITE(sc, MII_100T2CR, ktcr); 486 ktcr = PHY_READ(sc, MII_100T2CR); 487 DELAY(1000); 488 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 489 if (sc->mii_flags & MIIF_DOPAUSE) 490 anar |= ANAR_FC| ANAR_X_PAUSE_ASYM; 491 492 PHY_WRITE(sc, MII_ANAR, anar); 493 DELAY(1000); 494 PHY_WRITE(sc, MII_BMCR, 495 BMCR_AUTOEN | BMCR_STARTNEG); 496 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 497 498 return (EJUSTRETURN); 499 } 500 501 void 502 brgphy_loop(struct mii_softc *sc) 503 { 504 u_int32_t bmsr; 505 int i; 506 507 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 508 for (i = 0; i < 15000; i++) { 509 bmsr = PHY_READ(sc, MII_BMSR); 510 if (!(bmsr & BMSR_LINK)) 511 break; 512 DELAY(10); 513 } 514 } 515 516 static void 517 brgphy_reset(struct mii_softc *sc) 518 { 519 struct brgphy_softc *bsc = (void *)sc; 520 521 mii_phy_reset(sc); 522 523 switch (sc->mii_mpd_model) { 524 case MII_MODEL_BROADCOM_BCM5400: 525 brgphy_bcm5401_dspcode(sc); 526 break; 527 case MII_MODEL_BROADCOM_BCM5401: 528 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 529 brgphy_bcm5401_dspcode(sc); 530 break; 531 case MII_MODEL_BROADCOM_BCM5411: 532 brgphy_bcm5411_dspcode(sc); 533 break; 534 case MII_MODEL_BROADCOM_BCM5421: 535 brgphy_bcm5421_dspcode(sc); 536 break; 537 case MII_MODEL_BROADCOM_BCM54K2: 538 brgphy_bcm54k2_dspcode(sc); 539 break; 540 } 541 542 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 543 if (bsc->sc_isbge != 0) { 544 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 545 546 if (bsc->sc_bge_flags & BGE_PHY_ADC_BUG) 547 brgphy_adc_bug(sc); 548 if (bsc->sc_bge_flags & BGE_PHY_5704_A0_BUG) 549 brgphy_5704_a0_bug(sc); 550 if (bsc->sc_bge_flags & BGE_PHY_BER_BUG) 551 brgphy_ber_bug(sc); 552 else if (bsc->sc_bge_flags & BGE_PHY_JITTER_BUG) { 553 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 554 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 555 0x000a); 556 557 if (bsc->sc_bge_flags & BGE_PHY_ADJUST_TRIM) { 558 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 559 0x110b); 560 PHY_WRITE(sc, BRGPHY_TEST1, 561 BRGPHY_TEST1_TRIM_EN | 0x4); 562 } else { 563 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 564 0x010b); 565 } 566 567 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 568 } 569 if (bsc->sc_bge_flags & BGE_PHY_CRC_BUG) 570 brgphy_crc_bug(sc); 571 572 /* Set Jumbo frame settings in the PHY. */ 573 if (bsc->sc_bge_flags & BGE_JUMBO_CAPABLE) 574 brgphy_jumbo_settings(sc); 575 576 /* Adjust output voltage */ 577 if (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906) 578 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 579 580 /* Enable Ethernet@Wirespeed */ 581 if (!(bsc->sc_bge_flags & BGE_NO_ETH_WIRE_SPEED)) 582 brgphy_eth_wirespeed(sc); 583 584 #if 0 585 /* Enable Link LED on Dell boxes */ 586 if (bsc->sc_bge_flags & BGE_NO_3LED) { 587 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 588 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 589 & ~BRGPHY_PHY_EXTCTL_3_LED); 590 } 591 #endif 592 } 593 #if 0 /* not yet */ 594 /* Handle any bnx (NetXtreme II) workarounds. */ 595 } else if (sc->sc_isbnx != 0) { 596 bnx_sc = sc->mii_pdata->mii_ifp->if_softc; 597 598 if (sc->mii_mpd_model == MII_MODEL_xxBROADCOM2_BCM5708S) { 599 /* Store autoneg capabilities/results in digital block (Page 0) */ 600 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 601 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 602 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 603 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 604 605 /* Enable fiber mode and autodetection */ 606 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 607 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 608 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 609 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 610 611 /* Enable parallel detection */ 612 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 613 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 614 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 615 616 /* Advertise 2.5G support through next page during autoneg */ 617 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 618 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 619 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 620 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 621 622 /* Increase TX signal amplitude */ 623 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 624 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 625 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 626 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 627 BRGPHY_5708S_TX_MISC_PG5); 628 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 629 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 630 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 631 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 632 BRGPHY_5708S_DIG_PG0); 633 } 634 635 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 636 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 637 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 638 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 639 BRGPHY_5708S_TX_MISC_PG5); 640 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 641 bnx_sc->bnx_port_hw_cfg & 642 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 643 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 644 BRGPHY_5708S_DIG_PG0); 645 } 646 } else { 647 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 648 brgphy_ber_bug(sc); 649 650 /* Set Jumbo frame settings in the PHY. */ 651 brgphy_jumbo_settings(sc); 652 653 /* Enable Ethernet@Wirespeed */ 654 brgphy_eth_wirespeed(sc); 655 } 656 } 657 #endif 658 } 659 } 660 661 /* Turn off tap power management on 5401. */ 662 static void 663 brgphy_bcm5401_dspcode(struct mii_softc *sc) 664 { 665 static const struct { 666 int reg; 667 uint16_t val; 668 } dspcode[] = { 669 { BRGPHY_MII_AUXCTL, 0x0c20 }, 670 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 671 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 672 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 673 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 674 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 675 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 676 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 677 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 678 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 679 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 680 { 0, 0 }, 681 }; 682 int i; 683 684 for (i = 0; dspcode[i].reg != 0; i++) 685 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 686 delay(40); 687 } 688 689 static void 690 brgphy_bcm5411_dspcode(struct mii_softc *sc) 691 { 692 static const struct { 693 int reg; 694 uint16_t val; 695 } dspcode[] = { 696 { 0x1c, 0x8c23 }, 697 { 0x1c, 0x8ca3 }, 698 { 0x1c, 0x8c23 }, 699 { 0, 0 }, 700 }; 701 int i; 702 703 for (i = 0; dspcode[i].reg != 0; i++) 704 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 705 } 706 707 void 708 brgphy_bcm5421_dspcode(struct mii_softc *sc) 709 { 710 uint16_t data; 711 712 /* Set Class A mode */ 713 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 714 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 715 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 716 717 /* Set FFE gamma override to -0.125 */ 718 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 719 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 720 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 721 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 722 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 723 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 724 } 725 726 void 727 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 728 { 729 static const struct { 730 int reg; 731 uint16_t val; 732 } dspcode[] = { 733 { 4, 0x01e1 }, 734 { 9, 0x0300 }, 735 { 0, 0 }, 736 }; 737 int i; 738 739 for (i = 0; dspcode[i].reg != 0; i++) 740 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 741 } 742 743 static void 744 brgphy_adc_bug(struct mii_softc *sc) 745 { 746 static const struct { 747 int reg; 748 uint16_t val; 749 } dspcode[] = { 750 { BRGPHY_MII_AUXCTL, 0x0c00 }, 751 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 752 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 753 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 754 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 755 { BRGPHY_MII_AUXCTL, 0x0400 }, 756 { 0, 0 }, 757 }; 758 int i; 759 760 for (i = 0; dspcode[i].reg != 0; i++) 761 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 762 } 763 764 static void 765 brgphy_5704_a0_bug(struct mii_softc *sc) 766 { 767 static const struct { 768 int reg; 769 uint16_t val; 770 } dspcode[] = { 771 { 0x1c, 0x8d68 }, 772 { 0x1c, 0x8d68 }, 773 { 0, 0 }, 774 }; 775 int i; 776 777 for (i = 0; dspcode[i].reg != 0; i++) 778 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 779 } 780 781 static void 782 brgphy_ber_bug(struct mii_softc *sc) 783 { 784 static const struct { 785 int reg; 786 uint16_t val; 787 } dspcode[] = { 788 { BRGPHY_MII_AUXCTL, 0x0c00 }, 789 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 790 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 791 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 792 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 793 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 794 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 795 { BRGPHY_MII_AUXCTL, 0x0400 }, 796 { 0, 0 }, 797 }; 798 int i; 799 800 for (i = 0; dspcode[i].reg != 0; i++) 801 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 802 } 803 804 /* BCM5701 A0/B0 CRC bug workaround */ 805 void 806 brgphy_crc_bug(struct mii_softc *sc) 807 { 808 static const struct { 809 int reg; 810 uint16_t val; 811 } dspcode[] = { 812 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 813 { 0x1c, 0x8c68 }, 814 { 0x1c, 0x8d68 }, 815 { 0x1c, 0x8c68 }, 816 { 0, 0 }, 817 }; 818 int i; 819 820 for (i = 0; dspcode[i].reg != 0; i++) 821 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 822 } 823 824 static void 825 brgphy_jumbo_settings(struct mii_softc *sc) 826 { 827 u_int32_t val; 828 829 /* Set Jumbo frame settings in the PHY. */ 830 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 831 /* Cannot do read-modify-write on the BCM5401 */ 832 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 833 } else { 834 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 835 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 836 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 837 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 838 } 839 840 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 841 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 842 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 843 } 844 845 static void 846 brgphy_eth_wirespeed(struct mii_softc *sc) 847 { 848 u_int32_t val; 849 850 /* Enable Ethernet@Wirespeed */ 851 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 852 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 853 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 854 (val | (1 << 15) | (1 << 4))); 855 } 856
Indexes created Mon Oct 20 11:09:49 GMT 2025