brgphy.c revision 1.59.8.3
1 /* $NetBSD: brgphy.c,v 1.59.8.3 2013/11/17 18:24:05 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.59.8.3 2013/11/17 18:24:05 bouyer Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 }; 96 97 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 98 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 99 DVF_DETACH_SHUTDOWN); 100 101 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102 static void brgphy_status(struct mii_softc *); 103 static int brgphy_mii_phy_auto(struct mii_softc *); 104 static void brgphy_loop(struct mii_softc *); 105 static void brgphy_reset(struct mii_softc *); 106 static void brgphy_bcm5401_dspcode(struct mii_softc *); 107 static void brgphy_bcm5411_dspcode(struct mii_softc *); 108 static void brgphy_bcm5421_dspcode(struct mii_softc *); 109 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 110 static void brgphy_adc_bug(struct mii_softc *); 111 static void brgphy_5704_a0_bug(struct mii_softc *); 112 static void brgphy_ber_bug(struct mii_softc *); 113 static void brgphy_crc_bug(struct mii_softc *); 114 static void brgphy_disable_early_dac(struct mii_softc *); 115 static void brgphy_jumbo_settings(struct mii_softc *); 116 static void brgphy_eth_wirespeed(struct mii_softc *); 117 118 119 static const struct mii_phy_funcs brgphy_funcs = { 120 brgphy_service, brgphy_status, brgphy_reset, 121 }; 122 123 static const struct mii_phydesc brgphys[] = { 124 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 125 MII_STR_BROADCOM_BCM5400 }, 126 127 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 128 MII_STR_BROADCOM_BCM5401 }, 129 130 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 131 MII_STR_BROADCOM_BCM5411 }, 132 133 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 134 MII_STR_BROADCOM_BCM5421 }, 135 136 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 137 MII_STR_BROADCOM_BCM5462 }, 138 139 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 140 MII_STR_BROADCOM_BCM5461 }, 141 142 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 143 MII_STR_BROADCOM_BCM54K2 }, 144 145 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 146 MII_STR_BROADCOM_BCM5464 }, 147 148 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 149 MII_STR_BROADCOM_BCM5701 }, 150 151 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 152 MII_STR_BROADCOM_BCM5703 }, 153 154 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 155 MII_STR_BROADCOM_BCM5704 }, 156 157 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 158 MII_STR_BROADCOM_BCM5705 }, 159 160 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 161 MII_STR_BROADCOM_BCM5714 }, 162 163 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 164 MII_STR_BROADCOM_BCM5750 }, 165 166 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 167 MII_STR_BROADCOM_BCM5752 }, 168 169 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 170 MII_STR_BROADCOM_BCM5780 }, 171 172 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 173 MII_STR_BROADCOM_BCM5708C }, 174 175 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 176 MII_STR_BROADCOM2_BCM5481 }, 177 178 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 179 MII_STR_BROADCOM2_BCM5482 }, 180 181 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 182 MII_STR_BROADCOM2_BCM5709C }, 183 184 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 185 MII_STR_BROADCOM2_BCM5709S }, 186 187 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 188 MII_STR_BROADCOM2_BCM5709CAX }, 189 190 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 191 MII_STR_BROADCOM2_BCM5722 }, 192 193 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 194 MII_STR_BROADCOM2_BCM5754 }, 195 196 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 197 MII_STR_BROADCOM2_BCM5755 }, 198 199 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 200 MII_STR_BROADCOM2_BCM5756 }, 201 202 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 203 MII_STR_BROADCOM2_BCM5761 }, 204 205 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 206 MII_STR_BROADCOM2_BCM5784 }, 207 208 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 209 MII_STR_BROADCOM2_BCM5785 }, 210 211 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 212 MII_STR_BROADCOM3_BCM5717C }, 213 214 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 215 MII_STR_BROADCOM3_BCM5719C }, 216 217 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 218 MII_STR_BROADCOM3_BCM5720C }, 219 220 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 221 MII_STR_BROADCOM3_BCM57765 }, 222 223 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 224 MII_STR_BROADCOM3_BCM57780 }, 225 226 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 227 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 228 229 { 0, 0, 230 NULL }, 231 }; 232 233 static int 234 brgphymatch(device_t parent, cfdata_t match, void *aux) 235 { 236 struct mii_attach_args *ma = aux; 237 238 if (mii_phy_match(ma, brgphys) != NULL) 239 return (10); 240 241 return (0); 242 } 243 244 static void 245 brgphyattach(device_t parent, device_t self, void *aux) 246 { 247 struct brgphy_softc *bsc = device_private(self); 248 struct mii_softc *sc = &bsc->sc_mii; 249 struct mii_attach_args *ma = aux; 250 struct mii_data *mii = ma->mii_data; 251 const struct mii_phydesc *mpd; 252 prop_dictionary_t dict; 253 254 mpd = mii_phy_match(ma, brgphys); 255 aprint_naive(": Media interface\n"); 256 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 257 258 sc->mii_dev = self; 259 sc->mii_inst = mii->mii_instance; 260 sc->mii_phy = ma->mii_phyno; 261 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 262 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 263 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 264 sc->mii_pdata = mii; 265 sc->mii_flags = ma->mii_flags; 266 sc->mii_anegticks = MII_ANEGTICKS; 267 sc->mii_funcs = &brgphy_funcs; 268 269 if (device_is_a(parent, "bge")) 270 bsc->sc_isbge = true; 271 else if (device_is_a(parent, "bnx")) 272 bsc->sc_isbnx = true; 273 274 if (bsc->sc_isbge || bsc->sc_isbnx) { 275 dict = device_properties(parent); 276 if (!prop_dictionary_get_uint32(dict, "phyflags", 277 &bsc->sc_phyflags)) 278 aprint_error_dev(self, "failed to get phyflags\n"); 279 if (!prop_dictionary_get_uint32(dict, "chipid", 280 &bsc->sc_chipid)) 281 aprint_error_dev(self, "failed to get chipid\n"); 282 } 283 284 PHY_RESET(sc); 285 286 sc->mii_capabilities = 287 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 288 if (sc->mii_capabilities & BMSR_EXTSTAT) 289 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 290 291 aprint_normal_dev(self, ""); 292 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 293 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 294 aprint_error("no media present"); 295 else { 296 if (sc->mii_flags & MIIF_HAVEFIBER) { 297 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 298 299 /* 300 * Set the proper bits for capabilities so that the 301 * correct media get selected by mii_phy_add_media() 302 */ 303 sc->mii_capabilities |= BMSR_ANEG; 304 sc->mii_capabilities &= ~BMSR_100T4; 305 sc->mii_extcapabilities |= EXTSR_1000XFDX; 306 307 if (bsc->sc_isbnx) { 308 /* 309 * 2.5Gb support is a software enabled feature 310 * on the BCM5708S and BCM5709S controllers. 311 */ 312 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 313 if (bsc->sc_phyflags 314 & BNX_PHY_2_5G_CAPABLE_FLAG) { 315 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 316 IFM_FDX, sc->mii_inst), 0); 317 aprint_normal("2500baseSX-FDX, "); 318 #undef ADD 319 } 320 } 321 } 322 mii_phy_add_media(sc); 323 } 324 aprint_normal("\n"); 325 326 } 327 328 static int 329 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 330 { 331 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 332 int reg, speed, gig; 333 334 switch (cmd) { 335 case MII_POLLSTAT: 336 /* 337 * If we're not polling our PHY instance, just return. 338 */ 339 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 340 return (0); 341 break; 342 343 case MII_MEDIACHG: 344 /* 345 * If the media indicates a different PHY instance, 346 * isolate ourselves. 347 */ 348 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 349 reg = PHY_READ(sc, MII_BMCR); 350 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 351 return (0); 352 } 353 354 /* 355 * If the interface is not up, don't do anything. 356 */ 357 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 358 break; 359 360 PHY_RESET(sc); /* XXX hardware bug work-around */ 361 362 switch (IFM_SUBTYPE(ife->ifm_media)) { 363 case IFM_AUTO: 364 (void) brgphy_mii_phy_auto(sc); 365 break; 366 case IFM_1000_T: 367 speed = BMCR_S1000; 368 goto setit; 369 case IFM_100_TX: 370 speed = BMCR_S100; 371 goto setit; 372 case IFM_10_T: 373 speed = BMCR_S10; 374 setit: 375 brgphy_loop(sc); 376 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 377 speed |= BMCR_FDX; 378 gig = GTCR_ADV_1000TFDX; 379 } else { 380 gig = GTCR_ADV_1000THDX; 381 } 382 383 PHY_WRITE(sc, MII_100T2CR, 0); 384 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 385 PHY_WRITE(sc, MII_BMCR, speed); 386 387 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 388 break; 389 390 PHY_WRITE(sc, MII_100T2CR, gig); 391 PHY_WRITE(sc, MII_BMCR, 392 speed | BMCR_AUTOEN | BMCR_STARTNEG); 393 394 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 395 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 396 break; 397 398 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 399 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 400 PHY_WRITE(sc, MII_100T2CR, gig); 401 break; 402 default: 403 return (EINVAL); 404 } 405 break; 406 407 case MII_TICK: 408 /* 409 * If we're not currently selected, just return. 410 */ 411 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 412 return (0); 413 414 /* 415 * Is the interface even up? 416 */ 417 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 418 return 0; 419 420 /* 421 * Only used for autonegotiation. 422 */ 423 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 424 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 425 sc->mii_ticks = 0; 426 break; 427 } 428 429 /* 430 * Check for link. 431 * Read the status register twice; BMSR_LINK is latch-low. 432 */ 433 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 434 if (reg & BMSR_LINK) { 435 sc->mii_ticks = 0; 436 break; 437 } 438 439 /* 440 * mii_ticks == 0 means it's the first tick after changing the 441 * media or the link became down since the last tick 442 * (see above), so break to update the status. 443 */ 444 if (sc->mii_ticks++ == 0) 445 break; 446 447 /* 448 * Only retry autonegotiation every mii_anegticks seconds. 449 */ 450 KASSERT(sc->mii_anegticks != 0); 451 if (sc->mii_ticks <= sc->mii_anegticks) 452 break; 453 454 brgphy_mii_phy_auto(sc); 455 break; 456 457 case MII_DOWN: 458 mii_phy_down(sc); 459 return (0); 460 } 461 462 /* Update the media status. */ 463 mii_phy_status(sc); 464 465 /* 466 * Callback if something changed. Note that we need to poke the DSP on 467 * the Broadcom PHYs if the media changes. 468 */ 469 if (sc->mii_media_active != mii->mii_media_active || 470 sc->mii_media_status != mii->mii_media_status || 471 cmd == MII_MEDIACHG) { 472 switch (sc->mii_mpd_oui) { 473 case MII_OUI_BROADCOM: 474 switch (sc->mii_mpd_model) { 475 case MII_MODEL_BROADCOM_BCM5400: 476 brgphy_bcm5401_dspcode(sc); 477 break; 478 case MII_MODEL_BROADCOM_BCM5401: 479 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 480 brgphy_bcm5401_dspcode(sc); 481 break; 482 case MII_MODEL_BROADCOM_BCM5411: 483 brgphy_bcm5411_dspcode(sc); 484 break; 485 } 486 break; 487 } 488 } 489 490 /* Callback if something changed. */ 491 mii_phy_update(sc, cmd); 492 return (0); 493 } 494 495 static void 496 brgphy_status(struct mii_softc *sc) 497 { 498 struct mii_data *mii = sc->mii_pdata; 499 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 500 int bmcr, bmsr, auxsts, gtsr; 501 502 mii->mii_media_status = IFM_AVALID; 503 mii->mii_media_active = IFM_ETHER; 504 505 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 506 if (bmsr & BMSR_LINK) 507 mii->mii_media_status |= IFM_ACTIVE; 508 509 bmcr = PHY_READ(sc, MII_BMCR); 510 if (bmcr & BMCR_ISO) { 511 mii->mii_media_active |= IFM_NONE; 512 mii->mii_media_status = 0; 513 return; 514 } 515 516 if (bmcr & BMCR_LOOP) 517 mii->mii_media_active |= IFM_LOOP; 518 519 if (bmcr & BMCR_AUTOEN) { 520 /* 521 * The media status bits are only valid of autonegotiation 522 * has completed (or it's disabled). 523 */ 524 if ((bmsr & BMSR_ACOMP) == 0) { 525 /* Erg, still trying, I guess... */ 526 mii->mii_media_active |= IFM_NONE; 527 return; 528 } 529 530 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 531 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 532 /* 533 * 5709S has its own general purpose status registers 534 */ 535 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 536 BRGPHY_BLOCK_ADDR_GP_STATUS); 537 538 auxsts = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 539 540 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 541 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 542 543 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 544 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 545 mii->mii_media_active |= IFM_10_FL; 546 break; 547 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 548 mii->mii_media_active |= IFM_100_FX; 549 break; 550 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 551 mii->mii_media_active |= IFM_1000_SX; 552 break; 553 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 554 mii->mii_media_active |= IFM_2500_SX; 555 break; 556 default: 557 mii->mii_media_active |= IFM_NONE; 558 mii->mii_media_status = 0; 559 break; 560 } 561 562 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 563 mii->mii_media_active |= IFM_FDX; 564 else 565 mii->mii_media_active |= IFM_HDX; 566 567 } else { 568 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 569 570 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 571 case BRGPHY_RES_1000FD: 572 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 573 gtsr = PHY_READ(sc, MII_100T2SR); 574 if (gtsr & GTSR_MS_RES) 575 mii->mii_media_active |= IFM_ETH_MASTER; 576 break; 577 578 case BRGPHY_RES_1000HD: 579 mii->mii_media_active |= IFM_1000_T; 580 gtsr = PHY_READ(sc, MII_100T2SR); 581 if (gtsr & GTSR_MS_RES) 582 mii->mii_media_active |= IFM_ETH_MASTER; 583 break; 584 585 case BRGPHY_RES_100FD: 586 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 587 break; 588 589 case BRGPHY_RES_100T4: 590 mii->mii_media_active |= IFM_100_T4; 591 break; 592 593 case BRGPHY_RES_100HD: 594 mii->mii_media_active |= IFM_100_TX; 595 break; 596 597 case BRGPHY_RES_10FD: 598 mii->mii_media_active |= IFM_10_T | IFM_FDX; 599 break; 600 601 case BRGPHY_RES_10HD: 602 mii->mii_media_active |= IFM_10_T; 603 break; 604 605 default: 606 mii->mii_media_active |= IFM_NONE; 607 mii->mii_media_status = 0; 608 } 609 } 610 611 if (mii->mii_media_active & IFM_FDX) 612 mii->mii_media_active |= mii_phy_flowstatus(sc); 613 614 } else 615 mii->mii_media_active = ife->ifm_media; 616 } 617 618 int 619 brgphy_mii_phy_auto(struct mii_softc *sc) 620 { 621 int anar, ktcr = 0; 622 623 brgphy_loop(sc); 624 PHY_RESET(sc); 625 626 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 627 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 628 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 629 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 630 PHY_WRITE(sc, MII_100T2CR, ktcr); 631 ktcr = PHY_READ(sc, MII_100T2CR); 632 DELAY(1000); 633 634 if (sc->mii_flags & MIIF_HAVEFIBER) { 635 anar = ANAR_X_FD | ANAR_X_HD; 636 if (sc->mii_flags & MIIF_DOPAUSE) 637 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 638 } else { 639 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 640 if (sc->mii_flags & MIIF_DOPAUSE) 641 anar |= ANAR_FC | ANAR_X_PAUSE_ASYM; 642 } 643 PHY_WRITE(sc, MII_ANAR, anar); 644 DELAY(1000); 645 646 /* Start autonegotiation */ 647 PHY_WRITE(sc, MII_BMCR, 648 BMCR_AUTOEN | BMCR_STARTNEG); 649 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 650 651 return (EJUSTRETURN); 652 } 653 654 void 655 brgphy_loop(struct mii_softc *sc) 656 { 657 u_int32_t bmsr; 658 int i; 659 660 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 661 for (i = 0; i < 15000; i++) { 662 bmsr = PHY_READ(sc, MII_BMSR); 663 if (!(bmsr & BMSR_LINK)) 664 break; 665 DELAY(10); 666 } 667 } 668 669 static void 670 brgphy_reset(struct mii_softc *sc) 671 { 672 struct brgphy_softc *bsc = device_private(sc->mii_dev); 673 674 mii_phy_reset(sc); 675 switch (sc->mii_mpd_oui) { 676 case MII_OUI_BROADCOM: 677 switch (sc->mii_mpd_model) { 678 case MII_MODEL_BROADCOM_BCM5400: 679 brgphy_bcm5401_dspcode(sc); 680 break; 681 case MII_MODEL_BROADCOM_BCM5401: 682 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 683 brgphy_bcm5401_dspcode(sc); 684 break; 685 case MII_MODEL_BROADCOM_BCM5411: 686 brgphy_bcm5411_dspcode(sc); 687 break; 688 case MII_MODEL_BROADCOM_BCM5421: 689 brgphy_bcm5421_dspcode(sc); 690 break; 691 case MII_MODEL_BROADCOM_BCM54K2: 692 brgphy_bcm54k2_dspcode(sc); 693 break; 694 } 695 break; 696 case MII_OUI_BROADCOM3: 697 switch (sc->mii_mpd_model) { 698 case MII_MODEL_BROADCOM3_BCM5717C: 699 case MII_MODEL_BROADCOM3_BCM5719C: 700 case MII_MODEL_BROADCOM3_BCM5720C: 701 case MII_MODEL_BROADCOM3_BCM57765: 702 return; 703 } 704 break; 705 default: 706 break; 707 } 708 709 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 710 if (bsc->sc_isbge) { 711 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 712 713 if (bsc->sc_phyflags & BGE_PHY_ADC_BUG) 714 brgphy_adc_bug(sc); 715 if (bsc->sc_phyflags & BGE_PHY_5704_A0_BUG) 716 brgphy_5704_a0_bug(sc); 717 if (bsc->sc_phyflags & BGE_PHY_BER_BUG) 718 brgphy_ber_bug(sc); 719 else if (bsc->sc_phyflags & BGE_PHY_JITTER_BUG) { 720 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 721 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 722 0x000a); 723 724 if (bsc->sc_phyflags 725 & BGE_PHY_ADJUST_TRIM) { 726 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 727 0x110b); 728 PHY_WRITE(sc, BRGPHY_TEST1, 729 BRGPHY_TEST1_TRIM_EN | 0x4); 730 } else { 731 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 732 0x010b); 733 } 734 735 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 736 } 737 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 738 brgphy_crc_bug(sc); 739 740 /* Set Jumbo frame settings in the PHY. */ 741 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 742 brgphy_jumbo_settings(sc); 743 744 /* Adjust output voltage */ 745 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 746 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 747 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 748 749 /* Enable Ethernet@Wirespeed */ 750 if (!(bsc->sc_phyflags & BGE_PHY_NO_WIRESPEED)) 751 brgphy_eth_wirespeed(sc); 752 753 #if 0 754 /* Enable Link LED on Dell boxes */ 755 if (bsc->sc_phyflags & BGE_PHY_NO_3LED) { 756 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 757 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 758 & ~BRGPHY_PHY_EXTCTL_3_LED); 759 } 760 #endif 761 } 762 /* Handle any bnx (NetXtreme II) workarounds. */ 763 } else if (bsc->sc_isbnx) { 764 #if 0 /* not yet */ 765 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 766 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 767 /* Store autoneg capabilities/results in digital block (Page 0) */ 768 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 769 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 770 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 771 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 772 773 /* Enable fiber mode and autodetection */ 774 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 775 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 776 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 777 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 778 779 /* Enable parallel detection */ 780 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 781 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 782 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 783 784 /* Advertise 2.5G support through next page during autoneg */ 785 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 786 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 787 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 788 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 789 790 /* Increase TX signal amplitude */ 791 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 792 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 793 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 794 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 795 BRGPHY_5708S_TX_MISC_PG5); 796 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 797 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 798 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 799 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 800 BRGPHY_5708S_DIG_PG0); 801 } 802 803 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 804 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 805 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 806 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 807 BRGPHY_5708S_TX_MISC_PG5); 808 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 809 bnx_sc->bnx_port_hw_cfg & 810 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 811 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 812 BRGPHY_5708S_DIG_PG0); 813 } 814 } else 815 #endif 816 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 817 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 818 /* Select the SerDes Digital block of the AN MMD. */ 819 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 820 BRGPHY_BLOCK_ADDR_SERDES_DIG); 821 822 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 823 (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) & 824 ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 825 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 826 827 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 828 /* Select the Over 1G block of the AN MMD. */ 829 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 830 BRGPHY_BLOCK_ADDR_OVER_1G); 831 832 /* 833 * Enable autoneg "Next Page" to advertise 834 * 2.5G support. 835 */ 836 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 837 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) | 838 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 839 } 840 841 /* 842 * Select the Multi-Rate Backplane Ethernet block of 843 * the AN MMD. 844 */ 845 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 846 BRGPHY_BLOCK_ADDR_MRBE); 847 848 /* Enable MRBE speed autoneg. */ 849 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 850 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) | 851 BRGPHY_MRBE_MSG_PG5_NP_MBRE | 852 BRGPHY_MRBE_MSG_PG5_NP_T2); 853 854 /* Select the Clause 73 User B0 block of the AN MMD. */ 855 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 856 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 857 858 /* Enable MRBE speed autoneg. */ 859 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 860 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 861 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 862 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 863 864 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 865 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 866 867 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 868 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 869 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 870 brgphy_disable_early_dac(sc); 871 872 /* Set Jumbo frame settings in the PHY. */ 873 brgphy_jumbo_settings(sc); 874 875 /* Enable Ethernet@Wirespeed */ 876 brgphy_eth_wirespeed(sc); 877 } else { 878 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 879 brgphy_ber_bug(sc); 880 881 /* Set Jumbo frame settings in the PHY. */ 882 brgphy_jumbo_settings(sc); 883 884 /* Enable Ethernet@Wirespeed */ 885 brgphy_eth_wirespeed(sc); 886 } 887 } 888 } 889 } 890 891 /* Turn off tap power management on 5401. */ 892 static void 893 brgphy_bcm5401_dspcode(struct mii_softc *sc) 894 { 895 static const struct { 896 int reg; 897 uint16_t val; 898 } dspcode[] = { 899 { BRGPHY_MII_AUXCTL, 0x0c20 }, 900 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 901 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 902 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 903 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 904 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 905 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 906 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 907 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 908 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 909 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 910 { 0, 0 }, 911 }; 912 int i; 913 914 for (i = 0; dspcode[i].reg != 0; i++) 915 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 916 delay(40); 917 } 918 919 static void 920 brgphy_bcm5411_dspcode(struct mii_softc *sc) 921 { 922 static const struct { 923 int reg; 924 uint16_t val; 925 } dspcode[] = { 926 { 0x1c, 0x8c23 }, 927 { 0x1c, 0x8ca3 }, 928 { 0x1c, 0x8c23 }, 929 { 0, 0 }, 930 }; 931 int i; 932 933 for (i = 0; dspcode[i].reg != 0; i++) 934 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 935 } 936 937 void 938 brgphy_bcm5421_dspcode(struct mii_softc *sc) 939 { 940 uint16_t data; 941 942 /* Set Class A mode */ 943 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 944 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 945 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 946 947 /* Set FFE gamma override to -0.125 */ 948 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 949 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 950 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 951 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 952 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 953 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 954 } 955 956 void 957 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 958 { 959 static const struct { 960 int reg; 961 uint16_t val; 962 } dspcode[] = { 963 { 4, 0x01e1 }, 964 { 9, 0x0300 }, 965 { 0, 0 }, 966 }; 967 int i; 968 969 for (i = 0; dspcode[i].reg != 0; i++) 970 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 971 } 972 973 static void 974 brgphy_adc_bug(struct mii_softc *sc) 975 { 976 static const struct { 977 int reg; 978 uint16_t val; 979 } dspcode[] = { 980 { BRGPHY_MII_AUXCTL, 0x0c00 }, 981 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 982 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 983 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 984 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 985 { BRGPHY_MII_AUXCTL, 0x0400 }, 986 { 0, 0 }, 987 }; 988 int i; 989 990 for (i = 0; dspcode[i].reg != 0; i++) 991 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 992 } 993 994 static void 995 brgphy_5704_a0_bug(struct mii_softc *sc) 996 { 997 static const struct { 998 int reg; 999 uint16_t val; 1000 } dspcode[] = { 1001 { 0x1c, 0x8d68 }, 1002 { 0x1c, 0x8d68 }, 1003 { 0, 0 }, 1004 }; 1005 int i; 1006 1007 for (i = 0; dspcode[i].reg != 0; i++) 1008 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1009 } 1010 1011 static void 1012 brgphy_ber_bug(struct mii_softc *sc) 1013 { 1014 static const struct { 1015 int reg; 1016 uint16_t val; 1017 } dspcode[] = { 1018 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1019 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1020 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1021 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1022 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1023 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1024 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1025 { BRGPHY_MII_AUXCTL, 0x0400 }, 1026 { 0, 0 }, 1027 }; 1028 int i; 1029 1030 for (i = 0; dspcode[i].reg != 0; i++) 1031 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1032 } 1033 1034 /* BCM5701 A0/B0 CRC bug workaround */ 1035 void 1036 brgphy_crc_bug(struct mii_softc *sc) 1037 { 1038 static const struct { 1039 int reg; 1040 uint16_t val; 1041 } dspcode[] = { 1042 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1043 { 0x1c, 0x8c68 }, 1044 { 0x1c, 0x8d68 }, 1045 { 0x1c, 0x8c68 }, 1046 { 0, 0 }, 1047 }; 1048 int i; 1049 1050 for (i = 0; dspcode[i].reg != 0; i++) 1051 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1052 } 1053 1054 static void 1055 brgphy_disable_early_dac(struct mii_softc *sc) 1056 { 1057 uint32_t val; 1058 1059 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1060 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1061 val &= ~(1 << 8); 1062 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1063 1064 } 1065 1066 static void 1067 brgphy_jumbo_settings(struct mii_softc *sc) 1068 { 1069 u_int32_t val; 1070 1071 /* Set Jumbo frame settings in the PHY. */ 1072 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1073 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1074 /* Cannot do read-modify-write on the BCM5401 */ 1075 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1076 } else { 1077 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1078 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1079 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1080 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1081 } 1082 1083 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 1084 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1085 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1086 } 1087 1088 static void 1089 brgphy_eth_wirespeed(struct mii_softc *sc) 1090 { 1091 u_int32_t val; 1092 1093 /* Enable Ethernet@Wirespeed */ 1094 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1095 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1096 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1097 (val | (1 << 15) | (1 << 4))); 1098 } 1099
Indexes created Mon Oct 20 00:09:40 GMT 2025