brgphy.c revision 1.62
1 /* $NetBSD: brgphy.c,v 1.62 2013/03/19 04:10:12 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.62 2013/03/19 04:10:12 msaitoh Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 }; 96 97 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 98 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 99 DVF_DETACH_SHUTDOWN); 100 101 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102 static void brgphy_status(struct mii_softc *); 103 static int brgphy_mii_phy_auto(struct mii_softc *); 104 static void brgphy_loop(struct mii_softc *); 105 static void brgphy_reset(struct mii_softc *); 106 static void brgphy_bcm5401_dspcode(struct mii_softc *); 107 static void brgphy_bcm5411_dspcode(struct mii_softc *); 108 static void brgphy_bcm5421_dspcode(struct mii_softc *); 109 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 110 static void brgphy_adc_bug(struct mii_softc *); 111 static void brgphy_5704_a0_bug(struct mii_softc *); 112 static void brgphy_ber_bug(struct mii_softc *); 113 static void brgphy_crc_bug(struct mii_softc *); 114 static void brgphy_disable_early_dac(struct mii_softc *); 115 static void brgphy_jumbo_settings(struct mii_softc *); 116 static void brgphy_eth_wirespeed(struct mii_softc *); 117 118 119 static const struct mii_phy_funcs brgphy_funcs = { 120 brgphy_service, brgphy_status, brgphy_reset, 121 }; 122 123 static const struct mii_phydesc brgphys[] = { 124 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 125 MII_STR_BROADCOM_BCM5400 }, 126 127 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 128 MII_STR_BROADCOM_BCM5401 }, 129 130 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 131 MII_STR_BROADCOM_BCM5411 }, 132 133 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 134 MII_STR_BROADCOM_BCM5421 }, 135 136 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 137 MII_STR_BROADCOM_BCM5462 }, 138 139 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 140 MII_STR_BROADCOM_BCM5461 }, 141 142 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 143 MII_STR_BROADCOM_BCM54K2 }, 144 145 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 146 MII_STR_BROADCOM_BCM5464 }, 147 148 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 149 MII_STR_BROADCOM_BCM5701 }, 150 151 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 152 MII_STR_BROADCOM_BCM5703 }, 153 154 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 155 MII_STR_BROADCOM_BCM5704 }, 156 157 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 158 MII_STR_BROADCOM_BCM5705 }, 159 160 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 161 MII_STR_BROADCOM_BCM5714 }, 162 163 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 164 MII_STR_BROADCOM_BCM5750 }, 165 166 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 167 MII_STR_BROADCOM_BCM5752 }, 168 169 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 170 MII_STR_BROADCOM_BCM5780 }, 171 172 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 173 MII_STR_BROADCOM_BCM5708C }, 174 175 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 176 MII_STR_BROADCOM2_BCM5481 }, 177 178 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 179 MII_STR_BROADCOM2_BCM5482 }, 180 181 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 182 MII_STR_BROADCOM2_BCM5709C }, 183 184 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 185 MII_STR_BROADCOM2_BCM5709S }, 186 187 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 188 MII_STR_BROADCOM2_BCM5709CAX }, 189 190 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 191 MII_STR_BROADCOM2_BCM5722 }, 192 193 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 194 MII_STR_BROADCOM2_BCM5754 }, 195 196 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 197 MII_STR_BROADCOM2_BCM5755 }, 198 199 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 200 MII_STR_BROADCOM2_BCM5756 }, 201 202 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 203 MII_STR_BROADCOM2_BCM5761 }, 204 205 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 206 MII_STR_BROADCOM2_BCM5784 }, 207 208 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 209 MII_STR_BROADCOM2_BCM5785 }, 210 211 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 212 MII_STR_BROADCOM3_BCM5717C }, 213 214 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 215 MII_STR_BROADCOM3_BCM5719C }, 216 217 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 218 MII_STR_BROADCOM3_BCM5720C }, 219 220 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 221 MII_STR_BROADCOM3_BCM57765 }, 222 223 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 224 MII_STR_BROADCOM3_BCM57780 }, 225 226 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 227 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 228 229 { 0, 0, 230 NULL }, 231 }; 232 233 static int 234 brgphymatch(device_t parent, cfdata_t match, void *aux) 235 { 236 struct mii_attach_args *ma = aux; 237 238 if (mii_phy_match(ma, brgphys) != NULL) 239 return (10); 240 241 return (0); 242 } 243 244 static void 245 brgphyattach(device_t parent, device_t self, void *aux) 246 { 247 struct brgphy_softc *bsc = device_private(self); 248 struct mii_softc *sc = &bsc->sc_mii; 249 struct mii_attach_args *ma = aux; 250 struct mii_data *mii = ma->mii_data; 251 const struct mii_phydesc *mpd; 252 prop_dictionary_t dict; 253 254 mpd = mii_phy_match(ma, brgphys); 255 aprint_naive(": Media interface\n"); 256 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 257 258 sc->mii_dev = self; 259 sc->mii_inst = mii->mii_instance; 260 sc->mii_phy = ma->mii_phyno; 261 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 262 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 263 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 264 sc->mii_pdata = mii; 265 sc->mii_flags = ma->mii_flags; 266 sc->mii_anegticks = MII_ANEGTICKS; 267 sc->mii_funcs = &brgphy_funcs; 268 269 PHY_RESET(sc); 270 271 sc->mii_capabilities = 272 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 273 if (sc->mii_capabilities & BMSR_EXTSTAT) 274 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 275 276 277 if (device_is_a(parent, "bge")) 278 bsc->sc_isbge = true; 279 else if (device_is_a(parent, "bnx")) 280 bsc->sc_isbnx = true; 281 282 if (bsc->sc_isbge || bsc->sc_isbnx) { 283 dict = device_properties(parent); 284 if (!prop_dictionary_get_uint32(dict, "phyflags", 285 &bsc->sc_phyflags)) 286 aprint_error_dev(self, "failed to get phyflags\n"); 287 if (!prop_dictionary_get_uint32(dict, "chipid", 288 &bsc->sc_chipid)) 289 aprint_error_dev(self, "failed to get chipid\n"); 290 } 291 292 aprint_normal_dev(self, ""); 293 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 294 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 295 aprint_error("no media present"); 296 else { 297 if (sc->mii_flags & MIIF_HAVEFIBER) { 298 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 299 300 /* 301 * Set the proper bits for capabilities so that the 302 * correct media get selected by mii_phy_add_media() 303 */ 304 sc->mii_capabilities |= BMSR_ANEG; 305 sc->mii_capabilities &= ~BMSR_100T4; 306 sc->mii_extcapabilities |= EXTSR_1000XFDX; 307 308 if (bsc->sc_isbnx) { 309 /* 310 * 2.5Gb support is a software enabled feature 311 * on the BCM5708S and BCM5709S controllers. 312 */ 313 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 314 if (bsc->sc_phyflags 315 & BNX_PHY_2_5G_CAPABLE_FLAG) { 316 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 317 IFM_FDX, sc->mii_inst), 0); 318 aprint_normal("2500baseSX-FDX, "); 319 #undef ADD 320 } 321 } 322 } 323 mii_phy_add_media(sc); 324 } 325 aprint_normal("\n"); 326 327 } 328 329 static int 330 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 331 { 332 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 333 int reg, speed, gig; 334 335 switch (cmd) { 336 case MII_POLLSTAT: 337 /* 338 * If we're not polling our PHY instance, just return. 339 */ 340 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 341 return (0); 342 break; 343 344 case MII_MEDIACHG: 345 /* 346 * If the media indicates a different PHY instance, 347 * isolate ourselves. 348 */ 349 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 350 reg = PHY_READ(sc, MII_BMCR); 351 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 352 return (0); 353 } 354 355 /* 356 * If the interface is not up, don't do anything. 357 */ 358 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 359 break; 360 361 PHY_RESET(sc); /* XXX hardware bug work-around */ 362 363 switch (IFM_SUBTYPE(ife->ifm_media)) { 364 case IFM_AUTO: 365 (void) brgphy_mii_phy_auto(sc); 366 break; 367 case IFM_1000_T: 368 speed = BMCR_S1000; 369 goto setit; 370 case IFM_100_TX: 371 speed = BMCR_S100; 372 goto setit; 373 case IFM_10_T: 374 speed = BMCR_S10; 375 setit: 376 brgphy_loop(sc); 377 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 378 speed |= BMCR_FDX; 379 gig = GTCR_ADV_1000TFDX; 380 } else { 381 gig = GTCR_ADV_1000THDX; 382 } 383 384 PHY_WRITE(sc, MII_100T2CR, 0); 385 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 386 PHY_WRITE(sc, MII_BMCR, speed); 387 388 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 389 break; 390 391 PHY_WRITE(sc, MII_100T2CR, gig); 392 PHY_WRITE(sc, MII_BMCR, 393 speed|BMCR_AUTOEN|BMCR_STARTNEG); 394 395 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 396 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 397 break; 398 399 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 400 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 401 PHY_WRITE(sc, MII_100T2CR, gig); 402 break; 403 default: 404 return (EINVAL); 405 } 406 break; 407 408 case MII_TICK: 409 /* 410 * If we're not currently selected, just return. 411 */ 412 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 413 return (0); 414 415 if (mii_phy_tick(sc) == EJUSTRETURN) 416 return (0); 417 break; 418 419 case MII_DOWN: 420 mii_phy_down(sc); 421 return (0); 422 } 423 424 /* Update the media status. */ 425 mii_phy_status(sc); 426 427 /* 428 * Callback if something changed. Note that we need to poke the DSP on 429 * the Broadcom PHYs if the media changes. 430 */ 431 if (sc->mii_media_active != mii->mii_media_active || 432 sc->mii_media_status != mii->mii_media_status || 433 cmd == MII_MEDIACHG) { 434 switch (sc->mii_mpd_oui) { 435 case MII_OUI_BROADCOM: 436 switch (sc->mii_mpd_model) { 437 case MII_MODEL_BROADCOM_BCM5400: 438 brgphy_bcm5401_dspcode(sc); 439 break; 440 case MII_MODEL_BROADCOM_BCM5401: 441 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 442 brgphy_bcm5401_dspcode(sc); 443 break; 444 case MII_MODEL_BROADCOM_BCM5411: 445 brgphy_bcm5411_dspcode(sc); 446 break; 447 } 448 break; 449 } 450 } 451 452 /* Callback if something changed. */ 453 mii_phy_update(sc, cmd); 454 return (0); 455 } 456 457 static void 458 brgphy_status(struct mii_softc *sc) 459 { 460 struct mii_data *mii = sc->mii_pdata; 461 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 462 int bmcr, bmsr, auxsts, gtsr; 463 464 mii->mii_media_status = IFM_AVALID; 465 mii->mii_media_active = IFM_ETHER; 466 467 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 468 if (bmsr & BMSR_LINK) 469 mii->mii_media_status |= IFM_ACTIVE; 470 471 bmcr = PHY_READ(sc, MII_BMCR); 472 if (bmcr & BMCR_ISO) { 473 mii->mii_media_active |= IFM_NONE; 474 mii->mii_media_status = 0; 475 return; 476 } 477 478 if (bmcr & BMCR_LOOP) 479 mii->mii_media_active |= IFM_LOOP; 480 481 if (bmcr & BMCR_AUTOEN) { 482 /* 483 * The media status bits are only valid of autonegotiation 484 * has completed (or it's disabled). 485 */ 486 if ((bmsr & BMSR_ACOMP) == 0) { 487 /* Erg, still trying, I guess... */ 488 mii->mii_media_active |= IFM_NONE; 489 return; 490 } 491 492 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 493 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 494 /* 495 * 5709S has its own general purpose status registers 496 */ 497 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 498 BRGPHY_BLOCK_ADDR_GP_STATUS); 499 500 auxsts = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 501 502 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 503 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 504 505 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 506 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 507 mii->mii_media_active |= IFM_10_FL; 508 break; 509 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 510 mii->mii_media_active |= IFM_100_FX; 511 break; 512 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 513 mii->mii_media_active |= IFM_1000_SX; 514 break; 515 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 516 mii->mii_media_active |= IFM_2500_SX; 517 break; 518 default: 519 mii->mii_media_active |= IFM_NONE; 520 mii->mii_media_status = 0; 521 break; 522 } 523 524 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 525 mii->mii_media_active |= IFM_FDX; 526 else 527 mii->mii_media_active |= IFM_HDX; 528 529 } else { 530 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 531 532 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 533 case BRGPHY_RES_1000FD: 534 mii->mii_media_active |= IFM_1000_T|IFM_FDX; 535 gtsr = PHY_READ(sc, MII_100T2SR); 536 if (gtsr & GTSR_MS_RES) 537 mii->mii_media_active |= IFM_ETH_MASTER; 538 break; 539 540 case BRGPHY_RES_1000HD: 541 mii->mii_media_active |= IFM_1000_T; 542 gtsr = PHY_READ(sc, MII_100T2SR); 543 if (gtsr & GTSR_MS_RES) 544 mii->mii_media_active |= IFM_ETH_MASTER; 545 break; 546 547 case BRGPHY_RES_100FD: 548 mii->mii_media_active |= IFM_100_TX|IFM_FDX; 549 break; 550 551 case BRGPHY_RES_100T4: 552 mii->mii_media_active |= IFM_100_T4; 553 break; 554 555 case BRGPHY_RES_100HD: 556 mii->mii_media_active |= IFM_100_TX; 557 break; 558 559 case BRGPHY_RES_10FD: 560 mii->mii_media_active |= IFM_10_T|IFM_FDX; 561 break; 562 563 case BRGPHY_RES_10HD: 564 mii->mii_media_active |= IFM_10_T; 565 break; 566 567 default: 568 mii->mii_media_active |= IFM_NONE; 569 mii->mii_media_status = 0; 570 } 571 } 572 573 if (mii->mii_media_active & IFM_FDX) 574 mii->mii_media_active |= mii_phy_flowstatus(sc); 575 576 } else 577 mii->mii_media_active = ife->ifm_media; 578 } 579 580 int 581 brgphy_mii_phy_auto(struct mii_softc *sc) 582 { 583 int anar, ktcr = 0; 584 585 brgphy_loop(sc); 586 PHY_RESET(sc); 587 588 ktcr = GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX; 589 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 590 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 591 ktcr |= GTCR_MAN_MS|GTCR_ADV_MS; 592 PHY_WRITE(sc, MII_100T2CR, ktcr); 593 ktcr = PHY_READ(sc, MII_100T2CR); 594 DELAY(1000); 595 596 if (sc->mii_flags & MIIF_HAVEFIBER) { 597 anar = ANAR_X_FD | ANAR_X_HD; 598 if (sc->mii_flags & MIIF_DOPAUSE) 599 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 600 } else { 601 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 602 if (sc->mii_flags & MIIF_DOPAUSE) 603 anar |= ANAR_FC | ANAR_X_PAUSE_ASYM; 604 } 605 PHY_WRITE(sc, MII_ANAR, anar); 606 DELAY(1000); 607 608 /* Start autonegotiation */ 609 PHY_WRITE(sc, MII_BMCR, 610 BMCR_AUTOEN | BMCR_STARTNEG); 611 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 612 613 return (EJUSTRETURN); 614 } 615 616 void 617 brgphy_loop(struct mii_softc *sc) 618 { 619 u_int32_t bmsr; 620 int i; 621 622 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 623 for (i = 0; i < 15000; i++) { 624 bmsr = PHY_READ(sc, MII_BMSR); 625 if (!(bmsr & BMSR_LINK)) 626 break; 627 DELAY(10); 628 } 629 } 630 631 static void 632 brgphy_reset(struct mii_softc *sc) 633 { 634 struct brgphy_softc *bsc = device_private(sc->mii_dev); 635 636 mii_phy_reset(sc); 637 switch (sc->mii_mpd_oui) { 638 case MII_OUI_BROADCOM: 639 switch (sc->mii_mpd_model) { 640 case MII_MODEL_BROADCOM_BCM5400: 641 brgphy_bcm5401_dspcode(sc); 642 break; 643 case MII_MODEL_BROADCOM_BCM5401: 644 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 645 brgphy_bcm5401_dspcode(sc); 646 break; 647 case MII_MODEL_BROADCOM_BCM5411: 648 brgphy_bcm5411_dspcode(sc); 649 break; 650 case MII_MODEL_BROADCOM_BCM5421: 651 brgphy_bcm5421_dspcode(sc); 652 break; 653 case MII_MODEL_BROADCOM_BCM54K2: 654 brgphy_bcm54k2_dspcode(sc); 655 break; 656 } 657 break; 658 case MII_OUI_BROADCOM3: 659 switch (sc->mii_mpd_model) { 660 case MII_MODEL_BROADCOM3_BCM5717C: 661 case MII_MODEL_BROADCOM3_BCM5719C: 662 case MII_MODEL_BROADCOM3_BCM5720C: 663 case MII_MODEL_BROADCOM3_BCM57765: 664 return; 665 } 666 break; 667 default: 668 break; 669 } 670 671 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 672 if (bsc->sc_isbge) { 673 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 674 675 if (bsc->sc_phyflags & BGE_PHY_ADC_BUG) 676 brgphy_adc_bug(sc); 677 if (bsc->sc_phyflags & BGE_PHY_5704_A0_BUG) 678 brgphy_5704_a0_bug(sc); 679 if (bsc->sc_phyflags & BGE_PHY_BER_BUG) 680 brgphy_ber_bug(sc); 681 else if (bsc->sc_phyflags & BGE_PHY_JITTER_BUG) { 682 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 683 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 684 0x000a); 685 686 if (bsc->sc_phyflags 687 & BGE_PHY_ADJUST_TRIM) { 688 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 689 0x110b); 690 PHY_WRITE(sc, BRGPHY_TEST1, 691 BRGPHY_TEST1_TRIM_EN | 0x4); 692 } else { 693 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 694 0x010b); 695 } 696 697 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 698 } 699 if (bsc->sc_phyflags & BGE_PHY_CRC_BUG) 700 brgphy_crc_bug(sc); 701 702 /* Set Jumbo frame settings in the PHY. */ 703 if (bsc->sc_phyflags & BGE_JUMBO_CAPABLE) 704 brgphy_jumbo_settings(sc); 705 706 /* Adjust output voltage */ 707 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 708 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 709 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 710 711 /* Enable Ethernet@Wirespeed */ 712 if (!(bsc->sc_phyflags & BGE_PHY_NO_WIRESPEED)) 713 brgphy_eth_wirespeed(sc); 714 715 #if 0 716 /* Enable Link LED on Dell boxes */ 717 if (bsc->sc_phyflags & BGE_PHY_NO_3LED) { 718 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 719 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 720 & ~BRGPHY_PHY_EXTCTL_3_LED); 721 } 722 #endif 723 } 724 /* Handle any bnx (NetXtreme II) workarounds. */ 725 } else if (bsc->sc_isbnx) { 726 #if 0 /* not yet */ 727 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 728 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 729 /* Store autoneg capabilities/results in digital block (Page 0) */ 730 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 731 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 732 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 733 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 734 735 /* Enable fiber mode and autodetection */ 736 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 737 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 738 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 739 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 740 741 /* Enable parallel detection */ 742 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 743 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 744 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 745 746 /* Advertise 2.5G support through next page during autoneg */ 747 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 748 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 749 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 750 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 751 752 /* Increase TX signal amplitude */ 753 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 754 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 755 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 756 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 757 BRGPHY_5708S_TX_MISC_PG5); 758 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 759 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 760 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 761 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 762 BRGPHY_5708S_DIG_PG0); 763 } 764 765 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 766 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 767 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 768 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 769 BRGPHY_5708S_TX_MISC_PG5); 770 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 771 bnx_sc->bnx_port_hw_cfg & 772 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 773 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 774 BRGPHY_5708S_DIG_PG0); 775 } 776 } else 777 #endif 778 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 779 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 780 /* Select the SerDes Digital block of the AN MMD. */ 781 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 782 BRGPHY_BLOCK_ADDR_SERDES_DIG); 783 784 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 785 (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) & 786 ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 787 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 788 789 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 790 /* Select the Over 1G block of the AN MMD. */ 791 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 792 BRGPHY_BLOCK_ADDR_OVER_1G); 793 794 /* 795 * Enable autoneg "Next Page" to advertise 796 * 2.5G support. 797 */ 798 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 799 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) | 800 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 801 } 802 803 /* 804 * Select the Multi-Rate Backplane Ethernet block of 805 * the AN MMD. 806 */ 807 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 808 BRGPHY_BLOCK_ADDR_MRBE); 809 810 /* Enable MRBE speed autoneg. */ 811 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 812 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) | 813 BRGPHY_MRBE_MSG_PG5_NP_MBRE | 814 BRGPHY_MRBE_MSG_PG5_NP_T2); 815 816 /* Select the Clause 73 User B0 block of the AN MMD. */ 817 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 818 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 819 820 /* Enable MRBE speed autoneg. */ 821 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 822 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 823 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 824 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 825 826 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 827 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 828 829 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 830 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 831 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 832 brgphy_disable_early_dac(sc); 833 834 /* Set Jumbo frame settings in the PHY. */ 835 brgphy_jumbo_settings(sc); 836 837 /* Enable Ethernet@Wirespeed */ 838 brgphy_eth_wirespeed(sc); 839 } else { 840 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 841 brgphy_ber_bug(sc); 842 843 /* Set Jumbo frame settings in the PHY. */ 844 brgphy_jumbo_settings(sc); 845 846 /* Enable Ethernet@Wirespeed */ 847 brgphy_eth_wirespeed(sc); 848 } 849 } 850 } 851 } 852 853 /* Turn off tap power management on 5401. */ 854 static void 855 brgphy_bcm5401_dspcode(struct mii_softc *sc) 856 { 857 static const struct { 858 int reg; 859 uint16_t val; 860 } dspcode[] = { 861 { BRGPHY_MII_AUXCTL, 0x0c20 }, 862 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 863 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 864 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 865 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 866 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 867 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 868 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 869 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 870 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 871 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 872 { 0, 0 }, 873 }; 874 int i; 875 876 for (i = 0; dspcode[i].reg != 0; i++) 877 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 878 delay(40); 879 } 880 881 static void 882 brgphy_bcm5411_dspcode(struct mii_softc *sc) 883 { 884 static const struct { 885 int reg; 886 uint16_t val; 887 } dspcode[] = { 888 { 0x1c, 0x8c23 }, 889 { 0x1c, 0x8ca3 }, 890 { 0x1c, 0x8c23 }, 891 { 0, 0 }, 892 }; 893 int i; 894 895 for (i = 0; dspcode[i].reg != 0; i++) 896 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 897 } 898 899 void 900 brgphy_bcm5421_dspcode(struct mii_softc *sc) 901 { 902 uint16_t data; 903 904 /* Set Class A mode */ 905 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 906 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 907 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 908 909 /* Set FFE gamma override to -0.125 */ 910 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 911 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 912 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 913 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 914 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 915 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 916 } 917 918 void 919 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 920 { 921 static const struct { 922 int reg; 923 uint16_t val; 924 } dspcode[] = { 925 { 4, 0x01e1 }, 926 { 9, 0x0300 }, 927 { 0, 0 }, 928 }; 929 int i; 930 931 for (i = 0; dspcode[i].reg != 0; i++) 932 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 933 } 934 935 static void 936 brgphy_adc_bug(struct mii_softc *sc) 937 { 938 static const struct { 939 int reg; 940 uint16_t val; 941 } dspcode[] = { 942 { BRGPHY_MII_AUXCTL, 0x0c00 }, 943 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 944 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 945 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 946 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 947 { BRGPHY_MII_AUXCTL, 0x0400 }, 948 { 0, 0 }, 949 }; 950 int i; 951 952 for (i = 0; dspcode[i].reg != 0; i++) 953 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 954 } 955 956 static void 957 brgphy_5704_a0_bug(struct mii_softc *sc) 958 { 959 static const struct { 960 int reg; 961 uint16_t val; 962 } dspcode[] = { 963 { 0x1c, 0x8d68 }, 964 { 0x1c, 0x8d68 }, 965 { 0, 0 }, 966 }; 967 int i; 968 969 for (i = 0; dspcode[i].reg != 0; i++) 970 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 971 } 972 973 static void 974 brgphy_ber_bug(struct mii_softc *sc) 975 { 976 static const struct { 977 int reg; 978 uint16_t val; 979 } dspcode[] = { 980 { BRGPHY_MII_AUXCTL, 0x0c00 }, 981 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 982 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 983 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 984 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 985 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 986 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 987 { BRGPHY_MII_AUXCTL, 0x0400 }, 988 { 0, 0 }, 989 }; 990 int i; 991 992 for (i = 0; dspcode[i].reg != 0; i++) 993 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 994 } 995 996 /* BCM5701 A0/B0 CRC bug workaround */ 997 void 998 brgphy_crc_bug(struct mii_softc *sc) 999 { 1000 static const struct { 1001 int reg; 1002 uint16_t val; 1003 } dspcode[] = { 1004 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1005 { 0x1c, 0x8c68 }, 1006 { 0x1c, 0x8d68 }, 1007 { 0x1c, 0x8c68 }, 1008 { 0, 0 }, 1009 }; 1010 int i; 1011 1012 for (i = 0; dspcode[i].reg != 0; i++) 1013 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1014 } 1015 1016 static void 1017 brgphy_disable_early_dac(struct mii_softc *sc) 1018 { 1019 uint32_t val; 1020 1021 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1022 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1023 val &= ~(1 << 8); 1024 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1025 1026 } 1027 1028 static void 1029 brgphy_jumbo_settings(struct mii_softc *sc) 1030 { 1031 u_int32_t val; 1032 1033 /* Set Jumbo frame settings in the PHY. */ 1034 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1035 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1036 /* Cannot do read-modify-write on the BCM5401 */ 1037 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1038 } else { 1039 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1040 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1041 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1042 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1043 } 1044 1045 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 1046 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1047 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1048 } 1049 1050 static void 1051 brgphy_eth_wirespeed(struct mii_softc *sc) 1052 { 1053 u_int32_t val; 1054 1055 /* Enable Ethernet@Wirespeed */ 1056 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1057 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1058 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1059 (val | (1 << 15) | (1 << 4))); 1060 } 1061
Indexes created Thu Sep 25 16:09:42 GMT 2025