brgphy.c revision 1.69
1 /* $NetBSD: brgphy.c,v 1.69 2014/06/12 12:09:47 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.69 2014/06/12 12:09:47 msaitoh Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 }; 96 97 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 98 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 99 DVF_DETACH_SHUTDOWN); 100 101 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102 static void brgphy_status(struct mii_softc *); 103 static int brgphy_mii_phy_auto(struct mii_softc *); 104 static void brgphy_loop(struct mii_softc *); 105 static void brgphy_reset(struct mii_softc *); 106 static void brgphy_bcm5401_dspcode(struct mii_softc *); 107 static void brgphy_bcm5411_dspcode(struct mii_softc *); 108 static void brgphy_bcm5421_dspcode(struct mii_softc *); 109 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 110 static void brgphy_adc_bug(struct mii_softc *); 111 static void brgphy_5704_a0_bug(struct mii_softc *); 112 static void brgphy_ber_bug(struct mii_softc *); 113 static void brgphy_crc_bug(struct mii_softc *); 114 static void brgphy_disable_early_dac(struct mii_softc *); 115 static void brgphy_jumbo_settings(struct mii_softc *); 116 static void brgphy_eth_wirespeed(struct mii_softc *); 117 118 119 static const struct mii_phy_funcs brgphy_funcs = { 120 brgphy_service, brgphy_status, brgphy_reset, 121 }; 122 123 static const struct mii_phydesc brgphys[] = { 124 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 125 MII_STR_BROADCOM_BCM5400 }, 126 127 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 128 MII_STR_BROADCOM_BCM5401 }, 129 130 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 131 MII_STR_BROADCOM_BCM5411 }, 132 133 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 134 MII_STR_BROADCOM_BCM5421 }, 135 136 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 137 MII_STR_BROADCOM_BCM5462 }, 138 139 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 140 MII_STR_BROADCOM_BCM5461 }, 141 142 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 143 MII_STR_BROADCOM_BCM54K2 }, 144 145 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 146 MII_STR_BROADCOM_BCM5464 }, 147 148 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 149 MII_STR_BROADCOM_BCM5701 }, 150 151 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 152 MII_STR_BROADCOM_BCM5703 }, 153 154 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 155 MII_STR_BROADCOM_BCM5704 }, 156 157 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 158 MII_STR_BROADCOM_BCM5705 }, 159 160 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 161 MII_STR_BROADCOM_BCM5714 }, 162 163 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 164 MII_STR_BROADCOM_BCM5750 }, 165 166 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 167 MII_STR_BROADCOM_BCM5752 }, 168 169 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 170 MII_STR_BROADCOM_BCM5780 }, 171 172 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 173 MII_STR_BROADCOM_BCM5708C }, 174 175 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 176 MII_STR_BROADCOM2_BCM5481 }, 177 178 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 179 MII_STR_BROADCOM2_BCM5482 }, 180 181 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 182 MII_STR_BROADCOM2_BCM5709C }, 183 184 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 185 MII_STR_BROADCOM2_BCM5709S }, 186 187 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 188 MII_STR_BROADCOM2_BCM5709CAX }, 189 190 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 191 MII_STR_BROADCOM2_BCM5722 }, 192 193 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 194 MII_STR_BROADCOM2_BCM5754 }, 195 196 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 197 MII_STR_BROADCOM2_BCM5755 }, 198 199 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 200 MII_STR_BROADCOM2_BCM5756 }, 201 202 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 203 MII_STR_BROADCOM2_BCM5761 }, 204 205 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 206 MII_STR_BROADCOM2_BCM5784 }, 207 208 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 209 MII_STR_BROADCOM2_BCM5785 }, 210 211 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 212 MII_STR_BROADCOM3_BCM5717C }, 213 214 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 215 MII_STR_BROADCOM3_BCM5719C }, 216 217 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 218 MII_STR_BROADCOM3_BCM5720C }, 219 220 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 221 MII_STR_BROADCOM3_BCM57765 }, 222 223 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 224 MII_STR_BROADCOM3_BCM57780 }, 225 226 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 227 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 228 229 { 0, 0, 230 NULL }, 231 }; 232 233 static int 234 brgphymatch(device_t parent, cfdata_t match, void *aux) 235 { 236 struct mii_attach_args *ma = aux; 237 238 if (mii_phy_match(ma, brgphys) != NULL) 239 return (10); 240 241 return (0); 242 } 243 244 static void 245 brgphyattach(device_t parent, device_t self, void *aux) 246 { 247 struct brgphy_softc *bsc = device_private(self); 248 struct mii_softc *sc = &bsc->sc_mii; 249 struct mii_attach_args *ma = aux; 250 struct mii_data *mii = ma->mii_data; 251 const struct mii_phydesc *mpd; 252 prop_dictionary_t dict; 253 254 mpd = mii_phy_match(ma, brgphys); 255 aprint_naive(": Media interface\n"); 256 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 257 258 sc->mii_dev = self; 259 sc->mii_inst = mii->mii_instance; 260 sc->mii_phy = ma->mii_phyno; 261 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 262 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 263 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 264 sc->mii_pdata = mii; 265 sc->mii_flags = ma->mii_flags; 266 sc->mii_anegticks = MII_ANEGTICKS; 267 sc->mii_funcs = &brgphy_funcs; 268 269 if (device_is_a(parent, "bge")) 270 bsc->sc_isbge = true; 271 else if (device_is_a(parent, "bnx")) 272 bsc->sc_isbnx = true; 273 274 if (bsc->sc_isbge || bsc->sc_isbnx) { 275 dict = device_properties(parent); 276 if (!prop_dictionary_get_uint32(dict, "phyflags", 277 &bsc->sc_phyflags)) 278 aprint_error_dev(self, "failed to get phyflags\n"); 279 if (!prop_dictionary_get_uint32(dict, "chipid", 280 &bsc->sc_chipid)) 281 aprint_error_dev(self, "failed to get chipid\n"); 282 } 283 284 PHY_RESET(sc); 285 286 sc->mii_capabilities = 287 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 288 if (sc->mii_capabilities & BMSR_EXTSTAT) 289 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 290 291 aprint_normal_dev(self, ""); 292 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 293 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 294 aprint_error("no media present"); 295 else { 296 if (sc->mii_flags & MIIF_HAVEFIBER) { 297 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 298 299 /* 300 * Set the proper bits for capabilities so that the 301 * correct media get selected by mii_phy_add_media() 302 */ 303 sc->mii_capabilities |= BMSR_ANEG; 304 sc->mii_capabilities &= ~BMSR_100T4; 305 sc->mii_extcapabilities |= EXTSR_1000XFDX; 306 307 if (bsc->sc_isbnx) { 308 /* 309 * 2.5Gb support is a software enabled feature 310 * on the BCM5708S and BCM5709S controllers. 311 */ 312 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 313 if (bsc->sc_phyflags 314 & BNX_PHY_2_5G_CAPABLE_FLAG) { 315 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 316 IFM_FDX, sc->mii_inst), 0); 317 aprint_normal("2500baseSX-FDX, "); 318 #undef ADD 319 } 320 } 321 } 322 mii_phy_add_media(sc); 323 } 324 aprint_normal("\n"); 325 326 } 327 328 static int 329 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 330 { 331 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 332 int reg, speed, gig; 333 334 switch (cmd) { 335 case MII_POLLSTAT: 336 /* 337 * If we're not polling our PHY instance, just return. 338 */ 339 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 340 return (0); 341 break; 342 343 case MII_MEDIACHG: 344 /* 345 * If the media indicates a different PHY instance, 346 * isolate ourselves. 347 */ 348 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 349 reg = PHY_READ(sc, MII_BMCR); 350 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 351 return (0); 352 } 353 354 /* 355 * If the interface is not up, don't do anything. 356 */ 357 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 358 break; 359 360 PHY_RESET(sc); /* XXX hardware bug work-around */ 361 362 switch (IFM_SUBTYPE(ife->ifm_media)) { 363 case IFM_AUTO: 364 (void) brgphy_mii_phy_auto(sc); 365 break; 366 case IFM_1000_T: 367 speed = BMCR_S1000; 368 goto setit; 369 case IFM_100_TX: 370 speed = BMCR_S100; 371 goto setit; 372 case IFM_10_T: 373 speed = BMCR_S10; 374 setit: 375 brgphy_loop(sc); 376 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 377 speed |= BMCR_FDX; 378 gig = GTCR_ADV_1000TFDX; 379 } else 380 gig = GTCR_ADV_1000THDX; 381 382 PHY_WRITE(sc, MII_100T2CR, 0); 383 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 384 PHY_WRITE(sc, MII_BMCR, speed); 385 386 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 387 break; 388 389 PHY_WRITE(sc, MII_100T2CR, gig); 390 PHY_WRITE(sc, MII_BMCR, 391 speed | BMCR_AUTOEN | BMCR_STARTNEG); 392 393 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 394 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 395 break; 396 397 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 398 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 399 PHY_WRITE(sc, MII_100T2CR, gig); 400 break; 401 default: 402 return (EINVAL); 403 } 404 break; 405 406 case MII_TICK: 407 /* 408 * If we're not currently selected, just return. 409 */ 410 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 411 return (0); 412 413 /* 414 * Is the interface even up? 415 */ 416 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 417 return 0; 418 419 /* 420 * Only used for autonegotiation. 421 */ 422 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 423 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 424 sc->mii_ticks = 0; 425 break; 426 } 427 428 /* 429 * Check for link. 430 * Read the status register twice; BMSR_LINK is latch-low. 431 */ 432 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 433 if (reg & BMSR_LINK) { 434 sc->mii_ticks = 0; 435 break; 436 } 437 438 /* 439 * mii_ticks == 0 means it's the first tick after changing the 440 * media or the link became down since the last tick 441 * (see above), so break to update the status. 442 */ 443 if (sc->mii_ticks++ == 0) 444 break; 445 446 /* 447 * Only retry autonegotiation every mii_anegticks seconds. 448 */ 449 KASSERT(sc->mii_anegticks != 0); 450 if (sc->mii_ticks <= sc->mii_anegticks) 451 break; 452 453 brgphy_mii_phy_auto(sc); 454 break; 455 456 case MII_DOWN: 457 mii_phy_down(sc); 458 return (0); 459 } 460 461 /* Update the media status. */ 462 mii_phy_status(sc); 463 464 /* 465 * Callback if something changed. Note that we need to poke the DSP on 466 * the Broadcom PHYs if the media changes. 467 */ 468 if (sc->mii_media_active != mii->mii_media_active || 469 sc->mii_media_status != mii->mii_media_status || 470 cmd == MII_MEDIACHG) { 471 switch (sc->mii_mpd_oui) { 472 case MII_OUI_BROADCOM: 473 switch (sc->mii_mpd_model) { 474 case MII_MODEL_BROADCOM_BCM5400: 475 brgphy_bcm5401_dspcode(sc); 476 break; 477 case MII_MODEL_BROADCOM_BCM5401: 478 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 479 brgphy_bcm5401_dspcode(sc); 480 break; 481 case MII_MODEL_BROADCOM_BCM5411: 482 brgphy_bcm5411_dspcode(sc); 483 break; 484 } 485 break; 486 } 487 } 488 489 /* Callback if something changed. */ 490 mii_phy_update(sc, cmd); 491 return (0); 492 } 493 494 static void 495 brgphy_status(struct mii_softc *sc) 496 { 497 struct mii_data *mii = sc->mii_pdata; 498 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 499 int bmcr, bmsr, auxsts, gtsr; 500 501 mii->mii_media_status = IFM_AVALID; 502 mii->mii_media_active = IFM_ETHER; 503 504 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 505 if (bmsr & BMSR_LINK) 506 mii->mii_media_status |= IFM_ACTIVE; 507 508 bmcr = PHY_READ(sc, MII_BMCR); 509 if (bmcr & BMCR_ISO) { 510 mii->mii_media_active |= IFM_NONE; 511 mii->mii_media_status = 0; 512 return; 513 } 514 515 if (bmcr & BMCR_LOOP) 516 mii->mii_media_active |= IFM_LOOP; 517 518 if (bmcr & BMCR_AUTOEN) { 519 /* 520 * The media status bits are only valid of autonegotiation 521 * has completed (or it's disabled). 522 */ 523 if ((bmsr & BMSR_ACOMP) == 0) { 524 /* Erg, still trying, I guess... */ 525 mii->mii_media_active |= IFM_NONE; 526 return; 527 } 528 529 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 530 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 531 /* 532 * 5709S has its own general purpose status registers 533 */ 534 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 535 BRGPHY_BLOCK_ADDR_GP_STATUS); 536 537 auxsts = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 538 539 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 540 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 541 542 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 543 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 544 mii->mii_media_active |= IFM_10_FL; 545 break; 546 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 547 mii->mii_media_active |= IFM_100_FX; 548 break; 549 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 550 mii->mii_media_active |= IFM_1000_SX; 551 break; 552 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 553 mii->mii_media_active |= IFM_2500_SX; 554 break; 555 default: 556 mii->mii_media_active |= IFM_NONE; 557 mii->mii_media_status = 0; 558 break; 559 } 560 561 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 562 mii->mii_media_active |= IFM_FDX; 563 else 564 mii->mii_media_active |= IFM_HDX; 565 566 } else { 567 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 568 569 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 570 case BRGPHY_RES_1000FD: 571 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 572 gtsr = PHY_READ(sc, MII_100T2SR); 573 if (gtsr & GTSR_MS_RES) 574 mii->mii_media_active |= IFM_ETH_MASTER; 575 break; 576 577 case BRGPHY_RES_1000HD: 578 mii->mii_media_active |= IFM_1000_T; 579 gtsr = PHY_READ(sc, MII_100T2SR); 580 if (gtsr & GTSR_MS_RES) 581 mii->mii_media_active |= IFM_ETH_MASTER; 582 break; 583 584 case BRGPHY_RES_100FD: 585 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 586 break; 587 588 case BRGPHY_RES_100T4: 589 mii->mii_media_active |= IFM_100_T4; 590 break; 591 592 case BRGPHY_RES_100HD: 593 mii->mii_media_active |= IFM_100_TX; 594 break; 595 596 case BRGPHY_RES_10FD: 597 mii->mii_media_active |= IFM_10_T | IFM_FDX; 598 break; 599 600 case BRGPHY_RES_10HD: 601 mii->mii_media_active |= IFM_10_T; 602 break; 603 604 default: 605 mii->mii_media_active |= IFM_NONE; 606 mii->mii_media_status = 0; 607 } 608 } 609 610 if (mii->mii_media_active & IFM_FDX) 611 mii->mii_media_active |= mii_phy_flowstatus(sc); 612 613 } else 614 mii->mii_media_active = ife->ifm_media; 615 } 616 617 int 618 brgphy_mii_phy_auto(struct mii_softc *sc) 619 { 620 int anar, ktcr = 0; 621 622 sc->mii_ticks = 0; 623 brgphy_loop(sc); 624 PHY_RESET(sc); 625 626 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 627 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 628 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 629 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 630 PHY_WRITE(sc, MII_100T2CR, ktcr); 631 ktcr = PHY_READ(sc, MII_100T2CR); 632 DELAY(1000); 633 634 if (sc->mii_flags & MIIF_HAVEFIBER) { 635 anar = ANAR_X_FD | ANAR_X_HD; 636 if (sc->mii_flags & MIIF_DOPAUSE) 637 anar |= ANAR_X_PAUSE_TOWARDS; 638 } else { 639 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 640 if (sc->mii_flags & MIIF_DOPAUSE) 641 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 642 } 643 PHY_WRITE(sc, MII_ANAR, anar); 644 DELAY(1000); 645 646 /* Start autonegotiation */ 647 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 648 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 649 650 return (EJUSTRETURN); 651 } 652 653 void 654 brgphy_loop(struct mii_softc *sc) 655 { 656 u_int32_t bmsr; 657 int i; 658 659 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 660 for (i = 0; i < 15000; i++) { 661 bmsr = PHY_READ(sc, MII_BMSR); 662 if (!(bmsr & BMSR_LINK)) 663 break; 664 DELAY(10); 665 } 666 } 667 668 static void 669 brgphy_reset(struct mii_softc *sc) 670 { 671 struct brgphy_softc *bsc = device_private(sc->mii_dev); 672 673 mii_phy_reset(sc); 674 switch (sc->mii_mpd_oui) { 675 case MII_OUI_BROADCOM: 676 switch (sc->mii_mpd_model) { 677 case MII_MODEL_BROADCOM_BCM5400: 678 brgphy_bcm5401_dspcode(sc); 679 break; 680 case MII_MODEL_BROADCOM_BCM5401: 681 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 682 brgphy_bcm5401_dspcode(sc); 683 break; 684 case MII_MODEL_BROADCOM_BCM5411: 685 brgphy_bcm5411_dspcode(sc); 686 break; 687 case MII_MODEL_BROADCOM_BCM5421: 688 brgphy_bcm5421_dspcode(sc); 689 break; 690 case MII_MODEL_BROADCOM_BCM54K2: 691 brgphy_bcm54k2_dspcode(sc); 692 break; 693 } 694 break; 695 case MII_OUI_BROADCOM3: 696 switch (sc->mii_mpd_model) { 697 case MII_MODEL_BROADCOM3_BCM5717C: 698 case MII_MODEL_BROADCOM3_BCM5719C: 699 case MII_MODEL_BROADCOM3_BCM5720C: 700 case MII_MODEL_BROADCOM3_BCM57765: 701 return; 702 } 703 break; 704 default: 705 break; 706 } 707 708 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 709 if (bsc->sc_isbge) { 710 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 711 712 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 713 brgphy_adc_bug(sc); 714 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 715 brgphy_5704_a0_bug(sc); 716 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 717 brgphy_ber_bug(sc); 718 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 719 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 720 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 721 0x000a); 722 723 if (bsc->sc_phyflags 724 & BGEPHYF_ADJUST_TRIM) { 725 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 726 0x110b); 727 PHY_WRITE(sc, BRGPHY_TEST1, 728 BRGPHY_TEST1_TRIM_EN | 0x4); 729 } else { 730 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 731 0x010b); 732 } 733 734 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 735 } 736 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 737 brgphy_crc_bug(sc); 738 739 /* Set Jumbo frame settings in the PHY. */ 740 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 741 brgphy_jumbo_settings(sc); 742 743 /* Adjust output voltage */ 744 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 745 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 746 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 747 748 /* Enable Ethernet@Wirespeed */ 749 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 750 brgphy_eth_wirespeed(sc); 751 752 #if 0 753 /* Enable Link LED on Dell boxes */ 754 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 755 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 756 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 757 & ~BRGPHY_PHY_EXTCTL_3_LED); 758 } 759 #endif 760 } 761 /* Handle any bnx (NetXtreme II) workarounds. */ 762 } else if (bsc->sc_isbnx) { 763 #if 0 /* not yet */ 764 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 765 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 766 /* Store autoneg capabilities/results in digital block (Page 0) */ 767 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 768 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 769 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 770 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 771 772 /* Enable fiber mode and autodetection */ 773 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 774 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 775 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 776 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 777 778 /* Enable parallel detection */ 779 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 780 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 781 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 782 783 /* Advertise 2.5G support through next page during autoneg */ 784 if (bnx_sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) 785 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 786 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 787 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 788 789 /* Increase TX signal amplitude */ 790 if ((BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_A0) || 791 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B0) || 792 (BNX_CHIP_ID(bnx_sc) == BNX_CHIP_ID_5708_B1)) { 793 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 794 BRGPHY_5708S_TX_MISC_PG5); 795 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 796 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 797 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 798 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 799 BRGPHY_5708S_DIG_PG0); 800 } 801 802 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 803 if ((bnx_sc->bnx_shared_hw_cfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 804 (bnx_sc->bnx_port_hw_cfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 805 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 806 BRGPHY_5708S_TX_MISC_PG5); 807 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 808 bnx_sc->bnx_port_hw_cfg & 809 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 810 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 811 BRGPHY_5708S_DIG_PG0); 812 } 813 } else 814 #endif 815 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 816 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 817 /* Select the SerDes Digital block of the AN MMD. */ 818 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 819 BRGPHY_BLOCK_ADDR_SERDES_DIG); 820 821 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 822 (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) & 823 ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 824 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 825 826 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 827 /* Select the Over 1G block of the AN MMD. */ 828 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 829 BRGPHY_BLOCK_ADDR_OVER_1G); 830 831 /* 832 * Enable autoneg "Next Page" to advertise 833 * 2.5G support. 834 */ 835 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 836 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) | 837 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 838 } 839 840 /* 841 * Select the Multi-Rate Backplane Ethernet block of 842 * the AN MMD. 843 */ 844 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 845 BRGPHY_BLOCK_ADDR_MRBE); 846 847 /* Enable MRBE speed autoneg. */ 848 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 849 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) | 850 BRGPHY_MRBE_MSG_PG5_NP_MBRE | 851 BRGPHY_MRBE_MSG_PG5_NP_T2); 852 853 /* Select the Clause 73 User B0 block of the AN MMD. */ 854 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 855 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 856 857 /* Enable MRBE speed autoneg. */ 858 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 859 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 860 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 861 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 862 863 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 864 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 865 866 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 867 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 868 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 869 brgphy_disable_early_dac(sc); 870 871 /* Set Jumbo frame settings in the PHY. */ 872 brgphy_jumbo_settings(sc); 873 874 /* Enable Ethernet@Wirespeed */ 875 brgphy_eth_wirespeed(sc); 876 } else { 877 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 878 brgphy_ber_bug(sc); 879 880 /* Set Jumbo frame settings in the PHY. */ 881 brgphy_jumbo_settings(sc); 882 883 /* Enable Ethernet@Wirespeed */ 884 brgphy_eth_wirespeed(sc); 885 } 886 } 887 } 888 } 889 890 /* Turn off tap power management on 5401. */ 891 static void 892 brgphy_bcm5401_dspcode(struct mii_softc *sc) 893 { 894 static const struct { 895 int reg; 896 uint16_t val; 897 } dspcode[] = { 898 { BRGPHY_MII_AUXCTL, 0x0c20 }, 899 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 900 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 901 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 902 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 903 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 904 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 905 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 906 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 907 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 908 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 909 { 0, 0 }, 910 }; 911 int i; 912 913 for (i = 0; dspcode[i].reg != 0; i++) 914 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 915 delay(40); 916 } 917 918 static void 919 brgphy_bcm5411_dspcode(struct mii_softc *sc) 920 { 921 static const struct { 922 int reg; 923 uint16_t val; 924 } dspcode[] = { 925 { 0x1c, 0x8c23 }, 926 { 0x1c, 0x8ca3 }, 927 { 0x1c, 0x8c23 }, 928 { 0, 0 }, 929 }; 930 int i; 931 932 for (i = 0; dspcode[i].reg != 0; i++) 933 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 934 } 935 936 void 937 brgphy_bcm5421_dspcode(struct mii_softc *sc) 938 { 939 uint16_t data; 940 941 /* Set Class A mode */ 942 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 943 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 944 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 945 946 /* Set FFE gamma override to -0.125 */ 947 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 948 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 949 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 950 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 951 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 952 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 953 } 954 955 void 956 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 957 { 958 static const struct { 959 int reg; 960 uint16_t val; 961 } dspcode[] = { 962 { 4, 0x01e1 }, 963 { 9, 0x0300 }, 964 { 0, 0 }, 965 }; 966 int i; 967 968 for (i = 0; dspcode[i].reg != 0; i++) 969 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 970 } 971 972 static void 973 brgphy_adc_bug(struct mii_softc *sc) 974 { 975 static const struct { 976 int reg; 977 uint16_t val; 978 } dspcode[] = { 979 { BRGPHY_MII_AUXCTL, 0x0c00 }, 980 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 981 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 982 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 983 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 984 { BRGPHY_MII_AUXCTL, 0x0400 }, 985 { 0, 0 }, 986 }; 987 int i; 988 989 for (i = 0; dspcode[i].reg != 0; i++) 990 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 991 } 992 993 static void 994 brgphy_5704_a0_bug(struct mii_softc *sc) 995 { 996 static const struct { 997 int reg; 998 uint16_t val; 999 } dspcode[] = { 1000 { 0x1c, 0x8d68 }, 1001 { 0x1c, 0x8d68 }, 1002 { 0, 0 }, 1003 }; 1004 int i; 1005 1006 for (i = 0; dspcode[i].reg != 0; i++) 1007 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1008 } 1009 1010 static void 1011 brgphy_ber_bug(struct mii_softc *sc) 1012 { 1013 static const struct { 1014 int reg; 1015 uint16_t val; 1016 } dspcode[] = { 1017 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1018 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1019 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1020 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1021 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1022 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1023 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1024 { BRGPHY_MII_AUXCTL, 0x0400 }, 1025 { 0, 0 }, 1026 }; 1027 int i; 1028 1029 for (i = 0; dspcode[i].reg != 0; i++) 1030 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1031 } 1032 1033 /* BCM5701 A0/B0 CRC bug workaround */ 1034 void 1035 brgphy_crc_bug(struct mii_softc *sc) 1036 { 1037 static const struct { 1038 int reg; 1039 uint16_t val; 1040 } dspcode[] = { 1041 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1042 { 0x1c, 0x8c68 }, 1043 { 0x1c, 0x8d68 }, 1044 { 0x1c, 0x8c68 }, 1045 { 0, 0 }, 1046 }; 1047 int i; 1048 1049 for (i = 0; dspcode[i].reg != 0; i++) 1050 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1051 } 1052 1053 static void 1054 brgphy_disable_early_dac(struct mii_softc *sc) 1055 { 1056 uint32_t val; 1057 1058 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1059 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1060 val &= ~(1 << 8); 1061 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1062 1063 } 1064 1065 static void 1066 brgphy_jumbo_settings(struct mii_softc *sc) 1067 { 1068 u_int32_t val; 1069 1070 /* Set Jumbo frame settings in the PHY. */ 1071 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1072 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1073 /* Cannot do read-modify-write on the BCM5401 */ 1074 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1075 } else { 1076 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1077 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1078 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1079 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1080 } 1081 1082 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 1083 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1084 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1085 } 1086 1087 static void 1088 brgphy_eth_wirespeed(struct mii_softc *sc) 1089 { 1090 u_int32_t val; 1091 1092 /* Enable Ethernet@Wirespeed */ 1093 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1094 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1095 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1096 (val | (1 << 15) | (1 << 4))); 1097 } 1098
Indexes created Tue Sep 30 20:09:53 GMT 2025