brgphy.c revision 1.72
1 /* $NetBSD: brgphy.c,v 1.72 2014/06/18 06:35:19 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.72 2014/06/18 06:35:19 msaitoh Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 uint32_t sc_shared_hwcfg; /* shared hw config */ 96 uint32_t sc_port_hwcfg; /* port specific hw config */ 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_copper_status(struct mii_softc *); 105 static void brgphy_fiber_status(struct mii_softc *); 106 static void brgphy_5708s_status(struct mii_softc *); 107 static void brgphy_5709s_status(struct mii_softc *); 108 static int brgphy_mii_phy_auto(struct mii_softc *); 109 static void brgphy_loop(struct mii_softc *); 110 static void brgphy_reset(struct mii_softc *); 111 static void brgphy_bcm5401_dspcode(struct mii_softc *); 112 static void brgphy_bcm5411_dspcode(struct mii_softc *); 113 static void brgphy_bcm5421_dspcode(struct mii_softc *); 114 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 115 static void brgphy_adc_bug(struct mii_softc *); 116 static void brgphy_5704_a0_bug(struct mii_softc *); 117 static void brgphy_ber_bug(struct mii_softc *); 118 static void brgphy_crc_bug(struct mii_softc *); 119 static void brgphy_disable_early_dac(struct mii_softc *); 120 static void brgphy_jumbo_settings(struct mii_softc *); 121 static void brgphy_eth_wirespeed(struct mii_softc *); 122 123 124 static const struct mii_phy_funcs brgphy_copper_funcs = { 125 brgphy_service, brgphy_copper_status, brgphy_reset, 126 }; 127 128 static const struct mii_phy_funcs brgphy_fiber_funcs = { 129 brgphy_service, brgphy_fiber_status, brgphy_reset, 130 }; 131 132 static const struct mii_phy_funcs brgphy_5708s_funcs = { 133 brgphy_service, brgphy_5708s_status, brgphy_reset, 134 }; 135 136 static const struct mii_phy_funcs brgphy_5709s_funcs = { 137 brgphy_service, brgphy_5709s_status, brgphy_reset, 138 }; 139 140 static const struct mii_phydesc brgphys[] = { 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 142 MII_STR_BROADCOM_BCM5400 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 145 MII_STR_BROADCOM_BCM5401 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 148 MII_STR_BROADCOM_BCM5411 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 151 MII_STR_BROADCOM_BCM5421 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 154 MII_STR_BROADCOM_BCM5462 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 157 MII_STR_BROADCOM_BCM5461 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 160 MII_STR_BROADCOM_BCM54K2 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 163 MII_STR_BROADCOM_BCM5464 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 166 MII_STR_BROADCOM_BCM5701 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 169 MII_STR_BROADCOM_BCM5703 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 172 MII_STR_BROADCOM_BCM5704 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 175 MII_STR_BROADCOM_BCM5705 }, 176 177 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 178 MII_STR_BROADCOM_BCM5714 }, 179 180 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 181 MII_STR_BROADCOM_BCM5750 }, 182 183 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 184 MII_STR_BROADCOM_BCM5752 }, 185 186 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 187 MII_STR_BROADCOM_BCM5780 }, 188 189 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 190 MII_STR_BROADCOM_BCM5708C }, 191 192 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 193 MII_STR_BROADCOM2_BCM5481 }, 194 195 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 196 MII_STR_BROADCOM2_BCM5482 }, 197 198 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5708S, 199 MII_STR_BROADCOM2_BCM5708S }, 200 201 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 202 MII_STR_BROADCOM2_BCM5709C }, 203 204 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 205 MII_STR_BROADCOM2_BCM5709S }, 206 207 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 208 MII_STR_BROADCOM2_BCM5709CAX }, 209 210 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 211 MII_STR_BROADCOM2_BCM5722 }, 212 213 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 214 MII_STR_BROADCOM2_BCM5754 }, 215 216 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 217 MII_STR_BROADCOM2_BCM5755 }, 218 219 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 220 MII_STR_BROADCOM2_BCM5756 }, 221 222 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 223 MII_STR_BROADCOM2_BCM5761 }, 224 225 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 226 MII_STR_BROADCOM2_BCM5784 }, 227 228 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 229 MII_STR_BROADCOM2_BCM5785 }, 230 231 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 232 MII_STR_BROADCOM3_BCM5717C }, 233 234 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 235 MII_STR_BROADCOM3_BCM5719C }, 236 237 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 238 MII_STR_BROADCOM3_BCM5720C }, 239 240 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 241 MII_STR_BROADCOM3_BCM57765 }, 242 243 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 244 MII_STR_BROADCOM3_BCM57780 }, 245 246 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 247 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 248 249 { 0, 0, 250 NULL }, 251 }; 252 253 static int 254 brgphymatch(device_t parent, cfdata_t match, void *aux) 255 { 256 struct mii_attach_args *ma = aux; 257 258 if (mii_phy_match(ma, brgphys) != NULL) 259 return (10); 260 261 return (0); 262 } 263 264 static void 265 brgphyattach(device_t parent, device_t self, void *aux) 266 { 267 struct brgphy_softc *bsc = device_private(self); 268 struct mii_softc *sc = &bsc->sc_mii; 269 struct mii_attach_args *ma = aux; 270 struct mii_data *mii = ma->mii_data; 271 const struct mii_phydesc *mpd; 272 prop_dictionary_t dict; 273 274 mpd = mii_phy_match(ma, brgphys); 275 aprint_naive(": Media interface\n"); 276 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 277 278 sc->mii_dev = self; 279 sc->mii_inst = mii->mii_instance; 280 sc->mii_phy = ma->mii_phyno; 281 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 282 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 283 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 284 sc->mii_pdata = mii; 285 sc->mii_flags = ma->mii_flags; 286 sc->mii_anegticks = MII_ANEGTICKS; 287 288 if (device_is_a(parent, "bge")) 289 bsc->sc_isbge = true; 290 else if (device_is_a(parent, "bnx")) 291 bsc->sc_isbnx = true; 292 293 dict = device_properties(parent); 294 if (bsc->sc_isbge || bsc->sc_isbnx) { 295 if (!prop_dictionary_get_uint32(dict, "phyflags", 296 &bsc->sc_phyflags)) 297 aprint_error_dev(self, "failed to get phyflags\n"); 298 if (!prop_dictionary_get_uint32(dict, "chipid", 299 &bsc->sc_chipid)) 300 aprint_error_dev(self, "failed to get chipid\n"); 301 } 302 303 if (bsc->sc_isbnx) { 304 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */ 305 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg", 306 &bsc->sc_shared_hwcfg)) 307 aprint_error_dev(self, "failed to get shared_hwcfg\n"); 308 if (!prop_dictionary_get_uint32(dict, "port_hwcfg", 309 &bsc->sc_port_hwcfg)) 310 aprint_error_dev(self, "failed to get port_hwcfg\n"); 311 } 312 313 if (sc->mii_flags & MIIF_HAVEFIBER) { 314 if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5708) 315 sc->mii_funcs = &brgphy_5708s_funcs; 316 else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) 317 sc->mii_funcs = &brgphy_5709s_funcs; 318 else 319 sc->mii_funcs = &brgphy_fiber_funcs; 320 } else 321 sc->mii_funcs = &brgphy_copper_funcs; 322 323 PHY_RESET(sc); 324 325 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 326 if (sc->mii_capabilities & BMSR_EXTSTAT) 327 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 328 329 aprint_normal_dev(self, ""); 330 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 331 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 332 aprint_error("no media present"); 333 else { 334 if (sc->mii_flags & MIIF_HAVEFIBER) { 335 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 336 337 /* 338 * Set the proper bits for capabilities so that the 339 * correct media get selected by mii_phy_add_media() 340 */ 341 sc->mii_capabilities |= BMSR_ANEG; 342 sc->mii_capabilities &= ~BMSR_100T4; 343 sc->mii_extcapabilities |= EXTSR_1000XFDX; 344 345 if (bsc->sc_isbnx) { 346 /* 347 * 2.5Gb support is a software enabled feature 348 * on the BCM5708S and BCM5709S controllers. 349 */ 350 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 351 if (bsc->sc_phyflags 352 & BNX_PHY_2_5G_CAPABLE_FLAG) { 353 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 354 IFM_FDX, sc->mii_inst), 0); 355 aprint_normal("2500baseSX-FDX, "); 356 #undef ADD 357 } 358 } 359 } 360 mii_phy_add_media(sc); 361 } 362 aprint_normal("\n"); 363 364 } 365 366 static int 367 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 368 { 369 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 370 int reg, speed, gig; 371 372 switch (cmd) { 373 case MII_POLLSTAT: 374 /* 375 * If we're not polling our PHY instance, just return. 376 */ 377 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 378 return (0); 379 break; 380 381 case MII_MEDIACHG: 382 /* 383 * If the media indicates a different PHY instance, 384 * isolate ourselves. 385 */ 386 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 387 reg = PHY_READ(sc, MII_BMCR); 388 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 389 return (0); 390 } 391 392 /* 393 * If the interface is not up, don't do anything. 394 */ 395 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 396 break; 397 398 PHY_RESET(sc); /* XXX hardware bug work-around */ 399 400 switch (IFM_SUBTYPE(ife->ifm_media)) { 401 case IFM_AUTO: 402 (void) brgphy_mii_phy_auto(sc); 403 break; 404 case IFM_2500_SX: 405 speed = BRGPHY_5708S_BMCR_2500; 406 goto setit; 407 case IFM_1000_SX: 408 case IFM_1000_T: 409 speed = BMCR_S1000; 410 goto setit; 411 case IFM_100_TX: 412 speed = BMCR_S100; 413 goto setit; 414 case IFM_10_T: 415 speed = BMCR_S10; 416 setit: 417 brgphy_loop(sc); 418 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 419 speed |= BMCR_FDX; 420 gig = GTCR_ADV_1000TFDX; 421 } else 422 gig = GTCR_ADV_1000THDX; 423 424 PHY_WRITE(sc, MII_100T2CR, 0); 425 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 426 PHY_WRITE(sc, MII_BMCR, speed); 427 428 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) && 429 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) && 430 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX)) 431 break; 432 433 PHY_WRITE(sc, MII_100T2CR, gig); 434 PHY_WRITE(sc, MII_BMCR, 435 speed | BMCR_AUTOEN | BMCR_STARTNEG); 436 437 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 438 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 439 break; 440 441 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 442 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 443 PHY_WRITE(sc, MII_100T2CR, gig); 444 break; 445 default: 446 return (EINVAL); 447 } 448 break; 449 450 case MII_TICK: 451 /* 452 * If we're not currently selected, just return. 453 */ 454 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 455 return (0); 456 457 /* 458 * Is the interface even up? 459 */ 460 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 461 return 0; 462 463 /* 464 * Only used for autonegotiation. 465 */ 466 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 467 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 468 sc->mii_ticks = 0; 469 break; 470 } 471 472 /* 473 * Check for link. 474 * Read the status register twice; BMSR_LINK is latch-low. 475 */ 476 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 477 if (reg & BMSR_LINK) { 478 sc->mii_ticks = 0; 479 break; 480 } 481 482 /* 483 * mii_ticks == 0 means it's the first tick after changing the 484 * media or the link became down since the last tick 485 * (see above), so break to update the status. 486 */ 487 if (sc->mii_ticks++ == 0) 488 break; 489 490 /* 491 * Only retry autonegotiation every mii_anegticks seconds. 492 */ 493 KASSERT(sc->mii_anegticks != 0); 494 if (sc->mii_ticks <= sc->mii_anegticks) 495 break; 496 497 brgphy_mii_phy_auto(sc); 498 break; 499 500 case MII_DOWN: 501 mii_phy_down(sc); 502 return (0); 503 } 504 505 /* Update the media status. */ 506 mii_phy_status(sc); 507 508 /* 509 * Callback if something changed. Note that we need to poke the DSP on 510 * the Broadcom PHYs if the media changes. 511 */ 512 if (sc->mii_media_active != mii->mii_media_active || 513 sc->mii_media_status != mii->mii_media_status || 514 cmd == MII_MEDIACHG) { 515 switch (sc->mii_mpd_oui) { 516 case MII_OUI_BROADCOM: 517 switch (sc->mii_mpd_model) { 518 case MII_MODEL_BROADCOM_BCM5400: 519 brgphy_bcm5401_dspcode(sc); 520 break; 521 case MII_MODEL_BROADCOM_BCM5401: 522 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 523 brgphy_bcm5401_dspcode(sc); 524 break; 525 case MII_MODEL_BROADCOM_BCM5411: 526 brgphy_bcm5411_dspcode(sc); 527 break; 528 } 529 break; 530 } 531 } 532 533 /* Callback if something changed. */ 534 mii_phy_update(sc, cmd); 535 return (0); 536 } 537 538 static void 539 brgphy_copper_status(struct mii_softc *sc) 540 { 541 struct mii_data *mii = sc->mii_pdata; 542 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 543 int bmcr, bmsr, auxsts, gtsr; 544 545 mii->mii_media_status = IFM_AVALID; 546 mii->mii_media_active = IFM_ETHER; 547 548 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 549 if (bmsr & BMSR_LINK) 550 mii->mii_media_status |= IFM_ACTIVE; 551 552 bmcr = PHY_READ(sc, MII_BMCR); 553 if (bmcr & BMCR_ISO) { 554 mii->mii_media_active |= IFM_NONE; 555 mii->mii_media_status = 0; 556 return; 557 } 558 559 if (bmcr & BMCR_LOOP) 560 mii->mii_media_active |= IFM_LOOP; 561 562 if (bmcr & BMCR_AUTOEN) { 563 /* 564 * The media status bits are only valid of autonegotiation 565 * has completed (or it's disabled). 566 */ 567 if ((bmsr & BMSR_ACOMP) == 0) { 568 /* Erg, still trying, I guess... */ 569 mii->mii_media_active |= IFM_NONE; 570 return; 571 } 572 573 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 574 575 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 576 case BRGPHY_RES_1000FD: 577 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 578 gtsr = PHY_READ(sc, MII_100T2SR); 579 if (gtsr & GTSR_MS_RES) 580 mii->mii_media_active |= IFM_ETH_MASTER; 581 break; 582 583 case BRGPHY_RES_1000HD: 584 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 585 gtsr = PHY_READ(sc, MII_100T2SR); 586 if (gtsr & GTSR_MS_RES) 587 mii->mii_media_active |= IFM_ETH_MASTER; 588 break; 589 590 case BRGPHY_RES_100FD: 591 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 592 break; 593 594 case BRGPHY_RES_100T4: 595 mii->mii_media_active |= IFM_100_T4 | IFM_HDX; 596 break; 597 598 case BRGPHY_RES_100HD: 599 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 600 break; 601 602 case BRGPHY_RES_10FD: 603 mii->mii_media_active |= IFM_10_T | IFM_FDX; 604 break; 605 606 case BRGPHY_RES_10HD: 607 mii->mii_media_active |= IFM_10_T | IFM_HDX; 608 break; 609 610 default: 611 mii->mii_media_active |= IFM_NONE; 612 mii->mii_media_status = 0; 613 } 614 615 if (mii->mii_media_active & IFM_FDX) 616 mii->mii_media_active |= mii_phy_flowstatus(sc); 617 618 } else 619 mii->mii_media_active = ife->ifm_media; 620 } 621 622 void 623 brgphy_fiber_status(struct mii_softc *sc) 624 { 625 struct mii_data *mii = sc->mii_pdata; 626 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 627 int bmcr, bmsr; 628 629 mii->mii_media_status = IFM_AVALID; 630 mii->mii_media_active = IFM_ETHER; 631 632 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 633 if (bmsr & BMSR_LINK) 634 mii->mii_media_status |= IFM_ACTIVE; 635 636 bmcr = PHY_READ(sc, MII_BMCR); 637 if (bmcr & BMCR_LOOP) 638 mii->mii_media_active |= IFM_LOOP; 639 640 if (bmcr & BMCR_AUTOEN) { 641 int val; 642 643 if ((bmsr & BMSR_ACOMP) == 0) { 644 /* Erg, still trying, I guess... */ 645 mii->mii_media_active |= IFM_NONE; 646 return; 647 } 648 649 mii->mii_media_active |= IFM_1000_SX; 650 651 val = PHY_READ(sc, MII_ANAR) & 652 PHY_READ(sc, MII_ANLPAR); 653 654 if (val & ANAR_X_FD) 655 mii->mii_media_active |= IFM_FDX; 656 else 657 mii->mii_media_active |= IFM_HDX; 658 659 if (mii->mii_media_active & IFM_FDX) 660 mii->mii_media_active |= mii_phy_flowstatus(sc); 661 } else 662 mii->mii_media_active = ife->ifm_media; 663 } 664 665 void 666 brgphy_5708s_status(struct mii_softc *sc) 667 { 668 struct mii_data *mii = sc->mii_pdata; 669 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 670 int bmcr, bmsr; 671 672 mii->mii_media_status = IFM_AVALID; 673 mii->mii_media_active = IFM_ETHER; 674 675 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 676 if (bmsr & BMSR_LINK) 677 mii->mii_media_status |= IFM_ACTIVE; 678 679 bmcr = PHY_READ(sc, MII_BMCR); 680 if (bmcr & BMCR_LOOP) 681 mii->mii_media_active |= IFM_LOOP; 682 683 if (bmcr & BMCR_AUTOEN) { 684 int xstat; 685 686 if ((bmsr & BMSR_ACOMP) == 0) { 687 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 688 BRGPHY_5708S_DIG_PG0); 689 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 690 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) { 691 /* Erg, still trying, I guess... */ 692 mii->mii_media_active |= IFM_NONE; 693 return; 694 } 695 } 696 697 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 698 BRGPHY_5708S_DIG_PG0); 699 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 700 701 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 702 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 703 mii->mii_media_active |= IFM_10_FL; 704 break; 705 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 706 mii->mii_media_active |= IFM_100_FX; 707 break; 708 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 709 mii->mii_media_active |= IFM_1000_SX; 710 break; 711 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 712 mii->mii_media_active |= IFM_2500_SX; 713 break; 714 } 715 716 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 717 mii->mii_media_active |= IFM_FDX; 718 else 719 mii->mii_media_active |= IFM_HDX; 720 721 if (mii->mii_media_active & IFM_FDX) { 722 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE) 723 mii->mii_media_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 724 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE) 725 mii->mii_media_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 726 } 727 } else 728 mii->mii_media_active = ife->ifm_media; 729 } 730 731 static void 732 brgphy_5709s_status(struct mii_softc *sc) 733 { 734 struct mii_data *mii = sc->mii_pdata; 735 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 736 int bmcr, bmsr, auxsts; 737 738 mii->mii_media_status = IFM_AVALID; 739 mii->mii_media_active = IFM_ETHER; 740 741 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 742 if (bmsr & BMSR_LINK) 743 mii->mii_media_status |= IFM_ACTIVE; 744 745 bmcr = PHY_READ(sc, MII_BMCR); 746 if (bmcr & BMCR_ISO) { 747 mii->mii_media_active |= IFM_NONE; 748 mii->mii_media_status = 0; 749 return; 750 } 751 752 if (bmcr & BMCR_LOOP) 753 mii->mii_media_active |= IFM_LOOP; 754 755 if (bmcr & BMCR_AUTOEN) { 756 /* 757 * The media status bits are only valid of autonegotiation 758 * has completed (or it's disabled). 759 */ 760 if ((bmsr & BMSR_ACOMP) == 0) { 761 /* Erg, still trying, I guess... */ 762 mii->mii_media_active |= IFM_NONE; 763 return; 764 } 765 766 /* 5709S has its own general purpose status registers */ 767 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 768 BRGPHY_BLOCK_ADDR_GP_STATUS); 769 auxsts = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 770 771 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 772 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 773 774 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 775 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 776 mii->mii_media_active |= IFM_10_FL; 777 break; 778 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 779 mii->mii_media_active |= IFM_100_FX; 780 break; 781 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 782 mii->mii_media_active |= IFM_1000_SX; 783 break; 784 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 785 mii->mii_media_active |= IFM_2500_SX; 786 break; 787 default: 788 mii->mii_media_active |= IFM_NONE; 789 mii->mii_media_status = 0; 790 break; 791 } 792 793 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 794 mii->mii_media_active |= IFM_FDX; 795 else 796 mii->mii_media_active |= IFM_HDX; 797 798 if (mii->mii_media_active & IFM_FDX) 799 mii->mii_media_active |= mii_phy_flowstatus(sc); 800 } else 801 mii->mii_media_active = ife->ifm_media; 802 } 803 804 int 805 brgphy_mii_phy_auto(struct mii_softc *sc) 806 { 807 int anar, ktcr = 0; 808 809 sc->mii_ticks = 0; 810 brgphy_loop(sc); 811 PHY_RESET(sc); 812 813 if (sc->mii_flags & MIIF_HAVEFIBER) { 814 anar = ANAR_X_FD | ANAR_X_HD; 815 if (sc->mii_flags & MIIF_DOPAUSE) 816 anar |= ANAR_X_PAUSE_TOWARDS; 817 } else { 818 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 819 if (sc->mii_flags & MIIF_DOPAUSE) 820 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 821 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 822 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 823 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 824 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 825 PHY_WRITE(sc, MII_100T2CR, ktcr); 826 ktcr = PHY_READ(sc, MII_100T2CR); 827 DELAY(1000); 828 } 829 PHY_WRITE(sc, MII_ANAR, anar); 830 DELAY(1000); 831 832 /* Start autonegotiation */ 833 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 834 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 835 836 return (EJUSTRETURN); 837 } 838 839 void 840 brgphy_loop(struct mii_softc *sc) 841 { 842 u_int32_t bmsr; 843 int i; 844 845 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 846 for (i = 0; i < 15000; i++) { 847 bmsr = PHY_READ(sc, MII_BMSR); 848 if (!(bmsr & BMSR_LINK)) 849 break; 850 DELAY(10); 851 } 852 } 853 854 static void 855 brgphy_reset(struct mii_softc *sc) 856 { 857 struct brgphy_softc *bsc = device_private(sc->mii_dev); 858 859 mii_phy_reset(sc); 860 switch (sc->mii_mpd_oui) { 861 case MII_OUI_BROADCOM: 862 switch (sc->mii_mpd_model) { 863 case MII_MODEL_BROADCOM_BCM5400: 864 brgphy_bcm5401_dspcode(sc); 865 break; 866 case MII_MODEL_BROADCOM_BCM5401: 867 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 868 brgphy_bcm5401_dspcode(sc); 869 break; 870 case MII_MODEL_BROADCOM_BCM5411: 871 brgphy_bcm5411_dspcode(sc); 872 break; 873 case MII_MODEL_BROADCOM_BCM5421: 874 brgphy_bcm5421_dspcode(sc); 875 break; 876 case MII_MODEL_BROADCOM_BCM54K2: 877 brgphy_bcm54k2_dspcode(sc); 878 break; 879 } 880 break; 881 case MII_OUI_BROADCOM3: 882 switch (sc->mii_mpd_model) { 883 case MII_MODEL_BROADCOM3_BCM5717C: 884 case MII_MODEL_BROADCOM3_BCM5719C: 885 case MII_MODEL_BROADCOM3_BCM5720C: 886 case MII_MODEL_BROADCOM3_BCM57765: 887 return; 888 } 889 break; 890 default: 891 break; 892 } 893 894 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 895 if (bsc->sc_isbge) { 896 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 897 898 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 899 brgphy_adc_bug(sc); 900 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 901 brgphy_5704_a0_bug(sc); 902 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 903 brgphy_ber_bug(sc); 904 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 905 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 906 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 907 0x000a); 908 909 if (bsc->sc_phyflags 910 & BGEPHYF_ADJUST_TRIM) { 911 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 912 0x110b); 913 PHY_WRITE(sc, BRGPHY_TEST1, 914 BRGPHY_TEST1_TRIM_EN | 0x4); 915 } else { 916 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 917 0x010b); 918 } 919 920 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 921 } 922 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 923 brgphy_crc_bug(sc); 924 925 /* Set Jumbo frame settings in the PHY. */ 926 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 927 brgphy_jumbo_settings(sc); 928 929 /* Adjust output voltage */ 930 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 931 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 932 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 933 934 /* Enable Ethernet@Wirespeed */ 935 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 936 brgphy_eth_wirespeed(sc); 937 938 #if 0 939 /* Enable Link LED on Dell boxes */ 940 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 941 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 942 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 943 & ~BRGPHY_PHY_EXTCTL_3_LED); 944 } 945 #endif 946 } 947 /* Handle any bnx (NetXtreme II) workarounds. */ 948 } else if (bsc->sc_isbnx) { 949 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 950 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 951 /* Store autoneg capabilities/results in digital block (Page 0) */ 952 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 953 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 954 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 955 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 956 957 /* Enable fiber mode and autodetection */ 958 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 959 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 960 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 961 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 962 963 /* Enable parallel detection */ 964 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 965 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 966 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 967 968 /* Advertise 2.5G support through next page during autoneg */ 969 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) 970 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 971 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 972 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 973 974 /* Increase TX signal amplitude */ 975 if ((_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_A0) || 976 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B0) || 977 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B1)) { 978 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 979 BRGPHY_5708S_TX_MISC_PG5); 980 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 981 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 982 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 983 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 984 BRGPHY_5708S_DIG_PG0); 985 } 986 987 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 988 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 989 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 990 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 991 BRGPHY_5708S_TX_MISC_PG5); 992 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 993 bsc->sc_port_hwcfg & 994 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 995 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 996 BRGPHY_5708S_DIG_PG0); 997 } 998 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 999 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 1000 /* Select the SerDes Digital block of the AN MMD. */ 1001 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1002 BRGPHY_BLOCK_ADDR_SERDES_DIG); 1003 1004 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 1005 (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) & 1006 ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 1007 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 1008 1009 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 1010 /* Select the Over 1G block of the AN MMD. */ 1011 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1012 BRGPHY_BLOCK_ADDR_OVER_1G); 1013 1014 /* 1015 * Enable autoneg "Next Page" to advertise 1016 * 2.5G support. 1017 */ 1018 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 1019 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) | 1020 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1021 } 1022 1023 /* 1024 * Select the Multi-Rate Backplane Ethernet block of 1025 * the AN MMD. 1026 */ 1027 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1028 BRGPHY_BLOCK_ADDR_MRBE); 1029 1030 /* Enable MRBE speed autoneg. */ 1031 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 1032 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) | 1033 BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1034 BRGPHY_MRBE_MSG_PG5_NP_T2); 1035 1036 /* Select the Clause 73 User B0 block of the AN MMD. */ 1037 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1038 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1039 1040 /* Enable MRBE speed autoneg. */ 1041 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1042 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1043 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1044 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1045 1046 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1047 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1048 1049 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 1050 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 1051 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 1052 brgphy_disable_early_dac(sc); 1053 1054 /* Set Jumbo frame settings in the PHY. */ 1055 brgphy_jumbo_settings(sc); 1056 1057 /* Enable Ethernet@Wirespeed */ 1058 brgphy_eth_wirespeed(sc); 1059 } else { 1060 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 1061 brgphy_ber_bug(sc); 1062 1063 /* Set Jumbo frame settings in the PHY. */ 1064 brgphy_jumbo_settings(sc); 1065 1066 /* Enable Ethernet@Wirespeed */ 1067 brgphy_eth_wirespeed(sc); 1068 } 1069 } 1070 } 1071 } 1072 1073 /* Turn off tap power management on 5401. */ 1074 static void 1075 brgphy_bcm5401_dspcode(struct mii_softc *sc) 1076 { 1077 static const struct { 1078 int reg; 1079 uint16_t val; 1080 } dspcode[] = { 1081 { BRGPHY_MII_AUXCTL, 0x0c20 }, 1082 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 1083 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 1084 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 1085 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 1086 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1087 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 1088 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1089 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 1090 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1091 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 1092 { 0, 0 }, 1093 }; 1094 int i; 1095 1096 for (i = 0; dspcode[i].reg != 0; i++) 1097 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1098 delay(40); 1099 } 1100 1101 static void 1102 brgphy_bcm5411_dspcode(struct mii_softc *sc) 1103 { 1104 static const struct { 1105 int reg; 1106 uint16_t val; 1107 } dspcode[] = { 1108 { 0x1c, 0x8c23 }, 1109 { 0x1c, 0x8ca3 }, 1110 { 0x1c, 0x8c23 }, 1111 { 0, 0 }, 1112 }; 1113 int i; 1114 1115 for (i = 0; dspcode[i].reg != 0; i++) 1116 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1117 } 1118 1119 void 1120 brgphy_bcm5421_dspcode(struct mii_softc *sc) 1121 { 1122 uint16_t data; 1123 1124 /* Set Class A mode */ 1125 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 1126 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1127 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 1128 1129 /* Set FFE gamma override to -0.125 */ 1130 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 1131 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1132 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 1133 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 1134 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1135 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 1136 } 1137 1138 void 1139 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 1140 { 1141 static const struct { 1142 int reg; 1143 uint16_t val; 1144 } dspcode[] = { 1145 { 4, 0x01e1 }, 1146 { 9, 0x0300 }, 1147 { 0, 0 }, 1148 }; 1149 int i; 1150 1151 for (i = 0; dspcode[i].reg != 0; i++) 1152 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1153 } 1154 1155 static void 1156 brgphy_adc_bug(struct mii_softc *sc) 1157 { 1158 static const struct { 1159 int reg; 1160 uint16_t val; 1161 } dspcode[] = { 1162 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1163 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1164 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 1165 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1166 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 1167 { BRGPHY_MII_AUXCTL, 0x0400 }, 1168 { 0, 0 }, 1169 }; 1170 int i; 1171 1172 for (i = 0; dspcode[i].reg != 0; i++) 1173 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1174 } 1175 1176 static void 1177 brgphy_5704_a0_bug(struct mii_softc *sc) 1178 { 1179 static const struct { 1180 int reg; 1181 uint16_t val; 1182 } dspcode[] = { 1183 { 0x1c, 0x8d68 }, 1184 { 0x1c, 0x8d68 }, 1185 { 0, 0 }, 1186 }; 1187 int i; 1188 1189 for (i = 0; dspcode[i].reg != 0; i++) 1190 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1191 } 1192 1193 static void 1194 brgphy_ber_bug(struct mii_softc *sc) 1195 { 1196 static const struct { 1197 int reg; 1198 uint16_t val; 1199 } dspcode[] = { 1200 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1201 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1202 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1203 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1204 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1205 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1206 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1207 { BRGPHY_MII_AUXCTL, 0x0400 }, 1208 { 0, 0 }, 1209 }; 1210 int i; 1211 1212 for (i = 0; dspcode[i].reg != 0; i++) 1213 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1214 } 1215 1216 /* BCM5701 A0/B0 CRC bug workaround */ 1217 void 1218 brgphy_crc_bug(struct mii_softc *sc) 1219 { 1220 static const struct { 1221 int reg; 1222 uint16_t val; 1223 } dspcode[] = { 1224 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1225 { 0x1c, 0x8c68 }, 1226 { 0x1c, 0x8d68 }, 1227 { 0x1c, 0x8c68 }, 1228 { 0, 0 }, 1229 }; 1230 int i; 1231 1232 for (i = 0; dspcode[i].reg != 0; i++) 1233 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1234 } 1235 1236 static void 1237 brgphy_disable_early_dac(struct mii_softc *sc) 1238 { 1239 uint32_t val; 1240 1241 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1242 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1243 val &= ~(1 << 8); 1244 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1245 1246 } 1247 1248 static void 1249 brgphy_jumbo_settings(struct mii_softc *sc) 1250 { 1251 u_int32_t val; 1252 1253 /* Set Jumbo frame settings in the PHY. */ 1254 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1255 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1256 /* Cannot do read-modify-write on the BCM5401 */ 1257 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1258 } else { 1259 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1260 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1261 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1262 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1263 } 1264 1265 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 1266 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1267 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1268 } 1269 1270 static void 1271 brgphy_eth_wirespeed(struct mii_softc *sc) 1272 { 1273 u_int32_t val; 1274 1275 /* Enable Ethernet@Wirespeed */ 1276 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1277 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1278 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1279 (val | (1 << 15) | (1 << 4))); 1280 } 1281
Indexes created Sun Sep 28 16:09:52 GMT 2025