brgphy.c revision 1.73
1 /* $NetBSD: brgphy.c,v 1.73 2014/07/02 21:51:36 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.73 2014/07/02 21:51:36 msaitoh Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 uint32_t sc_shared_hwcfg; /* shared hw config */ 96 uint32_t sc_port_hwcfg; /* port specific hw config */ 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_copper_status(struct mii_softc *); 105 static void brgphy_fiber_status(struct mii_softc *); 106 static void brgphy_5708s_status(struct mii_softc *); 107 static void brgphy_5709s_status(struct mii_softc *); 108 static int brgphy_mii_phy_auto(struct mii_softc *); 109 static void brgphy_loop(struct mii_softc *); 110 static void brgphy_reset(struct mii_softc *); 111 static void brgphy_bcm5401_dspcode(struct mii_softc *); 112 static void brgphy_bcm5411_dspcode(struct mii_softc *); 113 static void brgphy_bcm5421_dspcode(struct mii_softc *); 114 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 115 static void brgphy_adc_bug(struct mii_softc *); 116 static void brgphy_5704_a0_bug(struct mii_softc *); 117 static void brgphy_ber_bug(struct mii_softc *); 118 static void brgphy_crc_bug(struct mii_softc *); 119 static void brgphy_disable_early_dac(struct mii_softc *); 120 static void brgphy_jumbo_settings(struct mii_softc *); 121 static void brgphy_eth_wirespeed(struct mii_softc *); 122 123 124 static const struct mii_phy_funcs brgphy_copper_funcs = { 125 brgphy_service, brgphy_copper_status, brgphy_reset, 126 }; 127 128 static const struct mii_phy_funcs brgphy_fiber_funcs = { 129 brgphy_service, brgphy_fiber_status, brgphy_reset, 130 }; 131 132 static const struct mii_phy_funcs brgphy_5708s_funcs = { 133 brgphy_service, brgphy_5708s_status, brgphy_reset, 134 }; 135 136 static const struct mii_phy_funcs brgphy_5709s_funcs = { 137 brgphy_service, brgphy_5709s_status, brgphy_reset, 138 }; 139 140 static const struct mii_phydesc brgphys[] = { 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 142 MII_STR_BROADCOM_BCM5400 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 145 MII_STR_BROADCOM_BCM5401 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 148 MII_STR_BROADCOM_BCM5411 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 151 MII_STR_BROADCOM_BCM5421 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 154 MII_STR_BROADCOM_BCM5462 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 157 MII_STR_BROADCOM_BCM5461 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 160 MII_STR_BROADCOM_BCM54K2 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 163 MII_STR_BROADCOM_BCM5464 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 166 MII_STR_BROADCOM_BCM5701 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 169 MII_STR_BROADCOM_BCM5703 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 172 MII_STR_BROADCOM_BCM5704 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 175 MII_STR_BROADCOM_BCM5705 }, 176 177 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 178 MII_STR_BROADCOM_BCM5714 }, 179 180 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 181 MII_STR_BROADCOM_BCM5750 }, 182 183 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 184 MII_STR_BROADCOM_BCM5752 }, 185 186 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 187 MII_STR_BROADCOM_BCM5780 }, 188 189 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 190 MII_STR_BROADCOM_BCM5708C }, 191 192 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 193 MII_STR_BROADCOM2_BCM5481 }, 194 195 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 196 MII_STR_BROADCOM2_BCM5482 }, 197 198 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5708S, 199 MII_STR_BROADCOM2_BCM5708S }, 200 201 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 202 MII_STR_BROADCOM2_BCM5709C }, 203 204 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 205 MII_STR_BROADCOM2_BCM5709S }, 206 207 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 208 MII_STR_BROADCOM2_BCM5709CAX }, 209 210 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 211 MII_STR_BROADCOM2_BCM5722 }, 212 213 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 214 MII_STR_BROADCOM2_BCM5754 }, 215 216 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 217 MII_STR_BROADCOM2_BCM5755 }, 218 219 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 220 MII_STR_BROADCOM2_BCM5756 }, 221 222 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 223 MII_STR_BROADCOM2_BCM5761 }, 224 225 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 226 MII_STR_BROADCOM2_BCM5784 }, 227 228 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 229 MII_STR_BROADCOM2_BCM5785 }, 230 231 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 232 MII_STR_BROADCOM3_BCM5717C }, 233 234 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 235 MII_STR_BROADCOM3_BCM5719C }, 236 237 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 238 MII_STR_BROADCOM3_BCM5720C }, 239 240 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 241 MII_STR_BROADCOM3_BCM57765 }, 242 243 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 244 MII_STR_BROADCOM3_BCM57780 }, 245 246 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 247 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 248 249 { 0, 0, 250 NULL }, 251 }; 252 253 static int 254 brgphymatch(device_t parent, cfdata_t match, void *aux) 255 { 256 struct mii_attach_args *ma = aux; 257 258 if (mii_phy_match(ma, brgphys) != NULL) 259 return (10); 260 261 return (0); 262 } 263 264 static void 265 brgphyattach(device_t parent, device_t self, void *aux) 266 { 267 struct brgphy_softc *bsc = device_private(self); 268 struct mii_softc *sc = &bsc->sc_mii; 269 struct mii_attach_args *ma = aux; 270 struct mii_data *mii = ma->mii_data; 271 const struct mii_phydesc *mpd; 272 prop_dictionary_t dict; 273 274 mpd = mii_phy_match(ma, brgphys); 275 aprint_naive(": Media interface\n"); 276 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 277 278 sc->mii_dev = self; 279 sc->mii_inst = mii->mii_instance; 280 sc->mii_phy = ma->mii_phyno; 281 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 282 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 283 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 284 sc->mii_pdata = mii; 285 sc->mii_flags = ma->mii_flags; 286 sc->mii_anegticks = MII_ANEGTICKS; 287 288 if (device_is_a(parent, "bge")) 289 bsc->sc_isbge = true; 290 else if (device_is_a(parent, "bnx")) 291 bsc->sc_isbnx = true; 292 293 dict = device_properties(parent); 294 if (bsc->sc_isbge || bsc->sc_isbnx) { 295 if (!prop_dictionary_get_uint32(dict, "phyflags", 296 &bsc->sc_phyflags)) 297 aprint_error_dev(self, "failed to get phyflags\n"); 298 if (!prop_dictionary_get_uint32(dict, "chipid", 299 &bsc->sc_chipid)) 300 aprint_error_dev(self, "failed to get chipid\n"); 301 } 302 303 if (bsc->sc_isbnx) { 304 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */ 305 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg", 306 &bsc->sc_shared_hwcfg)) 307 aprint_error_dev(self, "failed to get shared_hwcfg\n"); 308 if (!prop_dictionary_get_uint32(dict, "port_hwcfg", 309 &bsc->sc_port_hwcfg)) 310 aprint_error_dev(self, "failed to get port_hwcfg\n"); 311 } 312 313 if (sc->mii_flags & MIIF_HAVEFIBER) { 314 if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5708) 315 sc->mii_funcs = &brgphy_5708s_funcs; 316 else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) 317 sc->mii_funcs = &brgphy_5709s_funcs; 318 else 319 sc->mii_funcs = &brgphy_fiber_funcs; 320 } else 321 sc->mii_funcs = &brgphy_copper_funcs; 322 323 PHY_RESET(sc); 324 325 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 326 if (sc->mii_capabilities & BMSR_EXTSTAT) 327 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 328 329 aprint_normal_dev(self, ""); 330 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 331 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 332 aprint_error("no media present"); 333 else { 334 if (sc->mii_flags & MIIF_HAVEFIBER) { 335 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 336 337 /* 338 * Set the proper bits for capabilities so that the 339 * correct media get selected by mii_phy_add_media() 340 */ 341 sc->mii_capabilities |= BMSR_ANEG; 342 sc->mii_capabilities &= ~BMSR_100T4; 343 sc->mii_extcapabilities |= EXTSR_1000XFDX; 344 345 if (bsc->sc_isbnx) { 346 /* 347 * 2.5Gb support is a software enabled feature 348 * on the BCM5708S and BCM5709S controllers. 349 */ 350 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 351 if (bsc->sc_phyflags 352 & BNX_PHY_2_5G_CAPABLE_FLAG) { 353 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 354 IFM_FDX, sc->mii_inst), 0); 355 aprint_normal("2500baseSX-FDX, "); 356 #undef ADD 357 } 358 } 359 } 360 mii_phy_add_media(sc); 361 } 362 aprint_normal("\n"); 363 364 } 365 366 static int 367 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 368 { 369 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 370 int reg, speed, gig; 371 372 switch (cmd) { 373 case MII_POLLSTAT: 374 /* If we're not polling our PHY instance, just return. */ 375 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 376 return (0); 377 break; 378 379 case MII_MEDIACHG: 380 /* 381 * If the media indicates a different PHY instance, 382 * isolate ourselves. 383 */ 384 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 385 reg = PHY_READ(sc, MII_BMCR); 386 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 387 return (0); 388 } 389 390 /* If the interface is not up, don't do anything. */ 391 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 392 break; 393 394 PHY_RESET(sc); /* XXX hardware bug work-around */ 395 396 switch (IFM_SUBTYPE(ife->ifm_media)) { 397 case IFM_AUTO: 398 (void) brgphy_mii_phy_auto(sc); 399 break; 400 case IFM_2500_SX: 401 speed = BRGPHY_5708S_BMCR_2500; 402 goto setit; 403 case IFM_1000_SX: 404 case IFM_1000_T: 405 speed = BMCR_S1000; 406 goto setit; 407 case IFM_100_TX: 408 speed = BMCR_S100; 409 goto setit; 410 case IFM_10_T: 411 speed = BMCR_S10; 412 setit: 413 brgphy_loop(sc); 414 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 415 speed |= BMCR_FDX; 416 gig = GTCR_ADV_1000TFDX; 417 } else 418 gig = GTCR_ADV_1000THDX; 419 420 PHY_WRITE(sc, MII_100T2CR, 0); 421 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 422 PHY_WRITE(sc, MII_BMCR, speed); 423 424 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) && 425 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) && 426 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX)) 427 break; 428 429 PHY_WRITE(sc, MII_100T2CR, gig); 430 PHY_WRITE(sc, MII_BMCR, 431 speed | BMCR_AUTOEN | BMCR_STARTNEG); 432 433 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 434 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 435 break; 436 437 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 438 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 439 PHY_WRITE(sc, MII_100T2CR, gig); 440 break; 441 default: 442 return (EINVAL); 443 } 444 break; 445 446 case MII_TICK: 447 /* If we're not currently selected, just return. */ 448 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 449 return (0); 450 451 /* Is the interface even up? */ 452 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 453 return 0; 454 455 /* Only used for autonegotiation. */ 456 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 457 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 458 sc->mii_ticks = 0; 459 break; 460 } 461 462 /* 463 * Check for link. 464 * Read the status register twice; BMSR_LINK is latch-low. 465 */ 466 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 467 if (reg & BMSR_LINK) { 468 sc->mii_ticks = 0; 469 break; 470 } 471 472 /* 473 * mii_ticks == 0 means it's the first tick after changing the 474 * media or the link became down since the last tick 475 * (see above), so break to update the status. 476 */ 477 if (sc->mii_ticks++ == 0) 478 break; 479 480 /* Only retry autonegotiation every mii_anegticks seconds. */ 481 KASSERT(sc->mii_anegticks != 0); 482 if (sc->mii_ticks <= sc->mii_anegticks) 483 break; 484 485 brgphy_mii_phy_auto(sc); 486 break; 487 488 case MII_DOWN: 489 mii_phy_down(sc); 490 return (0); 491 } 492 493 /* Update the media status. */ 494 mii_phy_status(sc); 495 496 /* 497 * Callback if something changed. Note that we need to poke the DSP on 498 * the Broadcom PHYs if the media changes. 499 */ 500 if (sc->mii_media_active != mii->mii_media_active || 501 sc->mii_media_status != mii->mii_media_status || 502 cmd == MII_MEDIACHG) { 503 switch (sc->mii_mpd_oui) { 504 case MII_OUI_BROADCOM: 505 switch (sc->mii_mpd_model) { 506 case MII_MODEL_BROADCOM_BCM5400: 507 brgphy_bcm5401_dspcode(sc); 508 break; 509 case MII_MODEL_BROADCOM_BCM5401: 510 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 511 brgphy_bcm5401_dspcode(sc); 512 break; 513 case MII_MODEL_BROADCOM_BCM5411: 514 brgphy_bcm5411_dspcode(sc); 515 break; 516 } 517 break; 518 } 519 } 520 521 /* Callback if something changed. */ 522 mii_phy_update(sc, cmd); 523 return (0); 524 } 525 526 static void 527 brgphy_copper_status(struct mii_softc *sc) 528 { 529 struct mii_data *mii = sc->mii_pdata; 530 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 531 int bmcr, bmsr, auxsts, gtsr; 532 533 mii->mii_media_status = IFM_AVALID; 534 mii->mii_media_active = IFM_ETHER; 535 536 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 537 if (bmsr & BMSR_LINK) 538 mii->mii_media_status |= IFM_ACTIVE; 539 540 bmcr = PHY_READ(sc, MII_BMCR); 541 if (bmcr & BMCR_ISO) { 542 mii->mii_media_active |= IFM_NONE; 543 mii->mii_media_status = 0; 544 return; 545 } 546 547 if (bmcr & BMCR_LOOP) 548 mii->mii_media_active |= IFM_LOOP; 549 550 if (bmcr & BMCR_AUTOEN) { 551 /* 552 * The media status bits are only valid of autonegotiation 553 * has completed (or it's disabled). 554 */ 555 if ((bmsr & BMSR_ACOMP) == 0) { 556 /* Erg, still trying, I guess... */ 557 mii->mii_media_active |= IFM_NONE; 558 return; 559 } 560 561 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 562 563 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 564 case BRGPHY_RES_1000FD: 565 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 566 gtsr = PHY_READ(sc, MII_100T2SR); 567 if (gtsr & GTSR_MS_RES) 568 mii->mii_media_active |= IFM_ETH_MASTER; 569 break; 570 571 case BRGPHY_RES_1000HD: 572 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 573 gtsr = PHY_READ(sc, MII_100T2SR); 574 if (gtsr & GTSR_MS_RES) 575 mii->mii_media_active |= IFM_ETH_MASTER; 576 break; 577 578 case BRGPHY_RES_100FD: 579 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 580 break; 581 582 case BRGPHY_RES_100T4: 583 mii->mii_media_active |= IFM_100_T4 | IFM_HDX; 584 break; 585 586 case BRGPHY_RES_100HD: 587 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 588 break; 589 590 case BRGPHY_RES_10FD: 591 mii->mii_media_active |= IFM_10_T | IFM_FDX; 592 break; 593 594 case BRGPHY_RES_10HD: 595 mii->mii_media_active |= IFM_10_T | IFM_HDX; 596 break; 597 598 default: 599 mii->mii_media_active |= IFM_NONE; 600 mii->mii_media_status = 0; 601 } 602 603 if (mii->mii_media_active & IFM_FDX) 604 mii->mii_media_active |= mii_phy_flowstatus(sc); 605 606 } else 607 mii->mii_media_active = ife->ifm_media; 608 } 609 610 void 611 brgphy_fiber_status(struct mii_softc *sc) 612 { 613 struct mii_data *mii = sc->mii_pdata; 614 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 615 int bmcr, bmsr; 616 617 mii->mii_media_status = IFM_AVALID; 618 mii->mii_media_active = IFM_ETHER; 619 620 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 621 if (bmsr & BMSR_LINK) 622 mii->mii_media_status |= IFM_ACTIVE; 623 624 bmcr = PHY_READ(sc, MII_BMCR); 625 if (bmcr & BMCR_LOOP) 626 mii->mii_media_active |= IFM_LOOP; 627 628 if (bmcr & BMCR_AUTOEN) { 629 int val; 630 631 if ((bmsr & BMSR_ACOMP) == 0) { 632 /* Erg, still trying, I guess... */ 633 mii->mii_media_active |= IFM_NONE; 634 return; 635 } 636 637 mii->mii_media_active |= IFM_1000_SX; 638 639 val = PHY_READ(sc, MII_ANAR) & 640 PHY_READ(sc, MII_ANLPAR); 641 642 if (val & ANAR_X_FD) 643 mii->mii_media_active |= IFM_FDX; 644 else 645 mii->mii_media_active |= IFM_HDX; 646 647 if (mii->mii_media_active & IFM_FDX) 648 mii->mii_media_active |= mii_phy_flowstatus(sc); 649 } else 650 mii->mii_media_active = ife->ifm_media; 651 } 652 653 void 654 brgphy_5708s_status(struct mii_softc *sc) 655 { 656 struct mii_data *mii = sc->mii_pdata; 657 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 658 int bmcr, bmsr; 659 660 mii->mii_media_status = IFM_AVALID; 661 mii->mii_media_active = IFM_ETHER; 662 663 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 664 if (bmsr & BMSR_LINK) 665 mii->mii_media_status |= IFM_ACTIVE; 666 667 bmcr = PHY_READ(sc, MII_BMCR); 668 if (bmcr & BMCR_LOOP) 669 mii->mii_media_active |= IFM_LOOP; 670 671 if (bmcr & BMCR_AUTOEN) { 672 int xstat; 673 674 if ((bmsr & BMSR_ACOMP) == 0) { 675 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 676 BRGPHY_5708S_DIG_PG0); 677 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 678 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) { 679 /* Erg, still trying, I guess... */ 680 mii->mii_media_active |= IFM_NONE; 681 return; 682 } 683 } 684 685 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 686 BRGPHY_5708S_DIG_PG0); 687 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 688 689 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 690 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 691 mii->mii_media_active |= IFM_10_FL; 692 break; 693 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 694 mii->mii_media_active |= IFM_100_FX; 695 break; 696 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 697 mii->mii_media_active |= IFM_1000_SX; 698 break; 699 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 700 mii->mii_media_active |= IFM_2500_SX; 701 break; 702 } 703 704 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 705 mii->mii_media_active |= IFM_FDX; 706 else 707 mii->mii_media_active |= IFM_HDX; 708 709 if (mii->mii_media_active & IFM_FDX) { 710 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE) 711 mii->mii_media_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 712 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE) 713 mii->mii_media_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 714 } 715 } else 716 mii->mii_media_active = ife->ifm_media; 717 } 718 719 static void 720 brgphy_5709s_status(struct mii_softc *sc) 721 { 722 struct mii_data *mii = sc->mii_pdata; 723 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 724 int bmcr, bmsr, auxsts; 725 726 mii->mii_media_status = IFM_AVALID; 727 mii->mii_media_active = IFM_ETHER; 728 729 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 730 if (bmsr & BMSR_LINK) 731 mii->mii_media_status |= IFM_ACTIVE; 732 733 bmcr = PHY_READ(sc, MII_BMCR); 734 if (bmcr & BMCR_ISO) { 735 mii->mii_media_active |= IFM_NONE; 736 mii->mii_media_status = 0; 737 return; 738 } 739 740 if (bmcr & BMCR_LOOP) 741 mii->mii_media_active |= IFM_LOOP; 742 743 if (bmcr & BMCR_AUTOEN) { 744 /* 745 * The media status bits are only valid of autonegotiation 746 * has completed (or it's disabled). 747 */ 748 if ((bmsr & BMSR_ACOMP) == 0) { 749 /* Erg, still trying, I guess... */ 750 mii->mii_media_active |= IFM_NONE; 751 return; 752 } 753 754 /* 5709S has its own general purpose status registers */ 755 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 756 BRGPHY_BLOCK_ADDR_GP_STATUS); 757 auxsts = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 758 759 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 760 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 761 762 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 763 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 764 mii->mii_media_active |= IFM_10_FL; 765 break; 766 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 767 mii->mii_media_active |= IFM_100_FX; 768 break; 769 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 770 mii->mii_media_active |= IFM_1000_SX; 771 break; 772 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 773 mii->mii_media_active |= IFM_2500_SX; 774 break; 775 default: 776 mii->mii_media_active |= IFM_NONE; 777 mii->mii_media_status = 0; 778 break; 779 } 780 781 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 782 mii->mii_media_active |= IFM_FDX; 783 else 784 mii->mii_media_active |= IFM_HDX; 785 786 if (mii->mii_media_active & IFM_FDX) 787 mii->mii_media_active |= mii_phy_flowstatus(sc); 788 } else 789 mii->mii_media_active = ife->ifm_media; 790 } 791 792 int 793 brgphy_mii_phy_auto(struct mii_softc *sc) 794 { 795 int anar, ktcr = 0; 796 797 sc->mii_ticks = 0; 798 brgphy_loop(sc); 799 PHY_RESET(sc); 800 801 if (sc->mii_flags & MIIF_HAVEFIBER) { 802 anar = ANAR_X_FD | ANAR_X_HD; 803 if (sc->mii_flags & MIIF_DOPAUSE) 804 anar |= ANAR_X_PAUSE_TOWARDS; 805 } else { 806 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 807 if (sc->mii_flags & MIIF_DOPAUSE) 808 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 809 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 810 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 811 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 812 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 813 PHY_WRITE(sc, MII_100T2CR, ktcr); 814 ktcr = PHY_READ(sc, MII_100T2CR); 815 } 816 PHY_WRITE(sc, MII_ANAR, anar); 817 818 /* Start autonegotiation */ 819 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 820 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 821 822 return (EJUSTRETURN); 823 } 824 825 void 826 brgphy_loop(struct mii_softc *sc) 827 { 828 uint32_t bmsr; 829 int i; 830 831 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 832 for (i = 0; i < 15000; i++) { 833 bmsr = PHY_READ(sc, MII_BMSR); 834 if (!(bmsr & BMSR_LINK)) 835 break; 836 DELAY(10); 837 } 838 } 839 840 static void 841 brgphy_reset(struct mii_softc *sc) 842 { 843 struct brgphy_softc *bsc = device_private(sc->mii_dev); 844 845 mii_phy_reset(sc); 846 switch (sc->mii_mpd_oui) { 847 case MII_OUI_BROADCOM: 848 switch (sc->mii_mpd_model) { 849 case MII_MODEL_BROADCOM_BCM5400: 850 brgphy_bcm5401_dspcode(sc); 851 break; 852 case MII_MODEL_BROADCOM_BCM5401: 853 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 854 brgphy_bcm5401_dspcode(sc); 855 break; 856 case MII_MODEL_BROADCOM_BCM5411: 857 brgphy_bcm5411_dspcode(sc); 858 break; 859 case MII_MODEL_BROADCOM_BCM5421: 860 brgphy_bcm5421_dspcode(sc); 861 break; 862 case MII_MODEL_BROADCOM_BCM54K2: 863 brgphy_bcm54k2_dspcode(sc); 864 break; 865 } 866 break; 867 case MII_OUI_BROADCOM3: 868 switch (sc->mii_mpd_model) { 869 case MII_MODEL_BROADCOM3_BCM5717C: 870 case MII_MODEL_BROADCOM3_BCM5719C: 871 case MII_MODEL_BROADCOM3_BCM5720C: 872 case MII_MODEL_BROADCOM3_BCM57765: 873 return; 874 } 875 break; 876 default: 877 break; 878 } 879 880 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 881 if (bsc->sc_isbge) { 882 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 883 884 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 885 brgphy_adc_bug(sc); 886 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 887 brgphy_5704_a0_bug(sc); 888 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 889 brgphy_ber_bug(sc); 890 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 891 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 892 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 893 0x000a); 894 895 if (bsc->sc_phyflags 896 & BGEPHYF_ADJUST_TRIM) { 897 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 898 0x110b); 899 PHY_WRITE(sc, BRGPHY_TEST1, 900 BRGPHY_TEST1_TRIM_EN | 0x4); 901 } else { 902 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 903 0x010b); 904 } 905 906 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 907 } 908 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 909 brgphy_crc_bug(sc); 910 911 /* Set Jumbo frame settings in the PHY. */ 912 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 913 brgphy_jumbo_settings(sc); 914 915 /* Adjust output voltage */ 916 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 917 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 918 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 919 920 /* Enable Ethernet@Wirespeed */ 921 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 922 brgphy_eth_wirespeed(sc); 923 924 #if 0 925 /* Enable Link LED on Dell boxes */ 926 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 927 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 928 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 929 & ~BRGPHY_PHY_EXTCTL_3_LED); 930 } 931 #endif 932 } 933 /* Handle any bnx (NetXtreme II) workarounds. */ 934 } else if (bsc->sc_isbnx) { 935 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 936 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 937 /* Store autoneg capabilities/results in digital block (Page 0) */ 938 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 939 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 940 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 941 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 942 943 /* Enable fiber mode and autodetection */ 944 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 945 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 946 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 947 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 948 949 /* Enable parallel detection */ 950 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 951 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 952 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 953 954 /* Advertise 2.5G support through next page during autoneg */ 955 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) 956 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 957 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 958 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 959 960 /* Increase TX signal amplitude */ 961 if ((_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_A0) || 962 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B0) || 963 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B1)) { 964 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 965 BRGPHY_5708S_TX_MISC_PG5); 966 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 967 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 968 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 969 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 970 BRGPHY_5708S_DIG_PG0); 971 } 972 973 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 974 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 975 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 976 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 977 BRGPHY_5708S_TX_MISC_PG5); 978 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 979 bsc->sc_port_hwcfg & 980 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 981 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 982 BRGPHY_5708S_DIG_PG0); 983 } 984 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 985 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 986 /* Select the SerDes Digital block of the AN MMD. */ 987 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 988 BRGPHY_BLOCK_ADDR_SERDES_DIG); 989 990 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 991 (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) & 992 ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 993 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 994 995 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 996 /* Select the Over 1G block of the AN MMD. */ 997 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 998 BRGPHY_BLOCK_ADDR_OVER_1G); 999 1000 /* 1001 * Enable autoneg "Next Page" to advertise 1002 * 2.5G support. 1003 */ 1004 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 1005 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) | 1006 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1007 } 1008 1009 /* 1010 * Select the Multi-Rate Backplane Ethernet block of 1011 * the AN MMD. 1012 */ 1013 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1014 BRGPHY_BLOCK_ADDR_MRBE); 1015 1016 /* Enable MRBE speed autoneg. */ 1017 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 1018 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) | 1019 BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1020 BRGPHY_MRBE_MSG_PG5_NP_T2); 1021 1022 /* Select the Clause 73 User B0 block of the AN MMD. */ 1023 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1024 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1025 1026 /* Enable MRBE speed autoneg. */ 1027 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1028 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1029 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1030 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1031 1032 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1033 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1034 1035 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 1036 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 1037 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 1038 brgphy_disable_early_dac(sc); 1039 1040 /* Set Jumbo frame settings in the PHY. */ 1041 brgphy_jumbo_settings(sc); 1042 1043 /* Enable Ethernet@Wirespeed */ 1044 brgphy_eth_wirespeed(sc); 1045 } else { 1046 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 1047 brgphy_ber_bug(sc); 1048 1049 /* Set Jumbo frame settings in the PHY. */ 1050 brgphy_jumbo_settings(sc); 1051 1052 /* Enable Ethernet@Wirespeed */ 1053 brgphy_eth_wirespeed(sc); 1054 } 1055 } 1056 } 1057 } 1058 1059 /* Turn off tap power management on 5401. */ 1060 static void 1061 brgphy_bcm5401_dspcode(struct mii_softc *sc) 1062 { 1063 static const struct { 1064 int reg; 1065 uint16_t val; 1066 } dspcode[] = { 1067 { BRGPHY_MII_AUXCTL, 0x0c20 }, 1068 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 1069 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 1070 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 1071 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 1072 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1073 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 1074 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1075 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 1076 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1077 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 1078 { 0, 0 }, 1079 }; 1080 int i; 1081 1082 for (i = 0; dspcode[i].reg != 0; i++) 1083 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1084 delay(40); 1085 } 1086 1087 static void 1088 brgphy_bcm5411_dspcode(struct mii_softc *sc) 1089 { 1090 static const struct { 1091 int reg; 1092 uint16_t val; 1093 } dspcode[] = { 1094 { 0x1c, 0x8c23 }, 1095 { 0x1c, 0x8ca3 }, 1096 { 0x1c, 0x8c23 }, 1097 { 0, 0 }, 1098 }; 1099 int i; 1100 1101 for (i = 0; dspcode[i].reg != 0; i++) 1102 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1103 } 1104 1105 void 1106 brgphy_bcm5421_dspcode(struct mii_softc *sc) 1107 { 1108 uint16_t data; 1109 1110 /* Set Class A mode */ 1111 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 1112 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1113 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 1114 1115 /* Set FFE gamma override to -0.125 */ 1116 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 1117 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1118 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 1119 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 1120 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1121 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 1122 } 1123 1124 void 1125 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 1126 { 1127 static const struct { 1128 int reg; 1129 uint16_t val; 1130 } dspcode[] = { 1131 { 4, 0x01e1 }, 1132 { 9, 0x0300 }, 1133 { 0, 0 }, 1134 }; 1135 int i; 1136 1137 for (i = 0; dspcode[i].reg != 0; i++) 1138 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1139 } 1140 1141 static void 1142 brgphy_adc_bug(struct mii_softc *sc) 1143 { 1144 static const struct { 1145 int reg; 1146 uint16_t val; 1147 } dspcode[] = { 1148 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1149 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1150 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 1151 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1152 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 1153 { BRGPHY_MII_AUXCTL, 0x0400 }, 1154 { 0, 0 }, 1155 }; 1156 int i; 1157 1158 for (i = 0; dspcode[i].reg != 0; i++) 1159 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1160 } 1161 1162 static void 1163 brgphy_5704_a0_bug(struct mii_softc *sc) 1164 { 1165 static const struct { 1166 int reg; 1167 uint16_t val; 1168 } dspcode[] = { 1169 { 0x1c, 0x8d68 }, 1170 { 0x1c, 0x8d68 }, 1171 { 0, 0 }, 1172 }; 1173 int i; 1174 1175 for (i = 0; dspcode[i].reg != 0; i++) 1176 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1177 } 1178 1179 static void 1180 brgphy_ber_bug(struct mii_softc *sc) 1181 { 1182 static const struct { 1183 int reg; 1184 uint16_t val; 1185 } dspcode[] = { 1186 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1187 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1188 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1189 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1190 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1191 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1192 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1193 { BRGPHY_MII_AUXCTL, 0x0400 }, 1194 { 0, 0 }, 1195 }; 1196 int i; 1197 1198 for (i = 0; dspcode[i].reg != 0; i++) 1199 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1200 } 1201 1202 /* BCM5701 A0/B0 CRC bug workaround */ 1203 void 1204 brgphy_crc_bug(struct mii_softc *sc) 1205 { 1206 static const struct { 1207 int reg; 1208 uint16_t val; 1209 } dspcode[] = { 1210 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1211 { 0x1c, 0x8c68 }, 1212 { 0x1c, 0x8d68 }, 1213 { 0x1c, 0x8c68 }, 1214 { 0, 0 }, 1215 }; 1216 int i; 1217 1218 for (i = 0; dspcode[i].reg != 0; i++) 1219 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1220 } 1221 1222 static void 1223 brgphy_disable_early_dac(struct mii_softc *sc) 1224 { 1225 uint32_t val; 1226 1227 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1228 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1229 val &= ~(1 << 8); 1230 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1231 1232 } 1233 1234 static void 1235 brgphy_jumbo_settings(struct mii_softc *sc) 1236 { 1237 uint32_t val; 1238 1239 /* Set Jumbo frame settings in the PHY. */ 1240 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1241 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1242 /* Cannot do read-modify-write on the BCM5401 */ 1243 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1244 } else { 1245 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1246 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1247 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1248 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1249 } 1250 1251 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 1252 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1253 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1254 } 1255 1256 static void 1257 brgphy_eth_wirespeed(struct mii_softc *sc) 1258 { 1259 uint32_t val; 1260 1261 /* Enable Ethernet@Wirespeed */ 1262 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1263 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1264 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1265 (val | (1 << 15) | (1 << 4))); 1266 } 1267
Indexes created Thu Sep 25 16:09:42 GMT 2025