brgphy.c revision 1.74
1 /* $NetBSD: brgphy.c,v 1.74 2014/07/02 22:01:44 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.74 2014/07/02 22:01:44 msaitoh Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 uint32_t sc_shared_hwcfg; /* shared hw config */ 96 uint32_t sc_port_hwcfg; /* port specific hw config */ 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_copper_status(struct mii_softc *); 105 static void brgphy_fiber_status(struct mii_softc *); 106 static void brgphy_5708s_status(struct mii_softc *); 107 static void brgphy_5709s_status(struct mii_softc *); 108 static int brgphy_mii_phy_auto(struct mii_softc *); 109 static void brgphy_loop(struct mii_softc *); 110 static void brgphy_reset(struct mii_softc *); 111 static void brgphy_bcm5401_dspcode(struct mii_softc *); 112 static void brgphy_bcm5411_dspcode(struct mii_softc *); 113 static void brgphy_bcm5421_dspcode(struct mii_softc *); 114 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 115 static void brgphy_adc_bug(struct mii_softc *); 116 static void brgphy_5704_a0_bug(struct mii_softc *); 117 static void brgphy_ber_bug(struct mii_softc *); 118 static void brgphy_crc_bug(struct mii_softc *); 119 static void brgphy_disable_early_dac(struct mii_softc *); 120 static void brgphy_jumbo_settings(struct mii_softc *); 121 static void brgphy_eth_wirespeed(struct mii_softc *); 122 123 124 static const struct mii_phy_funcs brgphy_copper_funcs = { 125 brgphy_service, brgphy_copper_status, brgphy_reset, 126 }; 127 128 static const struct mii_phy_funcs brgphy_fiber_funcs = { 129 brgphy_service, brgphy_fiber_status, brgphy_reset, 130 }; 131 132 static const struct mii_phy_funcs brgphy_5708s_funcs = { 133 brgphy_service, brgphy_5708s_status, brgphy_reset, 134 }; 135 136 static const struct mii_phy_funcs brgphy_5709s_funcs = { 137 brgphy_service, brgphy_5709s_status, brgphy_reset, 138 }; 139 140 static const struct mii_phydesc brgphys[] = { 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 142 MII_STR_BROADCOM_BCM5400 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 145 MII_STR_BROADCOM_BCM5401 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 148 MII_STR_BROADCOM_BCM5411 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 151 MII_STR_BROADCOM_BCM5421 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 154 MII_STR_BROADCOM_BCM5462 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 157 MII_STR_BROADCOM_BCM5461 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 160 MII_STR_BROADCOM_BCM54K2 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 163 MII_STR_BROADCOM_BCM5464 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 166 MII_STR_BROADCOM_BCM5701 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 169 MII_STR_BROADCOM_BCM5703 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 172 MII_STR_BROADCOM_BCM5704 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 175 MII_STR_BROADCOM_BCM5705 }, 176 177 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 178 MII_STR_BROADCOM_BCM5714 }, 179 180 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 181 MII_STR_BROADCOM_BCM5750 }, 182 183 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 184 MII_STR_BROADCOM_BCM5752 }, 185 186 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 187 MII_STR_BROADCOM_BCM5780 }, 188 189 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 190 MII_STR_BROADCOM_BCM5708C }, 191 192 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 193 MII_STR_BROADCOM2_BCM5481 }, 194 195 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 196 MII_STR_BROADCOM2_BCM5482 }, 197 198 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5708S, 199 MII_STR_BROADCOM2_BCM5708S }, 200 201 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 202 MII_STR_BROADCOM2_BCM5709C }, 203 204 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 205 MII_STR_BROADCOM2_BCM5709S }, 206 207 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 208 MII_STR_BROADCOM2_BCM5709CAX }, 209 210 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 211 MII_STR_BROADCOM2_BCM5722 }, 212 213 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 214 MII_STR_BROADCOM2_BCM5754 }, 215 216 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 217 MII_STR_BROADCOM2_BCM5755 }, 218 219 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 220 MII_STR_BROADCOM2_BCM5756 }, 221 222 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 223 MII_STR_BROADCOM2_BCM5761 }, 224 225 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 226 MII_STR_BROADCOM2_BCM5784 }, 227 228 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 229 MII_STR_BROADCOM2_BCM5785 }, 230 231 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 232 MII_STR_BROADCOM3_BCM5717C }, 233 234 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 235 MII_STR_BROADCOM3_BCM5719C }, 236 237 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 238 MII_STR_BROADCOM3_BCM5720C }, 239 240 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 241 MII_STR_BROADCOM3_BCM57765 }, 242 243 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 244 MII_STR_BROADCOM3_BCM57780 }, 245 246 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 247 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 248 249 { 0, 0, 250 NULL }, 251 }; 252 253 static int 254 brgphymatch(device_t parent, cfdata_t match, void *aux) 255 { 256 struct mii_attach_args *ma = aux; 257 258 if (mii_phy_match(ma, brgphys) != NULL) 259 return (10); 260 261 return (0); 262 } 263 264 static void 265 brgphyattach(device_t parent, device_t self, void *aux) 266 { 267 struct brgphy_softc *bsc = device_private(self); 268 struct mii_softc *sc = &bsc->sc_mii; 269 struct mii_attach_args *ma = aux; 270 struct mii_data *mii = ma->mii_data; 271 const struct mii_phydesc *mpd; 272 prop_dictionary_t dict; 273 274 mpd = mii_phy_match(ma, brgphys); 275 aprint_naive(": Media interface\n"); 276 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 277 278 sc->mii_dev = self; 279 sc->mii_inst = mii->mii_instance; 280 sc->mii_phy = ma->mii_phyno; 281 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 282 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 283 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 284 sc->mii_pdata = mii; 285 sc->mii_flags = ma->mii_flags; 286 sc->mii_anegticks = MII_ANEGTICKS; 287 288 if (device_is_a(parent, "bge")) 289 bsc->sc_isbge = true; 290 else if (device_is_a(parent, "bnx")) 291 bsc->sc_isbnx = true; 292 293 dict = device_properties(parent); 294 if (bsc->sc_isbge || bsc->sc_isbnx) { 295 if (!prop_dictionary_get_uint32(dict, "phyflags", 296 &bsc->sc_phyflags)) 297 aprint_error_dev(self, "failed to get phyflags\n"); 298 if (!prop_dictionary_get_uint32(dict, "chipid", 299 &bsc->sc_chipid)) 300 aprint_error_dev(self, "failed to get chipid\n"); 301 } 302 303 if (bsc->sc_isbnx) { 304 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */ 305 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg", 306 &bsc->sc_shared_hwcfg)) 307 aprint_error_dev(self, "failed to get shared_hwcfg\n"); 308 if (!prop_dictionary_get_uint32(dict, "port_hwcfg", 309 &bsc->sc_port_hwcfg)) 310 aprint_error_dev(self, "failed to get port_hwcfg\n"); 311 } 312 313 if (sc->mii_flags & MIIF_HAVEFIBER) { 314 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 315 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) 316 sc->mii_funcs = &brgphy_5708s_funcs; 317 else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 318 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) 319 sc->mii_funcs = &brgphy_5709s_funcs; 320 else 321 sc->mii_funcs = &brgphy_fiber_funcs; 322 } else 323 sc->mii_funcs = &brgphy_copper_funcs; 324 325 PHY_RESET(sc); 326 327 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 328 if (sc->mii_capabilities & BMSR_EXTSTAT) 329 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 330 331 aprint_normal_dev(self, ""); 332 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 333 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 334 aprint_error("no media present"); 335 else { 336 if (sc->mii_flags & MIIF_HAVEFIBER) { 337 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 338 339 /* 340 * Set the proper bits for capabilities so that the 341 * correct media get selected by mii_phy_add_media() 342 */ 343 sc->mii_capabilities |= BMSR_ANEG; 344 sc->mii_capabilities &= ~BMSR_100T4; 345 sc->mii_extcapabilities |= EXTSR_1000XFDX; 346 347 if (bsc->sc_isbnx) { 348 /* 349 * 2.5Gb support is a software enabled feature 350 * on the BCM5708S and BCM5709S controllers. 351 */ 352 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 353 if (bsc->sc_phyflags 354 & BNX_PHY_2_5G_CAPABLE_FLAG) { 355 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 356 IFM_FDX, sc->mii_inst), 0); 357 aprint_normal("2500baseSX-FDX, "); 358 #undef ADD 359 } 360 } 361 } 362 mii_phy_add_media(sc); 363 } 364 aprint_normal("\n"); 365 366 } 367 368 static int 369 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 370 { 371 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 372 int reg, speed, gig; 373 374 switch (cmd) { 375 case MII_POLLSTAT: 376 /* If we're not polling our PHY instance, just return. */ 377 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 378 return (0); 379 break; 380 381 case MII_MEDIACHG: 382 /* 383 * If the media indicates a different PHY instance, 384 * isolate ourselves. 385 */ 386 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 387 reg = PHY_READ(sc, MII_BMCR); 388 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 389 return (0); 390 } 391 392 /* If the interface is not up, don't do anything. */ 393 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 394 break; 395 396 PHY_RESET(sc); /* XXX hardware bug work-around */ 397 398 switch (IFM_SUBTYPE(ife->ifm_media)) { 399 case IFM_AUTO: 400 (void) brgphy_mii_phy_auto(sc); 401 break; 402 case IFM_2500_SX: 403 speed = BRGPHY_5708S_BMCR_2500; 404 goto setit; 405 case IFM_1000_SX: 406 case IFM_1000_T: 407 speed = BMCR_S1000; 408 goto setit; 409 case IFM_100_TX: 410 speed = BMCR_S100; 411 goto setit; 412 case IFM_10_T: 413 speed = BMCR_S10; 414 setit: 415 brgphy_loop(sc); 416 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 417 speed |= BMCR_FDX; 418 gig = GTCR_ADV_1000TFDX; 419 } else 420 gig = GTCR_ADV_1000THDX; 421 422 PHY_WRITE(sc, MII_100T2CR, 0); 423 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 424 PHY_WRITE(sc, MII_BMCR, speed); 425 426 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) && 427 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) && 428 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX)) 429 break; 430 431 PHY_WRITE(sc, MII_100T2CR, gig); 432 PHY_WRITE(sc, MII_BMCR, 433 speed | BMCR_AUTOEN | BMCR_STARTNEG); 434 435 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 436 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 437 break; 438 439 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 440 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 441 PHY_WRITE(sc, MII_100T2CR, gig); 442 break; 443 default: 444 return (EINVAL); 445 } 446 break; 447 448 case MII_TICK: 449 /* If we're not currently selected, just return. */ 450 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 451 return (0); 452 453 /* Is the interface even up? */ 454 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 455 return 0; 456 457 /* Only used for autonegotiation. */ 458 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 459 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 460 sc->mii_ticks = 0; 461 break; 462 } 463 464 /* 465 * Check for link. 466 * Read the status register twice; BMSR_LINK is latch-low. 467 */ 468 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 469 if (reg & BMSR_LINK) { 470 sc->mii_ticks = 0; 471 break; 472 } 473 474 /* 475 * mii_ticks == 0 means it's the first tick after changing the 476 * media or the link became down since the last tick 477 * (see above), so break to update the status. 478 */ 479 if (sc->mii_ticks++ == 0) 480 break; 481 482 /* Only retry autonegotiation every mii_anegticks seconds. */ 483 KASSERT(sc->mii_anegticks != 0); 484 if (sc->mii_ticks <= sc->mii_anegticks) 485 break; 486 487 brgphy_mii_phy_auto(sc); 488 break; 489 490 case MII_DOWN: 491 mii_phy_down(sc); 492 return (0); 493 } 494 495 /* Update the media status. */ 496 mii_phy_status(sc); 497 498 /* 499 * Callback if something changed. Note that we need to poke the DSP on 500 * the Broadcom PHYs if the media changes. 501 */ 502 if (sc->mii_media_active != mii->mii_media_active || 503 sc->mii_media_status != mii->mii_media_status || 504 cmd == MII_MEDIACHG) { 505 switch (sc->mii_mpd_oui) { 506 case MII_OUI_BROADCOM: 507 switch (sc->mii_mpd_model) { 508 case MII_MODEL_BROADCOM_BCM5400: 509 brgphy_bcm5401_dspcode(sc); 510 break; 511 case MII_MODEL_BROADCOM_BCM5401: 512 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 513 brgphy_bcm5401_dspcode(sc); 514 break; 515 case MII_MODEL_BROADCOM_BCM5411: 516 brgphy_bcm5411_dspcode(sc); 517 break; 518 } 519 break; 520 } 521 } 522 523 /* Callback if something changed. */ 524 mii_phy_update(sc, cmd); 525 return (0); 526 } 527 528 static void 529 brgphy_copper_status(struct mii_softc *sc) 530 { 531 struct mii_data *mii = sc->mii_pdata; 532 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 533 int bmcr, bmsr, auxsts, gtsr; 534 535 mii->mii_media_status = IFM_AVALID; 536 mii->mii_media_active = IFM_ETHER; 537 538 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 539 if (bmsr & BMSR_LINK) 540 mii->mii_media_status |= IFM_ACTIVE; 541 542 bmcr = PHY_READ(sc, MII_BMCR); 543 if (bmcr & BMCR_ISO) { 544 mii->mii_media_active |= IFM_NONE; 545 mii->mii_media_status = 0; 546 return; 547 } 548 549 if (bmcr & BMCR_LOOP) 550 mii->mii_media_active |= IFM_LOOP; 551 552 if (bmcr & BMCR_AUTOEN) { 553 /* 554 * The media status bits are only valid of autonegotiation 555 * has completed (or it's disabled). 556 */ 557 if ((bmsr & BMSR_ACOMP) == 0) { 558 /* Erg, still trying, I guess... */ 559 mii->mii_media_active |= IFM_NONE; 560 return; 561 } 562 563 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 564 565 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 566 case BRGPHY_RES_1000FD: 567 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 568 gtsr = PHY_READ(sc, MII_100T2SR); 569 if (gtsr & GTSR_MS_RES) 570 mii->mii_media_active |= IFM_ETH_MASTER; 571 break; 572 573 case BRGPHY_RES_1000HD: 574 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 575 gtsr = PHY_READ(sc, MII_100T2SR); 576 if (gtsr & GTSR_MS_RES) 577 mii->mii_media_active |= IFM_ETH_MASTER; 578 break; 579 580 case BRGPHY_RES_100FD: 581 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 582 break; 583 584 case BRGPHY_RES_100T4: 585 mii->mii_media_active |= IFM_100_T4 | IFM_HDX; 586 break; 587 588 case BRGPHY_RES_100HD: 589 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 590 break; 591 592 case BRGPHY_RES_10FD: 593 mii->mii_media_active |= IFM_10_T | IFM_FDX; 594 break; 595 596 case BRGPHY_RES_10HD: 597 mii->mii_media_active |= IFM_10_T | IFM_HDX; 598 break; 599 600 default: 601 mii->mii_media_active |= IFM_NONE; 602 mii->mii_media_status = 0; 603 } 604 605 if (mii->mii_media_active & IFM_FDX) 606 mii->mii_media_active |= mii_phy_flowstatus(sc); 607 608 } else 609 mii->mii_media_active = ife->ifm_media; 610 } 611 612 void 613 brgphy_fiber_status(struct mii_softc *sc) 614 { 615 struct mii_data *mii = sc->mii_pdata; 616 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 617 int bmcr, bmsr; 618 619 mii->mii_media_status = IFM_AVALID; 620 mii->mii_media_active = IFM_ETHER; 621 622 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 623 if (bmsr & BMSR_LINK) 624 mii->mii_media_status |= IFM_ACTIVE; 625 626 bmcr = PHY_READ(sc, MII_BMCR); 627 if (bmcr & BMCR_LOOP) 628 mii->mii_media_active |= IFM_LOOP; 629 630 if (bmcr & BMCR_AUTOEN) { 631 int val; 632 633 if ((bmsr & BMSR_ACOMP) == 0) { 634 /* Erg, still trying, I guess... */ 635 mii->mii_media_active |= IFM_NONE; 636 return; 637 } 638 639 mii->mii_media_active |= IFM_1000_SX; 640 641 val = PHY_READ(sc, MII_ANAR) & 642 PHY_READ(sc, MII_ANLPAR); 643 644 if (val & ANAR_X_FD) 645 mii->mii_media_active |= IFM_FDX; 646 else 647 mii->mii_media_active |= IFM_HDX; 648 649 if (mii->mii_media_active & IFM_FDX) 650 mii->mii_media_active |= mii_phy_flowstatus(sc); 651 } else 652 mii->mii_media_active = ife->ifm_media; 653 } 654 655 void 656 brgphy_5708s_status(struct mii_softc *sc) 657 { 658 struct mii_data *mii = sc->mii_pdata; 659 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 660 int bmcr, bmsr; 661 662 mii->mii_media_status = IFM_AVALID; 663 mii->mii_media_active = IFM_ETHER; 664 665 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 666 if (bmsr & BMSR_LINK) 667 mii->mii_media_status |= IFM_ACTIVE; 668 669 bmcr = PHY_READ(sc, MII_BMCR); 670 if (bmcr & BMCR_LOOP) 671 mii->mii_media_active |= IFM_LOOP; 672 673 if (bmcr & BMCR_AUTOEN) { 674 int xstat; 675 676 if ((bmsr & BMSR_ACOMP) == 0) { 677 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 678 BRGPHY_5708S_DIG_PG0); 679 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 680 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) { 681 /* Erg, still trying, I guess... */ 682 mii->mii_media_active |= IFM_NONE; 683 return; 684 } 685 } 686 687 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 688 BRGPHY_5708S_DIG_PG0); 689 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 690 691 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 692 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 693 mii->mii_media_active |= IFM_10_FL; 694 break; 695 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 696 mii->mii_media_active |= IFM_100_FX; 697 break; 698 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 699 mii->mii_media_active |= IFM_1000_SX; 700 break; 701 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 702 mii->mii_media_active |= IFM_2500_SX; 703 break; 704 } 705 706 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 707 mii->mii_media_active |= IFM_FDX; 708 else 709 mii->mii_media_active |= IFM_HDX; 710 711 if (mii->mii_media_active & IFM_FDX) { 712 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE) 713 mii->mii_media_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 714 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE) 715 mii->mii_media_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 716 } 717 } else 718 mii->mii_media_active = ife->ifm_media; 719 } 720 721 static void 722 brgphy_5709s_status(struct mii_softc *sc) 723 { 724 struct mii_data *mii = sc->mii_pdata; 725 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 726 int bmcr, bmsr, auxsts; 727 728 mii->mii_media_status = IFM_AVALID; 729 mii->mii_media_active = IFM_ETHER; 730 731 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 732 if (bmsr & BMSR_LINK) 733 mii->mii_media_status |= IFM_ACTIVE; 734 735 bmcr = PHY_READ(sc, MII_BMCR); 736 if (bmcr & BMCR_ISO) { 737 mii->mii_media_active |= IFM_NONE; 738 mii->mii_media_status = 0; 739 return; 740 } 741 742 if (bmcr & BMCR_LOOP) 743 mii->mii_media_active |= IFM_LOOP; 744 745 if (bmcr & BMCR_AUTOEN) { 746 /* 747 * The media status bits are only valid of autonegotiation 748 * has completed (or it's disabled). 749 */ 750 if ((bmsr & BMSR_ACOMP) == 0) { 751 /* Erg, still trying, I guess... */ 752 mii->mii_media_active |= IFM_NONE; 753 return; 754 } 755 756 /* 5709S has its own general purpose status registers */ 757 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 758 BRGPHY_BLOCK_ADDR_GP_STATUS); 759 auxsts = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 760 761 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 762 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 763 764 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 765 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 766 mii->mii_media_active |= IFM_10_FL; 767 break; 768 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 769 mii->mii_media_active |= IFM_100_FX; 770 break; 771 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 772 mii->mii_media_active |= IFM_1000_SX; 773 break; 774 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 775 mii->mii_media_active |= IFM_2500_SX; 776 break; 777 default: 778 mii->mii_media_active |= IFM_NONE; 779 mii->mii_media_status = 0; 780 break; 781 } 782 783 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 784 mii->mii_media_active |= IFM_FDX; 785 else 786 mii->mii_media_active |= IFM_HDX; 787 788 if (mii->mii_media_active & IFM_FDX) 789 mii->mii_media_active |= mii_phy_flowstatus(sc); 790 } else 791 mii->mii_media_active = ife->ifm_media; 792 } 793 794 int 795 brgphy_mii_phy_auto(struct mii_softc *sc) 796 { 797 int anar, ktcr = 0; 798 799 sc->mii_ticks = 0; 800 brgphy_loop(sc); 801 PHY_RESET(sc); 802 803 if (sc->mii_flags & MIIF_HAVEFIBER) { 804 anar = ANAR_X_FD | ANAR_X_HD; 805 if (sc->mii_flags & MIIF_DOPAUSE) 806 anar |= ANAR_X_PAUSE_TOWARDS; 807 } else { 808 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 809 if (sc->mii_flags & MIIF_DOPAUSE) 810 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 811 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 812 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 813 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 814 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 815 PHY_WRITE(sc, MII_100T2CR, ktcr); 816 ktcr = PHY_READ(sc, MII_100T2CR); 817 } 818 PHY_WRITE(sc, MII_ANAR, anar); 819 820 /* Start autonegotiation */ 821 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 822 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 823 824 return (EJUSTRETURN); 825 } 826 827 void 828 brgphy_loop(struct mii_softc *sc) 829 { 830 uint32_t bmsr; 831 int i; 832 833 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 834 for (i = 0; i < 15000; i++) { 835 bmsr = PHY_READ(sc, MII_BMSR); 836 if (!(bmsr & BMSR_LINK)) 837 break; 838 DELAY(10); 839 } 840 } 841 842 static void 843 brgphy_reset(struct mii_softc *sc) 844 { 845 struct brgphy_softc *bsc = device_private(sc->mii_dev); 846 847 mii_phy_reset(sc); 848 switch (sc->mii_mpd_oui) { 849 case MII_OUI_BROADCOM: 850 switch (sc->mii_mpd_model) { 851 case MII_MODEL_BROADCOM_BCM5400: 852 brgphy_bcm5401_dspcode(sc); 853 break; 854 case MII_MODEL_BROADCOM_BCM5401: 855 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 856 brgphy_bcm5401_dspcode(sc); 857 break; 858 case MII_MODEL_BROADCOM_BCM5411: 859 brgphy_bcm5411_dspcode(sc); 860 break; 861 case MII_MODEL_BROADCOM_BCM5421: 862 brgphy_bcm5421_dspcode(sc); 863 break; 864 case MII_MODEL_BROADCOM_BCM54K2: 865 brgphy_bcm54k2_dspcode(sc); 866 break; 867 } 868 break; 869 case MII_OUI_BROADCOM3: 870 switch (sc->mii_mpd_model) { 871 case MII_MODEL_BROADCOM3_BCM5717C: 872 case MII_MODEL_BROADCOM3_BCM5719C: 873 case MII_MODEL_BROADCOM3_BCM5720C: 874 case MII_MODEL_BROADCOM3_BCM57765: 875 return; 876 } 877 break; 878 default: 879 break; 880 } 881 882 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 883 if (bsc->sc_isbge) { 884 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 885 886 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 887 brgphy_adc_bug(sc); 888 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 889 brgphy_5704_a0_bug(sc); 890 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 891 brgphy_ber_bug(sc); 892 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 893 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 894 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 895 0x000a); 896 897 if (bsc->sc_phyflags 898 & BGEPHYF_ADJUST_TRIM) { 899 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 900 0x110b); 901 PHY_WRITE(sc, BRGPHY_TEST1, 902 BRGPHY_TEST1_TRIM_EN | 0x4); 903 } else { 904 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 905 0x010b); 906 } 907 908 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 909 } 910 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 911 brgphy_crc_bug(sc); 912 913 /* Set Jumbo frame settings in the PHY. */ 914 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 915 brgphy_jumbo_settings(sc); 916 917 /* Adjust output voltage */ 918 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 919 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 920 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 921 922 /* Enable Ethernet@Wirespeed */ 923 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 924 brgphy_eth_wirespeed(sc); 925 926 #if 0 927 /* Enable Link LED on Dell boxes */ 928 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 929 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 930 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 931 & ~BRGPHY_PHY_EXTCTL_3_LED); 932 } 933 #endif 934 } 935 /* Handle any bnx (NetXtreme II) workarounds. */ 936 } else if (bsc->sc_isbnx) { 937 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 938 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 939 /* Store autoneg capabilities/results in digital block (Page 0) */ 940 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 941 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 942 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 943 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 944 945 /* Enable fiber mode and autodetection */ 946 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 947 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 948 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 949 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 950 951 /* Enable parallel detection */ 952 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 953 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 954 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 955 956 /* Advertise 2.5G support through next page during autoneg */ 957 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) 958 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 959 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 960 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 961 962 /* Increase TX signal amplitude */ 963 if ((_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_A0) || 964 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B0) || 965 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B1)) { 966 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 967 BRGPHY_5708S_TX_MISC_PG5); 968 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 969 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & 970 ~BRGPHY_5708S_PG5_TXACTL1_VCM); 971 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 972 BRGPHY_5708S_DIG_PG0); 973 } 974 975 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 976 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 977 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 978 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 979 BRGPHY_5708S_TX_MISC_PG5); 980 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 981 bsc->sc_port_hwcfg & 982 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 983 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 984 BRGPHY_5708S_DIG_PG0); 985 } 986 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 987 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 988 /* Select the SerDes Digital block of the AN MMD. */ 989 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 990 BRGPHY_BLOCK_ADDR_SERDES_DIG); 991 992 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 993 (PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1) & 994 ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 995 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 996 997 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 998 /* Select the Over 1G block of the AN MMD. */ 999 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1000 BRGPHY_BLOCK_ADDR_OVER_1G); 1001 1002 /* 1003 * Enable autoneg "Next Page" to advertise 1004 * 2.5G support. 1005 */ 1006 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 1007 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1) | 1008 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1009 } 1010 1011 /* 1012 * Select the Multi-Rate Backplane Ethernet block of 1013 * the AN MMD. 1014 */ 1015 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1016 BRGPHY_BLOCK_ADDR_MRBE); 1017 1018 /* Enable MRBE speed autoneg. */ 1019 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 1020 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP) | 1021 BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1022 BRGPHY_MRBE_MSG_PG5_NP_T2); 1023 1024 /* Select the Clause 73 User B0 block of the AN MMD. */ 1025 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1026 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1027 1028 /* Enable MRBE speed autoneg. */ 1029 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1030 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1031 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1032 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1033 1034 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1035 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1036 1037 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 1038 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 1039 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 1040 brgphy_disable_early_dac(sc); 1041 1042 /* Set Jumbo frame settings in the PHY. */ 1043 brgphy_jumbo_settings(sc); 1044 1045 /* Enable Ethernet@Wirespeed */ 1046 brgphy_eth_wirespeed(sc); 1047 } else { 1048 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 1049 brgphy_ber_bug(sc); 1050 1051 /* Set Jumbo frame settings in the PHY. */ 1052 brgphy_jumbo_settings(sc); 1053 1054 /* Enable Ethernet@Wirespeed */ 1055 brgphy_eth_wirespeed(sc); 1056 } 1057 } 1058 } 1059 } 1060 1061 /* Turn off tap power management on 5401. */ 1062 static void 1063 brgphy_bcm5401_dspcode(struct mii_softc *sc) 1064 { 1065 static const struct { 1066 int reg; 1067 uint16_t val; 1068 } dspcode[] = { 1069 { BRGPHY_MII_AUXCTL, 0x0c20 }, 1070 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 1071 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 1072 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 1073 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 1074 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1075 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 1076 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1077 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 1078 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1079 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 1080 { 0, 0 }, 1081 }; 1082 int i; 1083 1084 for (i = 0; dspcode[i].reg != 0; i++) 1085 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1086 delay(40); 1087 } 1088 1089 static void 1090 brgphy_bcm5411_dspcode(struct mii_softc *sc) 1091 { 1092 static const struct { 1093 int reg; 1094 uint16_t val; 1095 } dspcode[] = { 1096 { 0x1c, 0x8c23 }, 1097 { 0x1c, 0x8ca3 }, 1098 { 0x1c, 0x8c23 }, 1099 { 0, 0 }, 1100 }; 1101 int i; 1102 1103 for (i = 0; dspcode[i].reg != 0; i++) 1104 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1105 } 1106 1107 void 1108 brgphy_bcm5421_dspcode(struct mii_softc *sc) 1109 { 1110 uint16_t data; 1111 1112 /* Set Class A mode */ 1113 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 1114 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1115 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 1116 1117 /* Set FFE gamma override to -0.125 */ 1118 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 1119 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1120 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 1121 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 1122 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1123 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 1124 } 1125 1126 void 1127 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 1128 { 1129 static const struct { 1130 int reg; 1131 uint16_t val; 1132 } dspcode[] = { 1133 { 4, 0x01e1 }, 1134 { 9, 0x0300 }, 1135 { 0, 0 }, 1136 }; 1137 int i; 1138 1139 for (i = 0; dspcode[i].reg != 0; i++) 1140 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1141 } 1142 1143 static void 1144 brgphy_adc_bug(struct mii_softc *sc) 1145 { 1146 static const struct { 1147 int reg; 1148 uint16_t val; 1149 } dspcode[] = { 1150 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1151 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1152 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 1153 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1154 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 1155 { BRGPHY_MII_AUXCTL, 0x0400 }, 1156 { 0, 0 }, 1157 }; 1158 int i; 1159 1160 for (i = 0; dspcode[i].reg != 0; i++) 1161 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1162 } 1163 1164 static void 1165 brgphy_5704_a0_bug(struct mii_softc *sc) 1166 { 1167 static const struct { 1168 int reg; 1169 uint16_t val; 1170 } dspcode[] = { 1171 { 0x1c, 0x8d68 }, 1172 { 0x1c, 0x8d68 }, 1173 { 0, 0 }, 1174 }; 1175 int i; 1176 1177 for (i = 0; dspcode[i].reg != 0; i++) 1178 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1179 } 1180 1181 static void 1182 brgphy_ber_bug(struct mii_softc *sc) 1183 { 1184 static const struct { 1185 int reg; 1186 uint16_t val; 1187 } dspcode[] = { 1188 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1189 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1190 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1191 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1192 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1193 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1194 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1195 { BRGPHY_MII_AUXCTL, 0x0400 }, 1196 { 0, 0 }, 1197 }; 1198 int i; 1199 1200 for (i = 0; dspcode[i].reg != 0; i++) 1201 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1202 } 1203 1204 /* BCM5701 A0/B0 CRC bug workaround */ 1205 void 1206 brgphy_crc_bug(struct mii_softc *sc) 1207 { 1208 static const struct { 1209 int reg; 1210 uint16_t val; 1211 } dspcode[] = { 1212 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1213 { 0x1c, 0x8c68 }, 1214 { 0x1c, 0x8d68 }, 1215 { 0x1c, 0x8c68 }, 1216 { 0, 0 }, 1217 }; 1218 int i; 1219 1220 for (i = 0; dspcode[i].reg != 0; i++) 1221 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1222 } 1223 1224 static void 1225 brgphy_disable_early_dac(struct mii_softc *sc) 1226 { 1227 uint32_t val; 1228 1229 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1230 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 1231 val &= ~(1 << 8); 1232 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1233 1234 } 1235 1236 static void 1237 brgphy_jumbo_settings(struct mii_softc *sc) 1238 { 1239 uint32_t val; 1240 1241 /* Set Jumbo frame settings in the PHY. */ 1242 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1243 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1244 /* Cannot do read-modify-write on the BCM5401 */ 1245 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1246 } else { 1247 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1248 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1249 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1250 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1251 } 1252 1253 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 1254 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1255 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1256 } 1257 1258 static void 1259 brgphy_eth_wirespeed(struct mii_softc *sc) 1260 { 1261 uint32_t val; 1262 1263 /* Enable Ethernet@Wirespeed */ 1264 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1265 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 1266 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1267 (val | (1 << 15) | (1 << 4))); 1268 } 1269
Indexes created Tue Oct 21 19:09:51 GMT 2025